Optical sensor with trench etched through dielectric over silicon

Abstract

In described examples, an integrated circuit (IC) (100) has a plurality of layers of dielectric material (110) overlying at least a portion of a surface of a substrate (102). A trench (106) is etched through the layers of dielectric material to expose a portion of the substrate to form a trench floor (105), the trench being surrounded by trench walls formed by the layers of dielectric material. A metal perimeter band (321) surrounds the trench adjacent the trench walls, the perimeter band being embedded in one of the layers of dielectric material.

Description

Technical Field

[0001] This application relates to etching trenches through multiple dielectric layers above silicon for use in optical sensors. Background Technology

[0002] An optical sensor is a device that converts light into electronic signals. It detects the physical quantity of incident light and transforms it into a form that a signal processing system can read. Optical sensors are typically part of a larger system that integrates a light source, measuring devices, and optical sensors. One characteristic of an optical sensor is its ability to measure changes from one or more light beams. These changes are typically based on variations in light intensity. Optical sensors can operate using a single-point approach or by distributing points along a series of sensors. Optical sensors can be based on visible light, infrared (IR), or ultraviolet (UV) radiation.

[0003] Optical sensors are used in many research and commercial applications, such as quality and process control, medical technology, metrology, imaging, and remote sensing. Autonomous vehicles use optical sensors for navigation and collision avoidance.

[0004] A common type of photoelectric sensor uses a silicon-based photodiode. The photodiode converts the amount of incident light into an output current. Summary of the Invention

[0005] In the described example, the integrated circuit (IC) has multiple dielectric material layers covering at least a portion of the surface of a silicon substrate. Trenches are etched through the dielectric material layers to expose a portion of the substrate to form a trench base plate, the trenches being surrounded by trench walls formed by the dielectric material layers. A metal peripheral band, as part of a metal plate etch stop, surrounds the trench adjacent to the trench walls, the peripheral band being embedded in one of the dielectric material layers. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view of a portion of an integrated circuit (IC) that includes an optical sensor.

[0007] Figure 2 It is a drawing illustrating the operation of different optical sensors.

[0008] Figures 3A-3D-1 , Figure 3D-2 This is a cross-sectional view illustrating the trench fabrication within an IC.

[0009] Figure 4A , Figure 4B This is a cross-sectional view of a portion of an IC, illustrating an optical sensor with a single-layer anti-reflective coating (ARC).

[0010] Figure 5It is a plot of reflectivity versus wavelength for single-layer ARC with different incident angles and light polarizations.

[0011] Figure 6 yes Figures 4A-4B A top-view cross-sectional view of a portion of the IC.

[0012] Figures 7A-7D This is a cross-sectional view of a portion of another example IC, illustrating the formation of trenches using multiple etch stops.

[0013] Figure 8 This is a cross-sectional view of a portion of another example IC with trenches filled with printed filters.

[0014] Figures 9-11 This is a cross-sectional view of a portion of an example IC with back-incident light detection.

[0015] Figure 12 This is a flowchart illustrating the process of forming a trench for exposing an optical sensor. Detailed Implementation

[0016] In the accompanying drawings, the same elements are represented by the same reference numerals to maintain consistency.

[0017] Optical sensors using silicon photodiodes (Si) (visible, infrared (IR), and ultraviolet (UV)) require incident light to reach the silicon-based sensor so that the photodiode can convert the amount of incident light into an output current. The dielectric between the silicon photodiode and the environment can reflect or absorb incident light, thus reducing the amount of light reaching the sensor. Example complementary metal-oxide-semiconductor (CMOS) dielectric stacks with multiple metallization layers for interconnection create uncontrolled light reflection due to surface undulations and multiple layer-to-layer interfaces. Adding an anti-reflective coating (ARC) on top of the dielectric layers can slightly reduce, but not eliminate, this. To allow more light to fall on the sensor, a significant amount of dielectric removal is required, allowing the ARC to be placed directly above the photodiode.

[0018] Figure 1 This is a cross-sectional view of a portion of an integrated circuit (IC) 100 including a photodiode optical sensor 104. IC 100 is an example CMOS IC that includes other circuitry (not shown) fabricated on a silicon (Si) substrate 102 using known or later-developed CMOS fabrication techniques. Multiple dielectric and metal layers 110 are fabricated on top of the substrate 102. The individual metal layers are patterned using known or later-developed techniques to form a multilayer metal interconnect network to interconnect the photodiode 104 and other circuitry on the CMOS IC 100.

[0019] In this example, photodiode 104 is a PIN structure. A PIN structure comprises a wide, undoped intrinsic semiconductor region between p-type and n-type semiconductor regions. The p-type and n-type regions are heavily doped because they are used for ohmic contacts. In other examples, different types of photodiodes, such as pn junction diodes or avalanche photodiodes, can be used. When a photon of sufficient energy strikes the diode, it creates electron-hole pairs. If absorption occurs in the depletion region of the junction, or within a diffusion length of it, these carriers are swept out of the junction by the electric field in the depletion region formed by the bias voltage applied to the diode. Therefore, holes move towards the anode, and electrons move towards the cathode, generating a photocurrent. The total current through the photodiode is the sum of the dark current (the current generated in the absence of light) and the photocurrent, so the dark current should be minimized to maximize the sensitivity of the device. For a given spectral distribution, the photocurrent is approximately linearly proportional to the irradiance.

[0020] Trench 106 is etched through dielectric layer 110 to allow incident light (such as example incident light 101) to fall directly onto photodiode 104. In this way, uncontrolled reflections from various dielectric layers are eliminated. Anti-reflective coating (ARC) layer 108 is deposited on the surface of IC 100 and provides ARC on the bottom 105 and sides 109 of trench 106 to control reflections within trench 106.

[0021] The problem with etching trench 106 through a thick dielectric stack 110 with multiple metal layers is that plasma etching of the passivation coating (PO) layer or interconnect vias may lack selectivity for the silicon in the substrate 102 and photodiode 104. Large and highly variable over-etching of the silicon surface of photodiode 104 can occur due to the variability in etching rate and dielectric thickness. Such large variations in the amount of silicon removed are undesirable for a sensor. The etching process described in more detail below produces a smooth, flat bottom 105 for trench 106.

[0022] Figure 2 This is a plot showing the reflectance (%) versus wavelength (nm) of different optical sensors. The plot line 200 illustrates... Figure 1 The operation of the optical sensor 104 in the trench bottom 105 ( Figure 1 It is smooth and flat and covered with ARC 108 ( Figure 1 This produces a substantially linear response, where reflectivity can be controlled to be close to 0% at certain wavelengths of interest. The uniformly low reflectivity across the wavelength range contributes to the optical sensor 104 having a similar uniform responsivity.

[0023] Plot line 202 illustrates the operation of an optical sensor using a process with thick layers of dielectric stacked together. In this case, reflectivity varies significantly across the wavelength range (which would result in similar undesirable nonlinear responsivity in the operation of the optical sensor across the entire wavelength range), or varies significantly within the process tolerances for various layer thicknesses.

[0024] Figures 3A-3D-1 This is a cross-sectional view of a portion of IC 100, illustrating the fabrication of trench 106 within IC 100. A portion of substrate 102 is also shown, in which photodiode 104 is formed using known or later-developed fabrication techniques. Other circuitry (not shown) is also fabricated on substrate 102 using known or later-developed CMOS fabrication techniques.

[0025] Figure 3A This is a cross-sectional view of a portion of IC 100 after all front-end process (FEOL) operations have been performed to fabricate photodiode 104 and other CMOS circuit systems (not shown) on silicon substrate 102 using known or subsequently developed CMOS manufacturing techniques. FEOL is the first part of IC fabrication where individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor. FEOL typically covers everything except the deposition of metal interconnect layers. Deposition of metal layers, intermediate dielectric layers, and vias is performed during back-end process (BEOL) operations.

[0026] The BEOL process forms a thin silicon nitride (SiN) passivation layer 311, which provides a dielectric layer over the active CMOS circuit system. This is followed by a dielectric layer 312, and then a metal layer, which is patterned and etched to form circuit interconnects (such as 322) and isolated by dielectric layers 313, 314, 315, and 316. A passivation overcoat (PO) layer 317 is then applied. Thus, four metal interconnect layers are illustrated in this example. Another example may include fewer or more metal interconnect layers. In this example, dielectric layers 311-316 are silicon dioxide (SiO2), but in other examples, other types of known or later-developed dielectric layers can be fabricated. In this example, the metal layer is aluminum (Al). The SiN layer 311 is approximately 50 nm or smaller, and each thick SiO2 layer 312-316 is approximately 4 μm to 8 μm. Variations of + / -10% to + / -20% may occur in such an Al metal dielectric stack.

[0027] The metal plate etching stop element 320 is patterned in the first metal / dielectric layer 313 and covers the trench 106 to be processed. Figure 1The area of ​​the trench 106 to be processed is defined by applying and patterning a photoresist layer 330 using known or later-developed photolithography techniques to form an opening 331.

[0028] exist Figure 3B In the process, plasma etching has been performed through opening 331, which etches through PO 317 and SiO2 layers 313-316 and stops on metal plate 320 to form partial trench 306. The plasma etching process is selective to Al metal layer 320 and stops smoothly on the top surface of Al etch stop feature 320.

[0029] exist Figure 3C In the process, wet etching is performed through Al feature 320, stopping at SiO2 layer 312. Al metal plate 320 is intentionally larger than the extent of trench 106, such that a remaining metal peripheral band 321, adjacent to the trench walls, surrounds the trench, and the metal peripheral band is embedded in dielectric material layer 313. A third etching is performed through SiO2 layer 312, stopping at SiN layer 311. A fourth timed etching is then performed to etch through SiN layer 311, and only minimally etches the top Si surface of photodiode 104. In this way, a smooth, flat surface is formed on the top surface of photodiode 104 to form the smooth bottom 105 of trench 106. The photoresist layer 330 is then removed (see...). Figure 3B ).

[0030] exist Figure 3D-1 In this example, a multilayer anti-reflective coating 108 is deposited on the surface of the CMOS IC 100 in a manner that uniformly coats the sides 109 and bottom 105 of the trench 106. The ARC 108 includes a SiN layer 326, a SiO2 layer 327, and a silicon oxynitride (SiON) top layer, as shown below. Figure 3D-2 As shown.

[0031] Photoresist (not shown) is then applied and patterned, followed by etching to expose contact pads on IC 100, such as contact pad 324. In another example, SiON PO 317 can be omitted and the dielectric stack is combined with ARC 317. This reduces the thickness of PO that needs to be removed from metal pad 324.

[0032] Plasma etching can be used to remove most of the oxide above and below the metal etch stop 320. Plasma etching is easier to perform than wet etching and provides a tapered profile on the sides of the trench. This method is suitable for Al and copper (Cu) metallization. Cu metallization may require wet etching instead of plasma etching to remove Cu. Al can also be wet etched, but this may result in undercutting of the Al on the sides of the trench.

[0033] IC 100 is manufactured as one of many identical dies on a large semiconductor wafer, tested, separated into individual dies, and then packaged using known or later-developed CMOS manufacturing techniques. The CMOS die 100 is encapsulated with a molding compound using known or later-developed packaging techniques. In this example, openings or light guide paths are provided in the finished package to allow incident light to enter the package. In this example, the packaged IC is a square flat leadless package. Flat leadless packages (such as square flat leadless (QFN) and dual flat leadless (DFN)) physically connect and electrically connect the integrated circuit to a printed circuit board. Flat leadless (also known as micro leadframe (MLF) and SON (small outline leadless)) is a surface mount technology, one of several packaging technologies that connects an IC to the surface of a printed circuit board (PCB) without through-holes. Flat leadless is a near-chip-level package encapsulated in plastic made from a flat copper leadframe substrate. Peripheral solder pads on the bottom of the package provide electrical connection to the PCB. Other examples can be packaged using other known or later-developed packaging technologies, such as square flat packages, ball grid arrays, etc.

[0034] In this way, a trench 106 is formed above the photodiode 104, the trench 106 having a smooth planar base plate 105, which allows a smooth ARC 108 to be formed on the bottom of the trench above the photodiode 104. The smooth, flat ARC contributes to the uniform responsivity of the photodiode 104 across the incident light wavelength range.

[0035] Figure 4A , Figure 4B This is a cross-sectional view of a portion of IC 400, illustrating an optical sensor 104 with a single-layer anti-reflective coating 408. In the described example, the photoelectric sensor uses an ARC, which is one of multiple layers, at least one of which is SiN, SiON, or aluminum oxide (AlOx). This layer protects Si and SiO2 from metal contamination (such as Cu, Na, K, Ag, Au, Fe, etc.), which can degrade Si or metal wiring.

[0036] Narrow-wavelength sensors can use simple ARC (Automatic Reference Array). For example, near-infrared sensors can use one or more ARC layers. Figure 4B As shown, for infrared wavelengths around 850nm, the example optimized ARC is simply a single preferred SiN layer 408 approximately 115nm.

[0037] Figure 5 This applies to various incident angles within the 0-50 degree range, as well as to single-layer ARC (such as) for s-polarized and p-polarized polarization. Figures 4A-4BThe plot shows the reflectivity (%) versus wavelength (nm) of the ARC layer 408 shown. The reflectivity variation is less than 4% at 850 nm within the 0–50 degree incident range and for both polarizations. Further optimization of reflectivity performance can be achieved within specific wavelength ranges using different ARC layer thickness values ​​and material properties.

[0038] Figure 6 yes Figures 4A-4B A top cross-sectional view of a portion of IC 400, illustrating trench 106. A similar top cross-sectional view of IC 100 is shown. This cross-sectional view illustrates dielectric layer 313 and various metal interconnects, such as metal lines 322.

[0039] In this example, trench 106 has a generally rectangular shape. However, in other examples, various trench shapes can be used, such as circular, elliptical, or more complex shapes for special purposes. Trench walls 109 are clad with ARC 408, as referenced. Figures 4A-4B More detailed description.

[0040] Metal peripheral band 321 is the stop part 320 etched through the metal plate ( Figure 3B The part left after that, and in the completion Figure 3C The etching process shown retains the embedded dielectric layer 313. It surrounds the trench 106 and is adjacent to the wall 109 of the trench 106. In various examples, the size of the metal strip 321 can be minimal, just large enough to withstand the etching process. In other examples, the metal strip 321 can extend further into the dielectric layer 313 and can be used within the IC 400 for other functions, such as a ground plane or voltage plane.

[0041] Figures 7A-7D This is a cross-sectional view of a portion of another example IC 700, illustrating the formation of trench 706 using multiple etch stops. IC 700 is similar to IC 100. Figure 1 ) and IC 400 ( Figures 4A-4B Similar to, except for the second metal plate etch stop 720 in the dielectric layer 315.

[0042] Figure 7A This is a cross-sectional view of a portion of IC 700 after all FEOL processes have been performed to fabricate photodiode 104 and other CMOS circuit systems (not shown) on silicon substrate 102 using known or later-developed CMOS fabrication techniques.

[0043] The BEOL process forms a thin silicon nitride (SiN) passivation layer 311, which provides a dielectric layer over the active CMOS circuit system. This is followed by a dielectric layer 312, and then a metal layer, which is patterned and etched to form circuit interconnects (such as 322) and isolated by dielectric layers 313, 314, 315, and 316. A passivation overcoat (PO) layer 317 is then applied. Thus, four metal interconnect layers are illustrated in this example. Another example may include fewer or more metal interconnect layers. In this example, dielectric layers 311-316 are SiO2, but in other examples, other types of known or later-developed dielectric layers can be fabricated. In this example, the metal layer is aluminum (Al). The SiN layer 311 is approximately 50 nm thick, and each thick SiO2 layer 312-316 is approximately 4 μm to 8 μm thick. Variations of + / -10% to + / -20% may occur in such an Al metal dielectric stack.

[0044] A metal plate etch stop 320 is patterned in a first metal / dielectric layer 313 and covers the area of ​​the trench 706 to be processed. A second metal plate etch stop 720 is patterned in a metal / dielectric layer 315 and also covers the area of ​​the trench 706 to be processed. A photoresist layer 330 is applied and patterned using known or later-developed photolithography techniques to form an opening 331 that defines the area of ​​the trench 706 to be processed.

[0045] exist Figure 7B In the process, plasma etching is performed through opening 331, etching through PO 317 and SiO2 layers 315 and 316 and stopping on metal plate 720 to form a partial trench. The plasma etching process is selective for Al metal layer 720 and stops smoothly on the top surface of Al etching stop feature 720. Wet etching is performed through Al feature 720, stopping on SiO2 layer 314. Al metal plate 720 is intentionally larger than the extent of trench 706, such that a remaining metal peripheral band 721, adjacent to the trench wall, surrounds the trench and is embedded in dielectric material layer 315. A second plasma etching is performed through opening 331, etching SiO2 layers 313 and 314 and stopping on metal plate 320 to deepen the partial trench.

[0046] exist Figure 7CIn the process, a second wet etching is performed through Al feature 320, stopping at SiO2 layer 312. Al metal plate 320 is intentionally larger than the extent of trench 706, such that a remaining metal peripheral band 321, adjacent to the trench walls, surrounds the trench and is embedded in dielectric material layer 313. Another plasma etching is performed through SiO2 layer 312, stopping at SiN layer 311. Then a timed etching is performed to etch through SiN layer 311, and only minimally etches the top Si surface of photodiode 104. In this way, a smooth, flat surface is formed on the top surface of photodiode 104 to form the bottom 105 of trench 706. The photoresist layer 330 is then removed (see...). Figure 7B ).

[0047] exist Figure 7D In this example, a multilayer anti-reflective coating 108 is deposited on the surface of the CMOS IC 700 in a manner that uniformly coats the sides 109 and bottom 105 of the trench 706. The ARC 108 includes a SiN layer 326, a SiO2 layer 327, and a silicon oxynitride (SiON) top layer, as shown below. Figure 3D-2 As shown. In other examples, different types of ARC can be used, such as those related to... Figures 4A-4B The single-layer ARC 408 is described.

[0048] Then a photoresist (not shown) is applied and patterned, followed by another plasma etching to expose contact pads, such as contact pad 324.

[0049] Plasma etching can be used to remove most of the oxide above and below the metal etching stops 320 and 720. Plasma etching is easier to perform than wet etching and provides a tapered effect on the sides of the trench. This method is suitable for Al and copper (Cu) metallization. Cu metallization may require wet etching instead of plasma etching to remove Cu. Al can also be wet etched, but this may result in undercutting of Al on the sides of the trench.

[0050] IC 700 was manufactured as one of many identical dies on a large semiconductor wafer. It was tested, separated into individual dies, and then packaged using known or later-developed CMOS manufacturing and packaging technologies.

[0051] In this way, a trench 706 is formed above the photodiode 104, the trench 706 having a smooth planar base plate 105, which allows a smooth ARC 108 to be formed on the bottom of the trench above the photodiode 104. The smooth, flat ARC contributes to the uniform responsivity of the photodiode 104 across the incident light wavelength range.

[0052] Figure 8This is a cross-sectional view of a portion of another example IC 800 having a trench 106 filled with a filter 840. The presence of the trench 106 above the photoelectric sensor 104 advantageously provides a way to mount different filters 840 using polymer materials. By selecting a suitable filter material, the filter 840 can be used for wavelength selection, such as red, green, blue, violet, human light response, etc.

[0053] In this example, polymer filter material 840 is installed only within the area of ​​trench 106 using additive manufacturing processes, such as 3D printing using a printer similar to an inkjet printer. Additive manufacturing enables the deposition of patterned materials in a rapid and cost-effective manner. Additive manufacturing processes are now used in several fields. The International Society for Testing and Materials (ASTM) has now published ASTM F7292-12a, “Standard Terminology for Additive Manufacturing Technologies”, 2012. Currently, according to ASTM F2792, there are seven families of additive manufacturing processes, including: reduction photopolymerization, powder bed fusion, binder jetting, material jetting, sheet lamination, material extrusion, and directional energy deposition. Hybrid processes can combine one or more of these seven basic processes with other manufacturing processes to gain additional processing flexibility. Recent process advances have enabled additive manufacturing of 3D structures with feature resolutions less than 100 nm, such as direct laser lithography, multiphoton lithography, and two-photon polymerization.

[0054] The groove 106 helps to contain the polymer, preventing it from spreading over a larger area.

[0055] The polymer material(s) added to the groove 106 can be used for optical enhancement, such as lens 841. 3D printing technology can be used to customize lens properties, where position, volume, viscosity, and other characteristics can be customized. For example, the lens curvature and lens orientation can be controlled. In this example, lens 841 has a rounded surface that is convex and protrudes away from the groove 106. In another example, the lens can have a greater or lesser degree of convex curvature. In yet another example, the lens can be concave, or have another shape with optical properties useful for the target wavelength of the incident light.

[0056] This example illustrates a multi-layered ARC 108. In another example, an ARC with more or fewer layers can be used depending on the intended application and the incident light wavelength.

[0057] Although Figure 8The diagram illustrates a single trench 106, but IC 800 can contain multiple trenches for multiple light sensors. Different colored polymer materials can be added to different corresponding trenches, allowing each light sensor to respond to incident light of different colors / wavelengths. Different lens shapes can be provided for different trenches to vary the amount of incident light collected by each light sensor.

[0058] In another example, ARC can be optimized to serve as a PO layer for Si protection and potentially for infrared rejection.

[0059] In the described example, the ARC material / thickness / layer can be selected to optimize for a specific incident light wavelength. In another example, the ARC material / thickness / layer can be selected to produce infrared blocking.

[0060] In another example, ARC materials / thickness / layers can be selected to respond to a narrow range of infrared wavelengths for intended applications such as LIDAR (Light Detection and Ranging), a remote sensing method that uses light in the form of pulsed lasers to measure distance.

[0061] If the wafer is thicker than the sensor and the trench opening is much larger than the sensor (ideally with a tapered profile focused on the sensor), an optical lens can ideally and significantly increase the light intensity in the sensor compared to having no lens. The trench and the polymer can be used alone or together to concentrate the light.

[0062] Figure 9 This is a cross-sectional view of a portion of another example IC 900 with back-incident light detection. In some applications, it is desirable for light to enter from the back of the sensor, rather than from the front where metal and interconnects are present. Without additional processing, the light would be absorbed by the silicon substrate and would never reach the Si sensor. One reason for wanting light from the back is to allow wafer-level chip-scale packaging (WCSP) bonding on the front of the wafer.

[0063] WCSP is becoming increasingly popular in portable electronics due to its superior electrical parameters, smaller size, and lower manufacturing cost. Silicon chips can be packaged in a variety of options. While QFN packages completely enclose the silicon die in a plastic housing, contacting the printed circuit board (PCB) via bonding wires and lead frames, WCSP packages directly interconnect the silicon chip to the PCB via solder balls. This minimizes the footprint on the board, as the footprint is the same size as the die. It also minimizes parasitic resistance, inductance, and weight by eliminating additional bonding wires, lead frames, and encapsulation. There is minimal electrical distance between the circuitry on the silicon and the PCB. The interconnect is direct and through a very wide channel, namely the array of solder balls. By eliminating wire bonding and any substrate-related impedance, WCSP offers excellent electrical performance. It contributes to overall solutions that are more efficient, less expensive, have a smaller footprint, are lower in height, and are lighter in weight.

[0064] exist Figure 9 In the example portion of the WCSP IC 900, solder bumps 956 are formed on the front side of copper pads 954, which are then coupled to interconnects in the conductive layers of the dielectric stack 910, thereby coupling to various circuit components (not shown) within the IC 900. The dielectric stack 910 includes multiple patterned conductive layers separated by dielectric layers, and is similar to... Figure 1 The dielectric stack 110.

[0065] Example IC 900 is fabricated on a silicon-on-insulator (SOI) wafer using known or later-developed SOI technology. In this example, a silicon layer 903 is fabricated on top of a silicon dioxide (SiO2) layer 950 on a substrate 902. An optical sensor region 904 is fabricated within the silicon layer 903. In this example, to... Figure 1 The optical sensor region 904 is manufactured in a similar manner to the sensor 104.

[0066] Trench 906 is etched from the back side of wafer 902 using wet or dry etching techniques and stops at SiO2 layer 950, as shown at 951. A second timed etching can then be performed to remove a portion 952 of SiO2 layer 950 to move trench 906 closer to or in contact with the back side of optical sensor 904.

[0067] In some examples, reflector 954 is placed on the front side of wafer 902. This could be silicide, or MET1 (metal layer 1), or even a trench (etched in a dielectric, stopping at silicon, then ARC and metal), such as Figure 1The trench 906. The advantage of adding a reflector to the front side of the wafer is that, by reflecting light traveling through the optical sensor 904 from the back trench 906, the sensor 904 can receive a greater amount of light energy. If silicide is used as a reflector or part of a reflector, this layer can be used to enhance the Si diode sensor.

[0068] A dielectric or polymeric ARC / filter layer 908 is deposited on the back surface of IC 900, providing ARC on the bottom 905 and side 909 of trench 906 to control reflections within trench 906. The ARC layer 908 is similar to that shown in the reference. Figure 1 or Figure 3D-2 A more detailed description of ARC layer 108.

[0069] Polymer filters can be formed in trench 906 to create optical elements, such as reference filters. Figure 8 The filter 840 and lens 841 are described in more detail.

[0070] Figure 10 This is a cross-sectional view of a portion of another example IC 1000 WSCP optical sensor device with back-incident light detection. In this example, a back trench 906 is formed using trench etching on a very thin silicon wafer 1002. In this example, the wafer 1002 is ground to a thickness in the range of approximately 10 μm–50 μm. In this example, a sensor 904 is built on the wafer 1002 having an epitaxial silicon layer 1003. The sensor is built on top of the epitaxial Si. In this example, the bottom layer of the epitaxial wafer is fabricated to have different doping characteristics (concentration, type, element) than the substrate 1002. Wet etching or a combination of dry etching and / or wet etching with appropriate sensitivity is used to etch the substrate 1002, which stops on the epitaxial Si and therefore does not damage the sensor.

[0071] The thin wafer / device 1000 is mechanically supported using a glass wafer 1060 having optional ARC layers 1061, 1062 in trench 906 and an optional filter 1008. The glass wafer 1060 is bonded to the silicon wafer 1002 via a known or later-developed bonding film 1063. Alternatively, the filter material 1008 can be used to bond the support wafer 1060 to the sensor wafer 1002.

[0072] Figure 11 Therefore with Figure 10A cross-sectional view of a portion of another example IC1100 WSCP optical sensor device with back-incident light detection, manufactured in a similar manner to IC 1000. In this example, thin wafer 1002 is mechanically supported by silicon wafer 1160, which has etched openings 1164 aligned with trench 906 to allow back-incident light to enter trench 906 and proceed in parallel to optical sensor 904. Silicon wafer 1160 is bonded to thin wafer 1002 via bonding film 1063.

[0073] In this way, various example optical sensors can be fabricated, in which trenches are etched in the wafer from the front or back to allow ambient light to fall onto the optical sensor located within the wafer. An anti-reflective coating is deposited in the trenches to enhance the light signal entering the silicon photosensor.

[0074] Figure 12 The diagram illustrates the formation of trenches (such as those for exposing optical sensors) Figure 1 , Figure 3D-1 and Figures 4A-4B The flowchart of the groove 106 in the middle.

[0075] At 1200°, a sensor is formed in the silicon substrate using known or later-developed techniques. The sensor can be an optical sensor, such as... Figure 1 The photodiode 104.

[0076] At position 1202, a passivation layer is formed on the surface of the substrate and covers the optical sensor. A dielectric material layer alternating with patterned metal layers is deposited on top of the passivation layer, as shown in the reference. Figure 3A More detailed description. The metal plate etching stop element adjacent to the sensor is formed in the first metal layer, such as in... Figure 3A The metal plate 320 is described in more detail below.

[0077] At point 1204, an etched trench extends through a portion of the dielectric and metallic material layers. The etching process is stopped by the metal plate.

[0078] At position 1206, a second etching is performed through the metal plate, stopping at the dielectric layer beneath the metal plate. The metal plate is intentionally larger than the trench, such that a remaining metal peripheral band surrounds the trench adjacent to the trench walls. The metal peripheral band is embedded in the dielectric material layer. A third etching is performed through the dielectric layer, stopping at the passivation layer. A fourth timed etching is then performed to etch through the passivation layer and only minimally etch the top surface of the sensor. In this way, a smooth, flat surface is formed on the top surface of the sensor, creating a smooth bottom for the trench.

[0079] At 1208, the anti-reflective coating is deposited on the substrate surface in a manner that uniformly coats the sides and bottom of the trench, as shown in the reference. Figure 3D-1A more detailed description.

[0080] At 1210, in some examples, the trench is filled with a polymer material that can be used for wavelength selection by choosing appropriate filter materials, such as red, green, blue, violet, human light response, etc., as per [reference needed]. Figure 8 The filter 840 is described in more detail. In some examples, the polymer material can be formed with a convex surface protruding away from the groove to form a lens, which can concentrate more light to enhance the sensitivity of the sensor, such as... Figure 8 The lens 841 in the diagram is shown.

[0081] Other embodiments

[0082] In the described example, a single trench and optical sensor are illustrated. Other examples may include two or more sensors located in additional trenches.

[0083] In another example, ARC can be two or more alternating SiN and SiO2 layers.

[0084] In other examples, one or more ARC layers may be SiN, Si(x)N(y), SiNH(z), SiON, or other known or later discovered materials with low reflectivity and compatible with IC manufacturing.

[0085] In the described example, an optical sensor is depicted. In other examples, the sensor, trench, and anti-reflective coating may be designed for higher or lower frequencies, such as infrared or ultraviolet radiation.

[0086] In the described example, a CMOS IC is illustrated. In other examples, the trenches fabricated as described above can be fabricated in other types of integrated circuits.

[0087] In the described example, a silicon substrate is used to fabricate the sensor. In other examples, other types of semiconductor substrates can be used with trenches formed therein and coated with ARC.

[0088] In this specification, the term "coupled" and its derivatives refer to indirect, direct, optical, and / or wireless electrical connections. Therefore, if a first device is coupled to a second device, the connection can be via a direct electrical connection, via an indirect electrical connection via other devices and connections, via an optoelectronic connection, and / or via a radio connection.

[0089] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. An integrated circuit, or IC, comprising: A substrate having a first surface and an opposite second surface; A dielectric material layer is applied to at least a portion of the first surface; A trench that penetrates the dielectric material layer, the trench extending to a trench base plate at the first surface, and the trench being surrounded by the dielectric material layer forming the trench walls; A metal peripheral strip in at least one of the dielectric material layers, the metal peripheral strip surrounding the trench adjacent to the trench wall; as well as An optical sensor is located in the substrate, adjacent to the trench at the first surface.

2. The IC of claim 1, wherein the metal peripheral band is part of a metal plate etch stop, the metal plate etch stop being separated from the substrate only by one of the dielectric material layers.

3. The IC according to claim 1 further includes an anti-reflective coating on the trench bottom plate and the trench wall.

4. The IC according to claim 3, wherein the anti-reflective coating is a single-layer material.

5. The IC according to claim 3, wherein the antireflective coating is a single layer of silicon nitride.

6. The IC of claim 1, wherein the metal peripheral band is a first metal peripheral band, and the IC further comprises a second metal peripheral band in one of the dielectric material layers, the second metal peripheral band surrounding the trench adjacent to the trench wall.

7. The IC of claim 1, further comprising a back trench in the substrate, the back trench extending from the second surface to a back trench base plate at the optical sensor, and the back trench being surrounded by the substrate forming the back trench walls.

8. The IC according to claim 7, further comprising an anti-reflective coating on the back groove base plate and the back groove wall.

9. The IC of claim 8, further comprising a support wafer bonded to the second surface.

10. An integrated circuit, or IC, comprising: A substrate having a first surface and an opposite second surface; A dielectric material layer is applied to at least a portion of the first surface; A trench that penetrates the dielectric material layer, the trench extending to a trench base plate at the first surface, and the trench being surrounded by the dielectric material layer forming the trench walls; A metal peripheral strip in at least one of the dielectric material layers, the metal peripheral strip surrounding the trench adjacent to the trench wall; as well as The polymer filter material within the trench.

11. The IC of claim 10, wherein the polymer filter material has a convex surface protruding away from the groove.

12. An integrated circuit, or IC, comprising: A substrate having a first surface and an opposite second surface; A dielectric material layer is applied to at least a portion of the first surface; A sensor located in the substrate at the first surface; A back trench in the substrate, the back trench extending from the second surface to a back trench base plate at the sensor, and the back trench being surrounded by the substrate forming the back trench walls; as well as An anti-reflective coating is applied to the back groove base plate and the back groove wall.

13. The IC of claim 12, further comprising a reflector adjacent to the sensor.

14. The IC of claim 12, further comprising a support wafer bonded to the second surface.

15. The IC according to claim 12, further comprising: A front trench that penetrates the dielectric material layer, the front trench extending to the front trench base plate at the sensor, and the front trench being surrounded by the dielectric material layer forming the front trench wall; as well as A metal peripheral band in at least one of the dielectric material layers, the metal peripheral band being adjacent to the front trench wall surrounding the front trench.

16. The IC of claim 15 further includes an anti-reflective coating on the front trench base plate and the front trench wall.

17. A method for manufacturing an integrated circuit, the method comprising: A sensor is formed on a first surface of a substrate, the substrate having a second surface opposite to the first surface; A dielectric material layer is formed, the dielectric material layer covering at least a portion of the first surface of the substrate, wherein a metal plate etch stop is formed in the first metal layer adjacent to the sensor; The etched trench extends through a portion of the dielectric material layer and stops at the metal plate; as well as The trench is etched through the metal plate to expose a portion of the substrate to form a trench base plate, the trench being surrounded by trench walls formed by the dielectric material layer, wherein the remaining portion of the metal plate forms a metal peripheral band surrounding the trench adjacent to the trench walls.

18. The method of claim 17, further comprising depositing an anti-reflective coating on the trench bottom plate and the trench wall.

19. The method of claim 17, further comprising depositing a polymer filter material within the trench.

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