Storage system
By adjusting the programming time of each word line in the storage system, the problem of unstable write speed variation was solved, ensuring the performance consistency of the storage system within a predetermined time and meeting the customer's performance requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2022-01-17
- Publication Date
- 2026-06-23
Smart Images
Figure CN114792542B_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] Korean Patent Application No. 10-2021-0010170 entitled "Memory System", filed with the Korean Intellectual Property Office on January 25, 2021, is incorporated herein by reference in its entirety. Technical Field
[0003] The embodiments involve storage systems. Background Technology
[0004] In response to the increasing demand for storage devices with small size and high capacity, research has been actively conducted on storage devices with vertically stacked storage cells. Summary of the Invention
[0005] This embodiment relates to a storage system, including: non-volatile storage devices, each comprising a plurality of storage blocks, each storage block including a plurality of storage cells connected to a plurality of word lines; and a storage controller, which determines the programming time of each word line of each of the non-volatile storage devices and calculates a target programming time based on the programming time of each word line. Each of the non-volatile storage devices can receive the target programming time from the storage controller and adjust the programming time of each word line based on the target programming time. After the programming time of each word line is adjusted, the storage controller can determine the magnitude of the change in write speed of the storage system within a predetermined time. When the magnitude of the change in write speed is less than a reference value, the target programming time is set as the final target programming time.
[0006] This embodiment relates to a storage system, including: a non-volatile storage device including multiple word lines; and a storage controller that sets a target programming time such that the variation range of the write speed of the storage system within a predetermined time meets a reference value. The storage controller can send the target programming time corresponding to the word line to be programmed to the non-volatile storage device, and when the storage controller sends a programming command for the word line to the non-volatile storage device, the non-volatile storage device can confirm the programming time of the word line and adjust the programming time of the word line based on the target programming time.
[0007] This embodiment relates to a storage system, including: a non-volatile storage device comprising a plurality of storage blocks; and a storage controller that sets a target programming time such that the variation range of the write speed of the storage system within a predetermined time meets a reference value. When the storage system is powered on, when the storage controller sends the target programming time to the non-volatile storage device, the non-volatile storage device can store the target programming time, and when the storage controller sends a programming command for a word line to the non-volatile storage device, the non-volatile storage device can confirm the programming time of the word line and adjust the programming time of the word line based on the target programming time. Attached Figure Description
[0008] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:
[0009] Figure 1 This is a schematic block diagram illustrating a storage system including a storage device according to an example embodiment;
[0010] Figure 2 This is a schematic block diagram illustrating a non-volatile storage device according to an example embodiment;
[0011] Figure 3 This is a schematic circuit diagram illustrating a storage block of a non-volatile storage device according to an example embodiment;
[0012] Figure 4 and Figure 5 This is a schematic diagram illustrating a non-volatile storage device according to an example embodiment;
[0013] Figure 6 This is a view used to describe the magnitude of performance variations of a storage system according to an example embodiment;
[0014] Figure 7 This is a view used to describe the programming time differences per word line of a non-volatile memory device according to an example embodiment;
[0015] Figure 8A and Figure 8B This is a view used to describe the magnitude of performance variations of a storage system according to an example embodiment;
[0016] Figure 9 This is a view used to describe the programming time differences per word line of a non-volatile memory device according to an example embodiment;
[0017] Figure 10 and Figure 11 This is a view used to describe the performance flattening operation according to the example embodiment;
[0018] Figure 12 This is a view illustrating commands or data exchanged between a storage controller and a non-volatile storage device according to an example embodiment;
[0019] Figure 13 This is a view used to describe a method for confirming the programming time of word lines according to an example embodiment;
[0020] Figure 14 This is a view showing the target programming time according to an example embodiment;
[0021] Figure 15This is a view illustrating commands or data exchanged between a storage controller and a non-volatile storage device according to an example embodiment;
[0022] Figure 16 This is a view showing the target programming time according to an example embodiment; and
[0023] Figure 17 This is a block diagram illustrating a host storage system according to an example embodiment. Detailed Implementation
[0024] Figure 1 This is a schematic block diagram illustrating a storage system including a storage device according to an example embodiment.
[0025] Reference Figure 1 The storage system 1 may include a memory 10 and a storage controller 20. The storage system 1 may support multiple channels CH1 to CHm, and the memory 10 and the storage controller 20 may be interconnected through the multiple channels CH1 to CHm. The storage system 1 may be implemented as a storage device such as a solid-state drive (SSD).
[0026] The memory 10 may include a plurality of non-volatile memory devices NVM11 to NVMmn. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm in a corresponding manner. For example, non-volatile memory devices NVM11 to NVM1n may be connected to a first channel CH1 via paths W11 to W1n, and non-volatile memory devices NVM21 to NVM2n may be connected to a second channel CH2 via paths W21 to W2n. In an example embodiment, each of the non-volatile memory devices NVM11 to NVMmn may be implemented in any memory cell capable of operating according to individual commands from the memory controller 20. For example, each of the non-volatile memory devices NVM11 to NVMmn may be implemented as a chip or a die.
[0027] The storage controller 20 can send signals to and receive signals from the storage 10 through multiple channels CH1 to CHm. For example, the storage controller 20 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the storage 10 through channels CH1 to CHm, or receive data DATAa to DATAm from the storage 10.
[0028] The storage controller 20 can select one of the non-volatile storage devices connected to the corresponding channel through each channel, and send signals to and receive signals from the selected non-volatile storage device. For example, the storage controller 20 can select non-volatile storage device NVM11 among the non-volatile storage devices NVM11 to NVM1n connected to the first channel CH1. The storage controller 20 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile storage device NVM11 through the first channel CH1, or receive data DATAa from the selected non-volatile storage device NVM11.
[0029] The storage controller 20 can send signals to and receive signals from the memory 10 in parallel through different channels. For example, the storage controller 20 can send the command CMDb to the memory 10 through the second channel CH2, while simultaneously sending the command CMDa to the memory 10 through the first channel CH1. For example, the storage controller 20 can receive data DATAb from the memory 10 through the second channel CH2, while simultaneously receiving data DATAa from the memory 10 through the first channel CH1.
[0030] The storage controller 20 can control the general operation of the memory 10. The storage controller 20 can control each of the non-volatile storage devices NVM11 to NVM1n connected to channels CH1 to CHm by sending signals to channels CH1 to CHm. For example, the storage controller 20 can control a selected non-volatile storage device among the non-volatile storage devices NVM11 to NVM1n by sending command CMDa and address ADDRa to the first channel CH1.
[0031] Each of the non-volatile storage devices NVM11 to NVMmn can operate under the control of the storage controller 20. For example, non-volatile storage device NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided to the first channel CH1. For example, non-volatile storage device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and send the read data DATAb to the storage controller 20.
[0032] Figure 1 It has been shown that memory 10 communicates with memory controller 20 through m channels, and memory 10 includes n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to a channel can be modified in various ways.
[0033] The performance of storage system 1 can be defined as the amount of data programmed per unit time (MB / s). The amount of data programmed per unit time (MB / s) can refer to the write speed, and the write speed of storage system 1 can vary within a predetermined time. The range of variation in the write speed of storage system 1 within the predetermined time needs to be designed to meet a reference value. This reference value can be a value required by the customer. For example, the range of variation in the write speed of storage system 1 can be a value corresponding to the difference between the maximum and average write speeds, or it can be a value corresponding to the difference between the minimum and average write speeds. According to an example embodiment, the range of variation in the write speed of storage system 1 can be a value corresponding to the worst-case scenario of the difference between the maximum and average write speeds and the difference between the minimum and average write speeds, but is not limited to this.
[0034] For example, the variation in the write speed of storage system 1 can be the ratio of the difference between the maximum and minimum write speeds to the average write speed, and the reference value can be 10%.
[0035] According to an exemplary embodiment, in order to ensure that the variation range of the write speed of the storage system 1 within a predetermined time meets a reference value, the storage controller 20 can determine the programming time of each word line of each of the non-volatile storage devices NVM11 to NVMmn, and determine a target programming time based on the programming time of each word line of each of the non-volatile storage devices NVM11 to NVMmn. Each of the non-volatile storage devices NVM11 to NVMmn can adjust the programming time of each word line based on the target programming time. Therefore, by increasing the variation range of the write speed of the storage system 1 within a predetermined time to the value required by the customer, a constant quality of service can be provided to the customer.
[0036] In this example embodiment, the performance variation of storage system 1 can refer to the variation of the write speed of storage system 1.
[0037] Figure 2 This is a schematic block diagram illustrating a non-volatile storage device according to an example embodiment.
[0038] Reference Figure 2 The non-volatile storage device 30 may include control logic circuitry 32, a storage cell array 33, a page buffer unit 34, a voltage generator 35, and a row decoder 36. The non-volatile storage device 30 may also include interface circuitry 31, and may further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, a source driver, etc.
[0039] The control logic circuit 32 typically controls various operations within the non-volatile memory device 30. The control logic circuit 32 can output various control signals in response to commands CMD and / or addresses ADDR from the interface circuit 31. For example, the control logic circuit 32 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.
[0040] The storage cell array 33 may include multiple storage blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple storage blocks BLK1 to BLKz may include multiple storage cells. The storage cell array 33 may be connected to the page buffer unit 34 via the bit line BL, and may be connected to the line decoder 36 via the word line WL, the string select line SSL, and the ground select line GSL.
[0041] In an example embodiment, the memory cell array 33 may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines vertically stacked on a substrate. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an example embodiment, the memory cell array 33 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged along row and column directions.
[0042] Page buffer unit 34 may include multiple page buffers PB1 to PBn (n is an integer of 3 or greater), and the multiple page buffers PB1 to PBn may be connected to memory cells via multiple bit lines BL. Page buffer unit 34 may respond to column address Y-ADDR to select at least one bit line of the bit line BL. Page buffer unit 34 may be used as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer unit 34 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer unit 34 may sense the current or voltage of the selected bit line to sense the data stored in the memory cell.
[0043] Voltage generator 35 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 35 can generate programming voltage, reading voltage, pass voltage, programming verification voltage, erase voltage, etc. Some of the voltages generated by voltage generator 35 can be input to word line WL as word line voltage VWL by line decoder 36, while other voltages can be input to the common source line by source driver.
[0044] In response to the row address X-ADDR, the row decoder 36 can select one of multiple word lines WL and one of multiple string select lines SSL. For example, the row decoder 360 can apply a programming voltage and a programming verification voltage to the selected word line during a programming operation, and can apply a read voltage to the selected word line during a read operation.
[0045] According to an example embodiment, the non-volatile storage device 30 can receive a target programming time from the storage controller. Control logic circuitry 32 can adjust the word line programming time based on the target programming time. For example, control logic circuitry 32 can calculate the difference between the word line programming time and the target programming time, and delay the end time of the word line programming operation by this difference to adjust the word line programming time. Therefore, the variation in write speed of the storage system within a predetermined time can be increased to the value required by the customer.
[0046] Figure 3 This is a schematic circuit diagram illustrating a storage block of a non-volatile storage device according to an example embodiment.
[0047] Figure 3 The memory block BLKi shown is a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.
[0048] Reference Figure 3 The memory block BLKi may include multiple NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the multiple NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. Figure 3 The diagram shows that each of the multiple memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., MC8, but each of the multiple memory NAND strings NS11 to NS33 can vary.
[0049] The string select transistor (SST) can be connected to the corresponding string select line SSL1, SSL2, or SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8. Gate lines GTL1, GTL2, ..., GTL8 can correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select line GSL1, GSL2, or GSL3. The string select transistor SST can be connected to the corresponding bit line BL1, BL2, or BL3. The ground select transistor GST can be connected to the common source line CSL.
[0050] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1, GSL2, and GSL3 can be separated from string select lines SSL1, SSL2, and SSL3 respectively. Figure 3 The diagram shows that the memory block BLKi is connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2 and BL3, but the memory block BLKi can be varied.
[0051] As the number of word lines increases, the time required to program a memory block may increase. The performance of a storage system can be defined as the amount of data programmed per unit time (MB / s) and can be measured in units of one second. However, as the time required to program a memory block increases, the time required to program a block may become longer than the unit time. In this case, the performance variation of the storage system over a predetermined period may become larger.
[0052] According to an example embodiment, the storage system can adjust the programming time of each word line of a non-volatile storage device based on a target programming time. Therefore, the performance variation of the storage system can be increased to the value required by the customer.
[0053] Figure 4 and Figure 5 This is a schematic diagram illustrating a non-volatile storage device according to an example embodiment. Figure 5 It shows Figure 4 A perspective view of one of blocks BLK1 and BLK2 in the non-volatile storage device 100 shown.
[0054] Reference Figure 4 The non-volatile storage device 100 according to the example embodiment may include a plurality of blocks BLK1 and BLK2. The plurality of blocks BLK1 and BLK2 may have the same structure and may be separated by a separation layer 140.
[0055] Reference Figure 4 and Figure 5 The non-volatile memory device 100 according to the example embodiment may include a cell region C and a peripheral circuit region P disposed vertically on top of each other. The peripheral circuit region P may be disposed below the cell region C. The peripheral circuit region P may include a first substrate 101. The cell region C may include a second substrate 102 different from the first substrate 101.
[0056] The peripheral circuit region P may include a plurality of peripheral circuit elements 103 disposed on the first substrate 101, a plurality of wirings 105 connected to the peripheral circuit elements 103, a first interlayer insulating layer 107 covering the peripheral circuit elements 103 and the wirings 105, etc. The peripheral circuit elements 103 included in the peripheral circuit region P may provide circuitry for driving non-volatile memory devices 100 such as page buffers and line decoders.
[0057] A second substrate 102, included in cell region C, may be disposed on the first interlayer insulating layer 107. Cell region C may include a ground select line GSL, a word line WL, serial select lines SSL1 and SSL2, and a plurality of insulating layers IL stacked on the second substrate 102. The insulating layers IL may be stacked alternately with the ground select line GSL, the word line WL, and the serial select lines SSL1 and SSL2. The number of ground select lines GSL and serial select lines SSL1 and SSL2 can be determined from... Figure 5 The ones shown have been modified in various ways.
[0058] Cell region C may include channel structures CH extending in a first direction (Z-axis direction) perpendicular to the upper surface of the second substrate 102. Channel structures CH may pass through ground select line GSL, word line WL, and string select lines SSL1 and SSL2, and then connect to the second substrate 102. Each of the channel structures CH may include a channel region 110, a buried insulating layer 120 filling the internal space of the channel region 110, a bit line interconnect layer 130, etc. Each of the channel structures CH can be connected to at least one bit line via the bit line interconnect layer 130. Ground select line GSL, word line WL, string select lines SSL1 and SSL2, insulating layer IL, channel structures CH, etc., may be defined as a stacked structure.
[0059] At least one gate insulating layer may be disposed outside the channel region 110. In an example embodiment, the gate insulating layer may include a tunnel layer, a charge storage layer, a barrier layer, etc., disposed sequentially from the channel region 110. According to an example embodiment, at least one of the tunnel layer, charge storage layer, and barrier layer may also be formed around the ground select line GSL, the word line WL, and the serial select lines SSL1 and SSL2.
[0060] The ground select line GSL, word line WL, and serial select lines SSL1 and SSL2 may be covered by an interlayer insulating layer 150. The ground select line GSL, word line WL, and serial select lines SSL1 and SSL2 may be divided into multiple blocks BLK1 and BLK2 by a separator layer 140. In an example embodiment, between a pair of separator layers 140 adjacent to each other in the second direction (Y-axis direction), the serial select lines SSL1 and SSL2 may be divided into multiple regions by an upper separator layer 160.
[0061] In the example embodiment, a dummy channel structure DCH can be set in the region where the upper separation layer 160 is set. The dummy channel structure DCH can have the same structure as the channel structure CH, but can be unconnected to bit lines.
[0062] exist Figure 5 In the example embodiment shown, the channel structure CH and the separation layer 140 may have a shape in which they extend to elongate in a first direction, and therefore, the width of the channel structure CH and the separation layer 140 may vary in the first direction. The channel structure CH and the separation layer 140 may have a tapered structure whose width becomes narrower as they get closer to the second substrate 102.
[0063] Operations can be performed on a page-by-page basis to write data into or read data stored in a memory cell. Operations can also be performed to delete data written into a memory cell, on a per-page basis, within each of the memory blocks BLK1 and BLK2 separated by the separation layer 140.
[0064] The performance variation of the storage system within a predetermined time period needs to meet customer-required reference values. Storage system performance can be defined as the amount of data programmed per unit time (MB / s) and can be measured in units of one second. However, as the stack size of non-volatile storage devices increases, the time required to program a storage block may be longer than the unit time. The time required to program data per word line (hereinafter referred to as "programming time") varies, and when the time required to program a storage block is longer than the unit time, the performance variation of the storage system within a predetermined time period may become larger.
[0065] According to an example embodiment, the storage system can perform a performance flattening function to adjust the performance of the storage system by adjusting the programming time of each word line of the non-volatile storage device.
[0066] Figure 6 This is a view used to describe the magnitude of performance variations of a storage system according to an example embodiment.
[0067] Reference Figure 6The X-axis represents time (s), and the Y-axis represents data volume (MB). The performance of a storage system can be defined as the amount of data programmed per unit time (MB / s), and the performance variation of the storage system within a predetermined time period needs to meet the customer's required reference value.
[0068] Figure 7 This is a view used to describe the programming time differences of each word line in a non-volatile storage device according to an example embodiment.
[0069] Reference Figure 7 The X-axis represents different word lines (WL), and the Y-axis represents the programming time (μs). The programming time for each word line can be different. When the programming time for each word line varies significantly, it may affect the performance variation of the storage system.
[0070] Figure 8A and Figure 8B This is a view used to describe the magnitude of performance variations of a storage system according to an example embodiment.
[0071] Figure 8A This illustrates a case where programming a memory block takes less time than a unit of time.
[0072] Assuming a unit of time is 1 second, within N seconds, a portion of the 0th storage block BLK0 can be programmed, and a portion of the first storage block BLK1 can also be programmed. Within (N+1) seconds, the remaining portion of the first storage block BLK1 can be programmed, the entire second storage block BLK2 can be programmed, and a portion of the third storage block BLK3 can also be programmed.
[0073] The word line contact portions that do not overlap with each other within N seconds and (N+1) seconds (i.e., the shaded portions of the 0th storage block BLK0, the BLK1 first storage block, and the BLK3 third storage block) can be the portions that affect the magnitude of performance variation in the storage system.
[0074] Figure 8B This illustrates a case where programming a memory block takes longer than a unit of time.
[0075] Assuming a unit of time is 1 second, within N seconds, a portion of the 0th memory block BLK0 can be programmed. Within (N+1) seconds, the remaining portion of the 0th memory block BLK0 can be programmed, and a portion of the first memory block BLK1 can also be programmed.
[0076] The word line contact portions that do not overlap with each other within N seconds and (N+1) seconds (i.e., the shaded portions of the 0th storage block BLK0 and the 1st storage block BLK1) can be the portions that affect the magnitude of performance variation in the storage system.
[0077] and Figure 8A The difference lies in Figure 8B In this context, as the stacking level of non-volatile storage devices increases, the time required to program a storage block becomes longer than the unit of time, and therefore, the range of factors affecting the performance variation of the storage system may become relatively wider. Although Figure 8A and Figure 8B The programming time for each word line varies, but... Figure 8B In this context, the word lines that are touched between N seconds and (N+1) seconds are all different from each other, and therefore, the portion affecting the performance variation of the storage system becomes relatively wider. Consequently, the performance variation of the storage system may become larger.
[0078] Figure 9 This is a view used to describe the programming time differences of each word line in a non-volatile storage device according to an example embodiment.
[0079] Reference Figure 9 The storage system can adjust the programming time of each word line to the target programming time t. TARGET For example, if the programming time is longer than the target programming time, the programming time can remain unchanged, while if the programming time is shorter than the target programming time, the programming time can be delayed until the target programming time. Therefore, the programming time difference between word lines can be reduced by interval 'a'.
[0080] Figure 10 and Figure 11 This is a view used to describe the performance flattening operation according to the example embodiment.
[0081] Refer to together Figure 10 and Figure 11 The storage controller 50 can confirm the performance variation of the storage system 40 within a predetermined time period (S310). The performance of the storage system 40 can be defined as the amount of data programmed per unit time (MB / s), and the variation of the write speed of the storage system 40 within the predetermined time period needs to meet a reference value. When the performance variation of the storage system 40 within the predetermined time period is the reference value or greater ("Yes" in S320), the storage system 40 can perform a performance flattening operation to adjust the performance variation of the storage system 40 within the predetermined time period to the reference value.
[0082] The storage controller 50 can confirm the programming time tPROG (S330) for each word line of each of the non-volatile storage devices 61 and 62 included in the memory 60.
[0083] The storage controller 50 can calculate the target programming time t based on the programming time tPROG per word line. TARGET(S340). For example, assuming a reference value of 10%, the storage controller 50 can calculate the maximum programming time and the target programming time t for each word line. TARGET The average value, and calculate the target programming time t. TARGET This makes the maximum value equal to the target programming time t. TARGET The ratio of the difference to the mean satisfies (10% + α). Here, α represents the allowable error range.
[0084] When the storage controller 50 sends the target programming time t to the non-volatile storage devices 61 and 62 TARGET At that time, each of the non-volatile storage devices 61 and 62 can receive the target programming time t. TARGET The control logic of each of the non-volatile storage devices 61 and 62 can be based on the target programming time t. TARGET To adjust the programming time tPROG(S350) for each word line.
[0085] To ensure data integrity, the control logic can adjust the programming time tPROG for each word line. For example, when the programming time tPROG is longer than the target programming time t... TARGET When the programming time tPROG is shorter than the target programming time t, the programming time tPROG can be left unchanged. TARGET At that time, the programming time tPROG can be delayed until the target programming time t. TARGET Therefore, the programming time difference between word lines can be reduced.
[0086] Once the programming time adjustment for each word line is complete, the memory controller 50 can reconfirm the performance variation range of the memory system 40 within a predetermined time (S310). The performance flattening process can be repeated until the performance variation range of the memory system 40 meets a reference value. When the performance variation range of the memory system 40 is equal to or less than the reference value (S320), the memory controller 50 can adjust the target programming time t. TARGET Set the final target programming time and end the performance flattening process.
[0087] According to the example embodiment, when the number of program / erase (P / E) cycles is a reference number or more, the storage system 40 can perform performance flattening again, and the storage controller 50 can set the final target programming time again.
[0088] According to the example embodiment, when the external temperature of the storage system 40 exceeds the reference temperature range, the storage system 40 can perform performance flattening again, and the storage controller 50 can reset the final target programming time.
[0089] The performance flattening operation can be implemented as software in the central processing unit (CPU) 51 in the storage controller 50, or it can be implemented as separate hardware logic 52 in the storage controller 50.
[0090] Figure 12 This is a view illustrating commands or data exchanged between a storage controller and a non-volatile storage device according to an example embodiment.
[0091] Reference Figure 12 The storage controller (MC) can initially determine the programming time tPROG for each word line of the non-volatile storage device (NVM) to calculate the target programming time t. TARGET (S100). To confirm the programming time tPROG for each word line of the non-volatile storage device NVM, the storage controller MC can send programming commands CMD, data DATA, and address ADDR to the non-volatile storage device NVM, and receive a ready / busy signal RB from the non-volatile storage device NVM. (See reference...) Figure 13 The method for confirming the programming time tPROG for each word line by the storage controller MC is described in detail.
[0092] The storage controller MC can set and store the target programming time t. TARGET This ensures that the variation in the write speed of the storage system meets the reference value (S110). Figure 12 The method of setting the target programming time tTARGET by the storage controller MC and Figure 10 and Figure 11 The method for setting the final target programming time by the storage controller is the same, and therefore a detailed description thereof is omitted.
[0093] The target programming time tTARGET can be stored in a separate non-volatile storage device within the storage system, or it can be stored in a non-volatile storage device NVM, as described in steps S120 to S140 below. (Refer to...) Figure 14 Describe the target programming time t in detail TARGET .
[0094] When the storage system is powered on (S120), the storage controller MC can send the target programming time t to the non-volatile storage device NVM. TARGET (S130). The non-volatile storage device NVM can store the target programming time t. TARGET (S140).
[0095] The storage controller MC can send programming commands CMD, data DATA, and address ADDR to the non-volatile storage device NVM to program the data in the non-volatile storage device NVM (S150). The non-volatile storage device NVM can perform the programming operation and then confirm the programming time tPROG for each word line (S160).
[0096] Non-volatile storage devices (NVMs) can be based on the target programming time t. TARGET This adjusts the programming time tPROG for each word line. For example, when the word line's programming time tPROG is shorter than the target programming time t... TARGET When ("Yes" in S170), the non-volatile storage device (NVM) can delay the end time of the programming operation. For example, the NVM can calculate the target programming time t. TARGET The difference between the programming time tPROG of the word line and the programming time tPROG is used as the dummy programming time (dummy tPROG) (S180).
[0097] The non-volatile storage device (NVM) can delay the end time of the programming operation by dummy programming time (dummy tPROG). For example, the non-volatile storage device (NVM) can delay the ready / busy signal RB', which indicates that the non-volatile storage device (NVM) is in a ready state, by dummy programming time (dummy tPROG) and then send the ready / busy signal RB' to the storage controller MC (S190).
[0098] When the word line programming time tPROG is equal to or longer than the target programming time t TARGET When (No in S170), non-volatile memory devices (NVM) may not adjust the programming time (tPROG) for each word line.
[0099] According to an example embodiment, the non-volatile storage device NVM can be based on the target programming time t. TARGET Adjusting the programming time (tPROG) for each word line allows for a greater variation in the write speed of the storage system to meet customer requirements.
[0100] Figure 13 This is a view used to describe the method of programming the confirmation word line according to the example embodiment.
[0101] Reference Figure 13The storage controller can provide commands CMD1 and CMD2, address ADDR, and data DATA to the non-volatile storage device via input / output lines. The non-volatile storage device can provide a ready / busy signal RB to the storage controller via a ready / busy line. In an example embodiment, the commands may include commands for performing programming operations. These commands may include a set command CMD1 and a confirm command CMD2. The command to be executed by the non-volatile storage device can be determined based on the set command CMD1. The confirm command CMD2 may be a command instructing the non-volatile storage device to perform an operation. The programming command may be determined by the set command CMD1, and the non-volatile storage device can perform the programming operation via the confirm command CMD2. The storage controller may provide the address ADDR of the command determined by the set command to the non-volatile storage device after outputting the set command CMD1. The address ADDR refers to the region in which the set command CMD1 is to be executed. The address ADDR may include a row address and a column address. The non-volatile storage device can access the region selected by the address ADDR. In an example embodiment, the storage controller may provide data DATA to the non-volatile storage device after outputting the address. During the programming operation, the non-volatile storage device programs data DATA in an address-selected region. In an example embodiment, the storage controller may output an acknowledgment command CMD2 after outputting data to the non-volatile storage device. The acknowledgment command CMD2 may be a command instructing the non-volatile storage device 100 to perform an operation. The storage controller may provide the acknowledgment command CMD2 to the non-volatile storage device. The storage controller may determine the start time of the programming operation at the time t1 when the storage controller provides the acknowledgment command CMD2 to the non-volatile storage device. A ready / busy signal RB is provided from the non-volatile storage device to the storage controller via a ready / busy line. The ready / busy signal indicates whether the non-volatile storage device is in a ready state or a busy state. When the ready / busy signal is low, it indicates that the non-volatile storage device is in a busy state. When the ready / busy signal is high, it indicates that the non-volatile storage device is in a ready state. The storage controller may determine the end time of the programming operation at the time t2 when the state of the ready / busy signal changes from busy to ready. Non-volatile storage devices can perform programming operations during programming time tPROG.
[0102] Programming time can refer to the time from the start time t1 of the programming operation to the end time t2 of the programming operation.
[0103] Figure 14 This is a view showing the target programming time according to an example embodiment.
[0104] Multiple blocks of a non-volatile storage device can be grouped into multiple groups, and blocks belonging to the same group can have the same target programming time. (See reference...) Figure 14 The target programming time for the first storage block BLK1 to the hundredth storage block BLK100 can be set to the first target programming time t. TARGET 1. The target programming time for memory blocks 101 (BLK101) to 200 (BLK200) can be set to the second target programming time t. TARGET 2, and the target programming time for storage blocks k to m can be set to the target programming time t of the nth storage block. TARGET n. k equals (201 + 100 * x) (where x is an integer), m equals min(k + 99, total number of storage blocks), and n equals ceil(m / 100).
[0105] For example, the target programming time for the first word line of the first memory block can be the first target programming time t. TARGET 1. When the first programming operation time of the first word line is shorter than the first target programming time t TARGET At time 1, the non-volatile storage device can store the first programming operation time and the first target programming time t. TARGET The difference between 1 and 2 is set as the dummy programming time. Non-volatile memory devices can delay the ready / busy signal for the dummy programming time before outputting the ready / busy signal to the memory controller.
[0106] For example, the target programming time for the second word line of the 101st memory block could be the second target programming time t. TARGET 2. When the second programming operation time of the second word line is shorter than the second target programming time t TARGET At time 2, the non-volatile storage device can convert the second programming operation time and the second target programming time t TARGET The difference between 2 and 3 is set as the dummy programming time. Non-volatile memory devices can delay the ready / busy signal for the dummy programming time before outputting the ready / busy signal to the memory controller.
[0107] Figure 15 This is a view illustrating commands or data exchanged between a storage controller and a non-volatile storage device according to an example embodiment.
[0108] Reference Figure 15 The storage controller (MC) can initially determine the programming time tPROG for each word line of the non-volatile storage device (NVM) to calculate the target programming time t. TARGET(S200). In order to confirm the programming time tPROG of each word line of the non-volatile storage device NVM, the storage controller MC can send programming command CMD, data DATA and address ADDR to the non-volatile storage device NVM, and receive ready / busy signal RB from the non-volatile storage device NVM.
[0109] The storage controller MC can set and store the target programming time t. TARGET This ensures that the performance variation of the storage system meets the reference value (S210). Figure 15 The target programming time t is set by the storage controller MC. TARGET Methods and Figure 10 and Figure 11 The method for setting the final target programming time by the storage controller is the same, and therefore a detailed description thereof is omitted. Target programming time t TARGET It can be stored in a separate non-volatile storage device within the storage system. (Refer to...) Figure 16 Describe the target programming time t in detail TARGET .
[0110] The storage system can be powered on (S220), and the storage controller MC can send the target programming time t corresponding to the word line to be programmed to the non-volatile storage device NVM. TARGET (S225). The storage controller MC can send programming commands CMD, data DATA, and address ADDR to the non-volatile storage device NVM to program the data in the word line (S230). According to the example embodiment, the storage controller MC can target the programming time t TARGET The programming command CMD, data DATA, and address ADDR are sent together. The non-volatile storage device NVM can perform the programming operation and then confirm the programming time tPROG (S240) for each word line.
[0111] Non-volatile storage devices (NVMs) can be based on the target programming time t. TARGET This adjusts the programming time tPROG for each word line. For example, when the word line's programming time tPROG is shorter than the target programming time t... TARGET When ("Yes" in S250), the non-volatile storage device (NVM) can delay the end time of the programming operation. For example, the NVM can calculate the target programming time t. TARGET The difference between the programming time tPROG of the word line and the programming time tPROG is used as the dummy programming time (dummy tPROG) (S260).
[0112] The non-volatile storage device (NVM) can delay the end time of the programming operation by a virtual programming time (virtual tPROG). For example, the non-volatile storage device (NVM) can delay the ready / busy signal RB', which indicates that the non-volatile storage device is in a ready state, by a virtual programming time (virtual tPROG) and then send the ready / busy signal RB' to the storage controller MC (S270).
[0113] When the word line programming time tPROG is equal to or longer than the target programming time t TARGET When (No in S250), non-volatile memory devices (NVM) may not adjust the programming time (tPROG) for each word line.
[0114] According to an example embodiment, the non-volatile storage device NVM can be based on the target programming time t. TARGET Adjusting the programming time (tPROG) for each word line allows for a greater variation in the write speed of the storage system to meet customer requirements.
[0115] Figure 16 This is a view showing the target programming time according to an example embodiment.
[0116] The target programming time can be different for each word line. (See reference...) Figure 16 The target programming time for the first word line WL1 can be set to the first target programming time t. TARGET 1. Furthermore, the target programming time for the second word line WL2 can be set to the second target programming time t. TARGET 2, and the target programming time of the nth word line WLn can be set to the nth target programming time t. TARGET n.
[0117] For example, the target programming time suitable for the first word line of the first memory block can be the first target programming time t. TARGET 1. When the first programming operation time of the first word line is shorter than the first target programming time t TARGET At time 1, the first programming operation time and the first target programming time t TARGET The difference between 1 and 2 can be set as a dummy programming time. Non-volatile memory devices can delay the ready / busy signal for the dummy programming time before outputting the ready / busy signal to the memory controller.
[0118] For example, the target programming time for the second word line of the first memory block could be the second target programming time t. TARGET 2. When the second programming operation time of the second word line is shorter than the second target programming time t TARGET At time 2, the second programming operation time and the second target programming time t TARGETThe difference between 2 and 3 can be set as a dummy programming time. Non-volatile memory devices can delay the ready / busy signal for the dummy programming time before outputting the ready / busy signal to the memory controller.
[0119] Figure 17 This is a block diagram illustrating a host storage system according to an example embodiment.
[0120] The host storage system 500 may include a host 300 and a storage device 400. Each of the host 300 and the storage device 400 may generate and send packets according to the standard protocol adopted.
[0121] According to an example embodiment, host 300 may include host controller 310 and host memory 320. Host memory 320 may be used as a buffer memory for temporarily storing data to be sent to or from storage device 400.
[0122] Storage device 400 may include storage controller 410 and non-volatile storage device (NVM) 420. Storage device 400 may include storage media for storing data in response to requests from host 300. As an example, storage device 400 may include at least one of solid-state drive (SSD), embedded memory, and removable external memory. When storage device 400 is an SSD, it may be a device compliant with the Non-Volatile Memory Faster (NVMe) standard. When storage device 400 is embedded memory or external memory, it may be a device compliant with the Universal Flash Memory (UFS) or Embedded Multimedia Card (eMMC) standard.
[0123] When the non-volatile storage device 420 of storage device 400 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 400 may include various other types of non-volatile storage devices. For example, storage device 400 may include magnetic random access memory (MRAM), spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, and various other types of memory.
[0124] According to example embodiments, the host controller 310 and host memory 320 can be implemented as separate semiconductor chips. Alternatively, in some example embodiments, the host controller 310 and host memory 320 can be integrated on the same semiconductor chip. The host controller 310 can be any of a plurality of modules included in an application processor, and the application processor can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 320 can be embedded memory disposed within the application processor, or it can be a non-volatile storage device or memory module disposed externally to the application processor.
[0125] The host controller 310 can manage operations that store data (e.g., write data) from the host memory 320 into the non-volatile storage device 420 or that store data (e.g., read data) from the non-volatile storage device 420 into the host memory 320.
[0126] The storage controller 410 may include a host interface 411, a memory interface 412, and a central processing unit (CPU) 413. The storage controller 410 may also include a flash translation layer (FTL) 414, a packet manager 415, a buffer memory 416, an error correction code (ECC) engine 417, and an Advanced Encryption Standard (AES) engine 418. The storage controller 410 may also include working memory that loads the flash translation layer (FTL) 414, and data write and read operations on the non-volatile storage device may be controlled by the CPU 413, which executes the flash translation layer.
[0127] Host interface 411 can send packets to and receive packets from host 300. Packets sent from host 300 to host interface 411 may include commands, data to be written to non-volatile storage device 420, etc. Packets sent from host interface 411 to host 300 may include responses to commands, data to be read from non-volatile storage device 420, etc. Memory interface 412 can send data to be written to non-volatile storage device 420, or can receive data to be read from non-volatile storage device 420. This memory interface 412 can be implemented to conform to standard conventions, such as switching or opening the NAND flash interface (ONFI).
[0128] The flash translation layer 414 can perform several functions, such as address mapping, wear leveling, and garbage collection. Address mapping is the process of translating logical addresses received from the host into physical addresses used to actually store data in the non-volatile storage device 420. Wear leveling is a technique that prevents excessive degradation of specific blocks by allowing for uniform use of blocks in the non-volatile storage device 420, and can be implemented through firmware techniques, such as balancing the erase counts of physical blocks. Garbage collection is a technique used to ensure available capacity in the non-volatile storage device 420 by copying valid data from a block to a new block and then erasing the existing block.
[0129] The group manager 415 can generate groups according to the interface protocol negotiated with the host 300, or parse various information based on the groups received from the host 300.
[0130] The buffer memory 416 can temporarily store data to be written to or read from the non-volatile storage device 420. The buffer memory 416 can be located in the storage controller 410, or it can be located outside the storage controller 410.
[0131] ECC engine 417 can perform error detection and correction functions on read data read from non-volatile storage device 420. For example, ECC engine 417 can generate parity bits for write data to be written to non-volatile storage device 420, and the parity bits generated as described above can be stored in non-volatile storage device 420 along with the write data. When reading data from non-volatile storage device 420, ECC engine 417 can use the parity bits read from non-volatile storage device 420 along with the read data to correct errors in the read data and output the error-corrected read data.
[0132] The AES engine 418 can use a symmetric key algorithm to perform at least one of encryption and decryption operations on the data input to the storage controller 410.
[0133] According to an example embodiment, the storage controller 410 can set a target programming time such that the performance variation of the storage device 400 within a predetermined time meets a reference value. According to the example embodiment, the host 300 can also send the predetermined target programming time to the storage controller 410. The non-volatile storage device 420 can use the target programming time to adjust the programming time of each word line. Therefore, the performance variation of the storage device 400 can be increased to the value required by the customer.
[0134] This manual has explained and described how to determine the programming time for each word line and adjust the programming time for each word line based on the target programming time, but it is also possible to determine and adjust the programming time for each page.
[0135] According to an exemplary embodiment, the storage system can adjust the programming time of each word line to a target programming time, thereby improving the performance variation of the storage system within a predetermined time to the value required by the customer. Therefore, a constant Quality of Service (QoS) can be provided to the customer.
[0136] By summarizing and reviewing, it has been found that as the integration of storage devices increases, the number of vertically stacked storage cells tends to increase, and therefore, various methods have been considered to compensate for the differences in characteristics exhibited by multiple storage cells.
[0137] As described above, embodiments can provide a storage system that adjusts the programming time of each word line to a target programming time.
[0138] Example embodiments have been disclosed herein, and although specific terminology has been used, it is for descriptive purposes only and should be interpreted in a general descriptive sense, not for limiting purposes. In some instances, as will be appreciated by those skilled in the art upon which this application has been filed, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.
Claims
1. A storage system, comprising: A non-volatile storage device, comprising a plurality of storage blocks, each of the plurality of storage blocks comprising a plurality of storage cells connected to a plurality of word lines; as well as The storage controller determines the programming time for each word line of each of the non-volatile storage devices, and calculates a target programming time based on the programming time for each word line, wherein: Each of the non-volatile storage devices receives the target programming time from the storage controller and adjusts the programming time of each word line of the corresponding non-volatile storage device accordingly based on the target programming time. Once the programming time adjustment for each word line of the corresponding non-volatile storage device is completed, the storage controller confirms the magnitude of the change in write speed between the corresponding adjustments of the non-volatile storage devices in the storage system within a predetermined time, and when the magnitude of the change in write speed is less than a reference value, sets the target programming time as the final target programming time.
2. The storage system according to claim 1, wherein, When the number of programming / erasing P / E cycles is equal to or greater than the reference number, the memory controller sets the final target programming time again.
3. The storage system according to claim 1, wherein, When the external temperature exceeds the reference temperature range, the storage controller resets the final target programming time.
4. The storage system according to claim 1, wherein, The target programming time is different for each word line of the corresponding non-volatile memory device.
5. The storage system according to claim 1, wherein, The multiple storage blocks are divided into multiple groups, and storage blocks belonging to the same group have the same target programming time.
6. The storage system according to claim 1, wherein, The time point at which the storage controller provides an acknowledgment command to the non-volatile storage device is determined as the start time point of the programming operation, the time point at which the state of the ready / busy signal indicating that the non-volatile storage device is in a ready state changes from a busy state to a ready state is determined as the end time point of the programming operation, and the programming time is the time from the start time point of the programming operation to the end time point of the programming operation.
7. The storage system according to claim 1, wherein, When the programming time is shorter than the target programming time, the end time of the programming operation is delayed for each word line of each of the non-volatile storage devices.
8. The storage system according to claim 7, wherein, Each of the non-volatile storage devices calculates the difference between the programming time and the target programming time for each word line, and delays the end time of the programming operation by the difference.
9. The storage system according to claim 8, wherein, Each of the non-volatile storage devices delays the difference in the ready / busy signal indicating that the non-volatile storage device is in a ready state, and then sends the ready / busy signal to the storage controller.
10. The storage system according to claim 1, wherein, The variation in the write speed is a value corresponding to one of the following: the difference between the maximum write speed and the average write speed, and the difference between the minimum write speed and the average write speed.
11. A storage system, comprising: Non-volatile storage devices, including multiple word lines; as well as The storage controller sets an adjusted target programming time such that the variation in the write speed of the storage system within a predetermined time meets a reference value, wherein: The storage controller sends the initial target programming time corresponding to the word line to be programmed to the non-volatile storage device, and When the storage controller sends a programming command for the word line to the non-volatile storage device, the non-volatile storage device confirms the programming time of the word line and adjusts the initial target programming time of the word line based on the initial target programming time to form the adjusted target programming time.
12. The storage system according to claim 11, wherein, The adjusted target programming time is different for each word line.
13. The storage system according to claim 11, wherein, When the adjusted programming time of the word line is shorter than the initial target programming time, the non-volatile storage device delays the end time of the programming operation.
14. The storage system according to claim 11, wherein, The non-volatile memory device calculates the difference between the programming time and the initial target programming time for each word line, and delays the end time of the programming operation by the difference.
15. The storage system according to claim 14, wherein, The non-volatile storage device delays the difference in the ready / busy signal indicating that the non-volatile storage device is in a ready state, and then sends the ready / busy signal to the storage controller.
16. A storage system, comprising: Non-volatile storage devices, comprising multiple storage blocks; as well as The storage controller sets a target programming time such that the variation in the write speed of the storage system within a predetermined time meets a reference value, wherein: When the storage system is powered on, when the storage controller sends the target programming time to the non-volatile storage device, the non-volatile storage device stores the target programming time, and When the storage controller sends a programming command for a word line to the non-volatile storage device, the non-volatile storage device confirms the programming time of the word line and adjusts the programming time of the word line based on the target programming time.
17. The storage system according to claim 16, wherein, The multiple storage blocks are divided into multiple groups, and storage blocks belonging to the same group have the same target programming time.
18. The storage system according to claim 16, wherein, When the programming time of the word line is shorter than the target programming time, the non-volatile storage device delays the end time of the programming operation.
19. The storage system according to claim 16, wherein, The non-volatile memory device calculates the difference between the programming time and the target programming time for each word line, and delays the end time of the programming operation by the difference.
20. The storage system according to claim 19, wherein, The non-volatile storage device delays the difference in the ready / busy signal indicating that the non-volatile storage device is in a ready state, and then sends the ready / busy signal to the storage controller.