A method, system, device and medium for margin testing of a PCIE device
By accessing the central processing unit to obtain the BDF of the PCIe device, automatically performing MARGIN testing and sending back information, the problem of low testing efficiency and errors caused by manually changing serial port tools in the existing technology is solved, and efficient automated testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2022-04-25
- Publication Date
- 2026-07-24
AI Technical Summary
The current method of testing PCIe devices using MARGIN requires manual replacement of the serial port tool, which results in low testing efficiency and is prone to human error.
By accessing the central processing unit to obtain the BDF of the PCIe device, the MARGIN test is automatically performed based on the BDF, and the test information is transmitted back over the network, realizing a test process that does not require manual on-site waiting or manual replacement of serial port tools.
It improves the efficiency of MARGIN testing for PCIe devices, avoids human error, and simplifies the testing process.
Smart Images
Figure CN114816873B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of server testing technology, and in particular to a method, system, device, and medium for performing MARGIN testing on PCIe devices. Background Technology
[0002] PCIe (Peripheral Component Interconnect Express) is a common point-to-point transmission bus in various communication and storage computing facilities. It features differential full-duplex transmission, strong anti-interference capabilities, high serial output speed, clock data recovery circuitry, low requirements for data transmission synchronization, and diverse interface forms. Various interfaces and specifications have been developed around this bus standard. Physically, each PCIe lane contains a pair of TX differential lines and a pair of RX differential lines. Standard PCIe slots and PCIe devices are typically configured with x1, x4, x8, or x16 lanes.
[0003] To ensure server communication quality, MARGIN testing is frequently performed on all PCIe devices along the server's entire PCIe link. For example, the PCIe link of an AI (Artificial Intelligence) server includes: the motherboard, Retimer, Switch, and PCIe devices mounted on the Switch (e.g., graphics cards, hard drives, etc.). In addition to the PCIe devices mounted on the Switch, the CPU, Retimer, and Switch on the motherboard are also PCIe devices.
[0004] Since the CPU, Retimer, Switch, and the various PCIe devices connected to the Switch come from different manufacturers, and each manufacturer has reserved a debug serial port for each device, developers and testers need to use different serial port tools to connect to each device when performing firmware upgrades or MARGIN tests on each PCIe device. For example, if MARGIN tests need to be performed on 4 Retimers and 4 Switches in sequence, the machine needs to be disassembled after each device is tested, the serial cable needs to be unplugged from the Retimer device, and then connected to another Retimer to perform the MARGIN test again. After completing the Retimer test, a new serial port tool is used to perform MARGIN tests on different Switches.
[0005] The shortcomings of the existing testing scheme are obvious: it requires on-site personnel to wait for each PCIe device to complete its test and then manually change the serial port tool. On average, completing the test of a single PCIe x16 lane connection requires up to 20 minutes of on-site waiting and tedious machine disassembly and reassembly, resulting in a significant waste of manpower and time. Furthermore, this manual serial port changing method necessitates constantly confirming which connection is being tested, repeatedly powering on and off to enter the system or BIOS for verification. This can introduce human error, such as incorrectly recording the current test link, and severely reduces verification efficiency. Summary of the Invention
[0006] In view of this, the present invention proposes a method, system, device and medium for performing MARGIN testing on PCIe devices. It eliminates the need for testers to wait for test results, confirm the test link and manually change serial port tools to connect the PCIe devices for testing at the test site. By accessing the CPU and sending test data through the CPU, MARGIN testing of all PCIe devices on the entire link can be achieved.
[0007] To achieve the above objectives, one aspect of the present invention provides a method for performing MARGIN testing on a PCIe device, specifically including the following steps: Access the central processing unit via the network; Based on the central processing unit, obtain the BDF of all PCIe devices connected to the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information; In response to the completion of the MARGIN test on all PCIe devices, the test information is transmitted back to the local device via the network based on the central processing unit.
[0008] In some implementations, MARGIN testing is performed on each PCIe device sequentially based on BDF, including: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
[0009] In some implementations, performing a MARGIN test on each PCIe device sequentially based on BDF includes: Obtain the corresponding PCIe device to be tested according to BDF; Obtain the PCIe slot of the PCIe device to be tested, and perform MARGIN test on each channel of the PCIe slot in sequence.
[0010] In some implementations, performing a MARGIN test on each channel of the PCIe slot sequentially includes: Obtain the channel to be tested, set the trigger voltage and trigger time of the channel to be tested, and send the trigger voltage and trigger time to the channel to be tested to perform MARGIN test on the channel to be tested.
[0011] In some implementations, storing test information includes storing test information for each PCIe device based on the BDF.
[0012] In another aspect, the present invention provides a system for performing MARGIN testing on PCIe devices, comprising: An access module configured to access the central processing unit via a network; The test module is configured to obtain the BDF of all PCIe devices connected to the central processing unit based on the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information. The return module is configured to, in response to the completion of the MARGIN test for all PCIe devices, return the test information to the local device via the network based on the central processing unit.
[0013] In some implementations, the test module is further configured as follows: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
[0014] In some implementations, the test module is further configured as follows: Obtain the corresponding PCIe device to be tested according to BDF; Obtain the PCIe slot of the PCIe device to be tested, and perform MARGIN test on each channel of the PCIe slot in sequence.
[0015] In another aspect of the present invention, a computer device is provided, comprising: at least one processor; and a memory storing a computer program executable on the processor, the computer program performing the steps of the method described above when executed by the processor.
[0016] In another aspect, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method steps.
[0017] This invention has at least the following beneficial technical effects: By accessing the central processing unit (CPU), the BDF (Browser Detection Function) of all PCIe devices connected to the CPU is obtained, and MARGIN testing is performed on each PCIe device sequentially based on the BDF. After the MARGIN testing of all PCIe devices is completed, the test information is transmitted back to the local device via the network based on the CPU. This realizes MARGIN testing of all PCIe devices on the server PCIe link, eliminating the need for testers to wait for test results at the test site and manually change serial port tools to connect and test PCIe devices in the traditional MARGIN testing method, thus improving the efficiency of MARGIN testing. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a block diagram of an embodiment of the method for performing MARGIN testing on a PCIe device provided by the present invention; Figure 2 This is a system architecture diagram of an embodiment of the present invention for performing MARGIN testing on a PCIe device; Figure 3 A schematic diagram of an embodiment of the BDF distribution corresponding to a PCIe device provided by the present invention; Figure 4 This is a schematic diagram of an embodiment of the system for performing MARGIN testing on a PCIe device provided by the present invention; Figure 5 A schematic diagram of the structure of an embodiment of the computer device provided by the present invention; Figure 6 This is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.
[0021] To better understand the embodiments of the present invention, some related terms involved in the present invention will be explained below.
[0022] A retimer (a hybrid digital-analog signal device) extracts the embedded clock from the input signal using its internal Clock and Data Recovery (CDR) circuit, and then retransmits the data using the complete, undamaged clock signal to create a new copy of the original data signal. In addition to the CTLE and wideband gain node also present in the redriver, the retimer chip includes the aforementioned CDR circuit, a Decision Feedback Equalizer (DFE), and a Finite Impulse Response (FIR) driver for the transmission signal (Tx). It typically uses finite state machines (FSMs) or a microcontroller to automatically adapt the CTLE, wideband gain node, DFE, and FIR driver, implementing PCIe LTSSM (Link Training and Status State Machine) functionality. This retimer's method of recovering data first and then retransmitting the signal through the serial channel effectively solves the signal attenuation problem.
[0023] Switch: A device that reuses PCIe bandwidth based on the store-and-forward principle. It can expand the PCIe bus bandwidth and enable multiple PCIe devices to be online at the same time.
[0024] MARGIN test: The values of the link trigger voltage and trigger time for various PCIe End Points at a certain bit error rate. If these values are lower than the MASK value defined by the device, it may lead to a high bit error rate, causing the link to malfunction.
[0025] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.
[0026] Based on the above objectives, a first aspect of the present invention provides an embodiment of a method for performing MARGIN testing on a PCIe device. For example... Figure 1 As shown, it includes the following steps: S101, Accessing the central processing unit via the network; S103. Obtain the BDF of all PCIe devices connected to the central processing unit based on the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information. S105. In response to the completion of the MARGIN test for all PCIe devices, the test information is transmitted back to the local device via the network based on the central processing unit.
[0027] In step S101, the network card is mounted on the motherboard to provide network access for the central processing unit (CPU) on the motherboard, enabling remote terminal devices to access the CPU through the network and send test data to the CPU for MARGIN testing. In step S103, BDF (Bus Number, Device Number, Function Number) refers to the bus number, device number, and function number, such as... Figure 3 The diagram shows the distribution of BDFs corresponding to all PCIe devices in the server's PCIe link.
[0028] Each PCIe device can have only one function (Fun0) or up to eight functions (Fun0 to Fun8), making it a multi-function device. Even if a device has multiple functions, each function has a unique and independent configuration space. Each function in the PCIe bus has a unique identifier (BDF) (Bus Number, Device Number, Function Number). The PCIe bus topology logic is identified by the PCIe bus configuration software (i.e., the root application layer, typically the PC), including each bus, each device, and each function. In the BDF, BusNumber occupies 8 bits, Device Number occupies 5 bits, and Function Number occupies 3 bits. Therefore, the PCIe bus can support a maximum of 256 sub-buses, each sub-bus can support a maximum of 32 devices, and each device can support a maximum of eight functions. The PCIe bus uses a depth-first search topology algorithm, and Bus0 is always assigned to the Root Complex. The root contains an integrated end point and multiple ports. Each port has a virtual PCI-to-PCI bridge (P2P), and this bridge also has a device number and a function number. It's important to note that each device must have function 0 (Fun0); the other seven functions (Fun1~Fun7) are optional. Figure 3 As can be seen, the CPU can obtain the BDF of all PCIe devices on the PCIe link.
[0029] By accessing the central processing unit (CPU), the BDF (Browser Definition) of each PCIe device connected to the CPU is obtained. Then, on a remote terminal, a MARGIN test is performed on the PCIe device corresponding to the BDF.
[0030] In step S105, after the MARGIN test of all PCIe devices is completed, the remote terminal sends a command to the central processing unit (CPU) to send back the test information via the network. The CPU then sends the test information back to the local device, i.e., the remote terminal.
[0031] In this embodiment, by accessing the central processing unit (CPU), the BDF (Browser Detection Function) of all PCIe devices connected to the CPU is obtained. Based on the BDF, a MARGIN test is performed on each PCIe device sequentially. After the MARGIN test of all PCIe devices is completed, the test information is transmitted back to the local device via the network based on the CPU. This realizes the MARGIN test of all PCIe devices on the server's PCIe link, eliminating the need for testers to wait for test results at the test site and manually change serial port tools to connect the tested PCIe devices, which is required in traditional MARGIN test methods. This improves the efficiency of MARGIN test.
[0032] In some implementations, MARGIN testing is performed on each PCIe device sequentially based on BDF, including: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
[0033] like Figure 2 The diagram shown is a system architecture diagram for performing MARGIN testing on PCIe devices provided by this invention.
[0034] The system includes: a remote terminal, a network card and CPU mounted on the motherboard, a Retimer connected to the motherboard, a Switch connected to the Retimer, and multiple PCIe devices connected to the Switch.
[0035] Since the Switch is not housed in the same server chassis as the motherboard, but rather in a separate chassis far from the CPU, the Retimer card is inserted into the motherboard's PCIe slot to relay the PCIe signal. The Retimer and Switch are connected via a low-loss, high-speed cable to ensure signal quality.
[0036] Various PCIe devices are mounted under the Switch, such as graphics cards, network cards, hard drives, etc. The CPU, Retimer, and Switch mentioned above are also PCIe devices. Each PCIe device has its own BDF (Bus Number, Device Number, Function Number).
[0037] The corresponding device to be tested, such as a Retimer, is obtained through BDF on the remote terminal.
[0038] During testing, MARGIN tests are performed separately between the Retimer and the CPU, and between the Retimer and the Switch. Assuming the current test is between the Retimer and the CPU, the remote terminal sends remote commands to the CPU based on the Retimer's BDF (Browser Defender). These commands include the BDF of the device under test, test data, trigger voltage, and trigger time. The CPU configures the corresponding registers according to the remote commands to perform the MARGIN test on the Retimer, thus enabling the MARGIN test between the Retimer (receiver) and the CPU (sender). The specific process is as follows: When two PCIe devices enter a loopback state, the receiver first sends data to the sender's Rx (receiver). Then, the sender's Tx (sender) forwards the data back to the receiver's Rx (receiver) without modification. If no error occurs at this point, the receiver will continue to change its trigger voltage and trigger position until a data transmission error occurs. The test information is then recorded and saved to the server's hard drive.
[0039] In this embodiment, the trigger voltage and trigger time of the PCIe device under test are set based on BDF (Browser Detection Function). The trigger voltage and trigger time are then sent to the PCIe device under test according to BDF via the central processing unit for MARGIN testing. This enables MARGIN testing of all PCIe devices on the server's PCIe link, eliminating the need for testers to wait for test results on-site and manually change serial port tools to connect the PCIe devices in traditional MARGIN testing methods, thus improving the efficiency of MARGIN testing.
[0040] In some implementations, performing a MARGIN test on each PCIe device sequentially based on BDF includes: Obtain the corresponding PCIe device to be tested according to BDF; Obtain the PCIe slot of the PCIe device to be tested, and perform MARGIN test on each channel of the PCIe slot in sequence.
[0041] Specifically, PCIe slots for PCIe devices include X1 lanes and XN lanes (where N represents the number of lanes).
[0042] For PCIe devices with X1 lane, this lane is a normal communication lane when the PCIe device is in normal use, and it only enters test mode during MARGIN testing.
[0043] After configuring the lane on the remote terminal to enter debug mode via the network card, access the PCIe device through the lane to perform a MARGIN test on this lane of the PCIe device.
[0044] For PCIe devices with XN lanes, perform MARGIN tests on X1 to XN lanes of the PCIe device sequentially using the method described above.
[0045] In this embodiment, the corresponding PCIe device to be tested is obtained according to the BDF; the PCIe slot of the PCIe device to be tested is obtained; and MARGIN testing is performed on each channel of the PCIe slot in sequence. This realizes MARGIN testing on all channels of all PCIe devices on the server PCIe link. It eliminates the need for testers to wait for test results, confirm the test channel of the test device, and manually change the serial port tool to connect the PCIe device to the test in the traditional MARGIN testing method. This improves the efficiency of MARGIN testing and avoids the problem of errors caused by manual recording.
[0046] In some implementations, performing a MARGIN test on each channel of the PCIe slot sequentially includes: Obtain the channel to be tested, set the trigger voltage and trigger time of the channel to be tested, and send the trigger voltage and trigger time to the channel to be tested to perform MARGIN test on the channel to be tested.
[0047] In some implementations, storing test information includes storing test information for each PCIe device based on the BDF.
[0048] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 4 As shown, embodiments of the present invention also provide a system for performing MARGIN testing on PCIe devices, comprising: Access module 110, configured to access central processing unit via network; Test module 120 is configured to obtain the BDF of all PCIe devices connected to the central processing unit based on the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information. The return module 130 is configured to, in response to the completion of the MARGIN test for all PCIe devices, return the test information to the local device via the network based on the central processing unit.
[0049] In this embodiment, by accessing the central processing unit (CPU), the BDF (Browser Detection Function) of all PCIe devices connected to the CPU is obtained. Based on the BDF, a MARGIN test is performed on each PCIe device sequentially. After the MARGIN test of all PCIe devices is completed, the test information is transmitted back to the local device via the network based on the CPU. This realizes the MARGIN test of all PCIe devices on the server's PCIe link, eliminating the need for testers to wait for test results at the test site and manually change serial port tools to connect the tested PCIe devices, which is required in traditional MARGIN test methods. This improves the efficiency of MARGIN test.
[0050] In some embodiments, the test module 120 is further configured to: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
[0051] In this embodiment, the trigger voltage and trigger time of the PCIe device under test are set based on BDF (Browser Detection Function). The trigger voltage and trigger time are then sent to the PCIe device under test according to BDF via the central processing unit for MARGIN testing. This enables MARGIN testing of all PCIe devices on the server's PCIe link, eliminating the need for testers to wait for test results on-site and manually change serial port tools to connect the PCIe devices in traditional MARGIN testing methods, thus improving the efficiency of MARGIN testing.
[0052] In some embodiments, the test module 120 is further configured to: Obtain the corresponding PCIe device to be tested according to BDF; Obtain the PCIe slot of the PCIe device to be tested, and perform MARGIN test on each channel of the PCIe slot in sequence.
[0053] In this embodiment, the corresponding PCIe device to be tested is obtained according to the BDF; the PCIe slot of the PCIe device to be tested is obtained; and MARGIN testing is performed on each channel of the PCIe slot in sequence. This realizes MARGIN testing on all channels of all PCIe devices on the server PCIe link. It eliminates the need for testers to wait for test results, confirm the test channel of the test device, and manually change the serial port tool to connect the PCIe device to the test in the traditional MARGIN testing method. This improves the efficiency of MARGIN testing and avoids the problem of errors caused by manual recording.
[0054] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 5 As shown, an embodiment of the present invention also provides a computer device 30, which includes a processor 310 and a memory 320. The memory 320 stores a computer program 321 that can be run on the processor. When the processor 310 executes the program, it performs the following steps: Access the central processing unit via network; Based on the central processing unit, obtain the BDF of all PCIe devices connected to the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information; In response to the completion of the MARGIN test on all PCIe devices, the test information is transmitted back to the local device via the network based on the central processing unit.
[0055] In some implementations, MARGIN testing is performed on each PCIe device sequentially based on BDF, including: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
[0056] In some implementations, performing a MARGIN test on each PCIe device sequentially based on BDF includes: Obtain the corresponding PCIe device to be tested according to BDF; Obtain the PCIe slot of the PCIe device to be tested, and perform MARGIN test on each channel of the PCIe slot in sequence.
[0057] In some implementations, performing a MARGIN test on each channel of the PCIe slot sequentially includes: Obtain the channel to be tested, set the trigger voltage and trigger time of the channel to be tested, and send the trigger voltage and trigger time to the channel to be tested to perform MARGIN test on the channel to be tested.
[0058] In some implementations, storing test information includes storing test information for each PCIe device based on the BDF.
[0059] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 6 As shown, embodiments of the present invention also provide a computer-readable storage medium 40, which stores a computer program 410 that, when executed by a processor, performs the methods described above.
[0060] Embodiments of the present invention may further include a corresponding computer device. The computer device includes a memory, at least one processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it performs any of the following methods: Access the central processing unit via network; Based on the central processing unit, obtain the BDF of all PCIe devices connected to the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information; In response to the completion of the MARGIN test on all PCIe devices, the test information is transmitted back to the local device via the network based on the central processing unit.
[0061] In some implementations, MARGIN testing is performed on each PCIe device sequentially based on BDF, including: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
[0062] In some implementations, performing a MARGIN test on each PCIe device sequentially based on BDF includes: Obtain the corresponding PCIe device to be tested according to BDF; Obtain the PCIe slot of the PCIe device to be tested, and perform MARGIN test on each channel of the PCIe slot in sequence.
[0063] In some implementations, performing a MARGIN test on each channel of the PCIe slot sequentially includes: Obtain the channel to be tested, set the trigger voltage and trigger time of the channel to be tested, and send the trigger voltage and trigger time to the channel to be tested to perform MARGIN test on the channel to be tested.
[0064] In some implementations, storing test information includes storing test information for each PCIe device based on the BDF.
[0065] In this embodiment of the invention, the memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods described in the embodiments of this application. The processor executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in the memory, thereby implementing the methods of the above-described method embodiments.
[0066] The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the device, etc. Furthermore, the memory may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
[0067] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium for the program can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The above computer program embodiments can achieve the same or similar effects as any of the corresponding foregoing method embodiments.
[0068] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.
[0069] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. The sequence numbers of the disclosed embodiments of this invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.
[0070] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.
[0071] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.
Claims
1. A method for performing MARGIN testing on a PCIe device, characterized in that, include: Access the central processing unit via the network; Based on the central processing unit, obtain the BDF of all PCIe devices connected to the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information; The step of performing MARGIN testing on each PCIe device sequentially based on BDF includes: obtaining the corresponding PCIe device to be tested according to BDF; obtaining the PCIe slot of the PCIe device to be tested, and performing MARGIN testing on each channel of the PCIe slot sequentially; wherein, each channel of the PCIe slot of the PCIe device enters test mode when performing MARGIN testing, and is in normal communication state during normal use. In response to the completion of the MARGIN test on all PCIe devices, the test information is transmitted back to the local device via the network based on the central processing unit.
2. The method according to claim 1, characterized in that, Based on BDF, perform MARGIN tests on each PCIe device sequentially, including: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
3. The method according to claim 1, characterized in that, Performing a MARGIN test on each lane of the PCIe slot sequentially includes: Obtain the channel to be tested, set the trigger voltage and trigger time of the channel to be tested, and send the trigger voltage and trigger time to the channel to be tested to perform MARGIN test on the channel to be tested.
4. The method according to claim 1, characterized in that, Saving test information includes: saving test information for each PCIe device based on BDF.
5. A system for performing MARGIN testing on PCIe devices, characterized in that, include: An access module configured to access the central processing unit via a network; The test module is configured to obtain the BDF of all PCIe devices connected to the central processing unit based on the central processing unit, perform MARGIN test on each PCIe device in sequence based on the BDF, and save the test information. The step of performing MARGIN testing on each PCIe device sequentially based on BDF includes: obtaining the corresponding PCIe device to be tested according to BDF; obtaining the PCIe slot of the PCIe device to be tested, and performing MARGIN testing on each channel of the PCIe slot sequentially; wherein, each channel of the PCIe slot of the PCIe device enters test mode when performing MARGIN testing, and is in normal communication state during normal use. The return module is configured to, in response to the completion of the MARGIN test for all PCIe devices, return the test information to the local device via the network based on the central processing unit.
6. The system according to claim 5, characterized in that, The test module is further configured as follows: The test PCIe device is acquired using BDF, and the trigger voltage and trigger time of the test PCIe device are set. The central processing unit sends the trigger voltage and trigger time to the PCIe device under test according to the BDF to perform MARGIN testing.
7. A computer device, comprising: At least one processor; as well as A memory storing a computer program executable on the processor, characterized in that the processor executes the program and performs the steps of the method as described in any one of claims 1 to 4.
8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1 to 4.