Receive circuit of a deserializer

Abstract

A receiver circuit of a deserializer is disclosed. The receiver circuit of the deserializer receives an input signal and includes a signal receiving terminal to receive the input signal, a link equalizer having a first input terminal coupled to the signal receiving terminal, an out-of-band signaling circuit having a second input terminal coupled to the signal receiving terminal, a first resistor coupled between the signal receiving terminal and a first reference voltage, a second resistor coupled between the signal receiving terminal and a second reference voltage, and a buffer circuit having a third input terminal to receive a voltage and an output terminal coupled to the link equalizer or the out-of-band signaling circuit. The first input terminal of the link equalizer and the second input terminal of the out-of-band signaling circuit are not electrically connected, and the voltage is adjustable.

Description

TECHNICAL FIELD

[0001] The present application relates to a signal transmission circuit, in particular, a circuit for a receiver of a serializer / deserializer (SerDes). BACKGROUND

[0002] A link equalizer (LEQ) and an out-of-band signaling (OOBS) circuit are commonly found in a receiver of a serializer / deserializer. The link equalizer is used to equalize the signal received by the receiver so as to compensate for the high frequency attenuation of the signal as much as possible. The out-of-band signaling circuit is used to detect the amplitude of the signal and control the power of the signal. The detailed circuit and working principle of the link equalizer and the out-of-band signaling circuit are well known to those skilled in the art, and thus will not be described herein.

[0003] However, the receiver of the conventional serializer / deserializer establishes a common mode voltage (common mode voltage) by a resistive voltage divider and the link equalizer and the out-of-band signaling circuit, which is easy to cause load stacking and thus attenuate high-speed data. Therefore, designing a high-performance receiver circuit for a serializer / deserializer becomes a severe challenge in high-speed circuit design. SUMMARY

[0004] In view of the deficiencies of the prior art, one object of the present application is to provide a receiver circuit for a deserializer to solve the problems encountered in the prior art.

[0005] The present application discloses a receiver circuit for a deserializer, which receives an input signal, comprising: a signal receiving end for receiving the input signal; a link equalizer having a first input end coupled to the signal receiving end; an out-of-band signaling circuit having a second input end coupled to the signal receiving end; a first resistor coupled between the signal receiving end and a first reference voltage; a second resistor coupled between the signal receiving end and a second reference voltage; and a buffer circuit having a third input end and an output end, wherein the third input end receives a voltage, and the output end is coupled to the link equalizer or the out-of-band signaling circuit. The first input end of the link equalizer and the second input end of the out-of-band signaling circuit are not electrically connected, and the voltage is adjustable.

[0006] The application also discloses a receiving circuit of a deserializer, which receives an input signal and comprises a signal receiving end for receiving the input signal, a link equalizer having a first input end coupled to the signal receiving end, an out-of-band signal transmitting circuit having a second input end coupled to the signal receiving end, a first capacitor having a first end coupled to the signal receiving end and a second end coupled to the link equalizer or the out-of-band signal transmitting circuit, a second capacitor having a third end coupled to the signal receiving end and a fourth end coupled to the link equalizer or the out-of-band signal transmitting circuit, a first resistor having a fifth end coupled to a first reference voltage and a sixth end electrically connected to the signal receiving end, a second resistor having a seventh end coupled to a second reference voltage and an eighth end electrically connected to the link equalizer or the out-of-band signal transmitting circuit, and a buffer circuit having a third input end receiving a voltage and an output end coupled to the link equalizer or the out-of-band signal transmitting circuit. The first input end of the link equalizer and the second input end of the out-of-band signal transmitting circuit are not electrically connected, and the voltage is adjustable.

[0007] The features, implementations and effects of the application will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 Circuit diagram of an embodiment of the receiving circuit of the deserializer of the application;

[0009] Figure 2 Circuit diagram of another embodiment of the receiving circuit of the deserializer of the application;

[0010] Figure 3 Circuit diagram of another embodiment of the receiving circuit of the deserializer of the application;

[0011] Figure 4 Circuit diagram of another embodiment of the receiving circuit of the deserializer of the application;

[0012] Figure 5 Circuit diagram of another embodiment of the receiving circuit of the deserializer of the application;

[0013] Figure 6 Circuit diagram of another embodiment of the receiving circuit of the deserializer of the application;

[0014] Figure 7 Circuit diagram of another embodiment of the receiving circuit of the deserializer of the application;

[0015] Figure 8 Circuit diagram of another embodiment of the receiving circuit of the deserializer of the application;

[0016] Figure 9 Circuit diagram of another embodiment of a receiving circuit of a deserializer of the present invention; and

[0017] Figure 10 Circuit diagram of another embodiment of a receiving circuit of a deserializer of the present invention. DETAILED DESCRIPTION

[0018] The following description of background art is provided for technical use only.

[0019] The present disclosure includes a receiving circuit of a deserializer. Since the components included in the receiving circuit of the deserializer of the present invention can be known components individually, the following description will omit the details of the known components without affecting the sufficient disclosure and the implementability of the apparatus invention.

[0020] Figure 1 Circuit diagram of an embodiment of a receiving circuit of a deserializer of the present invention. The receiving circuit 100 includes a signal receiving terminal 110, a resistor 120, a resistor 130, a buffer circuit 140, a link equalizer 150, and an out-of-band signal transmitting circuit 160. The receiving circuit 100 is a DC-coupled receiving circuit.

[0021] An input signal Vin is inputted to the receiving circuit 100 by the signal receiving terminal 110 (i.e., the signal receiving terminal 110 receives the input signal Vin). The resistor 120 is coupled between a first reference voltage (e.g., a power supply voltage VDD) and the signal receiving terminal 110. The resistor 130 is a variable resistor coupled between the signal receiving terminal 110 and a second reference voltage (e.g., a ground level). The link equalizer 150 is electrically connected to the signal receiving terminal 110; in other words, the resistor 120 is coupled between the first reference voltage and an input terminal of the link equalizer 150, and the resistor 130 is coupled between the input terminal of the link equalizer 150 and the second reference voltage. The buffer circuit 140 is coupled between the resistor 130 and the out-of-band signal transmitting circuit 160; more specifically, an input terminal of the buffer circuit 140 is electrically connected to the resistor 130, and an output terminal of the buffer circuit 140 is electrically connected to an input terminal of the out-of-band signal transmitting circuit 160.

[0022] The input terminal of the buffer circuit 140 receives a voltage Vb, which is a voltage divided on the resistor 130. In other words, the voltage Vb can be changed by adjusting the resistance value of the resistor 130. Adjusting the voltage Vb is equivalent to adjusting the common-mode voltage of the out-of-band signal transmitting circuit 160.

[0023] In some embodiments, the voltage Vb is less than the voltage of the input terminal of the link equalizer 150.

[0024] In Figure 1 In an embodiment, the buffer circuit 140 is implemented by a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) (hereinafter referred to as PMOS) source follower circuit. The buffer circuit 140 includes a current source 142 and a PMOS 144. The gate of the PMOS 144 (i.e., the input of the buffer circuit 140) receives the voltage Vb, the source of the PMOS 144 (i.e., the output of the buffer circuit 140) is coupled to the first reference voltage through the current source 142, and the drain of the PMOS 144 is electrically connected to the second reference voltage. The operation principle of the source follower circuit is well known to those skilled in the art, and thus is not described herein.

[0025] One of the purposes of the buffer circuit 140 is to isolate the link equalizer 150 and the out-of-band signal transmitting circuit 160, so that the input of the link equalizer 150 and the input of the out-of-band signal transmitting circuit 160 are not electrically connected to each other. In this way, the common-mode voltage of the link equalizer 150 and the common-mode voltage of the out-of-band signal transmitting circuit 160 can be independently adjusted.

[0026] Another purpose of the buffer circuit 140 is to reduce the load seen by the out-of-band signal transmitting circuit 160, so that the data transmission rate of the receiver circuit 100 can be improved.

[0027] Figure 2 A circuit diagram of another embodiment of the receiver circuit of the present application. The receiver circuit 200 is similar to the receiver circuit 100, except that the link equalizer 150 and the out-of-band signal transmitting circuit 160 are exchanged. The receiver circuit 200 is a direct-coupled receiver circuit. In Figure 2 In an embodiment, the buffer circuit 140 can reduce the load seen by the link equalizer 150, and the common-mode voltage of the link equalizer 150 and the common-mode voltage of the out-of-band signal transmitting circuit 160 can be independently adjusted. Adjusting the voltage Vb is equivalent to adjusting the common-mode voltage of the link equalizer 150.

[0028] In some embodiments, the voltage Vb is less than the voltage at the input of the out-of-band signal transmitting circuit 160.

[0029] Figure 3FIG. 4 is a circuit diagram of another embodiment of a receiving circuit of a deserializer of the present application. Receiving circuit 400 is similar to receiving circuit 300, except that link equalizer 150 and out-of-band signaling circuit 160 are swapped. Receiving circuit 400 is a DC-coupled receiving circuit. In some embodiments, receiving circuit 400 is a DC-coupled receiving circuit that is capable of receiving a differential input signal.

[0030] Capacitor 370 is coupled between signal receiving terminal 110 and input of link equalizer 150. More specifically, one end of capacitor 370 is electrically connected to signal receiving terminal 110, and the other end of capacitor 370 is electrically connected to the input of link equalizer 150. Resistor 380 is connected in parallel with capacitor 370. The input of buffer circuit 140 is electrically connected to resistor 380. One of the purposes of capacitor 370 and resistor 380 is to create a peaking gain at the high frequencies of input signal Vin, which can compensate for the loss of input signal Vin at high frequencies.

[0031] The input of buffer circuit 140 receives voltage Vb, which is the voltage across resistor 380. In other words, voltage Vb can be changed by adjusting the resistance of resistor 380.

[0032] In some embodiments, voltage Vb is less than the voltage at the input of link equalizer 150.

[0033] Figure 4 FIG. 4 is a circuit diagram of another embodiment of a receiving circuit of a deserializer of the present application. Receiving circuit 400 is similar to receiving circuit 300, except that link equalizer 150 and out-of-band signaling circuit 160 are swapped. Receiving circuit 400 is a DC-coupled receiving circuit. In some embodiments, receiving circuit 400 is a DC-coupled receiving circuit that is capable of receiving a differential input signal. Figure 4 In some embodiments, buffer circuit 140 can reduce the load seen by link equalizer 150, and the common mode voltage of link equalizer 150 and the common mode voltage of out-of-band signaling circuit 160 can be adjusted independently.

[0034] In some embodiments, voltage Vb is less than the voltage at the input of link equalizer 150.

[0035] Figure 5 FIG. 4 is a circuit diagram of another embodiment of a receiving circuit of a deserializer of the present application. Receiving circuit 400 is similar to receiving circuit 300, except that link equalizer 150 and out-of-band signaling circuit 160 are swapped. Receiving circuit 400 is a DC-coupled receiving circuit. In some embodiments, receiving circuit 400 is a DC-coupled receiving circuit that is capable of receiving a differential input signal.

[0036] The input signal Vin is inputted to the receiving circuit 500 by the signal receiving terminal 510 (i.e., the signal receiving terminal 510 receives the input signal Vin). The resistor 520 is a variable resistor coupled between the first reference voltage and the signal receiving terminal 510. The resistor 530 is coupled between the signal receiving terminal 510 and the second reference voltage. The link equalizer 150 is electrically connected to the signal receiving terminal 510; in other words, the resistor 520 is coupled between the first reference voltage and the input terminal of the link equalizer 150, and the resistor 530 is coupled between the input terminal of the link equalizer 150 and the second reference voltage. The buffer circuit 540 is coupled between the resistor 520 and the out-of-band signal transmitting circuit 160; more specifically, the input terminal of the buffer circuit 540 is electrically connected to the resistor 520, and the output terminal of the buffer circuit 540 is electrically connected to the input terminal of the out-of-band signal transmitting circuit 160.

[0037] The input terminal of the buffer circuit 540 receives the voltage Vb, which is the voltage divided on the resistor 520. In other words, the voltage Vb can be changed by adjusting the resistance value of the resistor 520. Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the out-of-band signal transmitting circuit 160.

[0038] In some embodiments, the voltage Vb is greater than the voltage of the input terminal of the link equalizer 150.

[0039] In some embodiments, the voltage Vb is less than the voltage of the input terminal of the link equalizer 150. Figure 5 In some embodiments, the buffer circuit 540 is implemented by an N-type metal-oxide-semiconductor field-effect transistor (NMOS hereinafter) source follower circuit. The buffer circuit 540 includes a current source 542 and an NMOS 544. The gate of the NMOS 544 (i.e., the input terminal of the buffer circuit 540) receives the voltage Vb, the source of the NMOS 544 (i.e., the output terminal of the buffer circuit 540) is coupled to the second reference voltage through the current source 542, and the drain of the NMOS 544 is electrically connected to the first reference voltage. The operation principle of the source follower circuit is well known to those skilled in the art, and thus is not described herein.

[0040] The purpose of the buffer circuit 540 is similar to that of the buffer circuit 140, and thus is not described herein.

[0041] Figure 6 A circuit diagram of another embodiment of the receiving circuit of the de-serializer of the present application. The receiving circuit 600 is similar to the receiving circuit 500, except that the link equalizer 150 and the out-of-band signal transmitting circuit 160 are exchanged. The receiving circuit 600 is a DC-coupled receiving circuit. In Figure 6 In some embodiments, the buffer circuit 540 can reduce the load seen by the link equalizer 150, and the common mode voltage of the link equalizer 150 and the common mode voltage of the out-of-band signal transmitting circuit 160 can be adjusted independently. Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the link equalizer 150.

[0042] In some embodiments, the voltage Vb is greater than the voltage at the input of the out-of-band signaling circuit 160.

[0043] Figure 7 A circuit diagram of another embodiment of a receiving circuit of a deserializer of the present application. The receiving circuit 700 includes the signal receiving terminal 510, a resistor 720, the resistor 530, the buffer circuit 540, the link equalizer 150, the out-of-band signaling circuit 160, a capacitor 770, and a resistor 780. The receiving circuit 700 is a DC-coupled receiving circuit. The receiving circuit 700 is similar to the receiving circuit 500, except that the receiving circuit 700 further includes the capacitor 770 and the resistor 780. The resistor 780 is a variable resistor. The resistor 720 functions the same as the resistor 520, but the resistor 720 can not be a variable resistor.

[0044] The capacitor 770 is coupled between the signal receiving terminal 510 and the link equalizer 150. More specifically, one end of the capacitor 770 is electrically connected to the signal receiving terminal 510, and the other end of the capacitor 770 is electrically connected to the input of the link equalizer 150. The resistor 780 is connected in parallel with the capacitor 770. The input of the buffer circuit 540 is electrically connected to the resistor 780. One of the purposes of the capacitor 770 and the resistor 780 is to create a peaking gain at the high frequency of the input signal Vin, which can compensate for the loss of the input signal Vin at the high frequency.

[0045] The input of the buffer circuit 540 receives a voltage Vb, which is a voltage divided across the resistor 780. In other words, the voltage Vb can be changed by adjusting the resistance of the resistor 780.

[0046] In some embodiments, the voltage Vb is greater than the voltage at the input of the out-of-band signaling circuit 160.

[0047] Figure 8 A circuit diagram of another embodiment of a receiving circuit of a deserializer of the present application. The receiving circuit 800 is similar to the receiving circuit 700, except that the link equalizer 150 and the out-of-band signaling circuit 160 are swapped. The receiving circuit 800 is a DC-coupled receiving circuit. In Figure 8 In this embodiment, the buffer circuit 540 can reduce the load seen by the link equalizer 150, and the common mode voltage of the link equalizer 150 and the common mode voltage of the out-of-band signaling circuit 160 can be adjusted independently.

[0048] In some embodiments, the voltage Vb is greater than the voltage at the input of the out-of-band signaling circuit 160.

[0049] Figure 9FIG. 9 is a circuit diagram of another embodiment of the receiving circuit of the de-serializer of the present application. The receiving circuit 900 includes a signal receiving terminal 910, a resistor 920, a resistor 930, a buffer circuit 140, a capacitor 970, a capacitor 980, a link equalizer 150, and an out-of-band signaling circuit 160. The receiving circuit 900 is an AC-coupled receiving circuit.

[0050] An input signal Vin is input to the receiving circuit 900 by the signal receiving terminal 910 (i.e., the signal receiving terminal 910 receives the input signal Vin). The resistor 920 is coupled between a first reference voltage and the signal receiving terminal 910. The resistor 930 is a variable resistor, and is coupled between an input of the link equalizer 150 and a bias voltage Vbias. The capacitor 970 is coupled between the signal receiving terminal 910 and the link equalizer 150; more specifically, one end of the capacitor 970 is electrically connected to the signal receiving terminal 910, and the other end of the capacitor 970 is electrically connected to the link equalizer 150 and the resistor 930. The capacitor 980 is coupled between the signal receiving terminal 910 and the buffer circuit 140; more specifically, one end of the capacitor 980 is electrically connected to the signal receiving terminal 910, and the other end of the capacitor 980 is electrically connected to an input of the buffer circuit 140. The bias voltage Vbias can be a voltage generated by dividing a power supply voltage VDD. The buffer circuit 140 is coupled between the resistor 930 and the out-of-band signaling circuit 160; more specifically, an input of the buffer circuit 140 is electrically connected to the resistor 930, and an output of the buffer circuit 140 is electrically connected to an input of the out-of-band signaling circuit 160.

[0051] The input of the buffer circuit 140 receives a voltage Vb, which is a voltage divided across the resistor 930. In other words, the voltage Vb can be changed by adjusting the resistance of the resistor 930. Adjusting the voltage Vb is equivalent to adjusting the common mode voltage of the out-of-band signaling circuit 160.

[0052] In some embodiments, the voltage Vb is greater than the voltage at the input of the link equalizer 150.

[0053] One of the purposes of the buffer circuit 140 is to isolate the link equalizer 150 and the out-of-band signaling circuit 160, such that the input of the link equalizer 150 and the input of the out-of-band signaling circuit 160 are not electrically connected to each other. In this way, the common mode voltage of the link equalizer 150 and the common mode voltage of the out-of-band signaling circuit 160 can be adjusted independently.

[0054] Another purpose of the buffer circuit 140 is to reduce the load seen by the out-of-band signaling circuit 160, in which case the data transfer rate of the receiving circuit 100 can be improved.

[0055] Figure 10Circuit diagram of another embodiment of the receiving circuit of the deserializer of the present application. The receiving circuit 1000 is similar to the receiving circuit 900, except that the link equalizer 150 and the out-of-band signaling circuit 160 are swapped. The receiving circuit 1000 is an AC-coupled receiving circuit. In Figure 10 In the embodiment, the buffer circuit 140 can reduce the load seen by the link equalizer 150, and the common-mode voltage of the link equalizer 150 and the common-mode voltage of the out-of-band signaling circuit 160 can be adjusted independently. Adjusting the voltage Vb is equivalent to adjusting the common-mode voltage of the link equalizer 150.

[0056] In some embodiments, the voltage Vb is greater than the voltage at the input of the out-of-band signaling circuit 160.

[0057] Although the transistors in the embodiments disclosed above are exemplified by MOSFETs, this is not a limitation of the present application. Those skilled in the art know how to replace the MOSFETs with bipolar junction transistors (BJTs).

[0058] The receiving circuit of the deserializer of the present application includes a buffer circuit, one of the purposes of the buffer circuit is to isolate the link equalizer and the out-of-band signaling circuit, so that the input terminals of the two are not electrically connected. In this way, the input load of the link equalizer or the out-of-band signaling circuit is reduced, and the common-mode voltages of the two can be adjusted independently. Therefore, the receiving circuit of the deserializer of the present application does not have the problem of load stacking, and can achieve the effect of high-speed data transmission without attenuation.

[0059] Please note that in the figures disclosed above, the shapes, sizes and proportions of the components are only for the purpose of helping those skilled in the art to understand the present application, and are not intended to limit the present application.

[0060] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, and all such changes are likely to fall within the scope of the patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be determined by the patentable scope defined in the specification.

[0061] Explanation of reference signs:

[0062] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000: receiving circuit

[0063] 110, 510, 910: signal receiving terminal

[0064] 120, 130, 330, 380, 520, 530, 720, 780, 920, 930: resistor

[0065] 140, 540: buffer circuit

[0066] 150: link equalizer (LEQ)

[0067] 160: out-of-band signal transmission circuit (OOBS)

[0068] Vin: input signal

[0069] VDD: power supply voltage

[0070] Vb: voltage

[0071] 142, 542: current source

[0072] 144: P-type metal oxide semiconductor field effect transistor

[0073] 370, 770, 970, 980: capacitor

[0074] 544: N-type metal oxide semiconductor field effect transistor

[0075] Vbias: bias voltage

Claims

1. A receiver circuit of a deserializer receiving an input signal, comprising: a signal receiving terminal configured to receive the input signal; a link equalizer having a first input terminal coupled to the signal receiving terminal; an out-of-band signaling circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal coupled to the signal receiving terminal and an output terminal, wherein the third input terminal receives a voltage and the output terminal is coupled to the link equalizer or the out-of-band signaling circuit; wherein the first input terminal of the link equalizer and the second input terminal of the out-of-band signaling circuit are not electrically connected, and the voltage received by the third input terminal of the buffer circuit is adjustable.

2. The receiver circuit of the deserializer of claim 1, wherein the third input terminal of the buffer circuit is electrically connected to the first resistor or the second resistor, and the voltage is a voltage divided across the first resistor or the second resistor.

3. The receiver circuit of the deserializer of claim 2, wherein the first reference voltage is greater than the second reference voltage, the third input terminal of the buffer circuit is electrically connected to the second resistor, the voltage is a voltage divided across the second resistor, and the buffer circuit is a P-type metal-oxide-semiconductor field-effect transistor source follower.

4. The receiver circuit of the deserializer of claim 2, wherein the first reference voltage is greater than the second reference voltage, the third input terminal of the buffer circuit is electrically connected to the first resistor, the voltage is a voltage divided across the first resistor, and the buffer circuit is an N-type metal-oxide-semiconductor field-effect transistor source follower.

5. The receiver circuit of the deserializer of claim 1, further comprising: a capacitor coupled between the signal receiving terminal and the link equalizer or the out-of-band signaling circuit; and a third resistor in parallel with the capacitor; wherein the third input terminal of the buffer circuit is electrically connected to the third resistor, and the voltage is a voltage divided across the third resistor.

6. The receiver circuit of the deserializer of claim 5, wherein the first resistor is electrically connected to the link equalizer or the out-of-band signaling circuit, the second resistor is electrically connected to the signal receiving terminal, the first reference voltage is greater than the second reference voltage, and the buffer circuit is a P-type metal-oxide-semiconductor field-effect transistor source follower.

7. The receiver circuit of the deserializer of claim 5, wherein the first resistor is electrically connected to the signal receiving terminal, the second resistor is electrically connected to the link equalizer or the out-of-band signaling circuit, the first reference voltage is greater than the second reference voltage, and the buffer circuit is an N-type metal-oxide-semiconductor field-effect transistor source follower.

8. A receiver circuit of a deserializer receiving an input signal, comprising: a signal receiving terminal configured to receive the input signal; a link equalizer having a first input terminal coupled to the signal receiving terminal; an out-of-band signaling circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal coupled to the signal receiving terminal and an output terminal, wherein the third input terminal receives a voltage and the output terminal is coupled to the link equalizer or the out-of-band signaling circuit; wherein the first input terminal of the link equalizer and the second input terminal of the out-of-band signaling circuit are not electrically connected, and the voltage received by the third input terminal of the buffer circuit is adjustable. a first capacitor having a first end and a second end, wherein the first end is coupled to the signal receiving end and the second end is coupled to the link equalizer or the out-of-band signal transmitting circuit; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the signal receiving end and the fourth end is coupled to the link equalizer or the out-of-band signal transmitting circuit; a first resistor having a fifth end and a sixth end, wherein the fifth end is coupled to a first reference voltage and the sixth end is electrically connected to the signal receiving end; a second resistor having a seventh end and an eighth end, wherein the seventh end is coupled to a second reference voltage and the eighth end is electrically connected to the link equalizer or the out-of-band signal transmitting circuit; and a buffer circuit having a third input end coupled to the signal receiving end and an output end, wherein the third input end receives a voltage and the output end is coupled to the link equalizer or the out-of-band signal transmitting circuit; wherein the first input end of the link equalizer and the second input end of the out-of-band signal transmitting circuit are not electrically connected, and the voltage received by the third input end of the buffer circuit is adjustable.

9. The receiver circuit of the deserializer of claim 8, wherein the third input end of the buffer circuit is electrically connected to the second resistor, the voltage is a voltage divided on the second resistor, and the buffer circuit is a P-type metal-oxide-semiconductor field-effect transistor source follower.

10. The receiver circuit of the deserializer of claim 8, wherein the second end of the first capacitor is electrically connected to the link equalizer, and the output end of the buffer circuit is electrically connected to the out-of-band signal transmitting circuit. ​

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