A pipeline ADC digital front-end calibration method based on machine learning

Abstract

The present invention discloses a pipeline ADC digital front-end calibration method based on machine learning. The calibration method includes: determining a fitting formula between the input signal and output headroom voltage of a single-stage processing structure of the pipeline ADC; obtaining the input voltage signal and output headroom voltage of the i-th stage of the pipeline ADC, respectively recorded as the i-th stage input signal and the i-th stage output headroom voltage; wherein 0<i<N; substituting the i-th stage input signal and the i-th stage output headroom voltage into the fitting formula, and using a machine learning algorithm to calculate the numerical values ​​of the fitting parameters in the fitting formula; and compensating the i-th stage output headroom voltage according to the values ​​of the fitting parameters. The present invention regards the latter stages of the pipeline ADC as an ideal post-stage ADC processing structure, compares the i-th stage output headroom voltage with the ideal digital conversion value, iteratively calculates the corresponding fitting parameters, and then calibrates the stages from the back to the front, thereby achieving error calibration of the entire pipeline ADC.

Description

Technical Field

[0001] The present invention relates to the fields of artificial intelligence, digital signal processing technology and integrated circuit technology, and in particular to a pipeline ADC digital foreground calibration method based on machine learning. Background Art

[0002] High-quality digital video communications require high-speed, high-precision analog-to-digital converters (ADCs). The excellent trade-off between accuracy, speed, and power consumption of medium-precision pipeline ADCs is a hot research topic for high-performance ADCs. However, many factors affect the conversion accuracy of pipeline ADCs, such as insufficient open-loop DC gain of the operational amplifier and mismatch between capacitors. Therefore, to improve the conversion accuracy of pipeline ADCs, the pipeline ADC must be calibrated. Summary of the Invention

[0003] The purpose of the present invention is to provide a pipeline ADC digital foreground calibration method based on machine learning.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A pipeline ADC digital foreground calibration method based on machine learning, wherein the pipeline ADC includes an N-stage ADC processing structure connected in sequence, characterized in that the calibration method includes:

[0006] Determining a fitting formula between an input signal and an output headroom voltage of a single-stage ADC processing structure, wherein the fitting formula includes a plurality of interval fitting sub-formulas, each of the interval fitting sub-formulas includes a plurality of fitting parameters, the fitting parameters including an error fitting parameter caused by open-loop gain and capacitance adaptation and an interval constant fitting parameter; the interval is determined by a ratio of the input signal to a reference voltage;

[0007] Obtaining the input signal and output headroom voltage of the i-th stage ADC processing structure, which are respectively recorded as the i-th stage input signal and the i-th stage output headroom voltage; wherein 0<i<N;

[0008] Substituting the i-level input signal and the i-level output margin voltage into the fitting formula, and using a machine learning algorithm to calculate the values ​​of the fitting parameters in the fitting formula;

[0009] Compensation is performed based on the output margin voltage of level i for each fitting parameter value.

[0010] Optionally, also include:

[0011] The input signal and output margin voltage of the i-level ADC processing structure are collected, wherein the input signal is a preset analog signal.

[0012] Optionally, also include:

[0013] The analog signal is a full-scale sine wave signal or a cosine wave signal.

[0014] Optionally, also include:

[0015] The method of calculating the values ​​of the fitting parameters in the fitting formula using a machine learning algorithm includes: successively recording the digital output values ​​of the ADC processing structures of the i+1th to the Nth levels;

[0016] The digital output values ​​are added to obtain a digital value D(V res_i ), the digital value D(V res_i ) is compared with the i-level output headroom voltage obtained by the fitting formula and a difference between the two is calculated;

[0017] Substitute the difference into the parameter update expression For θ1 and θ 0-j Perform iterative calculations; where θ1 is the error fitting parameter caused by the open-loop gain and capacitor adaptation, θ 0-j is the interval constant fitting parameter, η is the learning rate, k is the number of sampling times, n is the number of iterative calculation data in each group, f θ (V in ) is the output margin voltage of the pipeline ADC stage i calculated by the fitting formula, D(V res_i ) are the digital output values ​​of the pipeline ADC from stage i+1 to stage N;

[0018] When the parameter values ​​before and after the iteration are less than the preset values, the iterative calculation is completed. Or when the number of iterations reaches the specified number and iterative optimization is no longer possible, the iteration is considered to be completed and the iteration is exited to obtain the optimal value of the fitting parameter.

[0019] Optionally, also include:

[0020] If the pipeline ADC has a 2.5-bit / stage structure, the fitting formula is:

[0021]

[0022] Among them, V in is the input voltage signal of level i, f θ (V in ) is the output margin voltage of level i, θ1 is the error fitting parameter caused by open-loop gain and capacitor adaptation, θ 0-1 ,θ 0-2 and θ 0-3 is the interval constant fitting parameter, V ref This is a stable reference voltage used in pipelined ADC circuits.

[0023] Optionally, also include:

[0024] The first several pipeline stages in an N-stage pipeline ADC are calibrated from back to front. When calibrating the i-th stage ADC processing structure, if 1<i<N, the input signal bypasses the 1st to i-1th pipeline stages before the i-th stage and is directly input to the i-th stage.

[0025] The present invention has the following technical effects:

[0026] The present invention determines a fitting formula between an input signal and an output headroom voltage of a single-stage ADC processing structure in a pipeline ADC. The fitting formula includes several fitting sub-formulas. Different intervals are determined according to the ratio of the input signal to a reference voltage. Each interval fitting sub-formula includes several fitting parameters. The fitting parameters include an error fitting parameter caused by open-loop gain and capacitance adaptation and an interval constant fitting parameter. The input signal and output headroom voltage of the i-th stage ADC processing structure are obtained, and then the input signal and output headroom voltage are substituted into the fitting formula. A machine learning algorithm is used to calculate the values ​​of the fitting parameters in the fitting formula. Finally, the i-th stage output headroom voltage is compensated according to the values ​​of the fitting parameters, thereby achieving digital front-end calibration of the pipeline ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 Schematic diagram of the structure of the pipeline ADC of the present invention;

[0029] Figure 2 A flow chart of a pipeline ADC digital front-end calibration method based on machine learning provided in an embodiment of the present invention;

[0030] Figure 3 2.5-bit / stage MDAC circuit diagram according to an embodiment of the present invention;

[0031] Figure 4 Graph showing an ideal transmission curve of a 2.5-bit / level MDAC circuit according to an embodiment of the present invention;

[0032] Figure 5 Schematic diagram of pipeline stage calibration in which the first stage of the pipeline ADC is composed of a 2.5-bit / stage pipeline stage circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] Figure 1 This is a schematic diagram of the structure of the pipeline ADC. Figure 1 The pipeline ADC shown in FIG, proposes a pipeline ADC digital foreground calibration method based on machine learning, wherein the pipeline ADC includes an N-stage ADC processing structure connected in sequence, see Figure 2 , the calibration method comprises the following steps:

[0035] Step 11: Determine a fitting formula between the input signal and the output headroom voltage of the single-stage ADC processing structure. The fitting formula includes several interval fitting sub-formulas. Each interval fitting sub-formula includes several fitting parameters. The fitting parameters include an error fitting parameter caused by open-loop gain and capacitor adaptation, and an interval constant fitting parameter. The interval is determined by the ratio of the input signal to the reference voltage.

[0036] Step 12: Obtain the input signal and output headroom voltage of the i-th stage ADC processing structure, which are respectively recorded as the i-th stage input signal and the i-th stage output headroom voltage; wherein 0<i<N;

[0037] Step 13: Substitute the level i input signal and the level i output margin voltage into the fitting formula, and use a machine learning algorithm to calculate the values ​​of the fitting parameters in the fitting formula;

[0038] Step 14: Compensate the output margin voltage of level i according to the values ​​of the fitting parameters.

[0039] In one example, before step 12, the method further includes:

[0040] The input signal and output headroom voltage of the i-level ADC processing structure are collected, wherein the input signal is a preset analog signal. Specifically, the preset analog signal can be a full-scale sine wave signal or a cosine wave signal.

[0041] In one example, step 13 above can be implemented by the following scheme:

[0042] Record the digital output values ​​of the pipeline stages from level i+1 to level N one by one;

[0043] Add the digital output values ​​to get the digital value D(V res_i), the digital value D(V res_i ) is compared with the level i output headroom voltage obtained by the fitting formula and the difference between the two is calculated;

[0044] Substitute the difference into the parameter update expression For θ1 and θ 0-j Perform iterative calculations; where θ1 is the error fitting parameter caused by open-loop gain and capacitor adaptation, θ 0-j is a constant, η is the learning rate, k is the number of sampling times, n is the number of data for each iterative calculation, and f θ (V in ) is the margin voltage output by the i-th pipeline stage calculated by the fitting formula, D(V res_i ) is the sum of the digital output values ​​from level i+1 to level N;

[0045] The iterative calculation is complete when the parameter values ​​before and after the iteration are less than the preset value. Alternatively, when the number of iterations reaches the specified number and no further iterative optimization is possible, the iteration is considered complete and the iteration is exited, resulting in the optimal value of the fitting parameter. This optimal value can be used as the final fitting parameter value for compensating the output headroom voltage of level i in step 14.

[0046] It should be noted that the present application adopts the above method to calibrate the N-stage pipeline ADC processing structure from back to front. When calibrating the i-stage ADC processing structure, if 1<i≤N, the input signal bypasses the 1st stage before the i-th stage to the i-1th stage pipeline and is directly input to the i-th stage.

[0047] The following describes the process of determining the fitting formula using a 2.5-bit / stage capacitor-flipping MDAC pipeline ADC as the first calibration stage. The process of determining the fitting formula for pipeline ADCs with other bit / stages is similar and will not be repeated here.

[0048] See also Figure 3 . Figure 3 This is a 2.5-bit / level capacitor flipping MDAC circuit. Taking this circuit as an example, the MDAC circuit first samples the input signal under the control of clock φ1, and then flips the capacitor under the control of clock φ2, outputting the residual voltage V res , the output margin voltage can be expressed as:

[0049]

[0050] Where A is the open-loop DC gain of the operational amplifier in the MDAC circuit, β is the closed-loop feedback coefficient of the MDAC circuit, and V in is the input voltage signal of the i-th level. Let α=-1 / Aβ, according to the working principle of 2.5-bit MDAC circuit, bj ={-1, 0, +1}; use δ j Indicates the capacitance C caused by the integrated circuit manufacturing process S，j and feedback capacitor C F The matching deviation between them is:

[0051] C s，j =C F +ΔC s，j =(1+ΔC s，j / C F )C F =(1+δ j )C F (2)

[0052] Put α and δ j Substituting into formula (1), we can get:

[0053]

[0054] An N-stage pipeline ADC includes the first N-1 stages of ADC processing structure. The Nth stage, or the last stage, is generally a Flash ADC. The accuracy of the first few stages is generally considered to have the most critical impact on the accuracy of the entire ADC, while the subsequent stages have less impact on the accuracy and are generally considered to be ideal ADCs. Before calibration, a full-scale sine wave or cosine wave signal is sampled to obtain an ideal discrete analog sampling signal. The calibration method of the present invention uses the ideal back-end ADC output data to measure the error of the front stage, referring to Figure 5 Taking the first stage of the pipeline ADC calibration as an example, the following N-1 stages are considered to be the ideal back-end ADC. The steps involved are as follows:

[0055] Step 1: After the chip is taped out, the ideal sine wave sampling voltage signal obtained is input to the calibrated pipeline ADC, and the digital output values ​​of the ideal ADC at the back end are recorded one by one.

[0056] Step 2: According to the previous formula (3) and Figure 4 The output of the first-level 2.5-bit pipeline can be divided into 7 regions according to the output curve. In each region, there is a linear expression:

[0057]

[0058] From the above formula (4), we can get a corresponding fitting formula as follows:

[0059]

[0060] To fit the 2.5-bit / stage pipeline transfer performance curve formula, where θ1 is used to represent the error in the amplification factor of the circuit caused by the open-loop gain and capacitor adaptation, and θ 0-j (j=1, 2, 3) represents the constant fitting parameters in the six intervals. Here, a Gaussian random number generator is used to generate four random numbers as the initial values ​​of these four parameters. The 3σ distribution range of the generated Gaussian random numbers is between [-0.5, 0.5]. The fitting parameter θ is calculated based on the digital value output by the sub-ADC in the first stage of the pipeline ADC to determine which interval it should belong to. 0-j and θ1.

[0061] Step 3: A set of digital signals D(V) output by the ideal ADC recorded in step 1 res1 (nT s )), This data is the output voltage V of the first-stage ADC out1 The ideal digital conversion value of , where n is a positive integer representing the number of sampling times, T s is the reciprocal of the sampling frequency, and the corresponding set of values ​​obtained by formula (4) is in the same interval as f θ (V in ) (i) Compare and calculate the difference between the two, parameter θ 0-j The update expressions of and θ1 are:

[0062]

[0063] Where η is the learning rate, and its initial value can be set to 0.0025; n in the formula can be 64, that is, 64 data are taken as a group each time, that is, k = [1, 2, 3, ..., 64], and the calculation parameter θ 0-j and the updated value of θ1.

[0064] Step 4: Iterate repeatedly according to formula (6) and finally converge to the obtained parameter θ 0-j Substituting θ1 into formula (4), we can obtain:

[0065] D(V in )=[f θ (V in )+b j θ 0-j ] / (4+θ1)j=1,2,3 (7)

[0066] Since f in formula (7) θ (V in )The final converged value is the same as the output D(V res1 ) is close, then formula (7) can be rewritten as:

[0067] D(Vin )=[D(V res1 )+b j θ 0-j ] / (4+θ1)j=1,2,3 (8)

[0068] Since the value of θ1 is very small and close to zero, (4+θ1) in formula (8) -1 Expanded by Taylor's formula, it is approximately:

[0069]

[0070] Substitute into formula (8):

[0071] D(V in )=[D(V res1 )+b j θ 0-j ]·(1-θ1 / 4) / 4j=1, 2, 3 (10)

[0072] That is the analog voltage V in The corresponding digital value after compensation, after Taylor formula approximation, turns the relatively difficult division into a relatively easy multiplication and shift calculation in the computer, greatly simplifying the calculation process. In the 7 intervals of the 2.5-bit / stage pipeline transfer curve, the two parameters θ in each univariate linear regression equation can be obtained according to formula (5). 0-j and θ1, the digital voltage value converted to each input analog voltage is calculated according to V in / V ref The range of the interval is compensated according to formula (10).

[0073] It should be noted that the input discrete analog signal is sampled by the sub-ADC and MDAC circuit simultaneously. The signal is compared by the sub-ADC to generate a digital output, and the specific interval is determined according to the digital output of the sub-ADC.

[0074] The following is a detailed example of the pipeline ADC front-end calibration method based on the machine learning algorithm of this application. The method includes the following steps:

[0075] Step 1: The errors in the pipeline ADC, the open-loop gain error of the op amp, and the capacitor mismatch error follow a Gaussian distribution. Therefore, referring to the previous formula (5), the Gaussian random number generator module is first used to generate four Gaussian random numbers. The process of generating Gaussian random numbers by the Gaussian random number module is mainly divided into two stages: the first stage is to generate uniform random numbers based on cellular automata, specifically using a uniform random number generator of a 64-order cellular automaton to generate uniform random numbers; the second stage is to convert the uniform random numbers into Gaussian random numbers using the Box-Muller algorithm.

[0076] Step 2: The pipeline ADC after tape-out receives the prepared discrete analog voltage signal, receives n discrete analog signals, and outputs D(V) corresponding to the first-stage pipeline output of these n discrete analog signals according to the output digital value of the sub-ADC in the first-stage pipeline. res1 (nT s )), distributed into 7 intervals according to the following formula:

[0077] V res1 (θ)=f θ (V in )=(4+θ1)V in -b j θ 0-j j = {1, 2, 3} (11)

[0078] The fitting parameter θ 0-j The four parameters θ and θ1 are generated by the Gaussian random number generator module.

[0079] Step 3: Refer to formula (5) and use 3 / 8>V in / V ref >1 / 8 is an example, and the rest of the intervals are similar. 0-j When θ1 is used, the initial value of the learning rate η is set to 0.0025 to facilitate the computer to express it in binary. If the initial value of the learning rate is too small, too many iterations are required to achieve convergence. However, if it is too large, it may cause failure to converge. Since the present invention uses a large number of signals input to the pipeline ADC to train the machine model, the training set is large. Here, we use the mini-batch gradient descent method to train and solve the parameters. Also, for the convenience of representation in the computer, the amount of data for each group of training data is 64, 128, 256, 512 and 1024. These are convenient data for computer to express in binary. In this method, 64 is used here. Formula (6) is rewritten as follows:

[0080]

[0081] 3 / 8>V in / V ref Taking the interval >1 / 8 as an example, the iterative formula (4) is rewritten as the corresponding fitting model formula:

[0082]

[0083] When V in / V ref In the range greater than 1 / 8 and 3 / 8, the pipeline ADC calculates f according to formula (13) every time it receives the input analog signal. θ (V in )(k) The result is then substituted into formula (12), minus the corresponding ideal back-end output D (V res1 ) (k) , calculate θ 0-1 It is only necessary to multiply it by the learning rate for the 64th time to update; each time θ1 is calculated, it is necessary to multiply it by the corresponding V in (k) , when the region is calculated 64 times cumulatively, the fitting parameter θ is updated once 0-1 and the value of θ1, the next iteration will use the updated θ 0-1 and θ1 values, and use registers to save the θ used in the previous iteration 0-1 and θ1, and compare the parameter values ​​before and after to determine whether the iteration should end.

[0084] When the difference between the parameter values ​​before and after the iteration is less than a very small preset value, that is, when the loss function reaches the minimum, the iterative calculation is completed; when the number of repeated iterations reaches the specified number and iterative optimization is no longer possible, the iteration is considered to be completed and exited.

[0085] Step 4: Recover the result of the calibrated input analog voltage, which is as follows according to the rewritten formula (10):

[0086] D(V in )=[D(V res1 )+θ 0-1 ]·(1-θ1 / 4) / 4 (14)

[0087] When the pipeline ADC receives a new analog voltage signal and the input voltage range is V in / V ref In the range greater than 1 / 8 and 3 / 8, the calibrated digital value of the analog voltage is output according to the above formula (14).

[0088] Step 5. After the calibration is completed, the fitting parameters are saved in four registers, that is, the learning stage of machine learning is completed and the process is transferred to the calibration stage of the pipeline ADC. The analog voltage value needs to be measured for the normal input of the pipeline ADC, and the compensation is obtained through the converged machine learning algorithm and the calibrated digital value is output.

[0089] In an embodiment of the present invention, the latter stages of a pipeline ADC are first treated as ideal latter ADCs. The output value of the ideal latter ADC is the ideal digital conversion value of the biased output analog voltage of the preceding pipeline stage. The ideal value is then compared with the value calculated by a fitting formula of a machine learning algorithm, and corresponding linear regression equation parameters are iteratively calculated. Calibration is then performed step by step from the back end to the front end, ultimately completing the calibration of all the preceding pipeline stages of the multi-stage pipeline ADC, thereby achieving foreground digital calibration of the multi-stage pipeline ADC. The present invention segments the output curve of the MDAC circuit and establishes the corresponding linear regression equation. Compared with existing artificial intelligence technology methods applied to ADCs, the present invention has a simpler model and greatly reduces the number of calculation parameters. The present invention calibrates the pipeline ADC based on a machine learning algorithm. Compared with other traditional digital background calibration algorithms, such as the dither algorithm and the LMS algorithm, the present invention does not require additional changes to the circuit structure of the ADC itself, and has good applicability.

[0090] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0091] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A pipeline ADC digital foreground calibration method based on machine learning, wherein the pipeline ADC includes an N-stage ADC processing structure connected in sequence, characterized in that: The calibration method comprises: Determining a fitting formula between an input signal and an output headroom voltage of a single-stage ADC processing structure, the fitting formula including a plurality of interval fitting sub-formulas, each of the interval fitting sub-formulas including a plurality of fitting parameters, the fitting parameters including an error fitting parameter caused by open-loop gain and capacitance adaptation and an interval constant fitting parameter; the interval being determined by a ratio of the input signal to a reference voltage; Obtaining the input signal and output headroom voltage of the i-th stage ADC processing structure, which are respectively recorded as the i-th stage input signal and the i-th stage output headroom voltage; wherein 0<i<N; Substituting the i-level input signal and the i-level output headroom voltage into the fitting formula, and using a machine learning algorithm to calculate the values ​​of the fitting parameters in the fitting formula; Compensating the output margin voltage of the i-th level according to each fitting parameter value; The method of using a machine learning algorithm to calculate the values ​​of the fitting parameters in the fitting formula includes: Successively record the digital output values ​​of the ADC processing structures of the i+1th to the Nth levels; The digital output values ​​are added to obtain a digital value D(V res_i ), the digital value D(V res_i ) is compared with the i-level output headroom voltage obtained by the fitting formula and a difference between the two is calculated; Substitute the difference into the parameter update expression For θ1 and θ 0-j Perform iterative calculations; where θ1 is the error fitting parameter caused by open-loop gain and capacitor adaptation, θ 0-j is the interval constant fitting parameter, η is the learning rate, k is the number of sampling times, n is the number of iterative calculation data in each group, f θ (V in ) is the output margin voltage of the pipeline ADC stage i calculated by the fitting formula, D(V res_i) is the digital output value from level i+1 to level N, i.e., the ideal back-end digital output value; When the parameter values ​​before and after the iteration are less than the preset minimum value, the iterative calculation is completed. Or when the number of iterations reaches the specified number and iterative optimization is no longer possible, the iteration is considered to be completed and the iteration is exited to obtain the optimal value of the fitting parameter.

2. The pipeline ADC digital foreground calibration method based on machine learning according to claim 1, wherein Also includes: The input signal and output margin voltage of the i-level ADC processing structure are collected, wherein the input signal is a preset analog signal.

3. The pipeline ADC digital foreground calibration method based on machine learning according to claim 2, wherein The analog signal is a full-scale sine wave signal or a cosine wave signal.

4. The pipeline ADC digital foreground calibration method based on machine learning according to claim 1, wherein If the pipeline ADC has a 2.5-bit / stage structure, the fitting formula is: Among them, V in is the input voltage signal of level i, f θ (V in ) is the output margin voltage of level i, θ1 is the error fitting parameter caused by open-loop gain and capacitor adaptation, θ 0-1 ,θ 0-2 and θ 0-3 is the interval constant fitting parameter, V ref is the reference voltage.

5. The pipeline ADC digital foreground calibration method based on machine learning according to claim 1, wherein The N-stage pipeline ADC processing structure is calibrated from back to front. When calibrating the i-th pipeline ADC stage, if 1<i≤N, the input signal bypasses the 1st to (i-1) pipeline stages before the i-th stage and is directly input to the i-th stage.

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