Server CPLD automatic compilation device and method

Abstract

The invention discloses a server CPLD automatic compilation device and method. The device collects a power-on timing specification table through a BMC management module and calls an embedded CPLD automatic compilation system. After reading the power-on timing specification table, the CPLD automatic compilation system feeds back a program compilation instruction to the BMC management module. The BMC management module implants a signal collection script into a CPLD unit module through an interface bus, collects signals of various IO pins of the CPLD unit module, determines the communication object, signal category and signal timing of each IO pin of the CPLD unit module, and transmits the collected signal information back to the CPLD automatic compilation system. The CPLD automatic compilation system classifies and screens the collected signal information of each IO pin according to the timing specification table, calls a compilation script to compile a CPLD program, and then transmits the compiled CPLD program to the BMC management module. The BMC management module burns the program into an internal register of a CPLD chip of the CPLD unit module through a burning module, thereby realizing automatic compilation of CPLD source code.

Description

Technical Field

[0001] The present invention relates to the field of server control, and in particular to a server CPLD automatic compiling device and method. Background Art

[0002] With the development of computer technology, CPLD (Complex Programmable Logic Device) allows users to generate specific circuit structures to complete certain functions according to their needs. More and more servers are using CPLD. In the design of server motherboards, CPLD plays an important role in the logic design of the entire motherboard. For example, it completes the timing control of power on and off, realizes the control of fan speed, and realizes the control of error signals. However, with the enrichment of functions, the difficulty of compiling CPLD programs has increased. Traditional manual compilation of CPLD programs is not only prone to various bugs, but also time-consuming and labor-intensive. This seriously leads to long subsequent design cycles for the entire server motherboard and insufficient server reliability and stability. Therefore, how to achieve automatic compilation of server CPLD is an urgent problem that technicians in this field need to solve.

[0003] In view of the above-mentioned defects in the prior art, it is very necessary to provide a server CPLD automatic compilation device and method. Summary of the Invention

[0004] The present invention provides a server CPLD automatic compiling device and method, which are used to solve the technical problems of manual compiling methods such as heavy workload, high difficulty, long compiling time, easy errors and poor compiling program reliability.

[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0006] A server CPLD automatic compilation device comprises: a BMC management module, a burning module, a CPLD unit module, a PCIE main control module, a Feiteng processor and a BIOS module; the BMC management module is respectively connected to the burning module and the CPLD unit module, the CPLD unit module is respectively connected to the burning module, the PCIE main control module, the Feiteng processor and the BIOS module, and the PCIE main control module is connected to the Feiteng processor.

[0007] Preferably, the BMC management module is connected to the CPLD unit through an interface bus, and the CPLD unit is also connected to the Feiteng processor through an interface bus; the BMC management module is connected to the burning module through a JATG port, and the burning module is connected to the CPLD unit module through a JATG port, and the CPLD unit is connected to the BIOS module through an SPI bus, and the PCIE main control module is connected to the Feiteng processor through a PCIE bus; the interface bus includes a UART bus, an I2C bus, an LPC bus, and an SPI bus;

[0008] The BMC management module is embedded in a CPLD program automatic compilation system, which includes four major functions: obtaining a power-on timing specification table, scheduling instruction of a CPLD program optimization module, monitoring the quality of level conversion signals, and monitoring the status of GPIO signals. Among them, the embedded CPLD program automatic compilation system integrates the functions of reading a power-on timing specification table, collecting IO pin signals, signal screening and classification, automatic compilation of CPLD programs, correction of CPLD program fault statements, optimization of CPLD program statements, and optimization of CPLD program statements.

[0009] Preferably, the BMC management module is used to collect a power-on timing specification table and call an embedded CPLD automatic compilation system so that the CPLD automatic compilation system reads the power-on timing specification table and then feeds back a program compilation instruction to the BMC management module; the BMC management module is also used to implant a signal collection script into the CPLD unit module through an interface bus according to the program compilation instruction, collect signals of each IO pin of the CPLD unit module, determine the communication object, signal category and signal timing of each IO pin of the CPLD unit module; and transmit the collected signal information back to the CPLD automatic compilation system; the CPLD automatic compilation system is used to classify and screen the collected signal information of each IO pin according to the timing specification table, call the compilation script to compile the CPLD program, and then transmit the compiled CPLD program to the BMC management module, and the BMC management module burns the program into the internal register of the CPLD chip of the CPLD unit module through the burning module.

[0010] Preferably, the BMC management module is also used to start and run the CPLD unit module through the GPIO port after the burning is completed, collect and analyze the serial port information of the Feiteng processor loading the BIOS firmware and the PCIE master control device through the UART bus, check the power-on timing fault information, and record the loading time of each timing signal. If there is timing fault information, the BMC management module will return the collected power-on timing fault information and the CPLD program to the CPLD automatic compilation system; the CPLD automatic compilation system will correct the statements of the CPLD program according to the fault information, and return to the BMC management module to re-burn the program to the internal register of the CPLD chip through the JATG port.

[0011] Preferably, if there is no timing fault information, the BMC management module is further used to compare the recorded loading time of each timing signal with the time in the power-on timing specification table. If there is a timing signal loading time that is greater than the time in the power-on timing specification table, the BMC management module will collect the timing signals that are greater than the time in the power-on timing specification table and the CPLD program and return them to the CPLD automatic compilation system. The CPLD automatic compilation system optimizes and shortens the CPLD program according to the shortest time allowed by the timing signal that is greater than the time in the power-on timing specification table, and returns it to the BMC management module to burn the program into the internal register of the CPLD chip through the JATG port.

[0012] Preferably, it also includes a TCM encryption module, which is connected to the CPLD unit; if there is no timing signal loading time greater than the power-on timing specification table time, the BMC management module is also used to output the CPLD program to the TCM encryption module for encrypted storage through the interface bus, and monitor the level conversion signal quality and GPIO signal application status of the CPLD unit module through the interface bus, and the CPLD unit module encrypts the access and operation of the CPLD program through the SPI bus.

[0013] A server CPLD automatic compilation method comprises the following steps:

[0014] The BMC management module collects the power-on timing specification table and calls the embedded CPLD automatic compilation system;

[0015] After the CPLD automatic compilation system reads the power-on timing specification table, it feeds back the program compilation instructions to the BMC management module;

[0016] The BMC management module implants a signal collection script into the CPLD unit module through the interface bus according to the program compilation instruction, collects signals of each IO pin of the CPLD unit module, determines the communication object, signal type and signal timing of each IO pin of the CPLD unit module, and transmits the collected signal information back to the CPLD automatic compilation system;

[0017] The CPLD automatic compilation system classifies and filters the collected signal information of each IO pin according to the timing specification table, calls the compilation script to compile the CPLD program, and then transmits the compiled CPLD program to the BMC management module. The BMC management module burns the program into the internal registers of the CPLD chip of the CPLD unit module through the burning module.

[0018] Preferably, after the burning is completed, the following steps are further included:

[0019] The BMC management module starts the CPLD unit module through the GPIO port, collects and analyzes the serial port information of the Feiteng processor loading BIOS firmware and PCIE master device through the UART bus, checks the power-on timing fault information, and records the loading time of each timing signal. If there is timing fault information, the BMC management module will return the collected power-on timing fault information and CPLD program to the CPLD automatic compilation system; the CPLD automatic compilation system will correct the CPLD program statement according to the fault information, and return it to the BMC management module to re-burn the program into the internal register of the CPLD chip through the JATG port.

[0020] Preferably, if there is no timing fault information, the BMC management module compares the recorded loading time of each timing signal with the time in the power-on timing specification table. If there is a timing signal loading time that is greater than the time in the power-on timing specification table, the BMC management module will collect the timing signals that are greater than the time in the power-on timing specification table and the CPLD program and return them to the CPLD automatic compilation system. The CPLD automatic compilation system optimizes and shortens the CPLD program statement according to the shortest time allowed by the timing signal that is greater than the time in the power-on timing specification table, and returns it to the BMC management module to burn the program into the internal register of the CPLD chip through the JATG port.

[0021] Preferably, if there is no timing signal loading time greater than the power-on timing specification table time, the BMC management module outputs the CPLD program to the TCM encryption module through the interface bus for encrypted storage, and monitors the level conversion signal quality and GPIO signal application status of the CPLD unit module through the interface bus, and the CPLD unit module encrypts the access and operation of the CPLD program through the SPI bus.

[0022] The present invention has the following beneficial effects:

[0023] 1. The server CPLD automatic compilation device and method of the present invention collects the power-on timing specification table through the BMC management module and calls the embedded CPLD automatic compilation system; after the CPLD automatic compilation system reads the power-on timing specification table, it feeds back the program compilation instruction to the BMC management module; the BMC management module implants a signal collection script into the CPLD unit module through the interface bus, collects the signals of each IO pin of the CPLD unit module, determines the communication object, signal type and signal timing of each IO pin of the CPLD unit module, and transmits the collected signal information back to the CPLD automatic compilation system; the CPLD automatic compilation system generates a signal according to the power-on timing specification table. The timing specification table classifies and filters the collected signal information of each IO pin, calls the compilation script to compile the CPLD program, and then transmits the compiled CPLD program to the BMC management module. The BMC management module burns the program into the internal registers of the CPLD chip of the CPLD unit module through the burning module, thereby realizing the automation of CPLD source code compilation, simplifying manual operations, and saving maintenance time and costs. It solves the current problems of manual CPLD source code compilation required for power-on debugging of domestic server whole machine research and development, as well as the drawbacks of large workload, high difficulty, long compilation time, easy errors and poor reliability of compiled programs.

[0024] 2. In the preferred embodiment, the present invention can improve the reliability of compiling the CPLD program by performing verification after compilation and correcting the CPLD program if a timing fault is found during the verification.

[0025] 3. In the preferred embodiment, the present invention compares the recorded loading time of each timing signal with the time in the power-on timing specification table after compilation. If there is a timing signal loading time that is longer than the time in the power-on timing specification table, the BMC management module will collect the timing signal with a long power-on loading time and the CPLD program and return it to the CPLD automatic compilation system. The CPLD automatic compilation system will optimize and shorten the CPLD program statement according to the shortest time allowed by the signal, thereby improving the operating efficiency of the compiled CPLD program.

[0026] 4. In the preferred embodiment, the present invention further encrypts the CPLD program through the TCM encryption module, thereby improving the security of compiling the CPLD program.

[0027] In addition to the above-described objects, features and advantages, the present invention has other objects, features and advantages. The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0029] Figure 1 A schematic diagram of the hardware structure of a server CPLD automatic compilation system provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of a process flow of a server CPLD automatic compilation system provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of the software architecture of a server CPLD automatic compilation system provided by an embodiment of the present invention;

[0032] Figure 4 Another hardware structure diagram of a server CPLD automatic compilation system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different ways as defined and covered by the claims.

[0034] Example 1:

[0035] This embodiment discloses a server CPLD automatic compilation device, including: a BMC management module, a burning module, a CPLD unit module, a PCIE main control module, a Feiteng processor and a BIOS module; the BMC management module is respectively connected to the burning module and the CPLD unit module, the CPLD unit module is respectively connected to the burning module, the PCIE main control module, the Feiteng processor and the BIOS module, and the PCIE main control module is connected to the Feiteng processor.

[0036] In addition, in this embodiment, Figure 2 As shown, a server CPLD automatic compilation method is also disclosed, comprising the following steps:

[0037] The BMC management module is used to collect the power-on timing specification table and call the embedded CPLD automatic compilation system;

[0038] After the CPLD automatic compilation system reads the power-on timing specification table, it feeds back the program compilation instructions to the BMC management module;

[0039] The BMC management module implants a signal collection script into the CPLD unit module through the interface bus according to the program compilation instruction, collects signals of each IO pin of the CPLD unit module, determines the communication object, signal type and signal timing of each IO pin of the CPLD unit module, and transmits the collected signal information back to the CPLD automatic compilation system;

[0040] The CPLD automatic compilation system classifies and filters the collected signal information of each IO pin according to the timing specification table, calls the compilation script to compile the CPLD program, and then transmits the compiled CPLD program to the BMC management module. The BMC management module burns the program into the internal registers of the CPLD chip of the CPLD unit module through the burning module.

[0041] The server CPLD automatic compilation device and method of the present invention can realize the automatic compilation of CPLD source code, simplify manual operations, and save maintenance time and cost.

[0042] Example 2:

[0043] The second embodiment is a preferred embodiment of the first embodiment. The difference between the second embodiment and the first embodiment is that the structure of the server CPLD automatic compilation system is introduced:

[0044] like Figure 1 As shown, this embodiment discloses a server CPLD automatic compilation device, including: a BMC management module, a burning module, a CPLD unit module, a PCIE main control module, a Feiteng processor, a BIOS module and a TCM encryption module; the BMC management module is connected to the CPLD unit via an interface bus, and the CPLD unit is also connected to the Feiteng processor via an interface bus; the BMC management module is connected to the burning module via a JATG port, the burning module is connected to the CPLD unit module via a JATG port, the CPLD unit is connected to the BIOS module via an SPI bus, the PCIE main control module is connected to the Feiteng processor via a PCIE bus, and the TCM encryption module is connected to the CPLD unit via an SPI bus, wherein the interface bus includes a UART bus, an I2C bus, an LPC bus, and an SPI bus.

[0045] like Figure 3 As shown in FIG, the BMC management module is embedded in the CPLD program automatic compilation system, which includes four major functions: obtaining the power-on timing specification table, scheduling the CPLD program optimization module instruction, monitoring the level conversion signal quality, and monitoring the GPIO signal status. The embedded CPLD program automatic compilation system integrates the functions of reading the power-on timing specification table, collecting IO pin signals, signal screening and classification, automatic compilation of CPLD programs, correction of CPLD program fault statements, optimization of CPLD program statements, and optimization of CPLD program statements.

[0046] like Figure 2 As shown, the workflow of the server CPLD automatic compiling device in the present invention is as follows:

[0047] The BMC management module collects the power-on timing specification table and calls the embedded CPLD program automatic compilation system. After reading the power-on timing specification table, the CPLD automatic compilation system feeds back the program compilation instructions to the BMC management module. The BMC management module implants a signal collection script into the CPLD unit module through the interface bus, collects the CPLD unit module IO pin signals, and transmits the signal information back to the CPLD automatic compilation system. The CPLD automatic compilation system classifies and filters the signals according to the timing specification table, calls the compilation script to compile the CPLD program, and then transmits the compiled CPLD program to the BMC management module. The BMC management module burns the program to the CPLD unit module through the JATG port. After the internal register of the CPLD chip is burned, the BMC management module starts the CPLD unit module through the GPIO port, collects and analyzes the serial port information of the Feiteng processor loading the BIOS firmware and the PCIE master device through the UART bus, checks the power-on timing fault information, and records the loading time of each timing signal. If there is timing fault information, the BMC management module will return the collected power-on timing fault information and the CPLD program to the CPLD automatic compilation system. The CPLD automatic compilation system will correct the CPLD program statement according to the fault information, and return it to the BMC management module to re-burn the program to the internal register of the CPLD chip through the JATG port;

[0048] If there is no timing fault information, the BMC management module compares the recorded loading time of each timing signal with the time in the power-on timing specification table. If there is a timing signal loading time longer than the time in the power-on timing specification table, the BMC management module collects the timing signals with long power-on loading time and the CPLD program and transmits them back to the CPLD automatic compilation system. The CPLD automatic compilation system optimizes and shortens the CPLD program statement based on the shortest time allowed by the signal. The module then returns to the BMC management module and burns the program into the internal registers of the CPLD chip through the JATG port. If there is no timing signal loading time longer than the time in the power-on timing specification table, the BMC management module outputs the CPLD program to the TCM encryption module through the interface bus for encrypted storage. The BMC management module also monitors the level conversion signal quality and GPIO signal application status of the CPLD unit module through the interface bus. The CPLD unit module then accesses the CPLD program for encrypted operation through the SPI bus.

[0049] like Figure 4As shown, the Feiteng processor integrates UART, I2C, GPIO, LPC, SPI, PCIE and other bus ports, and the CPLD unit module includes: a timing signal module, a level conversion module, and a custom GPIO module; the BMC management module is respectively connected to the timing signal module, the level conversion module, and the custom GPIO module, and the timing signal module is respectively connected to the PCIE master device and the Feiteng processor; the level conversion module is respectively connected to the Feiteng processor and the BIOS module; the custom GPIO module is connected to the Feiteng processor;

[0050] In this embodiment, the power-on timing signal includes the Feiteng processor power-on timing signal and the PCIE master device power-on timing signal; the timing specification table includes the Feiteng processor power-on timing specification table and the PCIE master device power-on timing specification table; when the server CPLD automatic compilation device is working, the user uploads the Feiteng processor power-on timing specification table and the PCIE master device power-on timing specification table through the BMC management module, and calls the CPLD automatic compilation system. The CPLD automatic compilation system scans the IO pin signal through the CPLD unit module according to the specification table, identifies the Feiteng processor power-on timing signal and the PCIE master device power-on timing signal, and generates the Feiteng power-on timing program and the PCIE master device power-on timing program in turn, and classifies the level conversion signal and the custom GPIO signal. The CPLD automatic compilation system calls the compilation script to automatically compile the classified signals and source code into a CPLD program. The CPLD automatic compilation system packages the CPLD program and saves it to the CPLD optimization module, and burns / updates the program to the internal register of the CPLD chip through the BMC management module JATG port.

[0051] In summary, the present invention can solve the current problems of manual CPLD source code compilation required for power-on debugging of domestic server whole machine research and development, as well as the drawbacks of large workload, high difficulty, long compilation time, easy error and poor reliability of compilation program. The present invention simplifies manual operation and saves maintenance time and cost.

[0052] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A server CPLD automatic compilation device, characterized in that: include: BMC management module, burning module, CPLD unit module, PCIE main control module, Feiteng processor and BIOS module; the BMC management module is respectively connected to the burning module and CPLD unit module, the CPLD unit module is respectively connected to the burning module, PCIE main control module, Feiteng processor and BIOS module, and the PCIE main control module is connected to the Feiteng processor; The BMC management module collects the power-on timing specification table and calls the embedded CPLD automatic compilation system; After the CPLD automatic compilation system reads the power-on timing specification table, it feeds back the program compilation instructions to the BMC management module; The BMC management module implants a signal collection script into the CPLD unit module through the interface bus according to the program compilation instruction, collects signals of each IO pin of the CPLD unit module, determines the communication object, signal type and signal timing of each IO pin of the CPLD unit module, and transmits the collected signal information back to the CPLD automatic compilation system; The CPLD automatic compilation system classifies and filters the collected signal information of each IO pin according to the timing specification table, calls the compilation script to compile the CPLD program, and then transmits the compiled CPLD program to the BMC management module. The BMC management module burns the program into the internal registers of the CPLD chip of the CPLD unit module through the burning module; The power-on timing specification table includes the Feiteng processor power-on timing specification table and the PCIE master device power-on timing specification table; when the server CPLD automatic compilation device is working, the user uploads the Feiteng processor power-on timing specification table and the PCIE master device power-on timing specification table through the BMC management module, and calls the CPLD automatic compilation system. The CPLD automatic compilation system scans the IO pin signal through the CPLD unit module according to the specification table, identifies the Feiteng processor power-on timing signal and the PCIE master device power-on timing signal, and generates the Feiteng power-on timing program and the PCIE master device power-on timing program in turn, and classifies the level conversion signal and the custom GPIO signal. The CPLD automatic compilation system calls the compilation script to automatically compile the classified signals and source code into a CPLD program. The CPLD automatic compilation system packages the CPLD program and saves it to the CPLD optimization module, and burns / updates the program to the internal register of the CPLD chip through the BMC management module JATG port.

2. Server CPLD automatic compiling device according to claim 1, is characterized in that, The BMC management module is connected to the CPLD unit through an interface bus, and the CPLD unit is also connected to the Feiteng processor through an interface bus; the BMC management module is connected to the burning module through a JATG port, and the burning module is connected to the CPLD unit module through a JATG port, and the CPLD unit is connected to the BIOS module through an SPI bus, and the PCIE master control module is connected to the Feiteng processor through a PCIE bus; the interface bus includes a UART bus, an I2C bus, an LPC bus, and an SPI bus; The BMC management module is embedded in a CPLD program automatic compilation system, which includes four major functions: obtaining a power-on timing specification table, scheduling instruction of a CPLD program optimization module, monitoring the quality of level conversion signals, and monitoring the status of GPIO signals. Among them, the embedded CPLD program automatic compilation system integrates the functions of reading a power-on timing specification table, collecting IO pin signals, signal screening and classification, automatic compilation of CPLD programs, correction of CPLD program fault statements, optimization of CPLD program statements, and optimization of CPLD program statements.

3. Server CPLD automatic compiling device according to claim 1, is characterized in that, The BMC management module is used to collect a power-on timing specification table and call an embedded CPLD automatic compilation system so that the CPLD automatic compilation system reads the power-on timing specification table and feeds back a program compilation instruction to the BMC management module. The BMC management module is also used to implant a signal collection script into the CPLD unit module through an interface bus according to the program compilation instruction, collect signals of each IO pin of the CPLD unit module, determine the communication object, signal category and signal timing of each IO pin of the CPLD unit module, and transmit the collected signal information back to the CPLD automatic compilation system. The CPLD automatic compilation system is used to classify and screen the collected signal information of each IO pin according to the timing specification table, call the compilation script to compile the CPLD program, and then transmit the compiled CPLD program to the BMC management module. The BMC management module burns the program into the internal register of the CPLD chip of the CPLD unit module through the burning module.

4. The server CPLD automatic compiling device according to claim 3, wherein The BMC management module is also used to start and run the CPLD unit module through the GPIO port after the burning is completed, collect and analyze the serial port information of the Feiteng processor loading the BIOS firmware and the PCIE master device through the UART bus, check the power-on timing fault information, and record the loading time of each timing signal. If there is timing fault information, the BMC management module will return the collected power-on timing fault information and the CPLD program to the CPLD automatic compilation system; the CPLD automatic compilation system will correct the CPLD program statement according to the fault information, and return to the BMC management module to re-burn the program to the internal register of the CPLD chip through the JATG port.

5. Server CPLD automatic compiling device according to claim 4, is characterized in that, If there is no timing fault information, the BMC management module is further used to compare the recorded loading time of each timing signal with the time in the power-on timing specification table. If there is a timing signal loading time that is longer than the time in the power-on timing specification table, the BMC management module will collect the timing signals that are longer than the time in the power-on timing specification table and the CPLD program and return them to the CPLD automatic compilation system. The CPLD automatic compilation system optimizes and shortens the CPLD program according to the shortest time allowed for the timing signals that are longer than the time in the power-on timing specification table, and returns the result to the BMC management module to burn the program into the internal register of the CPLD chip through the JATG port.

6. The server CPLD automatic compiling device according to claim 5, wherein: It also includes a TCM encryption module, which is connected to the CPLD unit; if there is no timing signal loading time greater than the power-on timing specification table time, the BMC management module is also used to output the CPLD program to the TCM encryption module for encrypted storage through the interface bus, and monitor the level conversion signal quality and GPIO signal application status of the CPLD unit module through the interface bus, and the CPLD unit module encrypts the access and operation of the CPLD program through the SPI bus.

7. A server CPLD automatic compilation method, characterized in that: The following steps are involved: The BMC management module collects the power-on timing specification table and calls the embedded CPLD automatic compilation system; After the CPLD automatic compilation system reads the power-on timing specification table, it feeds back the program compilation instructions to the BMC management module; The BMC management module implants a signal collection script into the CPLD unit module through the interface bus according to the program compilation instruction, collects signals of each IO pin of the CPLD unit module, determines the communication object, signal type and signal timing of each IO pin of the CPLD unit module, and transmits the collected signal information back to the CPLD automatic compilation system; The CPLD automatic compilation system classifies and filters the collected signal information of each IO pin according to the timing specification table, calls the compilation script to compile the CPLD program, and then transmits the compiled CPLD program to the BMC management module. The BMC management module burns the program into the internal registers of the CPLD chip of the CPLD unit module through the burning module; The power-on timing specification table includes the Feiteng processor power-on timing specification table and the PCIE master device power-on timing specification table; when the server CPLD automatic compilation device is working, the user uploads the Feiteng processor power-on timing specification table and the PCIE master device power-on timing specification table through the BMC management module, and calls the CPLD automatic compilation system. The CPLD automatic compilation system scans the IO pin signal through the CPLD unit module according to the specification table, identifies the Feiteng processor power-on timing signal and the PCIE master device power-on timing signal, and generates the Feiteng power-on timing program and the PCIE master device power-on timing program in turn, and classifies the level conversion signal and the custom GPIO signal. The CPLD automatic compilation system calls the compilation script to automatically compile the classified signals and source code into a CPLD program. The CPLD automatic compilation system packages the CPLD program and saves it to the CPLD optimization module, and burns / updates the program to the internal register of the CPLD chip through the BMC management module JATG port.

8. Server CPLD automatic compiling method according to claim 7, is characterized in that, After the burning is completed, the following steps are also included: The BMC management module starts the CPLD unit module through the GPIO port, collects and analyzes the serial port information of the Feiteng processor loading BIOS firmware and PCIE master device through the UART bus, checks the power-on timing fault information, and records the loading time of each timing signal. If there is timing fault information, the BMC management module will return the collected power-on timing fault information and CPLD program to the CPLD automatic compilation system; the CPLD automatic compilation system will correct the CPLD program statement according to the fault information, and return it to the BMC management module to re-burn the program into the internal register of the CPLD chip through the JATG port.

9. Server CPLD automatic compiling method according to claim 8, is characterized in that, If there is no timing fault information, the BMC management module compares the recorded loading time of each timing signal with the time in the power-on timing specification table. If any timing signal loading time exceeds the time in the power-on timing specification table, the BMC management module collects the timing signals that exceed the time in the power-on timing specification table and the CPLD program and returns them to the CPLD automatic compilation system. The CPLD automatic compilation system optimizes and shortens the CPLD program statements based on the shortest time allowed for the timing signals that exceed the time in the power-on timing specification table, and returns the results to the BMC management module to burn the program into the internal registers of the CPLD chip through the JATG port.

10. The server CPLD automatic compiling method according to claim 9, wherein: If there is no timing signal loading time greater than the power-on timing specification table time, the BMC management module outputs the CPLD program to the TCM encryption module through the interface bus for encrypted storage, and monitors the level conversion signal quality and GPIO signal application status of the CPLD unit module through the interface bus. The CPLD unit module encrypts and accesses the CPLD program through the SPI bus.

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