Direct current transmission converter valve light trigger board and trigger pulse signal redundant switching method thereof

Abstract

The application discloses a DC power transmission converter valve optical trigger board and a trigger pulse signal redundant switching method thereof, wherein the DC power transmission converter valve optical trigger board works in cooperation with each logic selection module, each optical port transmitting module, each waveform conditioning module and each optical port receiving module through two FPGA chips; and the two FPGA chips, a first power supply, a second power supply, a first crystal oscillator and a second crystal oscillator form a double-redundancy configuration, so that the two FPGA chips can be switched with each other, and when any FPGA chip is in a fault state, the other FPGA chip can realize a redundant function, thereby ensuring normal use of the whole optical trigger board. In addition, the trigger pulse signal redundant switching method is executed at an idle moment when the optical port transmitting module sends a trigger instruction of the flexible DC transmission valve, so that the integrity of a communication timing sequence of the flexible DC transmission valve sub-module is ensured, seamless switching can be realized, and when any FPGA chip is in a fault state, the other FPGA chip can continue to complete control and protection of the flexible DC transmission valve.

Description

Technical Field

[0001] This invention relates to the field of flexible DC power transmission technology, specifically to a DC power transmission converter valve optical trigger board and its trigger pulse signal redundancy switching method. Background Technology

[0002] DC transmission technology is a crucial component of building smart grids, primarily encompassing traditional DC transmission technology centered on Line Commutated Converters (LCCs) and flexible DC transmission technology centered on Voltage Source Converters (VSCs). In flexible DC transmission systems, the Valve-Based Controller (VBC), acting as an intermediary between pole control and protection devices and converter valves, is responsible for the operational control and safety protection of the converter valve submodules, the entire bridge arm, and even the entire converter valve system. Its operational reliability directly impacts the safety and stability of the DC transmission converter valves; therefore, redundant configurations are typically employed in engineering design.

[0003] The redundant configuration structure used in the optical trigger board of the DC transmission converter valve in the related technology has the problem that the downstream hardware structure is simple. If the downstream hardware structure fails, the redundancy function cannot be realized, and the entire optical trigger board still cannot be used normally. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problem that the redundant configuration structure adopted by the optical trigger board of the DC transmission converter valve in the prior art is such that if the downstream hardware structure fails, the redundancy function cannot be realized, and the entire optical trigger board still cannot be used normally. Thus, the present invention provides an optical trigger board for DC transmission converter valve and a method for redundancy switching of trigger pulse signals.

[0005] According to a first aspect, embodiments of the present invention provide a DC transmission converter valve optical trigger board, comprising: a first power supply, a second power supply, and a third power supply for supplying power to the DC transmission converter valve optical trigger board, and a first crystal oscillator and a second crystal oscillator for generating a clock signal on the DC transmission converter valve optical trigger board, and further comprising:

[0006] The first FPGA chip is connected to the first power supply and the first crystal oscillator respectively;

[0007] The second FPGA chip is connected to the second power supply, the second crystal oscillator and the first FPGA chip respectively;

[0008] At least one logic selection module is connected to the third power supply, the first FPGA chip and the second FPGA chip respectively;

[0009] At least one optical port transmitting module is connected to the third power supply, and each optical port transmitting module is connected to a corresponding logic selection module. The number of optical port transmitting modules is the same as the number of logic selection modules.

[0010] At least one waveform conditioning module is connected to the third power supply, the first FPGA chip and the second FPGA chip respectively;

[0011] At least one optical port receiving module is connected to the third power supply. Each optical port receiving module is connected to a corresponding waveform conditioning module. The number of optical port receiving modules is the same as the number of waveform conditioning modules, and the number of optical port receiving modules is the same as the number of optical port transmitting modules.

[0012] By implementing the first aspect, the present invention utilizes two FPGA chips that work in conjunction with each logic selection module, each optical port transmission module, each waveform conditioning module, and each optical port receiving module. Furthermore, the two FPGA chips, together with the first power supply, the second power supply, the first crystal oscillator, and the second crystal oscillator, form a dual redundancy configuration. Ultimately, this allows the two FPGA chips to switch between each other. If either FPGA chip is in a faulty state, the other FPGA chip can perform the redundancy function, thereby ensuring the normal operation of the entire optical trigger board.

[0013] In one embodiment of the first aspect, the communication signal between the first FPGA chip, the second FPGA chip, each logic selection module, each optical port transmitting module, each waveform conditioning module, and each optical port receiving module is a low-voltage differential signal.

[0014] By implementing the above embodiments, the present invention uses a low-voltage differential signal to avoid power supply coupling and improve anti-interference capability.

[0015] In another embodiment of the first aspect, the first FPGA chip and the second FPGA chip have the same structure, but the ID identity information set for them is different.

[0016] By implementing the above embodiments, this invention uses two FPGA chips with identical structures, but sets different ID information in the hardware, and can configure completely identical programs, thereby reducing the number of program versions and reducing maintenance costs.

[0017] In another embodiment of the first aspect, the data transmission port of the first FPGA chip is connected to the data reception port of the second FPGA chip, and the data transmission port of the second FPGA chip is connected to the data reception port of the first FPGA chip.

[0018] In another embodiment of the first aspect, the primary status signal or backup status signal or control status signal of the first FPGA chip and the second FPGA chip are transmitted through the data transmission port of the first FPGA chip and the data reception port of the second FPGA chip; or through the data transmission port of the second FPGA chip and the data reception port of the first FPGA chip.

[0019] By implementing the above embodiments, the present invention connects the data transmission port of the first FPGA chip to the data reception port of the second FPGA chip, and the data transmission port of the second FPGA chip to the data reception port of the first FPGA chip, thereby enabling flexible switching between the primary status signal, backup status signal, or control status signal of the two FPGA chips.

[0020] In another embodiment of the first aspect, the DC transmission converter valve optical trigger board described in this embodiment of the invention has the first FPGA chip connected to the first core control board and the second FPGA chip connected to the second core control board.

[0021] By implementing the above-described embodiments, the present invention connects two FPGA chips to their respective core control boards, enabling them to follow the communication timing of the upper-level board in real time.

[0022] In another embodiment of the first aspect, the communication interface between the first FPGA chip and the second FPGA chip is used to transmit working signals issued by the first core control board, or working signals issued by the second core control board, or busy signals issued by the first FPGA chip or the second FPGA chip, or control signals issued by the first FPGA chip or the second FPGA chip to each logic selection module.

[0023] By implementing the above embodiments, the first FPGA chip and the second FPGA chip can exchange working signals, busy signals, or control signals based on the communication interaction port.

[0024] In another embodiment of the first aspect, each optical port transmitting module includes: a transmitting optical port and a transmitting driving circuit, and each optical port receiving module includes: a receiving optical port and a receiving driving circuit.

[0025] In another embodiment of the first aspect, each logic selection module includes a plurality of first data selection ports, a plurality of first data input ports, and at least one data output port, wherein the at least one data output port is connected to the transmission drive circuit in each optical port transmission module.

[0026] In another embodiment of the first aspect, each logic selection module controls the transmission drive circuit in each optical port transmission module based on a digital truth table composed of multiple data selection ports, multiple data input ports, and at least one data output port.

[0027] By implementing the above embodiments, the present invention allows each logic selection module to control the transmission drive circuit in each optical port transmission module based on a digital truth table composed of multiple first data selection ports, multiple data input ports, and at least one data output port.

[0028] According to a second aspect, embodiments of the present invention also provide a method for trigger pulse signal redundancy switching, used in the optical trigger board of the DC transmission converter valve described in the first aspect or any embodiment of the first aspect, comprising the following steps:

[0029] Obtain the current signal indicating the state of the first or second FPGA chip;

[0030] If the current signal of the state of the first FPGA chip or the second FPGA chip is a working signal, control the first FPGA chip or the second FPGA chip to detect the control signals output by each logic selection module to each other.

[0031] When the first FPGA chip or the second FPGA chip is confirmed to be faulty based on the control signal, the normal FPGA chip is controlled to perform a redundancy switching action during idle time based on the control signal output by the counterpart to each logic selection module, and a trigger pulse signal is sent to each optical port transmission module.

[0032] By implementing the above-described embodiments, the present invention performs system switching during the idle time when the optical port transmitting module sends the trigger command for the flexible DC converter valve, ensuring the integrity of the communication timing of the flexible DC converter valve submodule and enabling seamless switching. If any FPGA chip fails, the other FPGA chip can continue to control and protect the flexible DC converter valve.

[0033] According to a third aspect, embodiments of the present invention also provide a trigger pulse signal redundancy switching device, comprising the following modules:

[0034] The current signal acquisition module is used to acquire the current signal of the state of the first FPGA chip or the second FPGA chip;

[0035] The first control module is used to control the first FPGA chip or the second FPGA chip to detect the control signals output by each other to each logic selection module if the current signal of the state of the first FPGA chip or the second FPGA chip is a working signal.

[0036] The second control module is used to control the normal FPGA chip to perform a redundancy switching action during idle time and send a trigger pulse signal to each optical port transmission module when the first FPGA chip or the second FPGA chip is confirmed to have failed based on the control signal.

[0037] According to a fourth aspect, embodiments of the present invention also provide a computer-readable storage medium storing computer instructions for causing the computer to execute the trigger pulse signal redundancy switching method described in the second aspect.

[0038] According to a fifth aspect, embodiments of the present invention also provide an electronic device, including: a memory and a processor, wherein the low-frequency power transmission voltage regulation system, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the trigger pulse signal redundancy switching method described in the second aspect. Attached Figure Description

[0039] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the optical trigger board structure of a DC transmission converter valve in the prior art, as shown in this embodiment of the invention.

[0041] Figure 2 This is a schematic diagram of another DC power transmission converter valve optical trigger board structure in the prior art of this invention;

[0042] Figure 3 This is a schematic diagram of the optical trigger board structure of the direct converter valve in an embodiment of the present invention;

[0043] Figure 4 This is a flowchart of the trigger pulse signal redundancy switching method in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the logical selection process during master-slave switching in an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of information interaction during master-slave switching in an embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of the master-slave switching timing in an embodiment of the present invention;

[0047] Figure 8 This is a hardware schematic diagram of the electronic device in an embodiment of the present invention.

[0048] Figure label:

[0049] 11-DC power transmission converter valve optical trigger board; 110-First power supply; 111-Second power supply;

[0050] 112 - Third power supply; 113 - First crystal oscillator; 114 - Second crystal oscillator;

[0051] 115 - First FPGA chip; 116 - Second FPGA chip; 117 - Logic selection module;

[0052] 118 - Optical port transmitting module; 119 - Waveform conditioning module; 120 - Optical port receiving module; 12 - First core control board; 13 - Second core control board. Detailed Implementation

[0053] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0055] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0056] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0057] As described in the background section, in related technologies, valve control redundancy design is mainly based on device-level redundancy, such as... Figure 1 As shown, the converter valve control and protection device in the valve control system uses two identical sets of devices, A and B, to achieve a redundancy configuration. It is generally believed that the optical trigger board of the fiber optic distribution panel directly connected to the converter valve cannot be redundant on a single board. Redundancy is typically achieved by using two identical trigger boards to send the same optical signal. However, using two identical trigger boards to send the same optical signal results in the two trigger boards only being able to send the same signal outward in pulses, which cannot be used to send protocol signals with strict time synchronization requirements.

[0058] Therefore, as Figure 2 As shown, the related technology discloses an optical trigger board for a flexible DC transmission converter valve, including at least two first FPGA components, a second FPGA component, an arbitration switch, and several optical ports. The first FPGA component includes a first FPGA, a first power supply, and a first crystal oscillator. The second FPGA component includes a second FPGA, at least two second power supplies, and at least two second crystal oscillators. The first power supply and the first crystal oscillator are connected to the first FPGA, and the second power supply and the second crystal oscillator are connected to the second FPGA. All first FPGAs are connected to the second FPGA, and all first FPGAs and the second FPGA are connected to the arbitration switch. The two first FPGA components and one second FPGA component are integrated onto a single board. Based on the arbitration switch, redundancy of the trigger pulse signal is achieved on a single board. The second FPGA component includes at least two second power supplies and two second crystal oscillators, allowing any one crystal oscillator in the circuit to be used.

[0059] Figure 2The existing technical solution is based on the combination of three FPGA components and arbitration switch to achieve dual redundancy. However, due to the large number of FPGA components in this solution, the economic efficiency is poor. Furthermore, it relies entirely on the second FPGA to achieve the redundancy function. The subsequent hardware structure connected to the second FPGA is simple. If the subsequent hardware structure fails, the redundancy function cannot be achieved, and the entire optical trigger board will still be unable to function properly.

[0060] To address the aforementioned issues, this invention provides a DC-DC converter valve optical trigger board and a redundancy switching method for trigger pulse signals. This involves two FPGA chips working in conjunction with various logic selection modules, optical port transmitting modules, waveform conditioning modules, and optical port receiving modules. Furthermore, the two FPGA chips, along with a first power supply, a second power supply, a first crystal oscillator, and a second crystal oscillator, form a dual-redundancy configuration. This allows the two FPGA chips to switch between each other. If either FPGA chip fails, the other FPGA chip provides redundancy, ensuring the normal operation of the entire optical trigger board. Additionally, the trigger pulse signal redundancy switching method performs the switching during idle moments when the optical port transmitting module sends trigger commands to the flexible DC-DC converter valve. This ensures the integrity of the communication timing of the flexible DC-DC converter valve submodules and enables seamless switching. Even if one FPGA chip fails, the other FPGA chip can continue to control and protect the flexible DC-DC converter valve. The above solution will be described in detail below.

[0061] This invention provides a DC transmission converter valve optical trigger board, such as... Figure 3 As shown, it includes: a first power supply 110, a second power supply 111 and a third power supply 112 for powering the optical trigger board 11 of the DC transmission converter valve, and a first crystal oscillator 113 and a second crystal oscillator 114 for generating clock signals on the optical trigger board of the DC transmission converter valve.

[0062] In addition, Figure 3 In this embodiment of the invention, the optical trigger board of the DC transmission converter valve further includes: a first FPGA chip 115, a second FPGA chip 116, four logic selection modules 117, four optical port transmission modules 118, four waveform conditioning modules 119, and four optical port receiving modules 120. The number of logic selection modules 117, optical port transmission modules 118, waveform conditioning modules 119, and optical port receiving modules 120 are the same, and there is at least one of each, but not limited to... Figure 3 The four of them.

[0063] exist Figure 3In this configuration, a first FPGA chip 115 is connected to a first power supply 110 and a first crystal oscillator 113. Specifically, the first FPGA chip 115 is connected to the first power supply 110 via a first power port and to the first crystal oscillator 113 via a first crystal oscillator port. A second FPGA chip 116 is connected to a second power supply 111, a second crystal oscillator 114, and the first FPGA chip 115. Specifically, the second FPGA chip 116 is connected to the second power supply 111 via a second power port, to the second crystal oscillator 114 via a second crystal oscillator port, and to the first FPGA chip 115 via a communication port. Each logic selection module 117 is connected to the third power supply 112, the first FPGA chip 115, and the second FPGA chip 116, respectively. Specifically, each logic selection module 117 can be connected to the third power supply 112 through a third power supply port, each logic selection module 117 can be connected to the data selection ports of the first FPGA chip 115 and the second FPGA chip 116 through its data selection port, and each logic selection module 117 can be connected to the data transmission ports of the first FPGA chip 115 and the second FPGA chip 116 through its data input port. Each optical port transmission module 118 is connected to the third power supply 112, specifically through a third power supply port. Each optical port transmission module 118 is correspondingly connected to each logic selection module 117, and the number of optical port transmission modules 118 is the same as the number of logic selection modules 117. Each waveform conditioning module 119 is connected to the third power supply 112, the first FPGA chip 115, and the second FPGA chip 116, respectively. Specifically, each waveform conditioning module 119 is connected to the third power supply 112 through a third power supply port, connected to the data receiving ports of the first FPGA chip 115 and the second FPGA chip 116 through its waveform conditioning port, and connected to the receiving optical port of each optical port receiving module 120 through its data input port. Each optical port receiving module 120 is connected to the third power supply 112, specifically through a third power supply port. Each optical port receiving module 120 is correspondingly connected to each waveform conditioning module 119. The number of optical port receiving modules 120 is the same as the number of waveform conditioning modules 119, and the number of optical port receiving modules 120 is the same as the number of optical port transmitting modules 118.

[0064] exist Figure 3 In the process, each waveform conditioning module can shape the waveform of the converter valve report data collected by the receiving optical port module, and then divide it into two information channels and send them to two FPGA chips respectively, so as to realize the redundancy distribution of the report signal of the flexible DC converter valve.

[0065] The optical trigger board of the DC power transmission converter valve in this embodiment of the invention works in cooperation with each logic selection module, each optical port transmission module, each waveform conditioning module and each optical port receiving module through two FPGA chips; and the two FPGA chips, together with the first power supply, the second power supply, the first crystal oscillator and the second crystal oscillator, form a dual redundancy configuration, which can ultimately enable the two FPGA chips to switch with each other. If either FPGA chip is in a fault state, the other FPGA chip will realize the redundancy function, thereby ensuring the normal use of the entire optical trigger board.

[0066] In one embodiment, the communication signal between the first FPGA chip, the second FPGA chip, each logic selection module, each optical port transmitting module, each waveform conditioning module, and each optical port receiving module of the DC transmission converter valve optical trigger board in this embodiment of the invention is a low voltage differential signal. This low voltage differential signal is abbreviated as LVDS (Low Voltage Differential Signaling). Using this low voltage differential signal can avoid power supply coupling and improve anti-interference capability.

[0067] In one embodiment, the DC transmission converter valve optical trigger board of this invention has the same structure for the first FPGA chip and the second FPGA chip, but they have different ID identification information. For example, the first FPGA chip and the second FPGA chip have the same model, the same internal program, and the same number of pin ports, and they can be distinguished by the ID identification information they are set.

[0068] In one embodiment, the DC transmission converter valve optical trigger board of the present invention has a data transmission port of the first FPGA chip connected to a data receiving port of the second FPGA chip, and the data transmission port of the second FPGA chip connected to a data receiving port of the first FPGA chip.

[0069] The primary status signal, backup status signal, or control status signal of the first FPGA chip and the second FPGA chip are transmitted through the data transmission port of the first FPGA chip and the data reception port of the second FPGA chip; or, through the data transmission port of the second FPGA chip and the data reception port of the first FPGA chip.

[0070] For example: the first transmit pin (ActiveMe) of the first FPGA chip is used to send the status information of whether the internal system of the first FPGA chip is "primary" or "standby"; it is connected to the first receive pin (ActiveOther) of the second FPGA chip; the first receive pin (ActiveOther) of the first FPGA chip is used to receive the status information of whether it is "primary" or "standby" sent by the second FPGA chip; it is connected to the first transmit pin (ActiveMe) of the second FPGA chip.

[0071] For example, the second transmit pin (CtrSigMe) of the first FPGA chip is connected to the second receive pin (CtrSigOther) of the second FPGA chip, and is used to transmit data selection control information of the first FPGA chip to the logic selection module; the second receive pin (CtrSigOther) of the first FPGA chip is connected to the second transmit pin (CtrSigMe) of the second FPGA chip, and is used to receive data selection control information of the second FPGA chip to the logic selection module.

[0072] In one embodiment, the optical trigger board of the DC transmission converter valve in this invention, in Figure 3 In the process, the first FPGA chip 115 is connected to the first core control board 12, and the second FPGA chip 116 is connected to the second core control board 13.

[0073] In one embodiment, the communication interface between the first FPGA chip and the second FPGA chip in the DC transmission converter valve optical trigger board of this invention is used to transmit working signals issued by the first core control board, or working signals issued by the second core control board, or busy signals issued by the first or second FPGA chip, or control signals issued by the first or second FPGA chip to each logic selection module. The two FPGA chips follow the communication timing of their respective upper-level boards (the first core control board and the second core control board).

[0074] The above-mentioned working signals issued by the first core control board or the second core control board are the duty signals (i.e., Active signals) issued by the upper-level board, and the busy signals (i.e., Busy signals) issued by the first FPGA chip or the second FPGA chip.

[0075] In one embodiment, the optical trigger board of the DC transmission converter valve in this invention includes an optical port transmitting module comprising a transmitting optical port and a transmitting drive circuit, and an optical port receiving module comprising a transmitting interface and a receiving drive circuit. The transmitting drive circuit drives the transmitting optical port to operate, and the receiving drive circuit drives the receiving optical port to operate.

[0076] In one embodiment, the DC transmission converter valve optical trigger board of the present invention includes a plurality of data selection ports, a plurality of data input ports and at least one data output port in each logic selection module, and the at least one data output port is connected to the transmission drive circuit in each optical port transmission module.

[0077] For example, each logic selection module includes two data selection ports (S0) and one data selection port (S1); four data input ports (In0), (In1), (In2), and (In3); and one data output port (Out). Specifically, data selection port (S0) is connected to the second transmit pin (CtrSigMe) of the first FPGA chip, and data selection port (S1) is connected to the second transmit pin (CtrSigMe) of the second FPGA chip. Data input ports (In1) and (In2) are connected to the first FPGA chip. Data input ports (In0) and (In3) are connected to the second FPGA chip. The data output port (Out) is connected to the transmit driver circuit in each optical port transmission module.

[0078] In one embodiment, the optical trigger board of the DC transmission converter valve in this invention uses a logic selection module to control the transmission drive circuit in each optical port transmission module based on a digital truth table composed of multiple data selection ports, multiple data input ports, and at least one data output port. The truth table of each logic selection module is shown in Table 1 below.

[0079] Table 1

[0080]

[0081]

[0082] The truth table in Table 1 above allows two FPGA chips to control the transmit optical port. By setting different ID information, the same program can be used with different truth tables to take over the control of each logic selection module, thereby reducing the number of program versions and maintenance costs.

[0083] The DC transmission converter valve optical trigger board in this embodiment of the invention adopts a dual FPGA chip configuration, which has a low cost. It only requires configuring the corresponding logic selection module, optical port transmission module, waveform conditioning module and optical port receiving module in the subsequent circuit of the dual FPGA chips, which can ultimately improve the reliability of redundancy.

[0084] Based on the same concept, this invention also provides a method for redundancy switching of trigger pulse signals, used in the optical trigger board of the DC transmission converter valve in the above embodiments, such as... Figure 4As shown, it includes the following steps:

[0085] Step S41: Obtain the current signal of the state of the first FPGA chip or the second FPGA chip.

[0086] Step S42: If the current signal of the state of the first FPGA chip or the second FPGA chip is a working signal, control the first FPGA chip or the second FPGA chip to detect the control signals output by each logic selection module.

[0087] Step S43: When the first FPGA chip or the second FPGA chip is confirmed to be faulty based on the control signal, the normal FPGA chip is controlled to perform a redundancy switching action during idle time based on the control signal output by the other party to each logic selection module, and a trigger pulse signal is sent to each optical port transmission module.

[0088] For example, if the current signal of either the first or second FPGA chip is a working signal (i.e., a duty signal), then either FPGA chip can control the corresponding logic selection module to send its own trigger pulse signal to the transmit optical port. The FPGA chip in "duty" mode monitors the control signals sent by the other FPGA chip to the corresponding logic selection module in real time. Combining this with its own ID information, the chip only needs to select and output the control signal it sent to the corresponding logic selection module to control that module to select its own trigger pulse signal.

[0089] Based on this, if the on-duty FPGA chip executes the switching logic when its own and another FPGA's "Busy" signal is 0, it ensures that the system can communicate with the flexible DC converter valve submodule before and after the switch. The "switching logic" is executed instantaneously during idle periods (i.e., non-"Busy" periods), without affecting the transmission of optical trigger commands during normal triggering periods. The "Busy" signal is a periodically changing signal and is also the lifeline of the FPGA chip. If any FPGA chip fails, this lifeline will no longer change periodically and can be quickly detected by the other FPGA chip.

[0090] The trigger pulse signal redundancy switching method in this embodiment of the invention, such as... Figure 5 The diagram shows the logical selection process in four typical master-slave switching processes.

[0091] exist Figure 5In (a), the first FPGA chip is in the on-duty state (i.e., ActiveA=1), and the second FPGA chip is in the off-duty state (i.e., ActiveB=0). At this time, the CtrSigMe output of the first FPGA chip is 1, and the CtrSigMe output of the second FPGA chip is 0. The logic selection module selects the input of In1 (i.e., the current signal of the first FPGA chip is the control signal) as the final output to control the optical port transmission module.

[0092] exist Figure 5 .(a) becomes Figure 5 (b) This indicates that a master-slave switch has occurred. At this time, the second FPGA chip in the new duty state detects that the first FPGA chip's CtrSigMe = 1. The second FPGA chip adjusts its own output CtrSigMe to 1. That is, the control logic selection module takes the input of In3 (i.e., the current signal of the second FPGA chip is the control signal) as the final output to control the optical port transmission module.

[0093] exist Figure 5 (b) becomes Figure 5 (c) This indicates that another master-slave switch has occurred. At this time, the first FPGA in the new duty state detects that the second FPGA's CtrSigMe = 1. The first FPGA adjusts its own output CtrSigMe to 0. That is, the control logic selection module takes the input of In2 (i.e., the current signal of the first FPGA chip is the control signal) as the final output to control the optical port transmission module.

[0094] exist Figure 5 In (c), it becomes... Figure 5 (d) This indicates that another master-slave switch has occurred. At this time, the second FPGA in the new duty state detects that the first FPGA chip's CtrSigMe = 0. The second FPGA chip adjusts its own output CtrSigMe to 0. That is, the control logic selection module takes the input of In0 (i.e., the current signal of the second FPGA chip is the control signal) as the final output to control the optical port transmission module.

[0095] If a switch to slave occurs again, the process repeats. Figure 5 (a) control signal.

[0096] like Figure 6 As shown, this is a schematic diagram of information interaction during master-slave switching. The two FPGAs exchange the duty signal (i.e., Active signal) and idle state (i.e. "Busy signal") sent by the upper-level board to perform master-slave logic judgment. This logic judgment is executed during the idle time (i.e., Busy=0).

[0097] like Figure 7 The diagram shown is a master-slave switching timing diagram. Figure 7 (a) This indicates that both the first FPGA and the second FPGA are busy transmitting (BusyMe / BusyOther are both 0). If a master-slave switch occurs at this time, the switch can be implemented immediately (i.e., Active changes position).

[0098] Figure 7 (b) Indicates that the first FPGA chip is busy transmitting (i.e., BusyMe=1). If a master-slave switch occurs at this time, it is necessary to wait until both the first FPGA chip and the second FPGA chip are no longer busy transmitting before the switch can be performed (i.e., Active changes).

[0099] If a master-slave switch is required while the second FPGA chip is busy sending data, then... Figure 7 (b) Same.

[0100] Figure 7 (c) This indicates that after both the first and second FPGA chips are busy transmitting (BusyMe / BusyOther are both 0), if a master-slave switch occurs at this time, the switch can be implemented immediately (i.e., Active changes position).

[0101] Figure 7 (d) indicates that both the first FPGA chip and the second FPGA chip are not in the transmission busy state (BusyMe / BusyOther are both 0). If a master-slave switch occurs at this time, the switch can be implemented immediately (i.e., Active changes position).

[0102] In this embodiment of the invention, the trigger pulse signal redundancy switching method allows the newly activated FPGA chip to take over control of the logic selection module simply by adjusting its own output control signal, based on the control signal output by the other FPGA chip to the logic selection module. During the redundancy switching process, the differences in the control timing of the two FPGA chips are carefully considered. System switching is performed during the idle time when the optical port transmitting module sends the trigger command for the flexible DC converter valve, ensuring the integrity of the communication timing of the flexible DC converter valve submodule and enabling seamless switching. Even if one FPGA chip fails, the other FPGA chip can continue to control and protect the flexible DC converter valve.

[0103] Based on the same concept, embodiments of the present invention also provide a trigger pulse signal redundancy switching device, comprising the following modules:

[0104] The current signal acquisition module is used to acquire the current signal of the state of the first FPGA chip or the second FPGA chip.

[0105] The first control module is used to control the first FPGA chip or the second FPGA chip to detect the control signals output by each other to the logic selection modules if the current signal of the state of the first FPGA chip or the second FPGA chip is a working signal.

[0106] The second control module is used to control the normal FPGA chip to perform redundancy switching during idle time based on the control signals output by the other party to each logic selection module when the first FPGA chip or the second FPGA chip is confirmed to have failed based on the control signals. It also sends trigger pulse signals to each optical port transmission module.

[0107] Based on the same concept, embodiments of the present invention also provide an electronic device, such as... Figure 8 As shown, the electronic device may include a processor 81 and a memory 82, wherein the processor 81 and the memory 82 can be connected via a bus or other means. Figure 8 Taking the example of a connection between China and Israel via a bus.

[0108] Processor 81 can be a central processing unit (CPU). Processor 81 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0109] The memory 82, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules. The processor 81 executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory 82, thereby implementing the trigger pulse signal redundancy switching method in the above method embodiments.

[0110] The memory 82 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor 81, etc. Furthermore, the memory 82 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 82 may optionally include memory remotely located relative to the processor 81, and these remote memories may be connected to the processor 81 via a network. Examples of such networks include, but are not limited to, power grids, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0111] The one or more modules are stored in the memory 82, and when executed by the processor 81, the trigger pulse signal redundancy switching method as shown in the embodiment of the attached figure is executed.

[0112] The specific details of the above-mentioned electronic device can be understood by referring to the relevant descriptions and effects in the embodiments shown in the accompanying drawings, and will not be repeated here.

[0113] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0114] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A DC transmission converter valve optical trigger board, comprising: The system comprises a first power supply, a second power supply, and a third power supply for supplying power to the optical trigger board of the DC transmission converter valve, and a first crystal oscillator and a second crystal oscillator for generating a clock signal on the optical trigger board of the DC transmission converter valve. The system is characterized by further comprising: The first FPGA chip is connected to the power supply and the first crystal oscillator respectively; The second FPGA chip is connected to the second power supply, the second crystal oscillator and the first FPGA chip respectively; At least one logic selection module is connected to the third power supply, the first FPGA chip and the second FPGA chip respectively; At least one optical port transmitting module is connected to the third power supply, and each optical port transmitting module is connected to a corresponding logic selection module. The number of optical port transmitting modules is the same as the number of logic selection modules. At least one waveform conditioning module is connected to the third power supply, the first FPGA chip and the second FPGA chip respectively; At least one optical port receiving module is connected to the third power supply, and each optical port receiving module is connected to a corresponding waveform conditioning module. The number of optical port receiving modules is the same as the number of waveform conditioning modules, and the number of optical port receiving modules is the same as the number of optical port transmitting modules. The logic selection module includes two data selection ports S0 and S1; four data input ports In0, In1, In2, and In3; and one data output terminal Out. Data selection port S0 is connected to the second transmit pin CtrSigMe of the first FPGA chip, data selection port S1 is connected to the second transmit pin CtrSigMe of the second FPGA chip, data input ports In1 and In2 are connected to the first FPGA chip, data input ports In0 and In3 are connected to the second FPGA chip, and the data output terminal Out is connected to the transmit drive circuit in each optical port transmit module. The redundancy switching method for trigger pulse signals on the optical trigger board of the DC transmission converter valve executes the control process, which includes the following steps: Obtain the current signal indicating the state of the first or second FPGA chip; If the current signal of the state of the first FPGA chip or the second FPGA chip is a working signal, control the first FPGA chip or the second FPGA chip to detect the control signals output by each logic selection module to each other. When the first FPGA chip or the second FPGA chip is confirmed to be faulty based on the control signal, the normal FPGA chip is controlled to perform a redundancy switching action during idle time based on the control signal output by the counterpart to each logic selection module, and a trigger pulse signal is sent to each optical port transmission module. The normally functioning FPGA chip performs redundancy switching during idle periods and sends trigger pulse signals to each optical port transmitter module. The specific master-slave switching process includes: When the first FPGA chip is in the on-duty state and the second FPGA chip is in the off-duty state, the first FPGA chip outputs CtrSigMe=1 and the second FPGA chip outputs CtrSigMe=0. The logic selection module selects the input of the data input port In1 as the final output to control the optical port transmission module. When the second FPGA chip detects that the first FPGA chip's CtrSigMe=1, the second FPGA chip in the new shift state adjusts its own output CtrSigMe to 1, and the logic selection module selects the data input port In3 as the final output to control the optical port transmission module. When the first FPGA in the new duty state detects that the second FPGA's CtrSigMe=1, the first FPGA adjusts its own output CtrSigMe to 0, and the logic selection module selects the input of the data input port In2 as the final output to control the optical port transmission module. When the second FPGA in the new duty state detects that the first FPGA chip's CtrSigMe=0, the second FPGA chip adjusts its own output CtrSigMe to 0, and the logic selection module selects the input of the data input port In0 as the final output to control the optical port transmission module.

2. The optical trigger board for DC power transmission converter valve according to claim 1, wherein the communication signal between the first FPGA chip, the second FPGA chip, each logic selection module, each optical port transmitting module, each waveform conditioning module, and each optical port receiving module is a low-voltage differential signal.

3. The DC transmission converter valve optical trigger board according to claim 1 or 2, wherein the first FPGA chip and the second FPGA chip have the same structure, but the ID identity information set for the two is different.

4. The optical trigger board for the DC transmission converter valve according to claim 3, characterized in that, The data transmission port of the first FPGA chip is connected to the data reception port of the second FPGA chip, and the data transmission port of the second FPGA chip is connected to the data reception port of the first FPGA chip.

5. The optical trigger board for the DC transmission converter valve according to claim 4, characterized in that, The primary status signal, backup status signal, or control status signal of the first FPGA chip and the second FPGA chip are transmitted through the data transmission port of the first FPGA chip and the data reception port of the second FPGA chip; or through the data transmission port of the second FPGA chip and the data reception port of the first FPGA chip.

6. The optical trigger board for a DC transmission converter valve according to claim 1, 4, or 5, characterized in that, The communication interface between the first FPGA chip and the second FPGA chip is used to transmit working signals issued by the first core control board, or working signals issued by the second core control board, or busy signals issued by the first FPGA chip or the second FPGA chip, or control signals issued by the first FPGA chip or the second FPGA chip to each logic selection module.

7. The optical trigger board for the DC transmission converter valve according to claim 1, characterized in that, Each optical port transmitting module includes a transmitting optical port and a transmitting driving circuit, and each optical port receiving module includes a receiving optical port and a receiving driving circuit.

8. The optical trigger board for the DC transmission converter valve according to claim 7, characterized in that, Each logic selection module includes multiple data selection ports, multiple data input ports, and at least one data output port. The at least one data output port is connected to the transmission drive circuit in each optical port transmission module.

9. The DC transmission converter valve optical trigger board according to claim 8, wherein each logic selection module controls the transmission drive circuit in each optical port transmission module based on a digital truth table formed by combining the plurality of data selection ports, the plurality of data input ports and the at least one data output port.

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