amplification circuit

Abstract

An amplification circuit with common mode voltage compensation circuit is provided. The common mode voltage compensation circuit has a first compensation resistor coupled between an input of a loop filter of the amplification circuit and a control node, and a second compensation resistor coupled between another input of the loop filter and the control node. The control node is coupled to a ground voltage when both output signals of the amplification circuit are high, and the control node is coupled to a power supply voltage when both output signals of the amplification circuit are low.

Description

Technical Field

[0001] This disclosure generally relates to amplification techniques, and more specifically, to an amplification circuit. Background Technology

[0002] Class-D amplifiers, also known as switching amplifiers or pulse-width modulation (PWM) amplifiers, use PWM control to ensure that the metal-oxide-semiconductor (MOS) transistors in the power driver are either fully on or fully off, significantly reducing power loss and achieving high-efficiency amplification.

[0003] There are several ways to convert analog signals into PWM signals to drive the MOS transistors of a power driver. To eliminate the need for an output filter, BD modulation switching technology has been developed. According to BD modulation switching technology, the duty cycle difference between the two output signals VOP and VON of a Class D amplifier is modulated so that the average content of the amplified result corresponds to the analog input signal. A Class D amplifier is a closed-loop circuit. The larger the analog input signal, the greater the difference in PWM width between the two output signals.

[0004] However, BD modulation switching technology can cause common-mode voltage fluctuations. Figure 1 The diagram illustrates the waveforms of the output signals VOP and VON and their common-mode voltage Out_CM. The ideal value for the common-mode voltage Out_CM is VDD / 2. When both output signals VOP and VON are low ('L', e.g., 0V), the common-mode voltage Out_CM is 0V. When both output signals VOP and VON are high ('H', e.g., VDD), the common-mode voltage Out_CM is VDD. The common-mode voltage Out_CM fluctuates significantly (0V or VDD) instead of being held at VDD / 2. When the common-mode voltage is fed back to the loop filter of the Class D amplifier, the common-mode voltage fluctuation reduces the gain of the differential operational amplifier within the loop filter.

[0005] Therefore, a Class D amplifier that can suppress or reduce common-mode voltage fluctuations is needed. Summary of the Invention

[0006] The following summary is illustrative only and is not intended to be limiting in any way. That is, it provides an overview to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Therefore, the following summary is neither intended to identify the essential features of the claimed subject matter nor to define the scope of the claimed subject matter.

[0007] One of the objectives of this invention is to provide an amplifier circuit (e.g., a Class D amplifier utilizing PWM technology) that can reduce or eliminate common-mode voltage fluctuations.

[0008] An amplifier circuit according to an exemplary embodiment of the present invention includes a loop filter, a pulse width modulation signal generator, a gate driver, a power driver, a signal feedback circuit, and a common-mode voltage compensation circuit. The loop filter, the pulse width modulation signal generator, the gate driver, the power driver, and the signal feedback circuit form a loop for signal amplification; and the common-mode voltage compensation circuit provides a control node coupled to a first input terminal and a second input terminal of the loop filter; wherein: when both the first output signal and the second output signal of the amplifier circuit are high, the common-mode voltage compensation circuit couples the control node to ground; and when both the first output signal and the second output signal of the amplifier circuit are low, the common-mode voltage compensation circuit couples the control node to a power supply voltage.

[0009] In some embodiments, the loop filter has a differential operational amplifier, with a first input terminal and a second input terminal of the loop filter coupled to a pair of input terminals of the differential operational amplifier; the signal feedback circuit includes a first feedback resistor and a second feedback resistor, the first feedback resistor coupling the first output signal of the amplifier circuit to the second input terminal of the loop filter, and the second feedback resistor coupling the second output signal of the amplifier circuit to the first input terminal of the loop filter; the common-mode voltage compensation circuit includes a first compensation resistor and a second compensation resistor, the first compensation resistor being coupled between the second input terminal of the loop filter and the control node, and the second compensation resistor being coupled between the first input terminal of the loop filter and the control node.

[0010] In some embodiments, the common-mode voltage compensation circuit is a switching digital-to-analog converter, and the common-mode voltage compensation circuit further includes: a first switch controlled to selectively couple the control node to the power supply voltage; and a second switch controlled to selectively couple the control node to the ground voltage. Unlike using active components, the switching digital-to-analog converter can save power. Furthermore, signal feedback is unaffected by common-mode voltage compensation.

[0011] In some embodiments, the power driver includes: a first p-channel silicon-oxide-semiconductor transistor (SiO2), controlled by a first control signal generated by the gate driver, to selectively couple a first output terminal of the amplifier circuit to the power supply voltage, thereby selectively pulling up the first output signal of the amplifier circuit; a first n-channel SiO2 transistor, controlled by a second control signal generated by the gate driver, to selectively couple the first output terminal of the amplifier circuit to the ground voltage, thereby selectively pulling down the first output signal of the amplifier circuit; a second p-channel SiO2 transistor, controlled by a third control signal generated by the gate driver, to selectively couple a second output terminal of the amplifier circuit to the power supply voltage, thereby selectively pulling up the second output signal of the amplifier circuit; and a second n-channel SiO2 transistor, controlled by a fourth control signal generated by the gate driver, to selectively couple the second output terminal of the amplifier circuit to the ground voltage, thereby selectively pulling down the second output signal of the amplifier circuit.

[0012] In some embodiments, the first switch is controlled by the first control signal and the third control signal; and the second switch is controlled by the second control signal and the fourth control signal.

[0013] In some embodiments, the first switch includes a third p-channel metal-oxide-semiconductor transistor, the source of which is coupled to the power supply voltage and the drain of which is coupled to the control node; and the second switch is a third n-channel metal-oxide-semiconductor transistor, the source of which is coupled to the ground voltage and the drain of which is coupled to the control node.

[0014] In some embodiments, the common-mode voltage compensation circuit further includes: a NAND gate, which receives the first control signal and the third control signal, and whose output terminal is coupled to the gate terminal of the third p-channel metal-oxide-semiconductor transistor; and a NOR gate, which receives the second control signal and the fourth control signal, and whose output terminal is coupled to the gate terminal of the third n-channel metal-oxide-semiconductor transistor.

[0015] In some embodiments, the common-mode voltage compensation circuit further includes: a first capacitor, which is connected in series with the first compensation resistor between the second input terminal of the loop filter and the control node; and a second capacitor, which is connected in series with the second compensation resistor between the first input terminal of the loop filter and the control node.

[0016] In some embodiments, the resistance ratio between the first feedback resistor and the first compensation resistor is equal to the resistance ratio between the second feedback resistor and the second compensation resistor.

[0017] In some embodiments, the first feedback resistor and the first compensation resistor have the same resistance value, and the second feedback resistor and the second compensation resistor have the same resistance value.

[0018] In some embodiments, the first feedback resistor, the second feedback resistor, the first compensation resistor, and the second compensation resistor have the same resistance value.

[0019] In some embodiments, the amplifier circuit uses the first output signal and the second output signal as positive and negative output signals, respectively, to drive the load; and the differential operational amplifier in the loop filter has a positive input terminal and a negative input terminal, the first input terminal of the loop filter is coupled to the positive input terminal of the differential operational amplifier, and the second input terminal of the loop filter is coupled to the negative input terminal of the differential operational amplifier.

[0020] In some embodiments, the amplifier circuit uses the first output signal and the second output signal as positive and negative output signals, respectively, to drive the load; and the differential operational amplifier in the loop filter has a positive input terminal and a negative input terminal, the first input terminal of the loop filter is coupled to the negative input terminal of the differential operational amplifier, and the second input terminal of the loop filter is coupled to the positive input terminal of the differential operational amplifier.

[0021] In some embodiments, the amplifier circuit is a Class D amplifier.

[0022] These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] A more complete understanding of the invention can be obtained by reading the following detailed description and referring to the examples given in the accompanying drawings, wherein:

[0024] Figure 1 This is a waveform diagram of the output signals VOP and VON and their common-mode voltage Out_CM.

[0025] Figure 2 A schematic diagram of an amplifier circuit according to an exemplary embodiment of the present invention is shown.

[0026] Figure 3 A schematic diagram of an amplifier circuit according to another exemplary embodiment of the present invention is shown.

[0027] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art may more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0028] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0029] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0030] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0031] Figure 2An amplifier circuit in a differential input and differential output architecture according to an exemplary embodiment of the present invention is shown. The amplifier circuit includes a loop filter 202, a pulse width modulation (PWM) signal generator 204, a gate driver 206, a power driver 208, a signal feedback circuit 210, and a common-mode voltage compensation circuit 212. The loop filter 202, PWM signal generator 204, gate driver 206, power driver 208, and signal feedback circuit 210 are configured to form a loop for signal amplification. The common-mode voltage compensation circuit 212 is used / designed to compensate for common-mode voltage fluctuations. Specifically, the common-mode voltage compensation circuit 212 is configured to compensate for the common-mode voltage when the output signals VOP and VON are simultaneously high or simultaneously low, for example, maintaining the common-mode voltage at VDD / 2. Understandably, when the output signals VOP and VON are not simultaneously high or simultaneously low, the transistors Mp1 and Mp2 in the common-mode voltage compensation circuit 212 are turned off.

[0032] As shown in the figure, the differential input pair (Vi1, Vi2) received by the amplifier circuit is coupled to a loop filter 202. The loop filter 202 is coupled to a PWM signal generator 204. In one example, by comparing the signal received from the loop filter 202 with a sawtooth signal Vsaw, the PWM signal generator 204 generates PWM signals Vpwmp and Vpwmn. It should be noted that the PWM signal generator is a well-known structure in the art, and the present invention is not limited to this. Figure 2Example from the diagram. Gate driver 206 converts PWM signals Vpwmp and Vpwmn into control signals CSAp, CSAn, CSBp, and CSBn. Power driver 208 includes an H-bridge circuit controlled by the control signals CSAp, CSAn, CSBp, and CSBn ​​to generate output signals VOP and VON to drive load 214. Output signals VOP and VON are fed back to loop filter 202 via signal feedback circuit 210. Common-mode voltage compensation circuit 212 is provided to compensate for fluctuations in the common-mode voltage Out_CM of output signals VOP and VON. It should be noted that the focus of this invention is on the common-mode voltage compensation circuit 212; other structures (such as loop filter 202, PWM signal generator 204, gate driver 206, power driver 208, and signal feedback circuit 210) are merely examples for ease of explanation and understanding.

[0033] The loop filter 202 includes a differential operational amplifier (op). The loop filter 202 has two input terminals, IN1 and IN2, which are coupled to a pair of input terminals of the differential operational amplifier op within the loop filter 202. Stable common-mode voltages are required at the two input terminals IN1 and IN2.

[0034] exist Figure 2In the exemplary embodiment shown, the signal feedback circuit 210 includes a feedback resistor Rfbp and a feedback resistor Rfbn. The feedback resistor Rfbp couples the output signal VOP to the input terminal IN2 of the loop filter 202, and the feedback resistor Rfbn couples the output signal VON to the input terminal IN1 of the loop filter 202. The common-mode voltage compensation circuit 212 includes a compensation resistor RCMp and a compensation resistor RCMn. The compensation resistor RCMp is coupled between the input terminal IN2 of the loop filter 202 and the control node ncs, and the compensation resistor RCMn is coupled between the input terminal IN1 of the loop filter 202 and the control node ncs. The common-mode voltage compensation circuit 212 is a switching DAC (digital-to-analog converter). In addition to the resistors RCMp and RCMn, the common-mode voltage compensation circuit 212 includes a switching design and logic circuitry for controlling the switching design. When both output signals VOP and VON are high, the switch design is configured to couple the control node ncs to ground voltage (GND). When both output signals VOP and VON are low, the switch design is configured to couple the control node ncs to the power supply voltage (VDD). In these cases, the feedback resistor Rfbp is combined with the compensation resistor RCMp, and the feedback resistor Rfbn is combined with the compensation resistor RCMn; two voltage dividers are established. That is, the feedback resistor Rfbp and the compensation resistor RCMp form one voltage divider, and the feedback resistor Rfbn and the compensation resistor RCMn form another voltage divider. Through these two voltage dividers, the two input terminals IN1 and IN2, coupled to a pair of input terminals of the differential operational amplifier op, are biased at the same stable DC voltage level. Common-mode voltage fluctuations are suppressed.

[0035] This section describes the structure of the power driver 208. The power driver 208 includes p-channel metal-oxide-silicon (PMOS) transistors Mp1 and Mp2, and n-channel metal-oxide-silicon (NMOS) transistors Mn1 and Mn2. PMOS transistor Mp1 is controlled by the control signal CSAp to pull the output signal VOP up to the power supply voltage VDD. NMOS transistor Mn1 is controlled by the control signal CSAn to pull the output signal VOP down to ground voltage GND. PMOS transistor Mp2 is controlled by the control signal CSBp to pull the output signal VON up to the power supply voltage VDD. NMOS transistor Mn2 is controlled by the control signal CSBn ​​to pull the output signal VON down to ground voltage GND. The control signals CSAp, CSAn, CSBp, and CSBn ​​are also used to switch the common-mode voltage compensation circuit 212.

[0036] The common-mode voltage compensation circuit 212 uses PMOS transistor Mp3 and NMOS transistor Mn3 in its switching design. When both output signals VOP and VON are high, the switch implemented by PMOS transistor Mp3 (in this embodiment, PMOS transistor Mp3 can also be called switch Mp3) is open (or disconnected), and the switch implemented by NMOS transistor Mn3 (in this embodiment, NMOS transistor Mn3 can also be called switch Mn3) is closed (or connected), thereby controlling the ground voltage GND of the control node ncs. The high level of the output signal VOP is divided by resistors Rfbp and RCMp. A stable DC voltage level VDD*RCMp / (Rfbp+RCMp) is provided to the input terminal IN2 of the loop filter 202. Similarly, the high voltage level of the output signal VON is divided by resistors Rfbn and RCMn. A stable DC voltage level VDD*RCMn / (Rfbn+RCMn) is provided to the input terminal IN1 of the loop filter 202. In an exemplary embodiment, switches Mp3 and Mn3 are opened or closed according to control signals CSAp, CSAn, CSBp, and CSBn ​​generated by the gate driver 206.

[0037] exist Figure 2The logic circuit, including NAND gate 216 and NOR gate 218, is used to control switches Mp3 and Mn3 respectively. The two inputs of NAND gate 216 receive control signals CSAp and CSBp, and its output is coupled to the gate of PMOS transistor Mp3. The two inputs of NOR gate 218 receive control signals CSAn and CSBn, and its output is coupled to the gate of NMOS transistor Mn3. When both output signals VOP and VON are high (VDD), this indicates that control signals CSAp and CSBp are both low to turn on (or enable) PMOS transistors Mp1 and Mp2, and control signals CSAn and CSBn ​​are both low to turn off (or disable) NMOS transistors Mn1 and Mn2. In response to the low-level control signals CSAp and CSBp, NAND gate 216 outputs a high-level signal, and switch Mp3 is open. In response to low-level control signals CSAn and CSAn, NOR gate 218 outputs a high-level signal and switch Mn3 is on / off. Control node ncs is grounded via switch Mn3. Resistors Rfbp and RCMp form a voltage divider between VOP (H, where VOP is high) and the grounded control node ncs. The input IN2 of loop filter 202 is biased at a stable voltage level VDD*RCMp / (RCMp+Rfbp). When RCMp equals Rfbp, the input IN2 of loop filter 202 is biased at VDD / 2. Resistors Rfbn and RCMn form another voltage divider between VON (H, where VON is high) and the grounded control node ncs. The input IN1 of loop filter 202 is biased at a stable voltage level VDD*RCMn / (RCMn+Rfbn). When RCMn equals Rfbn, the input IN1 of the loop filter 202 is biased at VDD / 2. In this design, the common-mode voltage is maintained at the ideal value of VDD / 2. Common-mode voltage fluctuations are successfully suppressed.

[0038] Compared to active components, the switching DAC that implements the common-mode voltage compensation circuit 212 is more energy-efficient.

[0039] Furthermore, the common-mode voltage compensation circuit 212 does not affect the feedback of the output signals VOP and VON. Regardless of whether the common-mode voltage compensation circuit 212 is enabled, the output signals VOP and VON are still fed back to the loop filter 202 as usual.

[0040] In one exemplary embodiment, the resistance ratio between the feedback resistor Rfbp and the compensation resistor RCMp is equal to the resistance ratio between the feedback resistor Rfbn and the compensation resistor RCMn. The common-mode voltage at the input terminals IN1 / IN2 can be changed by adjusting the resistance ratio. Therefore, the resistance ratio can be set according to the required common-mode voltage in the actual design. This invention does not impose any limitations on this.

[0041] In another exemplary embodiment, resistors Rfbp, Rfbn, RCMp, and RCMn have the same resistance. In this example, the common-mode voltage at inputs IN1 / IN2 is maintained at VDD / 2.

[0042] In an exemplary embodiment, the input terminal IN1 of the loop filter 202 is coupled to the positive input terminal "+" of the differential operational amplifier op, and the input terminal IN2 of the loop filter 202 is coupled to the negative input terminal "-" of the differential operational amplifier op.

[0043] In another exemplary embodiment, the input terminal IN1 of the loop filter 202 is coupled to the negative input terminal "-" of the differential operational amplifier op, and the input terminal IN2 of the loop filter 202 is coupled to the positive input terminal "+" of the differential operational amplifier op.

[0044] Figure 3 An amplifier circuit according to another exemplary embodiment of the present invention is shown. Figure 2 Compared to the common-mode voltage compensation circuit 212, Figure 3 The common-mode voltage compensation circuit 302 shown also includes two capacitors, Cp and Cn. Capacitor Cp is connected in series with compensation resistor RCMp between the input terminal IN2 of loop filter 202 and the control node ncs. Capacitor Cn is connected in series with compensation resistor RCMn between the input terminal IN1 of loop filter 202 and the control node ncs. Capacitors Cp and Cn can filter out the in-band noise of the common-mode voltage compensation circuit 302.

[0045] In some exemplary embodiments, the logic circuitry used to open or close switches Mp3 and Mn3 may be modified. Any logic circuitry that closes switch Mp3 (when switch Mn3 is open) when both output signals VOP and VON are low and closes switch Mn3 (when switch Mp3 is open) when both output signals VOP and VON are high should be considered within the scope of this invention.

[0046] The use of ordinal terms such as “first,” “second,” and “third” in the claims to modify patent elements does not in itself indicate any priority, order, or sequence of one patent element relative to another, or the chronological order of the actions of the method, but is merely used as a marker to distinguish one patent element with the same name from another element with the same name.

[0047] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. An amplifier circuit, characterized in that, The amplifier circuit includes a loop filter, a pulse width modulation signal generator, a gate driver, a power driver, a signal feedback circuit, and a common-mode voltage compensation circuit. The loop filter, the pulse width modulation signal generator, the gate driver, the power driver, and the signal feedback circuit form a loop for signal amplification; and, The common-mode voltage compensation circuit is used to provide control nodes coupled to the first and second input terminals of the loop filter; in: When both the first and second output signals of the amplifier circuit are high, the common-mode voltage compensation circuit couples the control node to ground; and... When both the first output signal and the second output signal of the amplifier circuit are low, the common-mode voltage compensation circuit couples the control node to the power supply voltage. The signal feedback circuit includes a first feedback resistor and a second feedback resistor. The first feedback resistor couples the first output signal of the amplifier circuit to the second input terminal of the loop filter, and the second feedback resistor couples the second output signal of the amplifier circuit to the first input terminal of the loop filter. The common-mode voltage compensation circuit includes a first compensation resistor, a first capacitor, a second capacitor, and a second compensation resistor. The first compensation resistor and the first capacitor are connected in series between the second input terminal of the loop filter and the control node, and the second compensation resistor and the second capacitor are connected in series between the first input terminal of the loop filter and the control node.

2. The amplifier circuit as described in claim 1, characterized in that: The loop filter includes a differential operational amplifier, and the first and second input terminals of the loop filter are coupled to a pair of input terminals of the differential operational amplifier.

3. The amplifier circuit as described in claim 2, characterized in that, The common-mode voltage compensation circuit is a switching digital-to-analog converter, and the common-mode voltage compensation circuit further includes: A first switch is controlled to selectively couple the control node to the power supply voltage; and, The second switch is controlled to selectively couple the control node to the ground voltage.

4. The amplifier circuit as described in claim 3, characterized in that, The power driver includes: The first p-channel metal-oxide-semiconductor transistor is controlled by a first control signal generated by the gate driver to selectively couple the first output terminal of the amplifier circuit to the power supply voltage, thereby selectively pulling up the first output signal of the amplifier circuit. The first n-channel metal-oxide-semiconductor transistor is controlled by a second control signal generated by the gate driver to selectively couple the first output terminal of the amplifier circuit to the ground voltage, thereby selectively pulling down the first output signal of the amplifier circuit. The second p-channel metal-oxide-semiconductor transistor is controlled by a third control signal generated by the gate driver to selectively couple the second output terminal of the amplifier circuit to the power supply voltage, thereby selectively pulling up the second output signal of the amplifier circuit; and, The second n-channel metal-oxide-semiconductor transistor is controlled by a fourth control signal generated by the gate driver to selectively couple the second output terminal of the amplifier circuit to the ground voltage, thereby selectively pulling down the second output signal of the amplifier circuit.

5. The amplifier circuit as described in claim 4, characterized in that, The first switch is controlled by the first control signal and the third control signal; and the second switch is controlled by the second control signal and the fourth control signal.

6. The amplifier circuit as described in claim 5, characterized in that, The first switch includes a third p-channel metal-oxide-semiconductor transistor, the source of which is coupled to the power supply voltage and the drain of which is coupled to the control node. Furthermore, the second switch is a third n-channel metal-oxide-semiconductor transistor, with its source terminal coupled to the ground voltage and its drain terminal coupled to the control node.

7. The amplifier circuit as described in claim 6, characterized in that, The common-mode voltage compensation circuit also includes: A NAND gate receives the first control signal and the third control signal, and its output is coupled to the gate of the third p-channel metal-oxide-semiconductor transistor; and, The NOR gate receives the second control signal and the fourth control signal, and its output is coupled to the gate of the third n-channel metal-oxide-semiconductor transistor.

8. The amplifier circuit as described in claim 2, characterized in that, The resistance ratio between the first feedback resistor and the first compensation resistor is equal to the resistance ratio between the second feedback resistor and the second compensation resistor.

9. The amplifier circuit as described in claim 2, characterized in that, The first feedback resistor and the first compensation resistor have the same resistance value, and the second feedback resistor and the second compensation resistor have the same resistance value.

10. The amplifier circuit as described in claim 2, characterized in that: The first feedback resistor, the second feedback resistor, the first compensation resistor, and the second compensation resistor have the same resistance value.

11. The amplifier circuit as described in claim 2, characterized in that, The amplifier circuit uses the first output signal and the second output signal as positive and negative output signals, respectively, to drive the load; and, The differential operational amplifier within the loop filter has a positive input terminal and a negative input terminal. The first input terminal of the loop filter is coupled to the positive input terminal of the differential operational amplifier, and the second input terminal of the loop filter is coupled to the negative input terminal of the differential operational amplifier.

12. The amplifier circuit as described in claim 2, characterized in that, The amplifier circuit uses the first output signal and the second output signal as positive and negative output signals, respectively, to drive the load; and, The differential operational amplifier within the loop filter has a positive input terminal and a negative input terminal. The first input terminal of the loop filter is coupled to the negative input terminal of the differential operational amplifier, and the second input terminal of the loop filter is coupled to the positive input terminal of the differential operational amplifier.

13. The amplifier circuit as described in claim 1, characterized in that, This amplifier circuit is a Class D amplifier.

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