A storage device and its operating method, and a storage system including the storage device.

Abstract

This application provides a storage device and its operating method, and a storage system including the storage device. The storage device includes a storage cell array, the storage cell array includes multiple word lines, each word line corresponds to a storage cell set, and each storage cell set includes multiple storage cells. The method includes: performing a programming operation on a first storage cell set corresponding to a selected word line in the storage device, such that the storage cells in the first storage cell set are respectively in an erase state and any one of multiple programming states; after the programming operation, performing an erase operation on a first subset of the first storage cell set; the first subset of the first storage cell set consists of the storage cells in the first storage cell set that are in the erase state after the programming operation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a storage device and its operation method, and a storage system including the storage device. Background Technology

[0002] As memory devices continue to shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] Currently, the Increment Step Pulse Program (ISPP) method is commonly used to program 3D memory. During programming, a programming voltage is applied to the word line of the memory cell, and then a verification voltage is applied to determine whether the programming voltage of the memory cell has reached the threshold voltage. If the threshold voltage is reached, the programming operation for that memory cell ends; if the threshold voltage is not reached, the programming voltage is increased by ΔV (i.e., the step size of the programming voltage increase) and the application continues. Then, a verification voltage is applied to determine whether the increased programming voltage on the memory cell has reached the threshold voltage. The above cycle is repeated until the threshold voltage of all memory cells that need to be programmed reaches the expected storage state, that is, all memory cells that need to be programmed have passed the verification.

[0004] However, existing step pulse programming methods still suffer from problems such as insufficient data reliability. Summary of the Invention

[0005] In view of the above, this application provides a storage device and its operation method, and a storage system including the storage device, to solve at least one technical problem existing in the prior art.

[0006] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0007] In a first aspect, this application provides a method for operating a storage device, the storage device including a storage cell array, the storage cell array including multiple word lines, each word line corresponding to a storage cell set, each storage cell set including multiple storage cells, the method including:

[0008] A programming operation is performed on the first set of storage cells corresponding to a selected word line in the storage device, such that the storage cells in the first set of storage cells are respectively in an erase state and any one of a plurality of programming states;

[0009] After the programming operation, an erase operation is performed on a first subset of the first storage cells in the first storage cell set; the first subset of the storage cells is the storage cells in the first storage cell set that are in an erased state after the programming operation.

[0010] Secondly, this application also provides a storage device, the storage device comprising:

[0011] A storage cell array, the storage cell array comprising multiple word lines, each word line corresponding to a storage cell set, and each storage cell set comprising multiple storage cells; and

[0012] Peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured as follows:

[0013] A programming operation is performed on the first set of storage cells corresponding to a selected word line in the storage device, such that the storage cells in the first set of storage cells are respectively in an erase state and any one of a plurality of programming states;

[0014] After the programming operation, an erase operation is performed on a first subset of the first storage cells in the first storage cell set; the first subset of the storage cells is the storage cells in the first storage cell set that are in an erased state after the programming operation.

[0015] Thirdly, this application also provides a storage system, including a controller and the storage device described in the above technical solutions; the controller is coupled to the storage device and is used to control the storage device.

[0016] This application provides a storage device and its operating method, and a storage system including the storage device. The storage device includes a storage cell array, the storage cell array includes multiple word lines, each word line corresponds to a storage cell set, and each storage cell set includes multiple storage cells. The method includes: performing a programming operation on a first storage cell set corresponding to a selected word line in the storage device, such that the storage cells in the first storage cell set are respectively in an erase state and any one of multiple programming states; after the programming operation, performing an erase operation on a first subset of storage cells in the first storage cell set; the first subset of storage cells is the storage cells in the first storage cell set that are in the erase state after the programming operation. In the operating method of the storage device provided by this application, by performing an erase operation on the first subset of storage cells that are in the erase state after the programming operation, i.e., the first subset of storage cells whose target state is erase, after the programming operation, the upper bound of the threshold voltage distribution of the first subset of storage cells is reduced, thereby increasing the read window and improving the reliability of reading data. Attached Figure Description

[0017] Figure 1 A block diagram illustrating an exemplary system with a storage device according to some embodiments of this application;

[0018] Figure 2A A diagram illustrating an exemplary memory card with a storage device according to some embodiments of this application;

[0019] Figure 2B A diagram illustrating an exemplary solid-state drive (SSD) with a storage device according to some embodiments of this application;

[0020] Figure 3 This is a schematic diagram of an exemplary storage device including peripheral circuitry, according to some embodiments of this application;

[0021] Figure 4 A side view of a cross-section of an exemplary memory cell array including strings of NAND memory cells, shown according to some embodiments of this application;

[0022] Figure 5 This is a block diagram of an exemplary memory device including a memory cell array and peripheral circuitry, according to some embodiments of this application;

[0023] Figure 6A This is a flowchart illustrating the operation method of a storage device according to some embodiments of this application. Figure 1 ;

[0024] Figure 6B Schematic timing diagram of word line voltage applied by the step pulse programming method according to some embodiments of this application Figure 1 ;

[0025] Figure 6C This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments of this application. Figure 1 ;

[0026] Figure 7 This is a schematic diagram illustrating the implementation process of an operation method for a storage device according to some embodiments of this application;

[0027] Figure 8A This is a schematic flowchart of an operation method of a storage device according to some embodiments of this application;

[0028] Figure 8B A schematic timing diagram 2 of the word line voltage applied according to some embodiments of the step pulse programming method of this application;

[0029] Figure 8C This is a schematic diagram (2) illustrating the threshold voltage distribution of a memory cell according to some embodiments of this application;

[0030] Figure 9This is a partial structural schematic diagram of a storage device according to some embodiments of this application;

[0031] Figure 10A This is a schematic diagram showing the threshold voltage distribution of a selected memory cell in different programming operations and multiple programming states according to some embodiments of this application.

[0032] Figure 10B This is a schematic diagram showing the threshold voltage distribution of the lowest state of a selected memory cell under different programming operations according to some embodiments of this application;

[0033] Figure 11 This is a schematic diagram illustrating the implementation process of an operation method for another storage device according to some embodiments of this application;

[0034] Figure 12 This is a schematic diagram illustrating the operation method of another storage device according to some embodiments of this application;

[0035] Figure 13 This is a schematic diagram of the threshold voltage distribution of the lowest state of another selected memory cell under different programming operations according to some embodiments of this application;

[0036] Figure 14 This is a circuit diagram of a storage device according to some embodiments of this application;

[0037] Figure 15 A waveform diagram of the applied voltage as described in the operation method of a storage device according to some embodiments of this application;

[0038] The diagram includes: 100, System; 102, Storage System; 104, Storage Device; 106, Controller; 108, Host; 202, Memory Card; 204, Memory Card Connector; 206, Solid State Drive (SSD); 208, SSD Connector; 300, Storage Device; 301, Memory Cell Array; 302, Peripheral Circuitry; 304, Memory Block; 306, Memory Cell; 308, NAND Memory Cell String; 310, Source Select Gate (SSG); 312, Drain Select Gate (DSG); 313, DSG Line; 314, Source Line (SL); 315, SSG Line; 316 504. Bit line; 318. Word line; 320. Memory page; 402. Substrate; 404. Memory stack layer; 406. Gate conductive layer; 408. Gate dielectric layer; 412. Channel structure; 414. Well; 416. Channel plug; 418. Memory film; 420. Semiconductor channel; 422. Barrier layer; 424. Memory layer; 426. Tunneling layer; 504. Page buffer / sensor amplifier; 506. Column driver / bit line driver; 508. Row driver / word line driver; 510. Voltage generator; 512. Control logic unit; 514. Register; 516. Interface (I / F); 518. Data bus. Detailed Implementation

[0039] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0041] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0045] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0046] refer to Figure 1 , Figure 1 This is a block diagram illustrating an exemplary system 100 with a storage device according to some embodiments of this application. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more storage devices 104 and a controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the storage device 104.

[0047] Storage device 104 can be any storage device disclosed herein. As disclosed in detail below, storage device 104 (e.g., NAND flash memory storage device (e.g., three-dimensional (3D) NAND flash memory storage device)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0048] According to some embodiments, controller 106 is coupled to storage device 104 and host 108 and is configured to control storage device 104. Controller 106 can manage data stored in storage device 104 and communicate with host 108. In some embodiments, controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Controller 106 can be configured to control the operation of storage device 104, such as read, erase, and program operations. Controller 106 can also be configured to manage various functions related to data stored or to be stored in storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 106 is also configured to process error correction codes (ECC) for data read from or written to storage device 104. Controller 106 may also perform any other suitable functions, such as formatting storage device 104. Controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0049] The controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, controller 106 and a single storage device 104 can be integrated into memory card 202. Memory card 202 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 202 may also include a connection between memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, controller 106 and multiple storage devices 104 may be integrated into SSD 206. SSD 206 may also include a connection between SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0050] refer to Figure 3 , Figure 3 This is a schematic diagram illustrating an exemplary storage device 300 including peripheral circuitry according to some embodiments of this application. The storage device 300 may be... Figure 1 An example of storage device 104 is provided. Storage device 300 may include a storage cell array 301 and peripheral circuitry 302 coupled to the storage cell array 301. The storage cell array 301 may be a NAND flash memory storage cell array, wherein storage cells 306 are provided in the form of an array of NAND storage cell strings 308, each NAND storage cell string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND storage cell string 308 includes a plurality of storage cells 306 coupled in series and stacked vertically. Each storage cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the storage cell 306. Each storage cell 306 may be a floating-gate type storage cell including a floating-gate transistor, or a charge-trapping type storage cell including a charge-trapping transistor.

[0051] In some embodiments, each memory cell 306 may be a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, an SLC may have a first memory state "1" and a second memory state "0," where the threshold voltage distribution of the first memory state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second memory state "0" may correspond to a second voltage range. The first memory state is an erase state, and the second memory state is a programmable state. In some embodiments, each memory cell 306 may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a three-level cell (TLC)), or four bits of data per cell (also known as a four-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC can have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00". Here, the threshold voltage distributions for the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is the erase state, and the second, third, and fourth storage states are all programming states. Similarly, a TLC can have 8 storage states, including an erase state and 7 programming states; a QLC can have 16 storage states, including an erase state and 15 programming states.

[0052] like Figure 3As shown, each NAND cell string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 can be configured to activate a selected NAND cell string 308 (column of the array) during read and program operations. In some embodiments, the sources of NAND cell strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND cell strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND cell string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory cell string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0053] like Figure 3As shown, NAND cell strings 308 can be organized into multiple memory blocks 304, each of which can have a common SL 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, a source line 314 biased to the selected memory block and unselected memory blocks on the same plane as the selected memory block can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND cell strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of a memory cell 306, the memory page 320 being a basic data unit for programming operations. The size of a memory page 320, in bits, can be related to the number of NAND memory cell strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320, as well as gate lines coupling the control gates.

[0054] refer to Figure 4 , Figure 4 This is a side view of a cross-section of an exemplary memory cell array 301 including NAND memory cell strings 308, shown according to some embodiments of this application. Figure 4 As shown, the NAND memory cell string 308 can extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0055] The memory stack 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a DSG line 313, at the bottom of the memory stack 404 as an SSG line 315, or between DSG lines 313 and SSG lines 315 as a word line 318.

[0056] like Figure 4 As shown, the NAND flash memory cell string 308 includes a channel structure 412 extending vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes channel holes filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a memory layer 424 (also referred to as a "charge trap / storage layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, memory layer 424, and barrier layer 422 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0057] According to some embodiments, such as Figure 4As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in the substrate 402, and the source terminal of the NAND memory cell string 308 is in contact with the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory cell string 308) during an erase operation. In some embodiments, the NAND memory cell string 308 also includes a channel plug 416 at the drain terminal of the NAND memory cell string 308. It should be understood that, although in Figure 4 Additional components, not shown, but which may form the memory cell array 301, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0058] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column driver / bit line driver 506, a row driver / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional components may be included. Figure 5 Additional peripheral circuitry not shown.

[0059] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a memory page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column driver / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory cell strings 308 by applying a bit line voltage generated from voltage generator 510.

[0060] The row driver / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row driver / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row driver / word line driver 508 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row driver / word line driver 508 is configured to perform an erase operation on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0061] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column driver / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0062] refer to Figure 6A and Figure 6B , Figure 6A This is a flowchart illustrating the operation method of a storage device according to some embodiments of this application. Figure 1 , Figure 6B Schematic timing of word line voltages applied during step pulse programming according to some embodiments of this application Figure 1 .like Figure 6A and Figure 6B As shown, in the Step-Pulse Programming (ISPP) method, a word line with an ever-increasing programming voltage Vpgm is applied to the selected memory cell. For example, if a memory page is selected for the programming operation, a bias voltage is applied to the word line coupled to the memory cell of the memory page. The ISPP method programs the selected memory page several times while gradually increasing the word line bias voltage based on a step voltage. The magnitude of this step (i.e., the increase of each pulse relative to the immediately preceding pulse) is referred to herein as the "step size" ΔV. Between each pulse with the increasing magnitude, a programming verification operation is performed, i.e., a verification voltage Vvfy is applied to confirm whether each selected memory cell has a threshold voltage that meets the target programming state. The ISPP method continues until the threshold voltage of each selected memory cell in the memory page meets the target programming state, i.e., each selected memory cell in the memory page has passed verification. In other words, the target programming state in the memory page has been verified, where the target programming state refers to any one of several programming states.

[0063] Still referencing Figure 3 and Figure 5The waveforms of ISPP, such as the programming voltage Vpgm (including step size ΔV) and the verification voltage Vvfy, are controlled by the peripheral circuitry and provided to the word line driver. The word line driver can be configured to select word lines and sequentially apply the corresponding waveform word line bias voltage to each selected word line to program the memory cell.

[0064] As mentioned earlier, for SLC, each memory cell can store one bit of data, and each memory cell can have a threshold voltage distribution with an erase state P0 and a threshold voltage distribution with one programming state. For MLC, each memory cell can store two bits of data, and each memory cell can have a threshold voltage distribution with an erase state P0 and a threshold voltage distribution with three programming states. For TLC, each memory cell can store three bits of data, and each memory cell can have a threshold voltage distribution with an erase state P0 and a threshold voltage distribution with seven programming states. Similarly, for QLC, each memory cell can store four bits of data, and each memory cell can have a threshold voltage distribution with an erase state P0 and a threshold voltage distribution with 15 programming states.

[0065] refer to Figure 6C , Figure 6C This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments of this application. Figure 1 .like Figure 6C As shown, the memory cell has an erase state P0 and multiple programming states (including Pm, Pm+1, ..., Pmax). Figure 6C In the erase and various programming states shown, the threshold voltage of the memory cell gradually increases from P0 to Pmax. The erase state P0 corresponds to the lowest-state memory cell, and the programming state Pmax corresponds to the highest-state memory cell. Although low-state memory cells are suppressed from programming after passing the verification operation, some memory cells on the current word line need to be programmed to higher states. Therefore, a higher programming voltage is applied to the gate. These voltages can interfere with the already programmed low-state memory cells during the actual programming process, especially the lowest-state memory cells, because the lowest-state memory cells are in a programming-suppressed state throughout the entire programming process.

[0066] It should be noted that after a memory cell completes programming to the target programming state, the threshold voltage distribution of the lowest-state memory cell will drift. Here, the target programming state refers to any one of the various programming states. Specifically, after interference from programming operations of other memory cells, the threshold voltage of the lowest-state memory cell will increase, causing the window between the threshold voltage distribution of the lowest-state memory cell and the threshold voltage distribution of its adjacent programming state to decrease, i.e., the read window of the lowest-state memory cell will decrease.

[0067] In view of this, embodiments of this application provide an operation method for a storage device. After a programming operation, an erasure operation is performed on a first subset of storage cells that is in an erasure state after the programming operation, i.e., the first subset of storage cells whose target state is an erasure state. This reduces the upper bound of the threshold voltage distribution of the first subset of storage cells, thereby increasing the read window and improving the reliability of reading data.

[0068] Here, the first subset of storage cells is the lowest-state storage cell. The first subset of storage cells includes all storage cells within the storage page where the selected storage cell is located, and whose target state is the erase state.

[0069] refer to Figure 7 , Figure 7 This is a schematic diagram illustrating the implementation flow of an operation method for a storage device according to some embodiments of this application. For example... Figure 7 As shown in the embodiment of this application, the method for operating a storage device includes a storage cell array, the storage cell array includes multiple word lines, each word line corresponds to a storage cell set, and each storage cell set includes multiple storage cells. The method includes:

[0070] Step S701: Perform a programming operation on the first set of storage cells corresponding to the selected word line in the storage device, so that the storage cells in the first set of storage cells are respectively in an erase state and any one of multiple programming states;

[0071] Step S702: After the programming operation, an erase operation is performed on a first subset of the first storage cells in the first storage cell set; the first subset of the storage cells is the storage cells in the first storage cell set that are in the erase state after the programming operation.

[0072] Here, the first set of storage cells can also be called the first storage cell layer. The first set of storage cells can be understood as the set of all storage cells in a storage page coupled to the selected word line.

[0073] refer to Figure 8A , Figure 8B and Figure 8C , Figure 8A This is a second schematic flowchart illustrating the operation method of a storage device according to some embodiments of this application. Figure 8B This is a schematic timing diagram 2 of the word line voltage applied according to some embodiments of the step pulse programming method of this application. Figure 8C This is a schematic diagram (2) illustrating the threshold voltage distribution of a memory cell according to some embodiments of this application. Figure 8A , Figure 8B and Figure 8CAs shown, after performing a programming operation on each selected memory cell in the first memory cell set, i.e., after the verification of the target programming state in the first memory cell set is passed, the threshold voltage distribution of the lowest-state memory cell drifts from the initial erase state to the first erase state. An erase operation is then performed on the lowest-state memory cell, changing its threshold voltage distribution from the first erase state to the second erase state. Here, the initial erase state, the first erase state, and the second erase state can be understood as the memory states where the target state of the corresponding memory cell is the erase state. In other words, the initial erase state, the first erase state, and the second erase state are essentially all manifestations of the erase state. Here, the target programming state refers to any one of the multiple programming states, i.e., any one of the programming states P1 to Pmax. In other words, when programming the memory cells sequentially, the lowest-state memory cell remains in a programming suppression state throughout the entire programming process. After completing the programming operation for the target programming state, the threshold voltage distribution of the lowest-state memory cell is adjusted through an erase operation.

[0074] Still referencing Figure 8C As shown, a memory cell can have an initial erase state and any of several programming states (including P1 to Pmax). During programming, after the first subset of memory cells is in the initial erase state, other memory cells are also programmed sequentially. Due to interference from the programming operations of other memory cells, the threshold voltage of the first subset of memory cells drifts, causing it to transition from the initial erase state to the first erase state. In this first erase state, the threshold voltage distribution of the first erase state is greater than the upper bound of the threshold voltage distribution of the initial erase state. After programming, an erase operation is performed on the first subset of memory cells, changing it from the first erase state to the second erase state. Again, the upper bound of the threshold voltage distribution of the first erase state is greater than the upper bound of the threshold voltage distribution of the second erase state. The difference between the upper bound of the threshold voltage distribution in the first erase state and the lower bound of the threshold voltage distribution in its immediate neighboring programming state is less than the difference between the upper bound of the threshold voltage distribution in the second erase state and the lower bound of the threshold voltage distribution in its immediate neighboring programming state. Therefore, the read window in the first erase state is smaller than the read window in the second erase state.

[0075] It should be noted that when an erase operation is performed on the first subset of storage cells in the first erase state, the threshold voltage distribution of the first subset of storage cells changes, and the threshold voltage distribution of the first subset of storage cells becomes the second erase state. The difference between the upper bound of the threshold voltage distribution of the second erase state and the lower bound of the threshold voltage distribution of the adjacent programming state is greater than the difference between the upper bound of the threshold voltage distribution of the first erase state and the lower bound of the threshold voltage distribution of the adjacent programming state. Therefore, by performing an erase operation, after the first subset of storage cells changes from the first erase state to the second erase state, the read window of the first subset of storage cells is increased, and the reliability of reading data is improved.

[0076] Still referencing Figure 8C The upper bound of the threshold voltage distribution of the first erase state is less than the lower bound of the threshold voltage distribution of the lowest programming state among the multiple programming states, that is, the upper bound of the threshold voltage distribution of the first erase state is less than the lower bound of the threshold voltage distribution of the lowest programming state.

[0077] In some preferred embodiments of this application, the programming operation ends after the lowest-state memory cell is erased, causing the threshold voltage distribution of the lowest-state memory cell to change from the first erase state to the second erase state. That is, after the lowest-state memory cell is erased, no further verification operation is performed on it, thus increasing the read window while reducing the impact on programming time.

[0078] Here, for MLC, each storage cell can store two bits of data and has four storage states, including an erase state and three programming states. The division of different storage states is based on the number of electrons in the storage layer. For example, less than 10 electrons are classified as the first storage state "11", 11 to 20 electrons are classified as the second storage state "10", 21 to 30 electrons are classified as the third storage state "01", and more than 30 electrons are classified as the fourth storage state "00". After verifying the target programming state, an erase operation is performed on the first subset of memory cells. An erase voltage is applied to the bit lines corresponding to the first subset of memory cells, and a ground voltage is applied to the selected word lines, creating a large potential difference between the channel potential and the gate potential. This injects erased carriers (i.e., holes) from the channel into the memory layer, neutralizing them with the electrons in the memory layer. This reduces the number of electrons in the memory layer of the first subset of memory cells, causing the first subset of memory cells to change from a first erase state to a second erase state. The threshold voltage of the first subset of memory cells decreases, meaning the upper bound of the threshold voltage distribution of the first subset of memory cells decreases. It should be noted that the lower bound of the threshold voltage distribution of the first subset of memory cells also decreases. In this embodiment, after performing the erase operation on the first subset of memory cells, the first subset of memory cells changes from the first erase state to the second erase state. In a preferred embodiment of this application, the threshold voltage distribution of the second erase state is the same as the threshold voltage distribution of the initial erase state. After the erase operation is performed on the first memory cell subset, the first memory cell subset is restored from the first erase state to the initial erase state.

[0079] refer to Figure 9 , Figure 9 This is a partial structural diagram of a storage device according to some embodiments of this application. The storage devices in the embodiments of this application include, but are not limited to, three-dimensional (3D) NAND storage devices. For ease of understanding, a three-dimensional NAND storage device will be used as an example for explanation. Figure 9As shown, a three-dimensional NAND flash memory device may include a string selection line (SSL), a word line (WL), and a ground selection line (GSL). The word line may include a dummy word line, a selected word line (Sel WLn), word lines adjacent to the selected word line among the unselected word lines (i.e., Unsel WLn+1 and Unsel WLn-1), and multiple word lines not adjacent to the selected word line among the unselected word lines (i.e., Unsel WLn+2 above and Unsel WLn-2 below).

[0080] In some embodiments of this application, a multi-step programming method, such as a two-step programming operation, can be used when performing programming operations to reduce the programming interference caused by a programmed memory cell to other adjacent unprogrammed memory cells.

[0081] Here, a multi-step programming operation can include at least one coarse programming operation and one fine programming operation. The coarse programming operation can form a coarse threshold voltage distribution. The fine programming operation can refine and narrow the threshold voltage distribution formed by the coarse programming operation.

[0082] For the sake of brevity, this application embodiment uses a two-step programming operation as an example for explanation; the two-step programming operation here includes a coarse programming operation and a fine programming operation.

[0083] As mentioned above, programming using the step pulse programming method allows for programming verification operations to be performed after each memory cell has been programmed. Alternatively, programming verification can be performed after a coarse programming operation or after a fine programming operation. This application embodiment does not impose any restrictions on the timing or number of programming verification operations. For brevity, the description of programming verification operations is omitted in the following description of the memory device operation methods provided in this application embodiment.

[0084] In some specific embodiments, performing a two-step programming operation on a three-dimensional NAND flash memory device includes:

[0085] Step 1: Perform coarse programming on the selected word line (WLn) and the unselected word line adjacent to the selected word line (Unsel WLn+1).

[0086] Step 2: Perform fine programming on the selected word line (WLn).

[0087] Here, in step one, firstly, a coarse programming operation is performed on the selected word line (WLn) in its initial state; wherein, refer to Figure 10A Distribution ① in the figure shows the threshold voltage distribution of the selected word line (WLn) in the initial state. Here, the initial state can be understood as the initial erase state. Here, the initial threshold voltage distribution of the memory cell corresponding to the selected word line (WLn) in the initial state is P0.

[0088] Here, after performing coarse programming on the selected word line (WLn), the memory cells corresponding to the selected word line (WLn) can form a first threshold voltage distribution based on the read data; (Refer to...) Figure 10A The distribution in ② is shown.

[0089] The first threshold voltage distribution includes multiple programming states, including a first lowest state P1 and multiple first programming states (Pm, Pm+1, ..., Pm(max)). The threshold voltage distribution of the first lowest state P1 is wider than that of the initial state P0, with a widening of L1. Here, the widening can be understood as the degree of change in the threshold voltage distribution. The first lowest state can be understood as the first subset of memory cells drifting from the initial erase state to the first lowest state after a coarse programming operation is performed on the selected word line. It should be noted that P1 has a slight rightward shift relative to P0; this small shift is ignored here.

[0090] Next, in order to reduce programming interference to the unselected word lines (Unsel WLn+1) adjacent to the selected word line, a coarse programming operation is performed on the unselected word lines (Unsel WLn+1) adjacent to the selected word line.

[0091] Here, after performing coarse programming on the unselected word line (Unsel WLn+1) adjacent to the selected word line, the memory cell corresponding to the selected word line (WLn) forms a second threshold voltage distribution; (Refer to...) Figure 10A The distribution in ③ is shown.

[0092] The second threshold voltage distribution includes a second lowest state P2 and multiple second programming states (Pn, Pn+1, ..., Pn(max)). The threshold voltage distribution of the second lowest state P2 is wider than that of the first lowest state P1, with a broadening of L2. The threshold voltage distributions of the second programming states (Pn, Pn+1, ..., Pn(max)) are also wider than the corresponding threshold voltage distributions of the first programming states (Pm, Pm+1, ..., Pm(max)), with a broadening of L3.

[0093] It should be noted that the second threshold voltage distribution is obtained by widening the threshold voltage distribution based on the first threshold voltage distribution for the memory cell corresponding to the selected word line (WLn).

[0094] In step two, when performing fine programming on the selected word line (WLn), a smaller programming step voltage is typically used, while the verification voltage for each state of the fine programming is increased.

[0095] Here, after performing fine-programming on the selected word line (WLn), the memory cell corresponding to the selected word line (WLn) forms a third threshold voltage distribution; (Refer to...) Figure 10A The distribution in ④ is shown.

[0096] The third threshold voltage distribution includes the third lowest state P3 and multiple third programming states (Pt, Pt+1, ..., Pt(max)). The threshold voltage distribution of the third lowest state P3 is wider than that of the second lowest state P2, with a width of L4. The width of the corresponding threshold voltage distribution in the third programming states (Pt, Pt+1, ..., Pt(max)) is either narrower or unchanged compared to the width of the corresponding threshold voltage distribution in the second programming states (Pn, Pn+1, ..., Pn(max)).

[0097] It should be noted that the third threshold voltage distribution is obtained by applying a smaller programming step voltage to the memory cell corresponding to the selected word line (WLn) based on the second threshold voltage distribution.

[0098] It should be noted that the first lowest state, the second lowest state, and the third lowest state can be understood as the storage state in which the target state of the corresponding storage unit is the erase state. In other words, the first lowest state, the second lowest state, and the third lowest state are all essentially manifestations of the erase state. On the other hand, the first programming state, the second programming state, and the third programming state can be understood as the storage state in which the target state of the corresponding storage unit is a certain programming state. This programming state needs to be further programmed based on the erase state.

[0099] Understandably, two-step programming operations can mitigate programming interference in programming states that require further programming operations in subsequent operations; however, they offer no improvement for the lowest-level state where programming operations are no longer needed. On the contrary, performing programming operations on selected word lines increases the number of programming interferences to the lowest-level state, resulting in a smaller read window for the memory cell corresponding to the lowest-level state. (Refer to...) Figure 10B .

[0100] In response to one or more of the above-mentioned problems, this application also proposes a method for operating a storage device. Figure 11 This illustration shows a schematic flowchart of another method of operating a storage device according to some embodiments of this application, with reference to... Figure 11 The method includes:

[0101] Step S1101: Perform a first type of sub-programming operation on the first set of storage cells corresponding to the selected word line in the storage device, so that the storage cells in the first set of storage cells are respectively in an erase state and any one of multiple programming states;

[0102] Step S1102: After performing the first type of subprogramming operation on the first set of storage cells, perform an erase operation on the first subset of storage cells in the first set of storage cells;

[0103] Step S1103: After the erase operation, perform a second type of sub-programming operation on the first storage cell set to complete the programming of the first storage cell set.

[0104] Here, the first set of storage cells can also be called the first storage cell layer. The first set of storage cells can be understood as the set of all storage cells in a storage page coupled to the selected word line.

[0105] In this embodiment, the storage device is programmed using a step-by-step programming method. The first type of sub-programming operation can be understood as the aforementioned coarse programming, and the second type of sub-programming can be understood as the aforementioned fine programming. In some specific examples, the step-by-step programming method can be divided into two steps, where the first type of sub-programming operation is performed once, and the second type of sub-programming operation is performed once. In other specific examples, the step-by-step programming method can be divided into three steps, where the first type of sub-programming operation is performed twice, and the second type of sub-programming operation is performed once. Of course, the step-by-step programming method can also be divided into more than three steps. It is understood that the storage unit of the storage device using the step-by-step programming method is generally a storage unit with multiple bits. When programming using the step-by-step programming method, the specific number of steps is also related to the number of bits in the storage unit. Generally speaking, the higher the number of bits, the more steps may be required.

[0106] Understandably, during the multi-step programming process of programming the set of memory cells corresponding to a selected word line in a storage device, each programming step affects the first subset of memory cells in the target erase state, widening the threshold voltage distribution of the first subset and thus reducing the read window for it. Therefore, before performing the second type of sub-programming operation on the first subset of memory cells, an erase operation can be added to the first subset of memory cells in the target erase state to reduce the threshold voltage distribution width of the first subset, i.e., increase the read window for the first subset of memory cells.

[0107] The erase operation added to the first subset of storage units can be added after each execution of the first type of subprogramming operation; it can also be added after the first set of storage units has performed several first type of subprogramming operations; or it can be added all at once after the first set of storage units has performed all first type of subprogramming operations.

[0108] In some specific examples, when programming the memory cells in the storage device using a two-step programming method, a first type of sub-programming operation (coarse programming) is performed on the first set of memory cells corresponding to the selected word line in the storage device. Then, an erase operation is performed on the first subset of memory cells in the first set whose target state is erased. After that, a second type of sub-programming operation (fine programming) is performed on the first set of memory cells. At this time, the first set of memory cells has completed the programming operation.

[0109] In some specific examples, when programming the memory cells in the storage device using a programming method with more than two steps, after each first type of sub-programming operation (coarse programming) is performed on the first memory cell set corresponding to the selected word line in the storage device, an erase operation is performed on the first memory cell subset of the first memory cell set whose target state is erased. After the last erase operation is completed, a second type of sub-programming operation (fine programming) is performed on the first memory cell set. At this time, the programming operation of the first memory cell set is completed.

[0110] In some specific examples, when programming the memory cells in the storage device using a programming method of more than two steps, after performing a certain number of first-type sub-programming operations (coarse programming) on ​​the first set of memory cells corresponding to the selected word line in the storage device (here, several times is more than one but less than all times of the first type of sub-programming operation), an erase operation is performed on the first set of memory cells whose target state is erased. After the last erase operation is completed, a second-type sub-programming operation (fine programming) is performed on the first set of memory cells. At this time, the first set of memory cells completes the programming operation.

[0111] In some specific examples, when programming the memory cells in a storage device using a programming method with more than two steps, after performing all first-type sub-programming operations (coarse programming) on ​​the first set of memory cells corresponding to the selected word line in the storage device, an erase operation is performed on the first memory cells in the first set whose target state is erased. After the erase operation is completed, a second-type sub-programming operation (fine programming) is performed on the first set of memory cells. At this point, the programming operation on the first set of memory cells is complete. It can be understood that this method of adding erase operations not only increases the read window of the first subset of memory cells, but also prevents the programming time from increasing excessively.

[0112] In some embodiments, the Gate Induced Drain Leakage (GIDL) method can be used to perform erase operations only on memory cells in the lowest state (i.e., erase state or target erase state) within the memory cell set corresponding to the selected word line. As previously mentioned, considering the problem of adjacent layer programming interference, in some embodiments, after performing a first type of sub-programming operation on the first set of memory cells corresponding to the selected word line, a first type of sub-programming operation is interspersed on the second set of memory cells corresponding to the memory cells adjacent to the selected word line, and then the second type of sub-programming operation is performed on the first set of memory cells. And from... Figure 10A and Figure 10B As can be seen from the above, performing the first type of subprogramming operation on the second set of memory cells corresponding to the memory cells adjacent to the selected word line will also affect the first set of memory cells in the first set of memory cells, thereby widening the threshold voltage distribution of the first set of memory cells and reducing the read window of the first set of memory cells.

[0113] Based on this, in some embodiments, the method further includes:

[0114] After performing the first type of subprogramming operation on the first set of memory cells, perform the first type of subprogramming operation on the second set of memory cells corresponding to the word line adjacent to the selected word line;

[0115] Performing an erase operation on a first subset of storage cells in the first set of storage cells includes:

[0116] After performing the first type of subprogramming operation on the second set of storage cells, an erase operation is performed on the first subset of storage cells.

[0117] At the same time, considering that performing an erase operation on the first memory unit set after each execution of the first type of subprogramming operation would increase the complexity of the programming operation, thus hindering the programming efficiency.

[0118] Therefore, in some specific examples, the first type of subprogramming operation can be performed once or multiple times on both the first set of memory cells corresponding to the selected word line and the second set of memory cells corresponding to the word lines adjacent to the selected word line in the storage device, before performing an erase operation on the first set of memory cells. This increases the read window of the first set of memory cells without increasing the complexity of the programming operations excessively.

[0119] Specifically, Figure 12 This illustration shows a schematic flowchart of an operation method implementation of another storage device according to some embodiments of this application, with reference to... Figure 12 The method includes:

[0120] Step S1201: Perform a first type of sub-programming operation on the first set of storage cells corresponding to the selected word line in the storage device, so that the storage cells in the first set of storage cells are respectively in an erase state and any one of multiple programming states;

[0121] Step S1202: After performing the first type of subprogramming operation on the first set of memory cells, perform the first type of subprogramming operation on the second set of memory cells corresponding to the word line adjacent to the selected word line;

[0122] Step S1203: After performing the first type of subprogramming operation on the second set of storage cells, perform an erase operation on the first subset of storage cells;

[0123] Step S1204: After the erase operation, perform a second type of sub-programming operation on the first storage cell set to complete the programming of the first storage cell set.

[0124] It should be understood that Figure 12 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 12 The steps shown can be adjusted in order according to actual needs.

[0125] Here, the first set of storage cells can also be referred to as the first storage cell layer, which can be understood as the set of all storage cells in a storage page coupled to the selected word line. Correspondingly, the second set of storage cells can also be referred to as the second storage cell layer, which can be understood as the set of all storage cells in a storage page coupled to a word line adjacent to the selected word line. Figure 13 This is a schematic diagram of the threshold voltage distribution of the lowest state of another selected memory cell under different programming operations according to some embodiments of this application; Figure 14 This is a circuit diagram of a storage device according to some embodiments of this application; Figure 15This is a voltage waveform diagram of the operating method of a storage device according to some embodiments of this application. The following will be combined with... Figure 13 , Figure 14 and Figure 15 This section further explains how to perform an erase operation on the lowest-level storage unit.

[0126] For ease of description, the following embodiments use the example of performing a first type of subprogramming operation once on both the first and second memory cell sets. It should be noted that in other specific embodiments of this application, the number of times the first type of subprogramming operation is performed on the first and second memory cell sets may include multiple times.

[0127] like Figure 14 As shown, the storage device includes a storage cell array, which may include multiple storage blocks, each storage block may include multiple storage cell strings, and each storage cell string is on a substrate ( Figure 14 (Not shown in the image) Extending vertically upwards. In embodiments of this application, each memory cell string includes multiple memory cells that are series-coupled and vertically stacked. Each memory cell string includes an upper selection transistor (String Selection Transistor, SST), multiple memory cells (MC), and a lower selection transistor (GST), and each memory cell string is connected to the bit line BL and the array common source ACS, respectively. The upper selection transistor and the lower selection transistor can be configured to activate the memory cell string during read and program operations.

[0128] In this embodiment, the down-select transistors of memory cell strings in the same memory block can be coupled to ground through the same source line, i.e., the common source line (CSL). Each memory cell string can be coupled to an up-select transistor at its drain end and to a down-select transistor at its source end, wherein the up-select transistor is located between the memory cell and the bit line, and the down-select transistor is located between the memory cell and the array common source (ACS).

[0129] Still referencing Figure 14 A memory block may include multiple memory cell strings, multiple word lines, multiple bit lines, multiple string select lines, multiple ground select lines, and a common source line. The number of memory cell strings, word lines, bit lines, string select lines, and ground select lines may vary depending on the embodiment. In the embodiments of this application, word lines at the same height in the direction perpendicular to the substrate may be connected to each other, string select lines at the same height may be separated from each other, and ground select lines at the same height may also be separated from each other.

[0130] In this embodiment, the lowest-state memory cell can be erased using a gate-induced drain leakage current method. Specifically, holes in the channel are injected into the memory layer to neutralize electrons within the layer, thus achieving erasure. This embodiment uses a subset of the first memory cells as an example for illustration. Figure 14 As shown, the word line corresponding to the first set of memory cells is defined as the selected word line, denoted as Sel WL. The word lines corresponding to other memory cells in the memory cell array besides the first set of memory cells are defined as unselected word lines, denoted as Unsel WL. The word lines of memory cells without storage function are defined as dummy word lines, that is, the word lines corresponding to the dummy memory cell set are defined as dummy word lines, denoted as Dummy WL. The select transistor corresponding to the first subset of memory cells is defined as the selected select transistor. The serial select line connected to the selected select transistor is defined as the selected serial select line, denoted as Sel SSL. The select transistors corresponding to other memory cells in the first set of memory cells besides the first subset of memory cells are defined as unselected select transistors. The serial select line connected to the unselected select transistor is defined as the unselected serial select line, denoted as Unsel SSL. The downselect transistors corresponding to the first subset of memory cells are designated as selected downselect transistors, and the ground selection lines connected to the selected downselect transistors are designated as selected ground selection lines, denoted as Sel GSL. The downselect transistors corresponding to other memory cells in the first subset of memory cells are designated as unselected downselect transistors, and the ground selection lines connected to the unselected downselect transistors are designated as unselected ground selection lines, denoted as Unsel GSL. The bit lines are divided into two parts: one part is the bit line corresponding to the first subset of memory cells, denoted as BL_min, and the other part is the bit line corresponding to other memory cells in the first subset of memory cells, denoted as BL_other.

[0131] In step S1201, a first type of subprogramming operation is performed on the first set of storage cells corresponding to the selected word line in the storage device.

[0132] Here, the first set of storage cells is all the storage cells corresponding to the selected word line (Sel WL) in the storage device, and the first type of subprogramming operation includes coarse programming operation.

[0133] After performing a coarse programming operation on all memory cells corresponding to the selected word line (Sel WL), all memory cells corresponding to the selected word line are in either an erase state or any of the multiple programming states.

[0134] In other words, after performing a coarse programming operation on all memory cells corresponding to the selected word line (Sel WL), some memory cells are in the erase state, while the other part of the memory cells are in the intermediate programming state.

[0135] It should be noted that some memory cells in the erased state among all memory cells corresponding to the selected word line (Sel WL) require further programming operations in subsequent programming; conversely, some memory cells in the erased state among all memory cells corresponding to the selected word line (Sel WL) do not require further programming operations in subsequent programming, meaning that the target state for these memory cells is the erased state. Here, the memory cells in the first memory cell set whose target state is the erased state constitute the first memory cell subset. The target state is the memory state that the memory cell needs to reach when completing the programming operation. Another portion of memory cells in the intermediate programming state also need to be further programmed.

[0136] At this time, the first subset of storage cells has a fourth threshold voltage distribution P1'; reference Figure 13 The distribution is shown in ⑥. It should be noted that... Figure 13 Distribution ⑤ in the figure shows the threshold voltage distribution P0' of the memory cell corresponding to the selected word line in the initial state.

[0137] Here, after the memory cells corresponding to the initial state of the selected word line undergo the first type of subprogramming operation (i.e., coarse programming operation), the threshold voltage width of the first memory cell subset increases by L5, that is, the increased width is L5, as referenced. Figure 13 .

[0138] In step S1202, the first type of subprogramming operation is performed on the second set of memory cells corresponding to the word lines adjacent to the selected word lines.

[0139] Here, the second set of storage units is all storage units corresponding to word lines adjacent to the selected word line; the first type of subprogramming operation includes coarse programming operations.

[0140] It is understood that the word line adjacent to the selected word line includes two word lines, namely Unsel WLn+1 and Unsel WLn-1. Here, in some specific examples, when the storage device performs programming operations according to the sequential programming method, Unsel WLn-1 has already been programmed. In this case, the word line adjacent to the selected word line can be understood as Unsel WLn+1. Of course, in some specific examples, when the storage device performs programming operations according to the reverse programming method, Unsel WLn+1 has already been programmed. In this case, the word line adjacent to the selected word line can be understood as Unsel WLn-1. For clarity and simplicity, the following explanation will only use Unsel WLn+1 as an example of adjacent word lines.

[0141] After performing a first type of subprogramming operation (coarse programming operation) on the memory cell (i.e., the second memory cell set) corresponding to the word line adjacent to the selected word line (i.e., Unsel WLn+1), some memory cells in the second memory cell set are in the erase state; the other part of the memory cells are in the intermediate programming state.

[0142] It should be noted that after performing a first type of subprogramming operation on the second set of memory cells, the width of the threshold voltage distribution of the first set of memory cells in the erased state and the memory cells in the intermediate programming state both increase.

[0143] At this time, the first subset of storage cells has the fifth threshold voltage distribution P2', referenced Figure 13 The distribution is shown in section ⑦. Here, compared to the fourth threshold voltage distribution, its broadening increases by L6. The read window of the first memory cell subset is further reduced.

[0144] In step S1203, an erase operation is performed on the first subset of storage cells.

[0145] Here, after performing an erase operation on the first subset of memory cells, the first subset of memory cells has a sixth threshold voltage distribution P3', as referenced. Figure 13 The distribution is shown in Figure ⑧. Here, compared to the fifth threshold voltage distribution, its broadening is reduced by L7. In other words, after performing an erase operation on the first subset of memory cells, the threshold voltage distribution of the first subset of memory cells decreases, and its read window increases.

[0146] It should be noted that, in order to perform the erase operation only on the memory cells in the lowest state (i.e., erase state or target state is erase state) of the memory cells corresponding to the selected word line, that is, to perform the erase operation only on the first subset of memory cells, the embodiments of this application use the gate-induced drain leakage current method for erasure, but are not limited to this.

[0147] Understandably, during the gate-induced drain leakage current erasure process, an erasure voltage is applied to the control gate of the memory cell, while maintaining the channel potential corresponding to the memory cell string, thus achieving the erasure of the memory cell. After performing gate-induced drain leakage current erasure on the first subset of memory cells, the threshold voltage distribution of the first subset of memory cells is reduced. This increases the read window of the first subset of memory cells, thereby improving the reliability of the memory device.

[0148] In some embodiments, performing an erase operation on a first subset of storage cells in the first set of storage cells includes:

[0149] An erase voltage is applied to the bit lines corresponding to the first subset of memory cells in the first memory cell set, and a first voltage is applied to the bit lines corresponding to other memory cells in the first memory cell set besides the first subset of memory cells; the first voltage is less than the erase voltage.

[0150] It should be noted that when performing an erase operation on the first subset of memory cells, the ground voltage can be applied to zero before applying any voltages; after performing the erase operation on the first subset of memory cells, that is, after stopping applying any voltages, the ground voltage can also be applied to zero.

[0151] After the first subset of memory cells passes verification, the erase operation on the first subset of memory cells begins. An erase voltage Vers is applied to the bit line (BL_min) corresponding to the first subset of memory cells, and a first voltage V1 is applied to the bit lines (BL_other) corresponding to other memory cells, wherein the first voltage V1 is less than the erase voltage Vers.

[0152] Here, an erase voltage Vers is applied to the bit line (BL_min) corresponding to the lowest state memory cell in the selected word line, and an intermediate voltage lower than Vers, i.e., the first voltage V1, is applied to the bit lines corresponding to the other memory cells. This can reduce the voltage difference between different bit lines and prevent breakdown. Moreover, since the intermediate voltage is low, a relatively high GIDL voltage will not be generated in the channel, and there will be no obvious erase effect on other memory cells in the first memory cell set other than the first memory cell subset.

[0153] In some embodiments of this application, the erase voltage Vers can be in the range of approximately 15V to 25V. In some preferred embodiments of this application, the erase voltage Vers can be approximately 20V.

[0154] In some embodiments of this application, the first voltage V1 can be in the range of approximately 5V to 10V. In some preferred embodiments of this application, the first voltage V1 can be approximately 10V.

[0155] In some embodiments, the column driver / bit line driver is simultaneously connected to the bit line (BL_min) corresponding to the first subset of memory cells in the first memory cell set and the bit line (BL_other) corresponding to the memory cells other than the first subset of memory cells in the first memory cell set. Therefore, the first voltage V1 can be applied to BL_other while the erase voltage Vers is applied to BL_min.

[0156] The row driver / word line driver is connected to the corresponding word line of the storage device. In other words, multiple row drivers correspond one-to-one with multiple word lines. Therefore, the row driver corresponding to a selected word line can be controlled individually, that is, voltage is applied only to the selected word line without interfering with other unselected word lines.

[0157] In some embodiments, applying an erase voltage to the bit lines corresponding to the first subset of memory cells in the first memory cell set includes:

[0158] By increasing the voltage over time, the voltage applied to the bit lines corresponding to the first subset of memory cells rises to the erase voltage.

[0159] In some specific examples of embodiments, the voltage on the bit lines corresponding to the first subset of memory cells rises uniformly over time to the erase voltage.

[0160] In some embodiments, the method further includes:

[0161] After the voltage on the bit line corresponding to the first subset of the first memory cells in the first memory cell set rises to the first preset voltage, a second voltage is applied to the selected string selection line connected to the selected up selection transistor or the selected string selection line connected to the selected up selection transistor is floated.

[0162] Wherein, the selected upselect transistor is the upselect transistor corresponding to the first subset of the first memory cells in the first memory cell set; the first preset voltage is less than the erase voltage; and the second voltage is less than the erase voltage.

[0163] Still referencing Figure 15 After the voltage on the bit line (BL_min) corresponding to the first subset of memory cells in the first memory cell set rises to the first preset voltage, a second voltage V2 is applied to the selected string selection line (Sel SSL) connected to the selected up selection transistor; wherein the second voltage V2 is less than the erase voltage Vers.

[0164] Here, in order to match the voltage at the bit line terminal, the selected string selection line (Sel SSL) needs to be kept in the Vss (usually 0V) state at the beginning stage. After the voltage on the bit line (BL_min) corresponding to the first memory cell subset rises to the first preset voltage, a second voltage is applied to the selected string selection line (Sel SSL). In this way, the first memory cell subset can be erased through GIDL without erasing other memory cells corresponding to (Sel SSL).

[0165] In some other embodiments of this application, to coordinate with the voltage at the bit line terminals, the Select String Select Line (Sel SSL) needs to be kept at Vss (usually 0V) in the initial stage. Once the voltage on the bit line (BL_min) corresponding to the first subset of memory cells rises to a first preset voltage, the Select String Select Line (Sel SSL) is floated, i.e., no voltage is applied. It should be noted that those skilled in the art can select the value of the second voltage or the timing of floating the Select String Select Line (Sel SSL) as needed to ensure that the first subset of memory cells can be erased via GIDL without erasing other memory cells corresponding to the Select String Select Line (Sel SSL).

[0166] In this embodiment, the first preset voltage is within the range of the erase voltage Vers. For example, the first preset voltage may be approximately 8V.

[0167] In this embodiment, the second voltage V2 is less than the erase voltage Vers. For example, the second voltage V2 is less than 10V.

[0168] In some embodiments, the method further includes:

[0169] While applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set, a third voltage is applied to the unselected string selection line connected to the unselected up selection transistor, or the unselected string selection line connected to the unselected up selection transistor is floated.

[0170] Wherein, the unselected upselect transistor is the upselect transistor corresponding to other memory cells in the first memory cell set besides the first memory cell subset; the third voltage is equal to the erase voltage.

[0171] Still referencing Figure 15 While applying the erase voltage Vers to the bit line (BL_min) corresponding to the first subset of memory cells, a third voltage V3 is applied to the unselected string selection line (Unsel SSL) connected to the unselected up selection transistor; wherein the third voltage V3 is equal to the erase voltage Vers.

[0172] Here, a third voltage V3, synchronized with the erase voltage Vers, is applied to the Unsel SSL line, thus preventing the Unsel SSL line from generating GIDL and avoiding erasing the memory cell corresponding to the Unsel SSL line.

[0173] In some other embodiments of this application, the Unsel SSL can also be floated, i.e., without any voltage applied. In this case, the Unsel SSL can also be coupled to a high potential due to the parasitic capacitance between the bit line and the array common source.

[0174] In some embodiments, the method further includes:

[0175] While applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set, a fourth voltage is applied to the ground selection line connected to the down selection transistor in the first memory cell set, or the ground selection line connected to the down selection transistor in the first memory cell set is floated.

[0176] Wherein, the fourth voltage is equal to the erase voltage.

[0177] Still referencing Figure 15 While applying an erase voltage Vers to the bit line (BL_min) corresponding to the first subset of memory cells in the first memory cell set, a fourth voltage V4 is applied to the ground selection line connected to the downselect transistor in the first memory cell set; wherein, the fourth voltage V4 is equal to the erase voltage. Here, the ground selection line includes the selected ground selection line (Sel GSL) and the unselected ground selection line (Unsel GSL).

[0178] Here, a fourth voltage synchronized with the erase voltage Vers is applied to the Unselected String Select line (Unsel SSL), thus preventing erase carriers (i.e., holes) from flowing from the lower select transistor corresponding to the memory cell string to the array common source ACS corresponding to the memory cell string.

[0179] Still referencing Figure 15 When the boost is started on the bit line corresponding to the first subset of memory cells, the array common source ACS is floated, i.e., no voltage is applied.

[0180] In other embodiments of this application, the selected ground selection line (Sel GSL) and the unselected ground selection line (Unsel GSL) can also be floated, i.e., no voltage is applied. In this case, the ground selection line is affected by the channel voltage, and the voltage of the ground selection line can be coupled to the erase voltage Vers.

[0181] In some embodiments, the method further includes:

[0182] After the voltage on the bit line corresponding to the first subset of the first memory cell set rises to the second preset voltage, a fifth voltage is applied to the word lines of other memory cells in the memory cell array other than the first memory cell set and the dummy word lines of the dummy memory cell set, or the word lines of other memory cells in the first memory cell set other than the first memory cell subset and the dummy word lines of the dummy memory cell set are floated.

[0183] Wherein, the second preset voltage is less than the erase voltage; the fifth voltage is less than the erase voltage.

[0184] Still referencing Figure 15 After the voltage on the bit line (BL_min) corresponding to the first subset of memory cells in the first memory cell set rises to the second preset voltage, a fifth voltage V5 is applied to the word lines (Unsel WL) of other memory cells in the memory cell array other than the first memory cell set and the dummy word lines (Dummy WL) of the dummy memory cell set; wherein the fifth voltage V5 is less than the erase voltage Vers.

[0185] Here, a ground voltage Vss, i.e. 0V, can be applied to the word lines (Sel WL) of the first subset of memory cells; a fifth voltage V5 can be applied to the unselected word lines (Unsel WL) and dummy word lines (Dummy WL).

[0186] Here, after the voltage on the bit line (BL_min) corresponding to the first subset of memory cells rises to the second preset voltage, the unselected word line (Unsel WL) and the dummy word line (Dummy WL) can be floated, i.e., no voltage is applied. At this time, due to the parasitic capacitance between the bit line and the common source, the unselected word line (Unsel WL) can also couple up to voltage V. H In the embodiments of this application, the voltage V H It can have a size close to the erase voltage Vers.

[0187] Here, setting the Unselected Word Line (Unsel WL) and Dummy Word Line (Dummy WL) to a floating state allows gate-induced drain leakage current to be generated in the memory device. On the other hand, the memory cells corresponding to the Serial Select Line (Sel SSL) connected to the first subset of memory cells cannot be erased by the gate-induced drain leakage current.

[0188] In this embodiment, the second preset voltage is greater than the first preset voltage, and both the first and second preset voltages are within the range of the erase voltage Vers. For example, the first preset voltage can be approximately 8V, and the second preset voltage can be approximately 10V.

[0189] In this embodiment, the fifth voltage V5 is less than the erase voltage Vers. For example, the fifth voltage V5 is less than 15V.

[0190] In step S1204, after the erase operation, a second type of sub-programming operation is performed on the first set of storage cells to complete the programming of the first set of storage cells.

[0191] Here, the second type of subprogramming operation is a fine-programming operation.

[0192] Wherein, after performing the second type of subprogramming operation on the first set of memory cells, the first subset of memory cells has a seventh threshold voltage distribution P4', referenced Figure 13 The distribution is shown in Figure 9. Here, compared to the sixth threshold voltage distribution, its broadening increases by L8.

[0193] In other words, after performing an erase operation on the first subset of storage cells, the threshold voltage distribution of the first subset of storage cells decreases and its read window increases; this increases the reliability of the first subset of storage cells when performing coarse programming operations; and thus improves the reliability of the storage device.

[0194] In some embodiments, the method further includes:

[0195] No erase verification operation is performed after the erase operation is executed.

[0196] Understandably, after the erase operation is performed, the read window of the lowest-state storage unit increases; therefore, there is no need to perform the erase verification operation on the lowest-state storage unit again.

[0197] It is understandable that during the programming operation of the set of memory cells corresponding to a selected word line in the storage device using a multi-step programming method, each programming step affects the first subset of memory cells in the target state of the erase state, causing the threshold voltage distribution of the first subset of memory cells to widen, thereby reducing the read window of the first subset of memory cells. Based on this, in various embodiments of this application, by adding an erase operation on the first subset of memory cells in the target state of the erase state before performing the second type of sub-programming operation on the first subset of memory cells, the threshold voltage distribution width of the first subset of memory cells is reduced, thereby increasing the read window of the first subset of memory cells and improving the reliability of the storage device.

[0198] This application embodiment also provides a storage device, the storage device comprising:

[0199] A storage cell array, the storage cell array comprising multiple word lines, each word line corresponding to a storage cell set, and each storage cell set comprising multiple storage cells; and

[0200] Peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured as follows:

[0201] A programming operation is performed on the first set of storage cells corresponding to a selected word line in the storage device, such that the storage cells in the first set of storage cells are respectively in an erase state and any one of a plurality of programming states;

[0202] After the programming operation, an erase operation is performed on a first subset of the first storage cells in the first storage cell set; the first subset of the storage cells is the storage cells in the first storage cell set that are in an erased state after the programming operation.

[0203] Here, the memory cells have an erase state and multiple programming states (including Pm, Pm+1, ..., Pmax). From Pm to Pmax, the threshold voltage of the memory cell gradually increases. The erase state corresponds to the lowest-state memory cell, and the programming state Pmax corresponds to the highest-state memory cell. During the programming process, after the first subset of memory cells is in the initial erase state, other memory cells are also programmed sequentially. Due to interference from the programming operations of other memory cells, the threshold voltage of the first subset of memory cells drifts, causing the first subset of memory cells to drift from the initial erase state to the first erase state. Here, the first subset of memory cells is the lowest-state memory cell.

[0204] In other words, after the target programming state is verified, the first subset of memory cells drifts from the initial erase state to the first erase state. By performing an erase operation on the first subset of memory cells, the first subset of memory cells changes from the first erase state to the second erase state. The upper bound of the threshold voltage distribution in the first erase state is greater than the upper bound of the threshold voltage distribution in the second erase state.

[0205] In some embodiments of this application, the peripheral circuit is further configured as follows:

[0206] Perform a first type of subprogramming operation on the first set of memory cells corresponding to the selected word line in the memory device;

[0207] After the first type of subprogramming operation, an erase operation is performed on the first subset of storage cells in the first storage cell set;

[0208] After the erase operation, a second type of subprogramming operation is performed on the first set of storage cells to complete the programming of the first set of storage cells.

[0209] In some embodiments of this application, the peripheral circuit is further configured as follows:

[0210] After performing the first type of subprogramming operation on the first set of memory cells, perform the first type of subprogramming operation on the second set of memory cells corresponding to the word line adjacent to the selected word line;

[0211] After performing the first type of subprogramming operation on the second set of storage cells, an erase operation is performed on the first subset of storage cells.

[0212] In some embodiments of this application, the peripheral circuit is specifically configured to: apply an erase voltage to the bit lines corresponding to the first subset of memory cells in the first memory cell set, and apply a first voltage to the bit lines corresponding to other memory cells in the first memory cell set besides the first subset of memory cells; the first voltage is less than the erase voltage.

[0213] In some embodiments of this application, each of the memory cell arrays includes a plurality of memory cell strings, each memory cell string includes an up-select transistor, a plurality of memory cells and a down-select transistor, and each memory cell string is respectively connected to a bit line and a common source.

[0214] The peripheral circuit is specifically configured to: after the voltage on the bit line corresponding to the first subset of the first memory cells in the first memory cell set rises to the first preset voltage, apply a second voltage to the selected string selection line connected to the selected up selection transistor or float the selected string selection line connected to the selected up selection transistor.

[0215] Wherein, the selected upselect transistor is the upselect transistor corresponding to the first subset of the first memory cells in the first memory cell set; the first preset voltage is less than the erase voltage; and the second voltage is less than the erase voltage.

[0216] In some embodiments of this application, the peripheral circuit is specifically configured to: apply an erase voltage to the bit line corresponding to the first subset of the first memory cells in the first memory cell set, while applying a third voltage to the unselected string selection line connected to the unselected up-select transistor or floating the unselected string selection line connected to the unselected up-select transistor.

[0217] Wherein, the unselected upselect transistor is the upselect transistor corresponding to other memory cells in the first memory cell set besides the first memory cell subset; the third voltage is equal to the erase voltage.

[0218] In some embodiments of this application, the peripheral circuit is specifically configured to: apply an erase voltage to the bit line corresponding to the first subset of the first memory cells in the first memory cell set, while applying a fourth voltage to the ground selection line in the first memory cell set connected to the down selection transistor, or float the ground selection line in the first memory cell set connected to the down selection transistor.

[0219] Wherein, the fourth voltage is equal to the erase voltage.

[0220] In some embodiments of this application, the peripheral circuit is specifically configured to: after the voltage on the bit line corresponding to the first subset of the first memory cell set rises to the second preset voltage, apply a fifth voltage to the word lines of the other memory cells in the memory cell array other than the first memory cell set and the dummy word lines of the dummy memory cell set, or float the word lines of the other memory cells in the memory cell array other than the first memory cell set and the dummy word lines of the dummy memory cell set;

[0221] Wherein, the second preset voltage is less than the erase voltage; the fifth voltage is less than the erase voltage.

[0222] In some embodiments of this application, the second preset voltage is greater than the first preset voltage.

[0223] This application embodiment also provides a storage system, including a controller and the storage device described in the above technical solution; the controller is coupled to the storage device and is used to control the storage device.

[0224] In some embodiments of this application, the storage system includes a solid-state drive or a memory card.

[0225] It should be noted that the storage system described in the embodiments of this application includes, but is not limited to, solid-state drives.

[0226] In some embodiments, the controller may include an integrated control device for controlling the phase-change memory to perform various operations such as read operations, write operations, and erase operations. Examples include a central processing unit (CPU), error checking and correcting (ECC) circuitry that implements error checking and correction algorithms, and other components primarily related to logic operations.

[0227] Here, the controller can be used to control the storage device to perform erase, read or write operations, and to decode, parse or perform operations on instructions issued or received in the storage device.

[0228] This application provides a storage device and its operating method, and a storage system including the storage device. The storage device includes a storage cell array, the storage cell array includes multiple word lines, each word line corresponds to a storage cell set, and each storage cell set includes multiple storage cells. The method includes: performing a programming operation on a first storage cell set corresponding to a selected word line in the storage device, such that the storage cells in the first storage cell set are respectively in an erase state and any one of multiple programming states; after the programming operation, performing an erase operation on a first subset of storage cells in the first storage cell set; the first subset of storage cells is the storage cells in the first storage cell set that are in the erase state after the programming operation. In the operating method of the storage device provided in this application, by performing an erase operation on the first subset of storage cells that are in the erase state after the programming operation, i.e., the first subset of storage cells whose target state is erase, the upper bound of the threshold voltage distribution of the first subset of storage cells is reduced, thereby increasing the read window and improving the reliability of reading data.

[0229] It should be noted that the description of the storage device above is similar to the description of the operation method embodiment of the storage device above, and has similar beneficial effects as the operation method embodiment of the storage device, therefore, it will not be repeated. For technical details not disclosed in the storage device of this disclosure embodiment, please refer to the description of the operation method of the storage device in this disclosure embodiment for understanding.

[0230] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0231] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for operating a storage device, characterized in that, The storage device includes a memory cell array, the memory cell array includes multiple word lines, each word line corresponds to a memory cell set, each memory cell set includes multiple memory cells, the memory cell array includes multiple memory cell strings, each memory cell string includes an up-select transistor, multiple memory cells, and a down-select transistor, and each memory cell string is connected to a bit line and a common source, respectively; the method includes: A programming operation is performed on the first set of storage cells corresponding to a selected word line in the storage device, such that the storage cells in the first set of storage cells are respectively in an erase state and any one of a plurality of programming states; After the programming operation, an erase operation is performed on a first subset of memory cells in the first memory cell set, including: applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set; the first subset of memory cells is the memory cells in the first memory cell set that are in an erased state after the programming operation. After the voltage on the bit line corresponding to the first subset of memory cells in the first memory cell set rises to the first preset voltage, a second voltage is applied to the selected string selection line connected to the selected up-select transistor, or the selected string selection line connected to the selected up-select transistor is left floating; wherein, the selected up-select transistor is the up-select transistor corresponding to the first subset of memory cells in the first memory cell set; the first preset voltage is less than the erase voltage; the second voltage is less than the erase voltage.

2. The method of operating the storage device according to claim 1, characterized in that, Performing a programming operation on the first set of memory cells corresponding to a selected word line in the memory device includes: Perform a first type of subprogramming operation on the first set of memory cells corresponding to the selected word line in the memory device; After the erasure operation, the method further includes: Perform a second type of subprogramming operation on the first set of storage cells to complete the programming of the first set of storage cells.

3. The method of operating the storage device according to claim 2, characterized in that, The method further includes: After performing the first type of subprogramming operation on the first set of memory cells, perform the first type of subprogramming operation on the second set of memory cells corresponding to the word line adjacent to the selected word line; Performing an erase operation on a first subset of storage cells in the first set of storage cells includes: After performing the first type of subprogramming operation on the second set of storage cells, an erase operation is performed on the first subset of storage cells.

4. The method of operating the storage device according to any one of claims 1 to 3, characterized in that, Performing an erase operation on a first subset of storage cells in the first set of storage cells includes: An erase voltage is applied to the bit lines corresponding to the first subset of memory cells in the first memory cell set, and a first voltage is applied to the bit lines corresponding to the other memory cells in the first memory cell set besides the first subset of memory cells; the first voltage is less than the erase voltage.

5. The method of operating the storage device according to claim 4, characterized in that, The method further includes: While applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set, a third voltage is applied to the unselected string selection line connected to the unselected up selection transistor, or the unselected string selection line connected to the unselected up selection transistor is floated. Wherein, the unselected upselect transistor is the upselect transistor corresponding to other memory cells in the first memory cell set besides the first memory cell subset; the third voltage is equal to the erase voltage.

6. The method of operating the storage device according to claim 4, characterized in that, The method further includes: While applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set, a fourth voltage is applied to the ground selection line connected to the down selection transistor in the first memory cell set, or the ground selection line connected to the down selection transistor in the first memory cell set is floated. Wherein, the fourth voltage is equal to the erase voltage.

7. The method of operating the storage device according to claim 4, characterized in that, The method further includes: After the voltage on the bit line corresponding to the first subset of the first memory cell set rises to the second preset voltage, a fifth voltage is applied to the word lines of the other memory cells in the memory cell array other than the first memory cell set and the dummy word lines of the dummy memory cell set, or the word lines of the other memory cells in the memory cell array other than the first memory cell set and the dummy word lines of the dummy memory cell set are floated. Wherein, the second preset voltage is less than the erase voltage; the fifth voltage is less than the erase voltage.

8. The method of operating the storage device according to claim 7, characterized in that, The second preset voltage is greater than the first preset voltage.

9. The method of operating the storage device according to claim 1, characterized in that, The method further includes: No erase verification operation is performed after the erase operation.

10. A storage device, characterized in that, The storage device includes: A memory cell array, comprising multiple word lines, each word line corresponding to a memory cell set, each memory cell set comprising multiple memory cells, the memory cell array comprising multiple memory cell strings, each memory cell string comprising an up-select transistor, multiple memory cells, and a down-select transistor, each memory cell string being connected to a bit line and a common source, respectively; and Peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured as follows: A programming operation is performed on the first set of storage cells corresponding to a selected word line in the storage device, such that the storage cells in the first set of storage cells are respectively in an erase state and any one of a plurality of programming states; After the programming operation, an erase operation is performed on a first subset of memory cells in the first memory cell set, including: applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set; the first subset of memory cells is the memory cells in the first memory cell set that are in an erased state after the programming operation. After the voltage on the bit line corresponding to the first subset of memory cells in the first memory cell set rises to the first preset voltage, a second voltage is applied to the selected string selection line connected to the selected up-select transistor, or the selected string selection line connected to the selected up-select transistor is left floating; wherein, the selected up-select transistor is the up-select transistor corresponding to the first subset of memory cells in the first memory cell set; the first preset voltage is less than the erase voltage; the second voltage is less than the erase voltage.

11. The storage device according to claim 10, characterized in that, The peripheral circuit is also configured to: Perform a first type of subprogramming operation on the first set of memory cells corresponding to the selected word line in the memory device; After the first type of subprogramming operation, an erase operation is performed on the first subset of storage cells in the first storage cell set; After the erase operation, a second type of subprogramming operation is performed on the first set of storage cells to complete the programming of the first set of storage cells.

12. The storage device according to claim 11, characterized in that, The peripheral circuit is also configured to: After performing the first type of subprogramming operation on the first set of memory cells, perform the first type of subprogramming operation on the second set of memory cells corresponding to the word line adjacent to the selected word line; After performing the first type of subprogramming operation on the second set of storage cells, an erase operation is performed on the first subset of storage cells.

13. The storage device according to any one of claims 10 to 12, characterized in that, The peripheral circuit is specifically configured as follows: An erase voltage is applied to the bit lines corresponding to the first subset of memory cells in the first memory cell set, and a first voltage is applied to the bit lines corresponding to the other memory cells in the first memory cell set besides the first subset of memory cells. The first voltage is less than the erase voltage.

14. The storage device according to claim 13, characterized in that, The peripheral circuit is specifically configured as follows: While applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set, a third voltage is applied to the unselected string selection line connected to the unselected up selection transistor, or the unselected string selection line connected to the unselected up selection transistor is floated. Wherein, the unselected upselect transistor is the upselect transistor corresponding to other memory cells in the first memory cell set besides the first memory cell subset; the third voltage is equal to the erase voltage.

15. The storage device according to claim 13, characterized in that, The peripheral circuit is specifically configured as follows: While applying an erase voltage to the bit line corresponding to the first subset of memory cells in the first memory cell set, a fourth voltage is applied to the ground selection line connected to the down selection transistor in the first memory cell set, or the ground selection line connected to the down selection transistor in the first memory cell set is floated. Wherein, the fourth voltage is equal to the erase voltage.

16. The storage device according to claim 13, characterized in that, The peripheral circuit is specifically configured as follows: After the voltage on the bit line corresponding to the first subset of the first memory cell set rises to the second preset voltage, a fifth voltage is applied to the word lines of the other memory cells in the memory cell array other than the first memory cell set and the dummy word lines of the dummy memory cell set, or the word lines of the other memory cells in the memory cell array other than the first memory cell set and the dummy word lines of the dummy memory cell set are floated. Wherein, the second preset voltage is less than the erase voltage; the fifth voltage is less than the erase voltage.

17. The storage device according to claim 16, characterized in that, The second preset voltage is greater than the first preset voltage.

18. A storage system, characterized in that, It includes a controller and a storage device according to any one of claims 10 to 17; the controller is coupled to the storage device and is used to control the storage device.

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