A programming method of a three-dimensional memory, a three-dimensional memory and a memory system

Abstract

The present disclosure discloses a programming method of a three-dimensional memory, a three-dimensional memory and a memory system. The programming method comprises: performing programming operation on a plurality of memory cell layers to be programmed in the three-dimensional memory according to a preset programming sequence; wherein when a first programming operation is performed on a first memory cell contained in a first memory cell layer among the plurality of memory cell layers to be programmed, a distribution of threshold voltage of the first memory cell is offset by a set amount from a target distribution; wherein the set amount is used to compensate for the offset of the target distribution of the first memory cell contained in the first memory cell layer caused by interlayer interference by a second programming operation on a second memory cell contained in a second memory cell layer among the plurality of memory cell layers.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a programming method for a three-dimensional memory, a three-dimensional memory, and a memory system. Background Technology

[0002] With the development of 5G and big data in modern society, the demand for storage capacity is constantly increasing. Currently, the mainstream memory uses 3D NAND flash memory. In pursuit of higher storage density, the number of stacked layers and the number of bits per individual memory cell are increasing. As the number of stacked layers increases, the distance between layers inevitably shrinks due to limitations in the trench etching process. This makes interlayer interference a significant factor restricting the reliability of Flash memory. Therefore, a programming method to reduce interlayer interference is urgently needed, which is crucial for improving the reliability of Flash memory. Summary of the Invention

[0003] In view of this, the present disclosure provides a programming method for a three-dimensional memory, a three-dimensional memory, and a memory system. By dividing multiple data states of a memory cell into multiple data groups according to the degree of interlayer interference, and performing fine programming on the interfered memory cell according to the different degree of interlayer interference in each data group, different verification induction currents are used during the verification operation to offset the distribution of the threshold voltage by a preset amount to compensate for the offset of the threshold voltage distribution caused by interlayer interference, thereby improving the reliability of Flash.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a programming method for a three-dimensional memory, the programming method comprising:

[0006] The programming operations are performed on multiple memory cell layers to be programmed in the three-dimensional memory according to a preset programming order; wherein,

[0007] When performing a first programming operation on a first memory cell contained in a first memory cell layer of the plurality of memory cell layers to be programmed, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount.

[0008] The set amount is used to compensate for the offset of the target distribution of the first memory cell contained in the first memory cell layer caused by inter-layer interference due to the second programming operation of the second memory cell contained in the second memory cell layer among the plurality of memory cell layers.

[0009] Secondly, embodiments of this disclosure provide a three-dimensional memory, comprising:

[0010] A storage array, comprising multiple layers of memory cells; each layer of memory cells contains multiple memory cells.

[0011] and peripheral circuitry coupled to and configured to control the memory array, wherein;

[0012] The peripheral circuit is configured as follows:

[0013] The programming operations are performed on multiple memory cell layers to be programmed in the three-dimensional memory according to a preset programming order; wherein,

[0014] When performing a first programming operation on a first memory cell contained in a first memory cell layer of the plurality of memory cell layers to be programmed, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount.

[0015] The set amount is used to compensate for the offset of the target distribution of the first memory cell contained in the first memory cell layer caused by inter-layer interference due to the second programming operation of the second memory cell contained in the second memory cell layer among the plurality of memory cell layers.

[0016] Thirdly, embodiments of this disclosure also provide a memory system, including one or more of the three-dimensional memories described above.

[0017] This disclosure provides a programming method for a three-dimensional memory, a three-dimensional memory, and a memory system. The programming method includes: performing programming operations on multiple memory cell layers to be programmed in the three-dimensional memory according to a preset programming order; wherein, when performing a first programming operation on a first memory cell contained in a first memory cell layer of the multiple memory cell layers, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount; wherein the set amount is used to compensate for the offset of the target distribution of the first memory cell contained in the first memory cell layer caused by inter-layer interference due to a second programming operation on a second memory cell contained in a second memory cell layer of the multiple memory cell layers. The programming method for a three-dimensional memory provided in this disclosure, when a first memory cell in a first memory cell layer performs a first programming operation, compensates for the offset of the target distribution of the first memory cell caused by interlayer interference by the second programming operation of the second memory cell in a second memory cell layer by shifting the distribution of the threshold voltage of the first memory cell by a set amount relative to the target distribution. That is, when the first programming operation is performed on the first memory cell, the distribution of the threshold voltage of the first memory cell is shifted in a first direction by a set amount, thereby weakening or offsetting the effect of the second programming operation of the second memory cell on the offset of the distribution of its threshold voltage in a second direction, where the first direction and the second direction are opposite. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form a part of this disclosure, illustrate aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use embodiments of this disclosure.

[0019] Figure 1 A block diagram of an exemplary system having memory according to some aspects of embodiments of this disclosure;

[0020] Figure 2A A schematic diagram of an exemplary memory card having memory according to some aspects of embodiments of the present disclosure;

[0021] Figure 2B This is a schematic diagram of an exemplary solid-state drive (SSD) with memory according to some aspects of embodiments of the present disclosure;

[0022] Figure 3 A schematic diagram of an exemplary memory including peripheral circuitry according to some aspects of this disclosure;

[0023] Figures 4A-4D This is a schematic diagram showing the correspondence between the distribution of threshold voltages of the storage cell and the data state provided in the embodiments of this disclosure.

[0024] Figure 5a A circuit diagram of a storage cell string exemplarily provided in accordance with some aspects of this disclosure;

[0025] Figure 5b This is a schematic diagram illustrating an exemplary structure of a storage cell string according to some aspects of this disclosure;

[0026] Figure 6 A block diagram of an exemplary memory including a memory cell array and peripheral circuitry according to some aspects of this disclosure;

[0027] Figures 7A-7C Schematic diagrams illustrating several multi-pass programming methods provided in embodiments of this disclosure;

[0028] Figure 8 This is a schematic diagram of a programming sequence provided in an embodiment of the present disclosure;

[0029] Figure 9 In accordance with Figure 8 The programming order is a schematic diagram of the threshold cell distribution of the first memory page when programming the memory;

[0030] Figure 10 A flowchart illustrating a method for programming a memory according to an embodiment of this disclosure;

[0031] Figure 11 The embodiments provided in this disclosure are based on Figure 8 The programming sequence is shown and coupled to the word line WL N+1 After the multiple target data states of the storage unit are divided into four data groups, each data group is coupled to the word line WL. N The distribution of the threshold voltage after the memory cell is shifted to the left is coupled to the word line WL. N+1 A comparative schematic diagram showing the distribution of threshold voltages after fine programming of the memory cells. Detailed Implementation

[0032] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements can be used without departing from the scope of this disclosure. Furthermore, it is apparent that this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, as well as in ways not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0033] Generally, terms can be interpreted at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, thus depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and can instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0034] As described in the background section, a significant factor limiting the reliability of 3D NAND flash memory is inter-layer interference. Inter-layer interference primarily manifests as programming interference caused by a subsequent programmed memory cell on a previous programmed memory cell within the same memory cell string. This interference leads to an increase in the threshold voltage of the previously programmed memory cell, ultimately causing the distribution of threshold voltages of memory cells coupled to the same word line to shift to the right and broaden. For example, in the same memory cell string, word line W... N+1 Coupled to the next programmed memory unit, word line W N Coupled to the previously programmed memory cell, interlayer interference manifests as interference from the programming of the memory cell coupled to word line WLn+1, causing an increase and broadening of the threshold voltage distribution of the memory cell coupled to word line WLn, which in turn leads to an increase in bit error rate and a decrease in reliability. Furthermore, as the number of stacked layers increases, the distance between layers inevitably decreases due to the limitations of the channel etching process, which makes interlayer interference even more severe.

[0035] In addition, when a memory cell has multiple data states, in order to compress the distribution width of each state, increase the read window, and save programming time, the memory is usually programmed in multiple passes, which include at least one coarse programming and one fine programming pass. This will cause more severe programming interference to the memory cell being programmed when the later programmed memory cell is being fine programmed, thus leading to a decrease in reliability.

[0036] To address the aforementioned issues, this disclosure introduces a solution in which, during Flash programming, multiple data states of a memory cell are divided into multiple data groups according to the degree of interlayer interference. When performing a post-programming verification operation on the interfered memory cell according to each data group, a different verification induced current is used to offset the distribution of the threshold voltage by a preset amount to compensate for the offset of the threshold voltage distribution caused by interlayer interference, thereby improving the reliability of the Flash.

[0037] The present disclosure is described below with reference to a specific memory structure.

[0038] Figure 1 A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more three-dimensional memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the three-dimensional memories 104.

[0039] Specifically, the three-dimensional memory 104 can be any memory disclosed in this disclosure, such as the three-dimensional memory 104 disclosed in detail below, for example, a NAND flash memory (such as a three-dimensional (3D) NAND flash memory), which can have reduced leakage current from the drive transistor coupled to the unselected word line during the erase operation, and the size of the drive transistor is further reduced.

[0040] According to some embodiments, a memory controller 106 is coupled to a 3D memory 104 and a host 108, and is configured to control the 3D memory 104. The memory controller 106 can manage data stored in the 3D memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), where the SSD or eMMC is used as data storage for mobile devices with high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the 3D memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the 3D memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the 3D memory 104. The memory controller 106 can also perform any other suitable function, such as formatting the 3D memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0041] The memory controller 106 and one or more three-dimensional memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the memory controller 106 and a single three-dimensional memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108 is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, the memory controller 106 and multiple 3D memories 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The host 108 is coupled to the SSD connector 208. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0042] Figure 3 A schematic circuit diagram of an exemplary three-dimensional memory 104, including peripheral circuitry, is shown according to some aspects of this disclosure. Figure 3 As shown, the three-dimensional memory 104 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein storage transistors 306 are provided in the form of an array of NAND memory cell strings 308, each NAND memory cell string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory cell string 308 includes a plurality of storage transistors 306 (also simply referred to as storage cells) that are series-coupled and vertically stacked. Each storage transistor 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the storage transistor 306. Each storage transistor 306 may be a floating-gate type storage transistor including a floating-gate transistor, or a charge-trapping type storage transistor including a charge-trapping transistor.

[0043] Each storage transistor 306 discussed above can be a single-level storage cell or a multi-level storage cell. A single-level storage cell can be a single-level cell (SLC) capable of storing 1 bit; a multi-level storage cell can be a multi-level cell (MLC) capable of storing 2 bits, a three-level cell (TLC) capable of storing 3 bits, a four-level cell (QLC) capable of storing 4 bits, a five-level cell (PLC) capable of storing 5 bits, and so on. In practical applications, different types of storage cells have different data states, specifically as follows... Figures 4A to 4D The distribution curves of the threshold voltage of the memory cells are shown for single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC) respectively.

[0044] like Figure 4A As shown, in an SLC, there are two threshold voltage distributions: E and P. The threshold voltage distribution E corresponds to the erase data state, and the threshold voltage distribution P corresponds to the program data state. The threshold voltage of the threshold voltage distribution E corresponding to the erase data state is lower than the threshold voltage of the threshold voltage distribution P corresponding to the program data state. Therefore, memory cells with threshold voltages in the threshold voltage distribution E are in the erase data state, and memory cells with threshold voltages in the threshold voltage distribution P are in the program data state. In some embodiments, an SLC-type memory cell stores one bit of data; specifically, an erased memory cell stores data 1, and a programmable memory cell stores data 0.

[0045] like Figure 4B As shown, in MLC, there are four corresponding threshold voltage distributions: E, P1, P2, and P3, with the threshold voltages increasing sequentially. Similarly, the threshold voltage distribution E corresponds to the erase data state; the threshold voltage distributions P1, P2, and P3 correspond to the programmable data state. In some embodiments, MLC-type memory cells store two bits of data. Specifically, the erased memory cell stores data 11, the memory cell programmed to the P1 data state stores data 10, the memory cell programmed to the P2 data state stores data 01, and the memory cell programmed to the P3 data state stores data 00.

[0046] like Figure 4CAs shown, in TLC, there are eight threshold voltage distributions: E, S1, S2, S3, S4, S5, S6, and S7, with the threshold voltages increasing sequentially. Similarly, the threshold voltage distribution E corresponds to the erase data state; the threshold voltage distributions S1, S2, S3, S4, S5, S6, and S7 correspond to the programmable data state. In some embodiments, TLC-type memory cells store three bits of data. Specifically, the erased memory cell can store data 111, the memory cell programmed to the S1 data state stores data 110, the memory cell programmed to the S2 data state stores data 101, the memory cell programmed to the S3 data state stores data 100, the memory cell programmed to the S4 data state stores data 011, the memory cell programmed to the S5 data state stores data 010, the memory cell programmed to the S6 data state stores data 001, and the memory cell programmed to the S7 data state stores data 000.

[0047] like Figure 4D As shown, in QLC, there is a distribution of 16 threshold voltages: E (also known as L0, described later), L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15, with the threshold voltages increasing sequentially. Similarly, the threshold voltage distribution E corresponds to the erase data state; the threshold voltage distributions L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15 correspond to the programming data states. For data state N, this data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. In some embodiments, a QLC-type memory cell stores four bits of data. Specifically, an erased memory cell can store the data 1111, and memory cells programmed into L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15 data states can sequentially store the data 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, and 0000.

[0048] It should be noted that, regardless of the type of memory cell mentioned above, the distribution of each threshold voltage (data state) corresponds to a predetermined value of a set of data bits stored in the memory cell. The specific relationship between the data programmed into the memory cell and the level of the threshold voltage of the memory cell depends on the data encoding scheme adopted by the memory cell, such as using Gray code encoding scheme.

[0049] Return to Figure 3As shown, each NAND cell string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 can be configured to activate a selected NAND cell string 308 (column of the array) during read and program operations. In some embodiments, the sources of NAND cell strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., common SL). In other words, according to some embodiments, all NAND cell strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND cell string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory cell string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0050] For example Figure 3As shown, the NAND memory cell string 308 can be organized into multiple blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is the basic data unit for an erase operation, i.e., all memory transistors 306 on the same block 304 are erased simultaneously. To erase the memory transistors 306 in a selected block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be biased and coupled to the source line 314 of the selected block 304 and the unselected blocks 304 on the same plane as the selected block 304. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. The memory transistors 306 of the NAND memory cell string 308 in the same layer can be coupled via word lines 318, and all memory cells coupled by a word line 318 constitute a memory cell layer. Word line 318 selects which row of storage transistor 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of storage transistor 306, which is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory cell strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each storage transistor 306 in the corresponding page 320 and gate lines coupled to the control gates.

[0051] Figure 5a and Figure 5b An exemplary circuit diagram and an exemplary structural schematic diagram of a memory cell string 308 are shown respectively. The memory cell string shown in this embodiment includes four memory transistors. It is understood that this disclosure is not limited thereto, and the number of memory transistors in the memory cell string can be any number, such as 32 or 64.

[0052] like Figure 5a As shown, the first end of the memory cell string 308 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 308 includes a plurality of transistors connected in series between the first and second ends, including an up-select transistor TSG, memory transistors M1 to M4, and a down-select transistor BSG. The up-select transistor TSG is connected to the string select line SSL through its included drain-select gate (DSG), and the down-select transistor BSG is connected to the ground select line GSL through its included source-select gate (SSG). The gate conductors of memory transistors M1 to M4 are respectively connected to the corresponding word lines 318 of word lines WL1 to WL4. In some embodiments, the drain-select gate (DSG) may also be referred to as the first control gate; the source-select gate (SSG) may also be referred to as the second control gate.

[0053] like Figure 5b As shown, the memory cell string 308 structure includes a channel pillar 110. A channel region 111 is included in the middle portion of the channel pillar 110, and a tunneling dielectric layer 112, a charge storage layer 113, and a barrier dielectric layer 114 are disposed in the channel region 111 to form memory transistors M1 to M4. In this embodiment, the channel region 111 is, for example, composed of doped polysilicon, and the tunneling dielectric layer 112, charge storage layer 113, and barrier dielectric layer 114 may be composed of nitrides, such as silicon nitride, silicon oxynitride, silicon, or any combination thereof. The channel region 111 serves as the channel region for the selection transistor and the memory transistor, and the doping type of the channel region 111 is the same as the type of the selection transistor and the memory transistor. For example, for N-type selection transistors and memory transistors, the channel region 111 may be N-type doped polysilicon.

[0054] In this embodiment, the core of the channel post 110 is a channel region 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the barrier dielectric layer 114 form a stacked structure fixed around the sidewall of the core. In an alternative embodiment, the core of the channel post 110 is an additional insulating layer, and the channel region 111, the tunneling dielectric layer 112, the charge storage layer 113, and the barrier dielectric layer 114 form a stacked structure surrounding the core.

[0055] In this embodiment, the upper selection transistor TSG, the lower selection transistor BSG, and the storage transistors M1 to M4 share a common channel region 111 and a barrier dielectric layer 114. In the channel pillar 110, the channel region 111 provides the source / drain regions and channel regions for the plurality of transistors. In an alternative embodiment, the semiconductor layers and barrier dielectric layers for the upper selection transistor TSG and the lower selection transistor BSG, as well as the semiconductor layers and barrier dielectric layers for the storage transistors M1 to M4, can be formed in separate steps.

[0056] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory transistor 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory transistor 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional components may be included. Figure 6 Additional peripheral circuitry not shown.

[0057] Page buffer / sensor amplifier 604 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic unit 612. In one example, page buffer / sensor amplifier 604 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory transistor 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 316 representing a data bit stored in memory transistor 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic unit 612 and select one or more NAND memory cell strings 308 by applying a bit line voltage generated from voltage generator 610.

[0058] The line decoder / word line driver 608 can be configured to be controlled by the control logic unit 612 and to select / deselect block 304 of the memory cell array 301 and to select / deselect word line 318 of block 304. The line decoder / word line driver 608 can also be configured to drive word line 318 using word line voltages generated from the voltage generator 610. In some embodiments, the line decoder / word line driver 608 can also select / deselect and drive SSG line 315 and DSG line 313. As described in detail below, the line decoder / word line driver 608 is configured to perform an erase operation on memory transistor 306 coupled to one or more selected word lines 318. The voltage generator 610 can be configured to be controlled by the control logic unit 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0059] Control logic unit 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 614 can be coupled to control logic unit 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic unit 612 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 612, and to buffer status information received from control logic unit 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bitline driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0060] In conjunction with the memory structure described above, as previously mentioned, to achieve higher storage density, the number of stacked layers in the memory is increasing. As the number of stacked layers increases, the distance between layers decreases, leading to more pronounced inter-layer interference between adjacent layers in 3D NAND flash memory. Inter-layer interference refers to the edge electric field generated during programming of memory cells in any layer of a 3D NAND flash memory chip. This field affects the number of electrons stored in programmed memory cells in adjacent layers, potentially causing changes in the threshold voltage of the programmed memory cells, especially those in adjacent layers belonging to the same memory cell string.

[0061] Furthermore, to achieve higher storage density, the number of bits stored in a single memory cell is increasing. Currently, the highest mass-produced single memory cell on the market can store 4 bits, known as a Quad-Level Cell (QLC). To achieve four-bit storage, a memory page needs to be divided into 16 data states. To compress the distribution width of the threshold voltage for each data state and improve the read window margin, the common approach is to perform multiple write operations on each memory page, often referred to as multi-pass programming involving at least one coarse programming and one fine programming pass. In practical implementation, one optional programming method for multi-pass programming can be as follows: Figure 7A The 16-16 two-pass programming shown can first roughly program to 16 intermediate data states, and then finely program from these 16 intermediate data states to the final 16 data states. However, to save programming time, usually m (m < 16) intermediate data states are not programmed during the rough programming, but rather... Figure 7BThe 8-16 two-pass programming shown can be roughly programmed to 8 intermediate data states first, and then finely programmed from these 8 intermediate data states to the final 16 data states. For example, ... Figure 7C The 4-16 two-pass programming shown can first roughly program to 4 intermediate data states, and then finely program from these 4 intermediate data states to the final 16 data states. This will cause the later finely programmed memory cell in the same memory cell string to seriously interfere with the threshold voltage of the previous finely programmed memory cell. In other words, the interference between fine to fine layers is relatively serious, which leads to a decrease in the reliability of the three-dimensional memory.

[0062] For example, if according to Figure 8 The programming order shown is as follows: When programming multiple memory cell layers to be programmed, first program the layers coupled to word line W. N The memory cell is subjected to coarse programming in multiple programming passes; then the memory cell coupled to the word line W is subjected to coarse programming. N+1 The memory cell is subjected to coarse programming in multiple programming passes; then the memory cell coupled to the word line W is subjected to coarse programming. N The memory cell undergoes fine-grained programming in multiple programming passes; then the memory cell coupled to the word line W is fine-grained. N+2 The memory cell is subjected to coarse programming in multiple programming passes; then the memory cell coupled to the word line W is subjected to coarse programming. N+1 The memory unit is used for fine-grained programming in multiple programming passes. When programming in this sequence, it is coupled to the word line W. N The distribution of threshold voltage of the memory cell is as follows Figure 9 As shown. The solid black line indicates the line coupled to the word line WL. N The distribution of threshold voltages after coarse programming of the memory cell; the dashed line adjacent to the black solid line (or the first dashed line from left to right) represents the voltage coupled to the word line W. N+1 After coarse programming in multiple programming passes, the memory cell is coupled to the word line WL. N The distribution of threshold voltages in the memory cells; the second dashed line from left to right represents the line coupled to word line W. N The memory cell undergoes fine-grained programming in multiple programming passes and is coupled to the word line W N+2 After coarse programming in multiple programming passes, the memory cell is coupled to word line W. N The distribution of threshold voltages in the memory cells; the third dashed line from left to right represents the line coupled to word line W. N+1 After fine-tuning the memory cell through multiple programming passes, it is coupled to word line W. N The distribution of threshold voltages in the memory cells. From Figure 9 As can be seen from this, the coupling is on the word line W N+1After multiple passes of fine-to-fine programming of the memory cell, interference between Fine to Fine layers causes the already finely programmed coupling word line W to... N The distribution of threshold voltages in the memory cells shifted to the right and broadened.

[0063] To address this issue, the applicant's research revealed that Fine to Fine inter-layer interference has the following characteristic: assuming that the interference is coupled to word line W on the same memory cell string... N+1 The threshold voltage of a memory cell after coarse programming is Vt1, and the threshold voltage of the memory cell after fine programming is Vt2. The larger the value of Vt2-Vt1, the more likely the memory cell is to be serially coupled to the word line W. N The greater the interlayer interference of finely programmed storage cells.

[0064] Therefore, in order to solve the above-mentioned technical problems, such as Figure 10 The diagram illustrates a flowchart of a programming method for a three-dimensional memory according to an embodiment of this disclosure. Specifically, the programming method may include:

[0065] S1001: Programming operations are performed on multiple memory cell layers to be programmed in the three-dimensional memory according to a preset programming sequence; wherein, when performing a first programming operation on a first memory cell contained in a first memory cell layer among the multiple memory cell layers to be programmed, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount; wherein, the set amount is used to compensate for the offset of the target distribution of the first memory cell contained in the first memory cell layer caused by inter-layer interference due to the second programming operation of the second memory cell contained in the second memory cell layer among the multiple memory cell layers.

[0066] It should be noted that the structure of the three-dimensional memory provided in this disclosure embodiment can be the structure described above, or it can be any type of three-dimensional memory that addresses the technical problems raised in this disclosure embodiment. In other words, the programming method for the three-dimensional memory provided in this disclosure embodiment has a certain degree of universality.

[0067] It should be noted that when data needs to be written to 3D NAND, the corresponding storage cell can be allocated to the data to be stored based on the number of bits that the storage cell in the 3D NAND can store (this process can be completed within the host or within the memory controller of the memory, i.e., specifying the corresponding storage cell for the data to be stored). After allocating the corresponding storage cell to the data to be stored, the memory cell layer to which each allocated storage cell belongs (coupled to which word line) can be determined. That is, the multiple memory cell layers to be programmed in the 3D memory are determined before the programming operation begins. Typically, the multiple memory cell layers are programmed according to a preset programming order, that is: the multiple memory cell layers to be programmed in the 3D memory are programmed according to the preset programming order.

[0068] In practical applications, the preset programming order can be any feasible order. Regardless of the programming order, for adjacent memory cell layers, the memory cells contained in the memory cell layer that is programmed later will cause fine-to-fine inter-layer interference to the memory cells contained in the memory cell layer that was programmed earlier. Therefore, the embodiments of this disclosure can use one of the preset programming orders to illustrate the solution provided by this disclosure.

[0069] For example, in some embodiments, the first programming operation and the second programming operation include multiple programming passes; the multiple programming passes are two programming passes including coarse programming and fine programming, and correspondingly, the preset programming order is as follows: coarse programming of the first memory cell contained in the first memory cell layer; coarse programming of the second memory cell contained in the second memory cell layer; fine programming of the first memory cell; coarse programming of the third memory cell contained in the third memory cell layer among the multiple memory cell layers to be programmed; fine programming of the second memory cell, wherein the second memory cell layer is located between the third memory cell layer and the first memory cell layer.

[0070] Here, both the first programming operation and the second programming operation are included within the aforementioned programming operations. The first memory cell layer, the second memory cell layer, and the third memory cell layer are merely illustrative descriptions of the programming order of different memory cell layers and are not intended to limit this disclosure.

[0071] For example, the first memory cell layer can be as described above. Figure 8 The coupling shown is on word line W N The first memory cell layer belongs to the second memory cell layer; the second memory cell layer can be the aforementioned. Figure 8 The coupling shown is on word line W N+1The corresponding memory cell layer; the third memory cell layer can be the aforementioned Figure 8 The coupling shown is on word line W N+2 The memory cell layer to which it belongs.

[0072] When programming the memory cell layers to be programmed according to the aforementioned preset programming order, the technical solution provided by this embodiment is as follows: When performing the first programming operation on the first memory cell included in the first memory cell layer, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount; the set amount is used to compensate for the offset of the target distribution caused by inter-layer interference when the second memory cell performs the second programming operation. That is, the distribution of the threshold voltage of the first memory cell is to reach the target distribution according to the user's requirements. Due to inter-layer interference, the distribution of the threshold voltage of the first memory cell is offset to the right compared to the target distribution. Therefore, when programming the first memory cell, the distribution of the threshold voltage of the first memory cell is first offset to the left by a set amount compared to the target distribution in order to compensate for the amount of subsequent offset to the right due to inter-layer interference, thereby offsetting the influence of inter-layer interference.

[0073] In some embodiments, the step of shifting the distribution of the threshold voltage of the first memory cell from the target distribution by a set amount may include:

[0074] Identify multiple target data states corresponding to the second memory cells contained in the second memory cell layer;

[0075] The plurality of target data states are divided into a plurality of data groups, the degree of inter-layer interference of the second memory unit contained in the first memory unit contained in the second memory unit layer to the second memory unit contained in the second memory unit layer increases sequentially.

[0076] Determine the reference verification sensing current corresponding to each of the plurality of data groups for verifying the successful programming of the first memory cell contained in the first memory cell layer;

[0077] When performing the first programming operation on the first storage cell, the first storage cell being programmed is verified based on the reference verification sensing current corresponding to the data group, so that the distribution of the threshold voltage of the first storage cell is offset from the target distribution by a set amount.

[0078] It should be noted that since the set amount of the threshold voltage distribution offset of the first memory cell is to compensate for the interlayer interference when the second memory cell performs the second programming operation, in actual operation, it is necessary to quantify the degree of interlayer interference of the second memory cell to the first memory cell, and how to obtain the offset of the set amount of the threshold voltage distribution of the first memory cell under different degrees.

[0079] According to the aforementioned applicant's research, Fine to Fine inter-layer interference has the following characteristic: assuming that it is coupled to word line W on the same memory cell string... N+1 The threshold voltage of a memory cell after coarse programming is Vt1, and the threshold voltage of the memory cell after fine programming is Vt2. The larger the value of Vt2-Vt1, the more likely the memory cell is to be serially coupled to the word line W. N The greater the interlayer interference of a finely programmed memory cell, the more complex the interlayer interference. Therefore, the second memory cell's multiple target data states are divided into multiple data groups with progressively increasing interlayer interference levels. Then, a reference verification current is determined for each data group to verify the successful programming of the first memory cell. Then, during the first programming operation on the first memory cell, the reference verification current corresponding to the data group is used to verify the programmed first memory cell, causing the threshold voltage distribution of the first memory cell to deviate from the target distribution by a set amount. The greater the interlayer interference level of a data group among the multiple data groups, the greater the reference verification current corresponding to that data group.

[0080] It should be noted that the multiple target data states mentioned here can refer to the final multiple data states to which the second storage unit will be programmed. For example, if the second storage unit is of type QLC, then the multiple target data states can be 16 data states. As another example, if the second storage unit is of type TLC, then the multiple target data states can be 8 data states.

[0081] In some embodiments, the control logic unit of the peripheral circuit can determine the target data state to which the memory unit should be programmed by reading the data latch connected to the memory unit. This process can be called re-load data. As described above, before programming, the host or memory controller allocates a memory unit for the data to be stored. The allocated data is temporarily stored in the latch so that the control logic unit can access it.

[0082] Regarding how to divide the data into multiple data groups, in some embodiments, when the second programming operation involves multiple programming passes; the multiple target data states are the final data states of the second memory cell after fine programming in the multiple programming passes; dividing the multiple target data states into multiple data groups according to the degree of inter-layer interference of the second programming operation of the second memory cell contained in the second memory cell layer to the first memory cell contained in the first memory cell layer increases sequentially includes:

[0083] Identify one or more intermediate data states included in the last rough programming pass of the multi-pass programming; the number of intermediate data states is not greater than the number of the multiple target data states;

[0084] Determine the correspondence between the one or more intermediate data states and the plurality of target data states;

[0085] Based on the correspondence, the plurality of target data states are divided into a plurality of data groups in which the degree of interlayer interference to the first memory cells contained in the first memory cell layer increases sequentially, wherein the number of the plurality of data groups is equal to the number of the intermediate data states.

[0086] It should be noted that, as Figures 7A-7C As shown in the two-pass programming examples, multi-pass programming can have different modes. Under different multi-pass programming, the number of intermediate data states included in the last rough programming is different, and the number of final data states (target data states) corresponding to each intermediate data state is different. Therefore, when dividing multiple target data states into multiple data groups according to the increasing degree of inter-layer interference, the multi-pass programming used should be considered.

[0087] The above-mentioned division process can be specifically as follows: First, determine one or more intermediate data states included in the last coarse programming pass of the multi-pass programming, wherein the number of intermediate data states is not greater than the number of multiple target data states. Then, determine the correspondence between the one or more intermediate data states and the multiple target data states, that is, determine that each of the one or more intermediate data states corresponds to at least one target data state among the multiple target data states after the fine programming. Then, based on the correspondence, divide the multiple target data states into multiple data groups in order of increasing interlayer interference to the first memory cells contained in the first memory cell layer, wherein the number of the multiple data groups is equal to the number of intermediate data states.

[0088] Specifically, in some embodiments, dividing the plurality of target data states into a plurality of data groups according to the correspondence relationship, with the degree of inter-layer interference to the first memory cells contained in the first memory cell layer increasing sequentially, includes:

[0089] The target data state corresponding to the largest threshold voltage of each intermediate data state in the correspondence is assigned to the first data group with the greatest inter-layer interference.

[0090] The target data state corresponding to the lowest threshold voltage of each intermediate data state in the correspondence is assigned to the second data group with the least interlayer interference.

[0091] The target data state corresponding to the intermediate threshold voltage of each intermediate data state in the correspondence is divided into at least one third data group with a medium level of interlayer interference.

[0092] The first data group, the second data group, and the third data group constitute the plurality of data groups.

[0093] Because of the aforementioned characteristics of Fine to Fine interlayer interference, when the threshold voltage of the second storage cell programmed to the first intermediate data state is the first threshold voltage and the threshold voltage of the second storage cell programmed to the first target data state corresponding to the first intermediate data state is the second threshold voltage, the greater the difference between the second threshold voltage and the first threshold voltage, the greater the degree of interlayer interference.

[0094] Therefore, multiple target data states are divided into multiple data groups with progressively increasing interlayer interference to the first storage unit according to their correspondence with intermediate data states.

[0095] The use of the terms "first data group," "second data group," and "at least one third data group" here is merely for illustrative purposes and is not intended to limit this disclosure.

[0096] In some embodiments, the plurality of target data states include 16 target data states from L0 to L15; the one or more intermediate data states include: a first intermediate data state, a second intermediate data state, a third intermediate data state, and a fourth intermediate data state; the correspondence includes: the first intermediate data state corresponds to four target data states from L0 to L3, the second intermediate data state corresponds to four target data states from L4 to L7, the third intermediate data state corresponds to four target data states from L8 to L11, and the fourth intermediate data state corresponds to four target data states from L12 to L15;

[0097] Correspondingly, the first data group includes: target data state L3, target data state L7, target data state L11, and target data state L15;

[0098] The second array includes: target data state L0, target data state L4, target data state L8, and target data state L12;

[0099] The at least one third data group includes: a third data group consisting of target data state L1, target data state L5, target data state L9, and target data state L13, and a third data group consisting of target data state L2, target data state L6, target data state L10, and target data state L14.

[0100] Here, taking the multi-pass programming as a two-step programming of 4-16 as an example, since L0 to L3 are finely programmed from the first state after coarse programming, compared to the word line WL... N+1 The coupled storage unit is the L0 target data state, WL N+1 When the coupled memory cell is in L3 target data state, its word line WL to the same memory cell string NThe interference between connected memory cells is greater (because Vt2-Vt1 is greater), while WL N+1 When the coupled memory cell is in the L0 state, its relationship with WL is... N Coupled memory cells experience less interference (because Vt2-Vt1 is smaller). Similarly, comparing WL... N+1 When the coupled memory cells are L4 to L7, and WLn+1 is coupled to L7, then WL... N Coupled memory cells experience greater interference. Therefore, WL can ultimately be... N+1 The multiple target data states (target levels) of the coupled memory cells are divided into four level groups: L0 / L4 / L8 / L12 is level group 1, L1 / L5 / L9 / L13 is level group 2, L2 / L6 / L10 / L14 is level group 3, and L3 / L7 / L11 / L15 is level group 4. These four level groups correspond to WL. N The severity of interference in coupled memory cells increases sequentially.

[0101] In some embodiments, the greater the interlayer interference level corresponding to a data group among the plurality of data groups, the greater the reference verification induced current corresponding to that data group; correspondingly, determining the reference verification induced current for verifying the successful programming of the first memory cell contained in the first memory cell layer for each data group among the plurality of data groups includes:

[0102] The reference verification induced current corresponding to the first data group is determined to be a first current value;

[0103] The reference verification induced current corresponding to the second data group is determined to be the second current value;

[0104] The reference verification induced current corresponding to each of the at least one third data group is determined as a third current value;

[0105] Wherein, the first current value is greater than the third current value; and the third current value is greater than the second current value.

[0106] It should be noted that as the programming pulse increases, the threshold voltage of the memory cell gradually increases, while the channel current gradually decreases as the threshold voltage of the memory cell increases. If different reference verification sense currents are used to verify whether the memory cell is programmed, the threshold voltage of the memory cell when programming is completed (verified by programming) is also different. For example, if the reference verification sense current I2 > I1, then the threshold voltage VT2 < VT1 of the memory cell when programming is completed (verified by programming). Therefore, by adjusting the reference verification sense current for programming verification, the threshold voltage position of the memory cell when programming is completed can be adjusted. Based on this, in the embodiments of the present disclosure, according to this principle, based on the degree of interlayer interference of the second memory cell on the first memory cell, the magnitude of the reference verification sense current for verifying the successful programming of the first memory cell is set, so that when the first memory cell performs the first programming operation, it shifts to the left by a set amount relative to the target distribution first, so as to offset the influence of the rightward shift of the distribution of the threshold voltage of the first memory cell caused by interlayer interference.

[0107] For example, as Figure 11 shown, it shows the programming sequence provided by the embodiments of the present disclosure and the Figure 8 threshold voltage distributions of multiple target data states of the memory cells coupled to the word line WL N+1 after being divided into four data groups and corresponding to each data group, and the comparison schematic diagram of the threshold voltage distributions of the memory cells coupled to the word line WL N after being offset to the left and the threshold voltage distributions of the memory cells coupled to the word line WL N+1 after fine programming. In Figure 11 , figure (a) corresponds to: After the fine programming of the memory cells coupled to the word line WL N , according to the different data groups level group of the memory cells coupled to the word line WL N+1 , the corresponding reference verification sense current for verifying the successful fine programming of the memory cells coupled to the word line WL N is adjusted, so that the memory cells coupled to the word line WL N form the following threshold voltage distributions after their fine programming. Among them, for the data group with a greater degree of interlayer interference, the larger the reference verification sense current used, the greater the preset amount of the leftward shift of the threshold voltage distribution of the memory cells coupled to the word line WL N . For example, the data group level group of the memory cells coupled to the word line WL N+1 has a greater influence on the memory cells coupled to the word line WL NThe inter-level interference levels of the memory cell layers are as follows: level group4 -> level group3 -> level group2 -> level group1. Correspondingly, the reference verification induced current for each data group decreases sequentially, coupled to the word line WL. N The preset amount by which the threshold voltage distribution of the memory cell shifts to the left decreases sequentially. Corresponding to Figure (b): After coupling to word line WL N+1 After fine programming of the memory cells, they are coupled to the word lines WL in the order of level group4->level group3->level group2->level group1. N The threshold voltage of the memory cell shifts to the right, decreasing sequentially. The final result is that this operation can eliminate or reduce coupling to the word line WL. N+1 The memory cells are coupled to the word line WL N Fine to Fine interlayer interference in the storage unit.

[0108] The memory programming method provided in this disclosure divides multiple data states of a memory cell into multiple data groups according to the degree of inter-layer interference. After performing fine programming on the interfered memory cell according to the different degree of inter-layer interference in each data group, different verification induced currents are used during the verification operation to offset the distribution of the threshold voltage by a preset amount to compensate for the offset of the threshold voltage distribution caused by inter-layer interference, thereby improving the reliability of Flash.

[0109] Based on the same inventive concept, this disclosure also provides a three-dimensional memory, which may include:

[0110] A storage array, comprising multiple layers of memory cells; each layer of memory cells contains multiple memory cells.

[0111] and peripheral circuitry coupled to and configured to control the memory array, wherein;

[0112] The peripheral circuit is configured as follows:

[0113] The programming operations are performed on multiple memory cell layers to be programmed in the three-dimensional memory according to a preset programming order; wherein,

[0114] When performing a first programming operation on a first memory cell contained in a first memory cell layer of the plurality of memory cell layers to be programmed, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount.

[0115] The set amount is used to compensate for the offset of the target distribution of the first memory cell contained in the first memory cell layer caused by inter-layer interference due to the second programming operation of the second memory cell contained in the second memory cell layer among the plurality of memory cell layers.

[0116] It should be noted that the aforementioned memory cell array 301 is a specific example of the memory array described here.

[0117] In some embodiments, the peripheral circuit is further configured to:

[0118] Identify multiple target data states corresponding to the second memory cells contained in the second memory cell layer;

[0119] The plurality of target data states are divided into a plurality of data groups, the degree of inter-layer interference of the second memory unit contained in the first memory unit contained in the second memory unit layer to the second memory unit contained in the second memory unit layer increases sequentially.

[0120] Determine the reference verification sensing current corresponding to each of the plurality of data groups for verifying the successful programming of the first memory cell contained in the first memory cell layer;

[0121] When performing the first programming operation on the first storage cell, the first storage cell being programmed is verified based on the reference verification sensing current corresponding to the data group, so that the distribution of the threshold voltage of the first storage cell is offset from the target distribution by a set amount.

[0122] In some embodiments, when the second programming operation includes multiple programming passes; the plurality of target data states are the final data states of the second storage cell after fine programming in the multiple programming passes; the peripheral circuit is further configured to: determine one or more intermediate data states included in the last coarse programming pass in the multiple programming passes; the number of intermediate data states is not greater than the number of the plurality of target data states;

[0123] Determine the correspondence between the one or more intermediate data states and the plurality of target data states;

[0124] Based on the correspondence, the plurality of target data states are divided into a plurality of data groups in which the degree of interlayer interference to the first memory cells contained in the first memory cell layer increases sequentially, wherein the number of the plurality of data groups is equal to the number of the intermediate data states.

[0125] In some embodiments, the peripheral circuit is further configured to: divide the target data state corresponding to the largest threshold voltage of each intermediate data state in the correspondence into the first data group with the greatest interlayer interference.

[0126] The target data state corresponding to the lowest threshold voltage of each intermediate data state in the correspondence is assigned to the second data group with the least interlayer interference.

[0127] The target data state corresponding to the intermediate threshold voltage of each intermediate data state in the correspondence is divided into at least one third data group with a medium level of interlayer interference.

[0128] The first data group, the second data group, and the third data group constitute the plurality of data groups.

[0129] In some embodiments, the plurality of target data states include 16 target data states from L0 to L15; the one or more intermediate data states include: a first intermediate data state, a second intermediate data state, a third intermediate data state, and a fourth intermediate data state; the correspondence includes: the first intermediate data state corresponds to four target data states from L0 to L3, the second intermediate data state corresponds to four target data states from L4 to L7, the third intermediate data state corresponds to four target data states from L8 to L11, and the fourth intermediate data state corresponds to four target data states from L12 to L15;

[0130] Correspondingly, the first data group includes: target data state L3, target data state L7, target data state L11, and target data state L15;

[0131] The second array includes: target data state L0, target data state L4, target data state L8, and target data state L12;

[0132] The at least one third data group includes: a third data group consisting of target data state L1, target data state L5, target data state L9, and target data state L13, and a third data group consisting of target data state L2, target data state L6, target data state L10, and target data state L14.

[0133] In some embodiments, the greater the interlayer interference level of the data group in the plurality of data groups, the greater the reference verification sensing current corresponding to the data group, and the peripheral circuit is further configured to: determine the reference verification sensing current corresponding to the first data group as a first current value;

[0134] The reference verification induced current corresponding to the second data group is determined to be the second current value;

[0135] The reference verification induced current corresponding to each of the at least one third data group is determined as a third current value;

[0136] Wherein, the first current value is greater than the third current value; and the third current value is greater than the second current value.

[0137] It should be noted that this memory belongs to the same inventive concept as the aforementioned memory programming method. All terms used in this memory have been explained in detail in the aforementioned programming method and are equally applicable here, and will not be repeated. It should be understood that only the structure of the memory most relevant to this disclosure is described here; other structures can be as described above. Figures 1 to 6 The structure shown can also be the structure of other memory.

[0138] Based on the same inventive concept, this disclosure also provides a memory system that may include:

[0139] The memory includes a storage array, one or more of the aforementioned three-dimensional memories.

[0140] In some embodiments, the memory system is a solid-state drive (SSD) or a memory card.

[0141] It should be noted that this memory system includes the aforementioned memory; therefore, they share the same technical features. All terms appearing in this memory system have been explained in detail in the aforementioned memory and are equally applicable here, without further repetition. It should be understood that only the structure of the memory system most relevant to the present disclosure is described herein; other structures can be as described above. Figures 1 to 7C The structure shown can also be the structure of other memory systems.

[0142] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

Claims

1. A programming method for a three-dimensional memory, characterized in that, The programming method includes: The programming operations are performed on multiple memory cell layers to be programmed in the three-dimensional memory according to a preset programming order; wherein, When performing a first programming operation on a first memory cell contained in a first memory cell layer of the plurality of memory cell layers to be programmed, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount. The set amount is used to compensate for the offset of the target distribution of the second memory cell contained in the second memory cell layer in the plurality of memory cell layers due to inter-layer interference caused by the second programming operation of the second memory cell in the second memory cell layer. The step of shifting the distribution of the threshold voltage of the first memory cell from the target distribution by a set amount includes: identifying multiple target data states corresponding to the second memory cells contained in the second memory cell layer; dividing the multiple target data states into multiple data groups whose interlayer interference with the first memory cells contained in the first memory cell layer increases sequentially according to the second programming operation of the second memory cells contained in the second memory cell layer; determining a reference verification sensing current corresponding to each data group in the multiple data groups for verifying the successful programming of the first memory cells contained in the first memory cell layer; and verifying the programmed first memory cell based on the reference verification sensing current corresponding to the data group when performing the first programming operation on the first memory cell, thereby shifting the distribution of the threshold voltage of the first memory cell from the target distribution by a set amount.

2. The programming method according to claim 1, characterized in that, When the second programming operation involves multiple programming passes; the multiple target data states are the final data states of the second memory cell after fine programming in the multiple programming passes; dividing the multiple target data states into multiple data groups according to the degree of inter-layer interference of the second programming operation of the second memory cell contained in the second memory cell layer to the first memory cell contained in the first memory cell layer increases sequentially includes: Identify one or more intermediate data states included in the last rough programming pass of the multi-pass programming; the number of intermediate data states is not greater than the number of the multiple target data states; Determine the correspondence between the one or more intermediate data states and the plurality of target data states; Based on the correspondence, the plurality of target data states are divided into a plurality of data groups in which the degree of interlayer interference to the first memory cells contained in the first memory cell layer increases sequentially, wherein the number of the plurality of data groups is equal to the number of the intermediate data states.

3. The programming method according to claim 2, characterized in that, The step of dividing the multiple target data states into multiple data groups based on the correspondence relationship, with the degree of inter-layer interference to the first memory cells contained in the first memory cell layer increasing sequentially, includes: The target data state corresponding to the largest threshold voltage of each intermediate data state in the correspondence is assigned to the first data group with the greatest inter-layer interference. The target data state corresponding to the lowest threshold voltage of each intermediate data state in the correspondence is assigned to the second data group with the least interlayer interference. The target data state corresponding to the intermediate threshold voltage of each intermediate data state in the correspondence is divided into at least one third data group with a medium level of interlayer interference. The first data group, the second data group, and the third data group constitute the plurality of data groups.

4. The programming method according to claim 2, characterized in that, When the threshold voltage of the second storage cell programmed to the first intermediate data state is the first threshold voltage and the threshold voltage of the second storage cell programmed to the first target data state corresponding to the first intermediate data state is the second threshold voltage, the greater the difference between the second threshold voltage and the first threshold voltage, the greater the degree of interlayer interference.

5. The programming method according to claim 3, characterized in that, The plurality of target data states include 16 target data states from L0 to L15; the one or more intermediate data states include: a first intermediate data state, a second intermediate data state, a third intermediate data state, and a fourth intermediate data state; the correspondence includes: the first intermediate data state corresponds to four target data states from L0 to L3, the second intermediate data state corresponds to four target data states from L4 to L7, the third intermediate data state corresponds to four target data states from L8 to L11, and the fourth intermediate data state corresponds to four target data states from L12 to L15; Correspondingly, the first data group includes: target data state L3, target data state L7, target data state L11, and target data state L15; The second data group includes: target data state L0, target data state L4, target data state L8, and target data state L12; The at least one third data group includes: a third data group consisting of target data state L1, target data state L5, target data state L9, and target data state L13, and a third data group consisting of target data state L2, target data state L6, target data state L10, and target data state L14.

6. The programming method according to claim 3, characterized in that, The greater the interlayer interference level of the data group among the plurality of data groups, the greater the reference verification induced current corresponding to the data group; correspondingly, determining the reference verification induced current for verifying the successful programming of the first memory cell contained in the first memory cell layer for each data group among the plurality of data groups includes: The reference verification induced current corresponding to the first data group is determined to be a first current value; The reference verification induced current corresponding to the second data group is determined to be the second current value; The reference verification induced current corresponding to each of the at least one third data group is determined as a third current value; Wherein, the first current value is greater than the third current value; and the third current value is greater than the second current value.

7. The programming method according to claim 1, characterized in that, The first programming operation and the second programming operation include multiple programming passes; the multiple programming passes are two programming passes including coarse programming and fine programming. Correspondingly, the preset programming order is as follows: coarse programming is performed on the first memory cell contained in the first memory cell layer; The second memory cells contained in the second memory cell layer are coarsely programmed. Perform fine programming on the first storage unit; Coarse programming is performed on the third memory cell contained in the third memory cell layer of the plurality of memory cell layers to be programmed; The second memory cell is finely programmed, wherein the second memory cell layer is located between the third memory cell layer and the first memory cell layer.

8. A three-dimensional memory, characterized in that, include: A storage array, comprising multiple layers of memory cells; Each memory cell layer contains multiple memory cells; and peripheral circuitry coupled to and configured to control the memory array, wherein; The peripheral circuit is configured as follows: The programming operations are performed on multiple memory cell layers to be programmed in the three-dimensional memory according to a preset programming order; wherein, When performing a first programming operation on a first memory cell contained in a first memory cell layer of the plurality of memory cell layers to be programmed, the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount. The set amount is used to compensate for the offset of the target distribution of the second memory cell contained in the second memory cell layer in the plurality of memory cell layers due to inter-layer interference caused by the second programming operation of the second memory cell in the second memory cell layer. The peripheral circuit is further configured to: identify multiple target data states corresponding to the second memory cells contained in the second memory cell layer; divide the multiple target data states into multiple data groups whose interlayer interference with the first memory cells contained in the first memory cell layer increases sequentially according to the second programming operation of the second memory cells contained in the second memory cell layer; determine a reference verification sensing current corresponding to each data group in the multiple data groups for verifying the successful programming of the first memory cell contained in the first memory cell layer; and verify the programmed first memory cell based on the reference verification sensing current corresponding to the data group when performing the first programming operation on the first memory cell, so that the distribution of the threshold voltage of the first memory cell is offset from the target distribution by a set amount.

9. The three-dimensional memory according to claim 8, characterized in that, When the second programming operation involves multiple programming passes; the plurality of target data states are the final data states of the second storage unit after fine programming in the multiple programming passes; the peripheral circuit is further configured to: determine one or more intermediate data states included in the last coarse programming pass in the multiple programming passes; the number of intermediate data states is not greater than the number of the plurality of target data states; Determine the correspondence between the one or more intermediate data states and the plurality of target data states; Based on the correspondence, the plurality of target data states are divided into a plurality of data groups in which the degree of interlayer interference to the first memory cells contained in the first memory cell layer increases sequentially, wherein the number of the plurality of data groups is equal to the number of the intermediate data states.

10. The three-dimensional memory according to claim 9, characterized in that, The peripheral circuit is further configured to: divide the target data state corresponding to the largest threshold voltage of each intermediate data state in the correspondence into the first data group with the greatest interlayer interference. The target data state corresponding to the lowest threshold voltage of each intermediate data state in the correspondence is assigned to the second data group with the least interlayer interference. The target data state corresponding to the intermediate threshold voltage of each intermediate data state in the correspondence is divided into at least one third data group with a medium level of interlayer interference. The first data group, the second data group, and the third data group constitute the plurality of data groups.

11. The three-dimensional memory according to claim 10, characterized in that, The multiple target data states include 16 target data states from L0 to L15; the one or more intermediate data states include: a first intermediate data state, a second intermediate data state, a third intermediate data state, and a fourth intermediate data state; the correspondence includes: the first intermediate data state corresponds to four target data states from L0 to L3, the second intermediate data state corresponds to four target data states from L4 to L7, the third intermediate data state corresponds to four target data states from L8 to L11, and the fourth intermediate data state corresponds to four target data states from L12 to L15; Correspondingly, the first data group includes: target data state L3, target data state L7, target data state L11, and target data state L15; The second data group includes: target data state L0, target data state L4, target data state L8, and target data state L12; The at least one third data group includes: a third data group consisting of target data state L1, target data state L5, target data state L9, and target data state L13, and a third data group consisting of target data state L2, target data state L6, target data state L10, and target data state L14.

12. The three-dimensional memory according to claim 10, characterized in that, The greater the interlayer interference level of the data group in the plurality of data groups, the greater the reference verification sensing current corresponding to the data group. The peripheral circuit is also configured to: determine the reference verification sensing current corresponding to the first data group as a first current value. The reference verification induced current corresponding to the second data group is determined to be the second current value; The reference verification induced current corresponding to each of the at least one third data group is determined as a third current value; Wherein, the first current value is greater than the third current value; and the third current value is greater than the second current value.

13. A memory system, characterized in that, include: One or more three-dimensional memories according to any one of claims 8 to 12.

14. The memory system according to claim 13, characterized in that, The memory system is a solid-state drive (SSD) or a memory card.

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