Parallel system synchronization method, processing terminal, UPS, parallel system

Abstract

The present invention provides a parallel system synchronization method, a processing terminal, a UPS, and a parallel system, the aforementioned method comprising: obtaining a first Ecap count value at the moment when the bypass phase of the local machine crosses zero and a second Ecap count value after a first preset time at the aforementioned zero-crossing moment, obtaining a first CAN count value after a first preset time at the aforementioned zero-crossing moment; determining a second CAN count value of the local machine at the aforementioned zero-crossing moment based on the first Ecap count value, the second Ecap count value, and the first CAN count value, uploading the second CAN count value and the local cycle to the CAN bus; obtaining a third CAN count value when data is successfully uploaded to the CAN bus, uploading the third CAN count value to the CAN bus; the second CAN count value, the local cycle, and the third CAN count value are all used for the slave machine to achieve carrier synchronization with the local machine. The present invention achieves parallel synchronization in a simpler way.

Description

Technical Field

[0001] The present invention belongs to the technical field of parallel synchronization, and more specifically, relates to a parallel system synchronization method, a processing terminal, a UPS, and a parallel system. Background Art

[0002] With the diversification of demand scenarios, multi-machine parallel technology has gradually become an application trend. In order to ensure the stable operation of the parallel system, it is necessary to achieve carrier synchronization of multiple machines when multiple machines are connected in parallel. The parallel synchronization in the existing technology mainly includes the following two solutions: the first is the analog signal processing method, and the second is the CAN interrupt timing method. However, the analog signal processing method has complex hardware circuits and quite cumbersome processing logic. In order to improve the phase-locking accuracy between multiple machines, the CAN interrupt timing method needs to increase the interrupt priority and implement interrupt nesting in the program, which is not simple enough.

[0003] Therefore, how to provide a simpler way to achieve parallel synchronization has become a problem that technical personnel in this field need to solve urgently. Summary of the invention

[0004] The object of the present invention is to provide a parallel system synchronization method, a processing terminal, a UPS, and a parallel system to solve the technical problem that the parallel synchronization scheme in the prior art is not simple enough.

[0005] According to a first aspect of an embodiment of the present invention, a method for synchronizing a parallel system is provided, wherein the parallel system comprises a host machine and at least one slave machine, and each machine in the parallel system is connected via a CAN bus communication. The method for synchronizing the parallel system is applied to any machine in the parallel system, and the method for synchronizing the parallel system comprises:

[0006] Real-time detection of the current master-slave status of the machine;

[0007] If the master-slave status shows that the local machine is the master, the master synchronization step is executed;

[0008] The host synchronization step comprises:

[0009] Obtaining a first Ecap count value corresponding to the zero-crossing moment of the local bypass phase from the local Ecap register, obtaining a second Ecap count value after a first preset time from the local Ecap register, and obtaining a first CAN count value after a first preset time from the local CAN register;

[0010] Determine a second CAN count value corresponding to the local CAN register at the zero-crossing moment based on the first Ecap count value, the second Ecap count value, and the first CAN count value, and upload the second CAN count value and the local cycle to the CAN bus;

[0011] A third CAN count value is obtained from the local CAN register when the second CAN count value and the local cycle are successfully uploaded to the CAN bus, and the third CAN count value is uploaded to the CAN bus; wherein the second CAN count value, the local cycle, and the third CAN count value are all used for the slave to achieve carrier synchronization with the local machine.

[0012] In a possible implementation, the parallel system synchronization method further includes:

[0013] If the master-slave status shows that the local machine is a slave machine, then the slave machine synchronization step is executed;

[0014] The slave synchronization step comprises:

[0015] Receive a second CAN count value and a host cycle uploaded by the host from the CAN bus, and obtain a fourth CAN count value when the second CAN count value and the host cycle are successfully received from the local CAN register;

[0016] Record the time when the second CAN count value and the host cycle are successfully received as the successful reception time, obtain the third Ecap count value after the second preset time of the successful reception time from the local Ecap register, and obtain the fifth CAN count value after the second preset time of the successful reception time from the local CAN register;

[0017] Receive the third CAN count value uploaded by the host from the CAN bus, and determine the fourth Ecap count value corresponding to the local Ecap register at the host bypass phase zero crossing moment according to the fourth CAN count value, the third Ecap count value, the fifth CAN count value, the second CAN count value, and the third CAN count value;

[0018] Carrier synchronization with the host is achieved based on the fourth Ecap count value and the host period.

[0019] In a possible implementation, in the host synchronization step, determining the second CAN count value corresponding to the local CAN register at the zero-crossing moment based on the first Ecap count value, the second Ecap count value, and the first CAN count value includes:

[0020] Ecan_cnt1_M=Ecan_cnt2_M-(Ecap_cnt2_M-Ecap_cnt1_M) / K

[0021] Among them, Ecan_cnt1_M is the second CAN count value corresponding to the local CAN register at the zero-crossing moment, Ecap_cnt1_M is the first Ecap count value, Ecap_cnt2_M is the second Ecap count value, Ecan_cnt2_M is the first CAN count value, and K is the time base ratio between the local CAN register and the local Ecap register.

[0022] In a possible implementation, in the slave synchronization step, determining the fourth Ecap count value corresponding to the local Ecap register at the host bypass phase zero crossing moment according to the fourth CAN count value, the third Ecap count value, the fifth CAN count value, the second CAN count value, and the third CAN count value includes:

[0023] Ecap_cnt1_S=Ecap_cnt4_S-[(Ecan_cnt4_S-Ecan_cnt3_S)+(Ecan_cnt3_M-Ecan_cnt1_M)]*K

[0024] Among them, Ecap_cnt1_S is the fourth Ecap count value of the local Ecap register corresponding to the moment when the host bypass phase passes through zero, Ecan_cnt3_S is the fourth CAN count value, Ecap_cnt4_S is the third Ecap count value, Ecan_cnt4_S is the fifth CAN count value, Ecan_cnt1_M is the second CAN count value, Ecan_cnt3_M is the third CAN count value, and K is the time base ratio of the local CAN register and the local Ecap register.

[0025] In a possible implementation, in the slave synchronization step, implementing carrier synchronization with the host based on the fourth Ecap count value and the host cycle includes:

[0026] Obtaining the zero-crossing time of the host bypass phase by reverse calculation according to the fourth Ecap count value;

[0027] The zero-crossing moment of the host bypass phase obtained by reverse calculation is used as the common square wave edge of the local machine, and the host cycle is used as the local machine cycle to achieve carrier synchronization with the host.

[0028] In a possible implementation, the first preset time and the second preset time are both less than 1 / 2 of a host cycle.

[0029] According to a second aspect of an embodiment of the present invention, a processing terminal is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned parallel system synchronization method when executing the computer program.

[0030] According to a third aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned parallel system synchronization method are implemented.

[0031] According to a fourth aspect of the embodiments of the present invention, a UPS is provided, wherein the UPS includes the processing terminal described above.

[0032] According to a fifth aspect of the embodiments of the present invention, a parallel system is provided, wherein the parallel system includes at least one UPS as described above.

[0033] The beneficial effects of the parallel system synchronization method, processing terminal, UPS, and parallel system provided by the embodiments of the present invention are:

[0034] Different from the analog signal processing method and CAN interruption timing method in the prior art, the parallel synchronization of the present invention is realized based on the time recording function of the Ecap register and the CAN register.

[0035] Based on this principle, when the present invention determines that the local machine is the host, the count value of the local CAN register at the time when the local bypass phase passes through zero is first obtained by reverse deduction through the moment recording function of the Ecap register and the CAN register, that is, the second CAN count value, and the second CAN count value and the local cycle are uploaded to the CAN bus for the slave to obtain. Afterwards, the local machine records the count value of the local CAN register when the second CAN count value and the local cycle are successfully uploaded, that is, the third CAN count value, and the third CAN count value is also uploaded to the CAN bus for the slave to obtain. So far, the slave can obtain three quantities through the CAN bus, namely the second CAN count value, the third CAN count value, and the host cycle, wherein the second CAN count value is essentially a characterization quantity of the host bypass zero-crossing moment, and the third CAN count value is essentially a characterization quantity of the data upload moment corresponding to the second CAN count value and the host cycle, so the difference between the third CAN count value and the second CAN count value is essentially a characterization quantity of the time difference of the data upload moment relative to the aforementioned zero-crossing moment. The time difference is essentially the time difference between the slave data acquisition time (i.e., the aforementioned host data upload time) and the host bypass phase zero crossing time, and it is obvious that after knowing the time difference, the slave can achieve carrier synchronization with the host. In other words, without the help of CAN interruption and analog signal processing, the present invention realizes parallel synchronization based on simple data calculation, that is, the present invention provides a simpler parallel synchronization method. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A schematic diagram of a flow chart of a parallel system synchronization method provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a three-stage phase locking process according to an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of waveforms during synchronization of a master and a slave provided by an embodiment of the present invention;

[0040] Figure 4 A schematic flow chart of a parallel system synchronization method provided by another embodiment of the present invention;

[0041] Figure 5 A schematic diagram of time synchronization during master-slave synchronization provided by an embodiment of the present invention;

[0042] Figure 6 A schematic block diagram of a processing terminal provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0044] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0045] First of all, it should be pointed out that the parallel system synchronization method provided by the present invention is applied to the parallel system, which is implemented in a master-slave mode, that is, there is a master and at least one slave, wherein the master-slave status of each machine in the parallel system can be switched according to the current status information of each machine, that is, the master in the parallel system is not necessarily fixed. The subsequent parallel system synchronization method provided by the present invention can be applied to any machine in the parallel system. On this basis, please refer to Figure 1, Figure 1 A schematic flow chart of a method for synchronizing a parallel system provided in an embodiment of the present invention, the method comprising:

[0046] S101: Real-time detection of the current master-slave status of the machine.

[0047] S102: If the master-slave status shows that the local machine is the master, the master synchronization step is executed.

[0048] In this embodiment, the current master-slave status of the machine can be detected first, and the steps to be performed can be determined according to the current master-slave status of the machine. If the master-slave status shows that the machine is the master, the master synchronization step is performed. The master synchronization step includes:

[0049] The first Ecap count value corresponding to the zero-crossing moment of the local bypass phase is obtained from the local Ecap register, the second Ecap count value after the first preset time at the zero-crossing moment is obtained from the local Ecap register, and the first CAN count value after the first preset time at the zero-crossing moment is obtained from the local CAN register. Based on the first Ecap count value, the second Ecap count value, and the first CAN count value, the second CAN count value corresponding to the local CAN register at the zero-crossing moment is determined, and the second CAN count value and the local cycle are uploaded to the CAN bus. The third CAN count value when the second CAN count value and the local cycle are successfully uploaded to the CAN bus is obtained from the local CAN register, and the third CAN count value is uploaded to the CAN bus. Among them, the second CAN count value, the local cycle, and the third CAN count value are all used for the slave to achieve carrier synchronization with the local machine.

[0050] Among them, it should be pointed out that the "obtaining the first Ecap count value corresponding to the zero-crossing moment of the local bypass phase from the local Ecap register" described in the embodiment of the present invention has implicitly disclosed the scheme of "before this, the local Ecap module needs to be controlled to capture the bypass square wave and record the relevant moment", and the "obtaining the first CAN count value after the first preset time after the zero-crossing moment from the local CAN register" described in the embodiment of the present invention has implicitly disclosed the scheme of "before this, the local CAN register needs to be controlled to record the relevant moment". Regarding this point, the subsequent embodiments are similar and will not be repeated here.

[0051] In this embodiment, the second CAN count value can be understood as a characterization of the local phase (zero-crossing moment), that is, the local machine as the host determines its own inverter phase based on its own phase-locked result, and subsequently the local machine will upload the phase (that is, the second CAN count value) and period (or frequency) near the phase zero crossing to the CAN bus for transmission to the slave machine. After the data is successfully uploaded, the local machine will also record the phase / moment when the data is successfully uploaded (corresponding to the third CAN count value), and upload the phase / moment when the data is successfully uploaded to the CAN bus, so as to facilitate the slave machine to reversely infer the zero-crossing moment of the local machine based on the data sent by the local machine, thereby achieving carrier synchronization with the local machine (that is, achieving the slave machine's common square wave following the local machine's common square wave).

[0052] In this embodiment, reference may be made to Figure 2 and Figure 3 ( Figure 3 Ecap_TSCTR in the embodiment represents the count value of the host Ecap register). Based on the overall solution of the embodiment of the present invention, it can be seen that the system phase-locking function corresponding to the embodiment of the present invention can be specifically divided into three levels:

[0053] First-level phase lock: The host captures the frequency and phase information of the bypass.

[0054] Second stage phase lock: host common square wave follows bypass or self-oscillation.

[0055] The third level phase lock: the host sends a common square wave synchronization information through the CAN bus.

[0056] The parallel system synchronization solution provided in the embodiment of the present invention is mainly used in the third-level phase-locking process. The embodiment of the present invention can achieve the alignment of the host and slave moments in the three-level phase-locking process based on the time recording function of the Ecap register and the CAN register, thereby achieving carrier synchronization between the master and slave.

[0057] It can be concluded from the above that, different from the analog signal processing method and the CAN interrupt timing method in the prior art, the parallel synchronization of the embodiment of the present invention is realized based on the moment recording function of the Ecap register and the CAN register. Based on this principle, when the embodiment of the present invention determines that the local machine is the host, the count value of the local CAN register at the moment of zero crossing of the local bypass phase is first obtained by reverse deduction through the moment recording function of the Ecap register and the CAN register, that is, the second CAN count value, and the second CAN count value and the local cycle are uploaded to the CAN bus for the slave to obtain. Afterwards, the local machine records the count value of the local CAN register when the second CAN count value and the local cycle are successfully uploaded, that is, the third CAN count value, and the third CAN count value is also uploaded to the CAN bus for the slave to obtain. So far, the slave can obtain three quantities through the CAN bus, namely the second CAN count value, the third CAN count value, and the host cycle, wherein the second CAN count value is essentially the characterization quantity of the host bypass zero crossing moment, and the third CAN count value is essentially the characterization quantity of the data upload moment corresponding to the second CAN count value and the host cycle, so the difference between the third CAN count value and the second CAN count value is essentially the characterization quantity of the time difference of the data upload moment relative to the aforementioned zero crossing moment. The time difference is essentially the time difference between the slave data acquisition time (i.e., the aforementioned host data upload time) and the host bypass phase zero crossing time, and it is obvious that after knowing the time difference, the slave can achieve carrier synchronization with the host. In other words, without the help of CAN interruption and analog signal processing, the embodiment of the present invention realizes parallel synchronization based on simple data calculation, that is, the embodiment of the present invention provides a simpler parallel synchronization method.

[0058] In one possible implementation, see Figure 4 The parallel system synchronization method also includes:

[0059] S103: If the master-slave status shows that the local machine is a slave machine, the slave machine synchronization step is executed.

[0060] The slave synchronization steps include:

[0061] Receive the second CAN count value and host cycle uploaded by the host from the CAN bus, and obtain the fourth CAN count value when the second CAN count value and the host cycle are successfully received from the local CAN register. The moment when the second CAN count value and the host cycle are successfully received is recorded as the successful reception moment, and the third Ecap count value after the second preset time of the successful reception moment is obtained from the local Ecap register, and the fifth CAN count value after the second preset time of the successful reception moment is obtained from the local CAN register. Receive the third CAN count value uploaded by the host from the CAN bus, and determine the fourth Ecap count value corresponding to the local Ecap register at the time when the host bypass phase passes zero based on the fourth CAN count value, the third Ecap count value, the fifth CAN count value, the second CAN count value, and the third CAN count value. Carrier synchronization with the host is achieved based on the fourth Ecap count value and the host cycle.

[0062] In this embodiment, a slave synchronization step is provided on the basis of the host synchronization step, that is, when the second CAN count value (essentially the zero-crossing phase of the host) and the host cycle sent by the host are received from the CAN bus, the time of receiving this data is recorded to obtain a fourth CAN count value, and then the third CAN count value uploaded by the host is continuously received from the CAN bus. On the basis of the received data, combined with the corresponding relationship between the counts of the Ecap register and the CAN register, the zero-crossing time of the host bypass phase can be inferred, and then combined with the zero-crossing time of the host bypass phase and the host cycle, synchronization with the host can be achieved.

[0063] In this embodiment, the fourth Ecap count value is a characterization of the host bypass phase zero-crossing moment. In a possible implementation, carrier synchronization with the host is achieved based on the fourth Ecap count value and the host cycle, which can be described in detail as follows: the zero-crossing moment of the host bypass phase is obtained by reverse calculation according to the fourth Ecap count value. The zero-crossing moment of the host bypass phase obtained by reverse calculation is used as the common square wave edge of the local machine, and the host cycle is used as the local cycle to achieve carrier synchronization with the host.

[0064] From the above description, it can be seen that the slave synchronization step provided in the embodiment of the present invention cleverly utilizes the postmark function of the CAN module (that is, the register timing function of successful CAN mailbox sending and receiving). When the CAN data is sent successfully, the sending node (host) will record the CANTSC count value and save it in the CANMOTS register, and the receiving node (slave) will also save the corresponding CANTSC count value in its own CANMOTS register. Based on this point, the host can upload the phase difference (that is, the difference between the third CAN count value and the second CAN count value) to the CAN bus so that the slave can compensate for the corresponding phase difference, thereby realizing master-slave synchronization.

[0065] In a possible implementation, in the host synchronization step, determining the second CAN count value corresponding to the local CAN register at the zero-crossing moment based on the first Ecap count value, the second Ecap count value, and the first CAN count value includes:

[0066] Ecan_cnt1_M=Ecan_cnt2_M-(Ecap_cnt2_M-Ecap_cnt1_M) / K

[0067] Among them, Ecan_cnt1_M is the second CAN count value corresponding to the local CAN register at the zero-crossing moment, Ecap_cnt1_M is the first Ecap count value, Ecap_cnt2_M is the second Ecap count value, Ecan_cnt2_M is the first CAN count value, and K is the time base ratio between the local CAN register and the local Ecap register.

[0068] In this embodiment, a method for calculating the second CAN count value is provided, that is, a method for inferring the host bypass phase zero-crossing time through the counting characteristics of the Ecap register and the CAN register. In the calculation of this embodiment, the time base difference of the counters corresponding to different registers is taken into account, so that data conversion is performed based on the time base ratio of different counters, thereby ensuring the accuracy of the time inversion.

[0069] In a possible implementation, in the slave synchronization step, determining the fourth Ecap count value corresponding to the local Ecap register at the local bypass phase zero crossing moment according to the fourth CAN count value, the third Ecap count value, the fifth CAN count value, the second CAN count value, and the third CAN count value includes:

[0070] Ecap_cnt1_S=Ecap_cnt4_S-[(Ecan_cnt4_S-Ecan_cnt3_S)+(Ecan_cnt3_M-Ecan_cnt1_M)]*K

[0071] Among them, Ecap_cnt1_S is the fourth Ecap count value of the local Ecap register corresponding to the moment when the local bypass phase crosses zero, Ecan_cnt3_S is the fourth CAN count value, Ecap_cnt4_S is the third Ecap count value, Ecan_cnt4_S is the fifth CAN count value, Ecan_cnt1_M is the second CAN count value, Ecan_cnt3_M is the third CAN count value, and K is the time base ratio of the local CAN register and the local Ecap register.

[0072] In this embodiment, a method for calculating the fourth Ecap count value of the local Ecap register corresponding to the local bypass phase zero-crossing moment is provided, that is, a method for inferring the host bypass phase zero-crossing moment in the slave counting scenario through the counting characteristics of the Ecap register and the CAN register is provided. In the calculation of this embodiment, the time base difference problem of the counters corresponding to different registers is taken into account, so that data conversion is performed based on the time base ratio of different counters, thereby ensuring the accuracy of the time inversion.

[0073] In a specific implementation of the parallel system synchronization method provided in an embodiment of the present invention, please refer to Figure 5 The parallel system synchronization method of the embodiment of the present invention can be specifically implemented as follows:

[0074] 1) At time t1, the host Ecap module will capture the bypass square wave. At this time, the Ecap_TSCTR register in the host Ecap module will record Ecap_cnt1_M. At this time, Ecan_cnt1_M is the common square wave zero-crossing point calculated by the subsequent host (Ecan_cnt1_M is only inferred, and the CAN module does not perform any operation at this time).

[0075] 2) At time t2, after the host public square wave has passed zero, the host Ecap_TSCTR register and the Ecan_CANTSC register in the host CAN module will record Ecap_cnt2_M and Ecan_cnt2_M at this time respectively. On this basis, the value of Ecan_cnt1_M at time t1 can be calculated through the following mathematical relationship:

[0076] Ecan_cnt1_M=Ecan_cnt2_M-(Ecap_cnt2_M-Ecap_cnt1_M) / K

[0077] After that, Ecan_cnt1_M can be sent to the slave through the CAN bus as the phase of the master together with the master cycle.

[0078] 3) At time t3, after the host successfully sends the message, the value of Ecan_cnt3_M is automatically recorded by the postmark of the host CAN module. The slave also receives the phase and period of the host's public square wave, and the slave CAN module also automatically records Ecan_cnt3_S.

[0079] 4) At time t4, the host sends Ecan_cnt3_M recorded by the CAN module to the slave.

[0080] 5) At t5, the slave receives Ecan_cnt3_M sent by the host, and calculates the edge of the host bypass common square wave (that is, the zero-crossing moment of the host bypass phase) through the following mathematical relationship:

[0081] Ecap_cnt1_S=Ecap_cnt4_S-[(Ecan_cnt4_S-Ecan_cnt3_S)+(Ecan_cnt3_M-Ecan_cnt1_M)]*K

[0082] After that, the slave uses the host's zero-crossing moment as its own public square wave edge, and calculates the public square wave edge of the next cycle of the local machine (for example, Ecap_cnt5_S, which corresponds to the host's Ecap_cnt3_M at this time), and continues to operate with the cycle received from the host. When the host public square wave synchronization is not received, the slave will keep the cycle sent by the host in the previous cycle and continue to calculate the square wave edge of each cycle until it confirms that it is the host resynchronization or re-receives the synchronization information of the host.

[0083] In this embodiment, K is determined by actual register parameters, for example, K may be 150.

[0084] In summary, the master-slave common square wave synchronization timing provided by the embodiment of the present invention can be shown in the following Table 1:

[0085] Table 1 Master-slave common square wave synchronization timing table

[0086]

[0087] In summary, the embodiment of the present invention can achieve synchronization between the master and slave machines by only using simple data calculations without resorting to CAN interrupts and analog signal processing. Therefore, the embodiment of the present invention provides a simpler parallel system synchronization solution, solving the problems of the prior art.

[0088] In a possible implementation, the first preset time and the second preset time are both less than 1 / 2 of the host cycle.

[0089] In this embodiment, the first preset time and the second preset time can be set based on actual needs, and both can be greater than 1 / 2 of the host cycle, or even exceed the host cycle. The above examples can achieve the implementation purpose of the present invention. In the embodiment of the present invention, setting the first preset time and the second preset time to be less than 1 / 2 of the host cycle can effectively ensure the real-time synchronization, avoid the error accumulation caused by slow synchronization, and more effectively ensure the stable operation of the parallel system.

[0090] It should also be pointed out that when processing the count value of the aforementioned register, it is necessary to consider the overflow processing of the register and the overflow processing of the corresponding cycle. The specific processing method belongs to the existing means and does not affect the implementation of the concept of the present invention, so it will not be repeated here.

[0091] Based on the above embodiments, it can be seen that the synchronization timing scheme based on the CAN mail register of the present invention cleverly utilizes the register timing function of the successful sending and receiving of the CAN mailbox, thereby solving the problem of CAN interrupt nesting due to the need for timing. This scheme can be applied to phase synchronization and PWM synchronization of multiple machines in parallel. This scheme can also be used for parallel synchronization based on single-phase and three-phase inverters, and can also be extended to scenarios of timing of different time base nodes. In other words, the parallel system synchronization scheme provided by the embodiment of the present invention has a wide range of applications.

[0092] A second aspect of an embodiment of the present invention provides a processing terminal, see Figure 6 , Figure 6 FIG. 1 is a schematic block diagram of a processing terminal provided by an embodiment of the present invention. Figure 6 The terminal 600 in the embodiment shown may include: one or more processors 601, one or more input devices 602, one or more output devices 603 and one or more memories 604. The processors 601, input devices 602, output devices 603 and memories 604 communicate with each other via a communication bus 605. The memory 604 is used to store computer programs, which include program instructions. The processor 601 is used to execute the program instructions stored in the memory 604. The processor 601 is configured to execute each step of the aforementioned parallel system synchronization method, such as steps S101-S103.

[0093] It should be understood that in the embodiment of the present invention, the processor 601 may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0094] The input device 602 may include a touch panel, a fingerprint sensor (for collecting the user's fingerprint information and fingerprint direction information), a microphone, etc., and the output device 603 may include a display (LCD, etc.), a speaker, etc.

[0095] The memory 604 may include a read-only memory and a random access memory, and provide instructions and data to the processor 601. A portion of the memory 604 may also include a non-volatile random access memory. For example, the memory 604 may also store information about the device type.

[0096] In a specific implementation, the processor 601, input device 602, and output device 603 described in the embodiment of the present invention can execute the implementation methods described in the first and second embodiments of the parallel system synchronization method provided in the embodiment of the present invention, and can also execute the implementation methods of the terminal described in the embodiment of the present invention, which will not be repeated here.

[0097] In a third aspect of the embodiments of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, wherein the program instructions are executed by a processor to implement all or part of the processes in the above-mentioned embodiment method, and may also be completed by instructing related hardware through a computer program, wherein the computer program may be stored in a computer-readable storage medium, and wherein the computer program may be executed by a processor to implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code may be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the contents contained in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electric carrier signal and telecommunication signal.

[0098] The computer-readable storage medium may be an internal storage unit of the terminal of any of the foregoing embodiments, such as a hard disk or memory of the terminal. The computer-readable storage medium may also be an external storage device of the terminal, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the terminal. Further, the computer-readable storage medium may also include both an internal storage unit of the terminal and an external storage device. The computer-readable storage medium is used to store computer programs and other programs and data required by the terminal. The computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

[0099] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0100] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the terminals and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0101] In the several embodiments provided in the present application, it should be understood that the disclosed terminal and method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces or units, or it can be an electrical, mechanical or other form of connection.

[0102] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0103] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0104] According to a fourth aspect of the embodiments of the present invention, a UPS is provided, which includes the processing terminal described above.

[0105] According to a fifth aspect of the embodiments of the present invention, a parallel system is provided. The parallel system includes at least one UPS as described above. Each UPS can be connected to each other via a CAN bus communication.

[0106] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for synchronizing a parallel system, characterized in that: The parallel system comprises a host and at least one slave, and the machines in the parallel system are connected via a CAN bus communication. The parallel system synchronization method is applied to any machine in the parallel system, and the method comprises: Real-time detection of the current master-slave status of the machine; If the master-slave status shows that the local machine is the master, the master synchronization step is executed; The host synchronization step comprises: Obtaining a first Ecap count value corresponding to the zero-crossing moment of the local bypass phase from the local Ecap register, obtaining a second Ecap count value after a first preset time from the local Ecap register, and obtaining a first CAN count value after a first preset time from the local CAN register; Determine a second CAN count value corresponding to the local CAN register at the zero-crossing moment based on the first Ecap count value, the second Ecap count value, and the first CAN count value, and upload the second CAN count value and the local cycle to the CAN bus; Acquire a third CAN count value when the second CAN count value and the local cycle are successfully uploaded to the CAN bus from the local CAN register, and upload the third CAN count value to the CAN bus; wherein the second CAN count value, the local cycle, and the third CAN count value are all used for the slave to achieve carrier synchronization with the local; Wherein, determining the second CAN count value corresponding to the local CAN register at the zero-crossing moment based on the first Ecap count value, the second Ecap count value, and the first CAN count value includes: Ecan_cnt1_M=Ecan_cnt2_M-(Ecap_cnt2_M-Ecap_cnt1_M) / K Among them, Ecan_cnt1_M is the second CAN count value corresponding to the local CAN register at the zero-crossing moment, Ecap_cnt1_M is the first Ecap count value, Ecap_cnt2_M is the second Ecap count value, Ecan_cnt2_M is the first CAN count value, and K is the time base ratio between the local CAN register and the local Ecap register.

2. The method for synchronizing a parallel system according to claim 1, characterized in that: The parallel system synchronization method further includes: If the master-slave status shows that the local machine is a slave machine, then the slave machine synchronization step is executed; The slave synchronization step comprises: Receive a second CAN count value and a host cycle uploaded by the host from the CAN bus, and obtain a fourth CAN count value when the second CAN count value and the host cycle are successfully received from the local CAN register; Record the time when the second CAN count value and the host cycle are successfully received as the successful reception time, obtain the third Ecap count value after the second preset time of the successful reception time from the local Ecap register, and obtain the fifth CAN count value after the second preset time of the successful reception time from the local CAN register; Receive a third CAN count value uploaded by the host from the CAN bus, and determine a fourth Ecap count value corresponding to the local Ecap register at the host bypass phase zero crossing moment according to the fourth CAN count value, the third Ecap count value, the fifth CAN count value, the second CAN count value, and the third CAN count value; Carrier synchronization with the host is achieved based on the fourth Ecap count value and the host period.

3. The method for synchronizing a parallel system according to claim 2, characterized in that: In the slave synchronization step, determining the fourth Ecap count value corresponding to the local Ecap register at the host bypass phase zero crossing moment according to the fourth CAN count value, the third Ecap count value, the fifth CAN count value, the second CAN count value, and the third CAN count value includes: Ecap_cnt1_S=Ecap_cnt4_S-[(Ecan_cnt4_S-Ecan_cnt3_S)+(Ecan_cnt3_M-Ecan_cnt1_M)]*K Among them, Ecap_cnt1_S is the fourth Ecap count value corresponding to the local Ecap register at the moment when the host bypass phase passes zero, Ecan_cnt3_S is the fourth CAN count value, Ecap_cnt4_S is the third Ecap count value, Ecan_cnt4_S is the fifth CAN count value, Ecan_cnt1_M is the second CAN count value, and Ecan_cnt3_M is the third CAN count value.

4. The method for synchronizing a parallel system according to claim 2, characterized in that: In the slave synchronization step, the carrier synchronization with the host is achieved based on the fourth Ecap count value and the host cycle, including: Obtaining the zero-crossing time of the host bypass phase by reverse calculation according to the fourth Ecap count value; The zero-crossing moment of the host bypass phase obtained by reverse calculation is used as the common square wave edge of the local machine, and the host cycle is used as the local machine cycle to achieve carrier synchronization with the host.

5. The method for synchronizing a parallel system according to any one of claims 2 to 4, characterized in that: The first preset time and the second preset time are both less than 1 / 2 of the host cycle.

6. A processing terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

7. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A UPS, characterized in that: Comprising the processing terminal as claimed in claim 6.

9. A parallel system, characterized in that: The invention comprises at least one UPS as claimed in claim 8.

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