A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof, which comprises a plurality of channel structures vertically penetrating a stack, at least two first gate line slits vertically penetrating the stack and extending in a transverse direction parallel to the substrate, and a plurality of top selection gate tangents between two adjacent first gate line slits and extending in the transverse direction. The plurality of top selection gate tangents between the two adjacent first gate line slits can separate the top selection gates of the plurality of channel structures into multiple parts, and the storage function of each channel structure can be realized by controlling the top selection gates of different parts. Therefore, the application can simultaneously increase the number of channel structures and the number of top selection gate tangents to improve the storage capacity.

Description

Technical Field

[0001] This invention relates generally to electronic devices, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Currently, in 3D memory, nine channels are typically arranged between two gate line slits (GLS) (a block structure). These nine channels correspond to a top select gate (TSG), hence the term "9-channel array." In a 9-channel array, the top select gate is divided into two parts by a top select gate cut (TSG cut), which is generally formed of an insulating oxide material. In a block structure, a bit line connects the two channel structures located on either side of the top select gate cut. By controlling the two parts of the top select gate, one of the channel structures can be selected, thus enabling the storage function of each channel structure.

[0003] Two grid lines can define a block structure. Increasing the number of block structures by adding multiple grid lines is a common method to increase storage capacity. However, how to further improve storage capacity is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which aims to increase the number of channel structures and top select gate tangents in a block structure, thereby improving memory capacity.

[0005] In one aspect, the present invention provides a semiconductor device, comprising:

[0006] Substrate;

[0007] A stack disposed on the substrate, the stack comprising alternately stacked interlayer insulating layers and gate layers;

[0008] Multiple channel structures penetrate the stack vertically;

[0009] At least two first gate line slots penetrate the stack perpendicularly and extend in a lateral direction parallel to the substrate;

[0010] Multiple top-selected grid tangents are located between the gaps of two adjacent first grid lines and extend in the lateral direction.

[0011] More preferably, it also includes one or more second gate line slots that run vertically through the stack and are located between two adjacent first gate line slots.

[0012] More preferably, the plurality of top-selected gate tangents divide the channel structure between two adjacent first gate line slots into a plurality of storage areas, and the second gate line slot is located between two adjacent storage areas.

[0013] More preferably, the plurality of second grid line slots are arranged in a row along the top selected grid tangent, and the distance from each second grid line slot to the two adjacent first grid line slots is equal.

[0014] More preferably, the plurality of second grid line slots are arranged in multiple columns along the top selected grid tangent, and adjacent columns of second grid line slots are staggered in the lateral direction.

[0015] More preferably, two storage areas are spaced between two adjacent columns of the second gate line slots, and two storage areas are spaced between each first gate line slot and an adjacent column of the second gate line slots.

[0016] More preferably, multiple second grid line slots in the same column of second grid line slots are spaced apart along the lateral direction.

[0017] More preferably, there is a gap between two adjacent storage areas, each of the top selected gate tangents is located in one of the gaps, and each of the second gate gaps is located in one of the gaps.

[0018] More preferably, the semiconductor device is divided into a plurality of block structures in a longitudinal direction parallel to the substrate, and the block structures are divided into a plurality of finger structures in the longitudinal direction, with at least one first gate line gap located between adjacent finger structures in the same block structure.

[0019] More preferably, the first gate line gap includes a first gate line cut that penetrates the stack vertically and extends in the lateral direction, and an insulating layer and a conductive layer that are sequentially filled in the first gate line cut.

[0020] More preferably, the second gate line gap includes a second gate line cut that extends vertically through the stack, and an insulating layer and a conductor layer that are sequentially filled in the second gate line cut.

[0021] More preferably, the second gate line slot includes a second gate line cut that extends vertically through the stack, and an insulating layer filling the second gate line cut.

[0022] On the other hand, the present invention provides a method for fabricating a semiconductor device, comprising:

[0023] Provide substrate;

[0024] A stack is formed on the substrate, the stack comprising alternately stacked interlayer insulating layers and interlayer sacrificial layers;

[0025] Multiple channel structures are formed, and the multiple channel structures penetrate the stack vertically;

[0026] At least two first gate line cuts are formed, the at least two first gate line cuts perpendicularly penetrating the stack and extending in a lateral direction parallel to the substrate;

[0027] The interlayer sacrificial layer is replaced with a gate layer;

[0028] Multiple top selection grid tangents are formed;

[0029] The plurality of top selection grid cut lines are located between two adjacent first grid line cuts and extend in the lateral direction.

[0030] More preferably, the step of forming at least two first gate line cuts further includes: forming one or more second gate line cuts, the second gate line cuts penetrating the stack perpendicularly and located between two adjacent first gate line cuts.

[0031] More preferably, the step of replacing the interlayer sacrificial layer with a gate layer includes: replacing the interlayer sacrificial layer with a gate layer through the first gate line cut and the second gate line cut.

[0032] More preferably, the plurality of top-selected gate cut lines divide the channel structure between two adjacent first gate line cuts into a plurality of storage areas, and the second gate line cuts are located between two adjacent storage areas.

[0033] More preferably, the plurality of second gate line cuts are arranged in a row along the top selected gate tangent, and the distance from each second gate line cut to the two adjacent first gate line cuts is equal.

[0034] More preferably, the step of forming multiple top select gate cut lines is performed after the step of replacing the interlayer sacrificial layer with the gate layer through the first gate cut and the second gate cut; wherein the top select gate cut line also cuts a portion of the second gate cut.

[0035] More preferably, the plurality of second grid line cuts are arranged in multiple columns along the top selected grid tangent, and adjacent columns of second grid line cuts are staggered in the lateral direction.

[0036] More preferably, two storage areas are spaced between two adjacent columns of the second gate line cuts, and two storage areas are spaced between each first gate line cut and an adjacent column of the second gate line cuts.

[0037] More preferably, multiple second grid line cuts in the same column of second grid line cuts are arranged at intervals along the lateral direction.

[0038] More preferably, the step of forming multiple top selection gate tangents is performed before the step of forming at least two first gate line cuts; wherein the second gate line cuts also penetrate the top selection gate tangents.

[0039] More preferably, the semiconductor device is divided into a plurality of block structures in a longitudinal direction parallel to the substrate, and the block structures are divided into a plurality of finger structures in the longitudinal direction, with at least one first gate line cutout located between adjacent finger structures in the same block structure.

[0040] Further preferably, after the step of replacing the interlayer sacrificial layer with the gate layer through the first gate line cut and the second gate line cut, the method further includes: sequentially filling the first gate line cut and the second gate line cut with an insulating layer and a conductive layer to form a first gate line gap and a second gate line gap.

[0041] Further preferably, after the step of replacing the interlayer sacrificial layer with the gate layer through the first gate line cut and the second gate line cut, the method further includes: sequentially filling the first gate line cut with an insulating layer and a conductive layer, and filling the second gate line cut with the insulating layer to form a first gate line gap and a second gate line gap.

[0042] The beneficial effects of this invention are: it provides a semiconductor device and its fabrication method, comprising multiple channel structures perpendicularly penetrating a stack, at least two first gate line slots perpendicularly penetrating the stack and extending in a lateral direction parallel to the substrate, and multiple top select gate tangents located between adjacent first gate line slots and extending in the lateral direction. The multiple top select gate tangents between adjacent first gate line slots can separate the top select gates of the multiple channel structures into multiple portions. By controlling the top select gates of different portions, the storage function of each channel structure can be realized. Therefore, this invention can simultaneously increase the number of channel structure columns and the number of top select gate tangents to improve storage capacity. Attached Figure Description

[0043] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0044] Figure 1 This is a top view of a semiconductor device provided by existing technology;

[0045] Figure 2This is a top view schematic diagram of the semiconductor device provided in the first embodiment of the present invention;

[0046] Figure 3 This is a top view schematic diagram of another semiconductor device provided by existing technology;

[0047] Figure 4 This is a top view of the semiconductor device provided in the second embodiment of the present invention;

[0048] Figure 5 This is a top view of the semiconductor device provided in the third embodiment of the present invention;

[0049] Figure 6 This is a top view of the semiconductor device provided in the fourth embodiment of the present invention;

[0050] Figure 7 This is a top view of a semiconductor device provided in a modified embodiment of the fourth embodiment of the present invention;

[0051] Figure 8 This is a schematic flowchart of the semiconductor device fabrication method provided in the fifth embodiment of the present invention;

[0052] Figures 9a-9b This is a top view of the semiconductor device during the fabrication process according to the fifth embodiment of the present invention;

[0053] Figure 10 This is a schematic flowchart of the method for fabricating a semiconductor device provided in the sixth embodiment of the present invention;

[0054] Figures 11a-11c This is a top view of the semiconductor device fabrication process provided in the sixth embodiment of the present invention. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0056] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0057] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0058] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0059] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends vertically relative to the substrate. As used herein, the term "vertical" means perpendicular to the substrate; the term "lateral" means a direction parallel to the substrate, denoted by "X," and the direction of the term "column" is parallel to the "X" direction; the term "longitudinal" means a direction parallel to the substrate, denoted by "Y," and the "Y" direction is perpendicular to the "X" direction.

[0060] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0061] Please see Figure 1 , Figure 1This is a top view schematic diagram of a semiconductor device provided by the prior art. The semiconductor device includes multiple gate line slits (GLS) 10 extending in the lateral (X) direction. Channel structures 21 between adjacent gate line slits 10 form a block structure 20. Each block structure 20 has a top select gate cut (TSG cut) 22 extending in the lateral (X) direction, which divides the block structure 20 into two memory regions 20a. Therefore, the top select gate of each memory region 20a can be controlled independently. When a bit line 30 is selected, the top select gate in a memory region 20a is turned on, thus selecting the channel structure 21 connected to the bit line 30 in that memory region 20a. When a word line is selected, a memory cell in that channel structure 21 can be selected, thereby realizing the storage function of a single memory cell.

[0062] In one block structure 20, there are nine columns of channel structures (the direction of the "columns" is parallel to X), and the position of the middle column of channel structures is sacrificed due to the presence of the top select gate tangent 22. In one block structure 20, a bit line 30 connects two channel structures 21, and the top select gates of these two channel structures 21 are separated by the top select gate tangent 22.

[0063] Please see Figure 2 , Figure 2 This is a top view schematic diagram of a semiconductor device provided in the first embodiment of the present invention. The semiconductor device 100 includes a substrate and a stack (not shown) on the substrate, formed by alternating layers of interlayer insulating layers and gate layers (replaced by interlayer sacrificial layers), a plurality of channel structures 101 perpendicularly penetrating the stack, at least two first gate line slots 102 perpendicularly penetrating the stack and extending laterally (X) (adjacent first gate line slots 102 define a block structure 104), and a plurality of top select gate tangents 103 located between adjacent first gate line slots 102 and extending laterally (X). The plurality of top select gate tangents 103 divide the block structure 104 between adjacent first gate line slots 102 into a plurality of memory regions 104a. The gate layer at the top of the stack can serve as a top select gate, and the top select gate tangents 103 separate the top select gate into multiple portions, thereby enabling individual control of the separated different top select gates.

[0064] In this embodiment, the semiconductor device 100 is divided into multiple block structures 104 by multiple first gate line slots 102 in a longitudinal (Y) direction parallel to the substrate, i.e., multiple block structures 104 are arranged in the Y direction. In some embodiments, the block structure 104 is further divided into multiple finger structures (not shown in the figure) in the longitudinal (Y) direction by multiple first gate line slots 102, and at least one first gate line slot 102 is located between adjacent finger structures within the same block structure 104.

[0065] In this embodiment, the first gate line gap 102 is a gate line gap that divides the block structure 104. This first gate line gap 102 extends continuously; therefore, the block structure 104 in this embodiment is different from the block structure containing multiple finger structures mentioned earlier. From the arrangement of the channel structure, compared to the prior art, the semiconductor device 100 uses… Figure 1 The middle grid line gap 10 was replaced with Figure 2 The top of the middle line is selected as tangent line 103, which means... Figure 1 The two block structures 20 in the middle became Figure 2 One of the block structures is 104. It's understandable that, since the top-select gate tangent only requires cutting the top-select gate, the process for fabricating the top-select gate tangent is much simpler than the process for fabricating the gate gap. Furthermore, theoretically... Figure 2 The middle top selection of the gate tangent 103 sacrifices a row of channel structures, relative to Figure 1 The width of the middle gate line gap 10 is narrower, so the semiconductor device 100 can increase the storage density from the perspective of the entire chip.

[0066] From a block structure perspective, existing technologies provide Figure 1 In a block structure 20, there is only one top select gate tangent line 22 and only 8 columns of memory channel structures. However, the semiconductor device 100 provided in this embodiment can add more columns of channel structures in the Y direction in a block structure 104, and add more (greater than or equal to 2) top select gate tangent lines 103 in a block structure 104 to divide the block structure 104 into multiple (greater than 2) memory regions 104a, so that the channel structure 101 in each memory region 104a can be controlled independently, thereby increasing the memory capacity.

[0067] Please see Figure 3 , Figure 3 This is a top view schematic diagram of another semiconductor device provided by the prior art, which is related to... Figure 1 The same structural designation indicates the same structure. In a block structure 20 of this semiconductor device, there is only one top select gate tangent line 22, compared to... Figure 1In existing technology, two rows of channel structures 21 are added to a storage area 20a to increase storage capacity, but... Figure 3 The semiconductor device therefore also increases the number of bit lines 30, making the spacing between bit lines 30 smaller.

[0068] Compared to existing technologies Figure 3 In the semiconductor device provided in the first embodiment of the present invention, the semiconductor device 100 can increase the storage capacity without increasing the number of bit lines 105 or reducing the spacing between bit lines 105 while increasing the channel structure in the Y direction.

[0069] Please see Figure 4 , Figure 4 This is a top view schematic diagram of a semiconductor device provided in the second embodiment of the present invention. The semiconductor device 200 includes at least two first gate line slots 202 extending laterally (X), a channel structure 201 located between adjacent first gate line slots 202, and multiple top select gate tangents 203. The top select gate tangents 203 extend laterally (X) and divide the block structure 204 into multiple memory regions 204a. The semiconductor device 200 and... Figure 2 The difference in the semiconductor device 100 is that there is a spacer region 204b between the multiple memory regions 204a, meaning that there is no row of channel structures between the memory regions 204a. Therefore, the semiconductor device 200 provided in the second embodiment does not sacrifice a row of channel structures at the location of the top selected gate tangent 203, thus avoiding waste of channel structure. Moreover, this spacer region 204b only needs to accommodate one top selected gate tangent 203, which is smaller than the width required to accommodate a row of channel structures, thereby increasing storage density.

[0070] Please see Figure 5 , Figure 5This is a top view schematic diagram of a semiconductor device provided in the third embodiment of the present invention. Similar to the second embodiment, the semiconductor device 300 includes a channel structure 301, a first gate line slot 302, and a top select gate tangent 303 dividing the block structure 304 into multiple memory regions 304a. The semiconductor device 300 also includes one or more second gate line slots 305 that vertically penetrate the stack and are located between adjacent first gate line slots 302. The shape of the second gate line slot 305 can be circular, rectangular, or other suitable shapes. The size of the second gate line slot 305 can be determined according to actual needs. Since the width between adjacent first gate line slots 302 increases with the increase of the top select gate tangent 303 and memory regions 304a, the difficulty of replacing the interlayer sacrificial layer with a gate layer through the first gate line slots 302 increases. Therefore, the second gate line slots 305 located in the block structure 304 can, together with the first gate line slots 302, replace the interlayer sacrificial layer with a gate layer, thereby reducing process difficulty.

[0071] Preferably, the second grid line gap 305 is located between two adjacent storage areas 304a. Since the top selection grid tangent 303 is also located between two adjacent storage areas 304a, the second grid line gap 305 and the top selection grid tangent 303 have an overlapping portion. This can save space and prevent the second grid line gap 305 from occupying other space in other locations, thereby increasing the storage density.

[0072] Further preferably, a plurality of second gate line slots 305 are arranged in a row along the top selected gate tangent line 303, and the plurality of second gate line slots 305 in the row are arranged at horizontal (X) intervals. The distance from each second gate line slot 305 to the two adjacent first gate line slots 302 is equal, so that the etchant of the sacrificial layer between the etch layers and the material of the deposited gate layer can be uniformly distributed, thereby further reducing the difficulty of the replacement process and improving the effect of the replacement process. Wherein, in order for the second gate line slots 305 to be located between two adjacent memory regions 304a and to be equidistant from the two first gate line slots 302, that is, to make the top selected gate tangent line 303 located in the exact center of the block structure 304, the number of memory regions 304a is even.

[0073] In some embodiments, the number of storage areas 304a can be odd, and the number of top selection gate tangents 303 will be even. If the second gate slot 305 is to be located between two adjacent storage areas 304a and overlap with the top selection gate tangent 303, the distance from the second gate slot 305 to the two adjacent first gate slots 302 will not be equal. Preferably, the second gate slots 305 can be arranged along one of the two middle top selection gate tangents 303, or they can be distributed on the two middle top selection gate tangents 303.

[0074] Preferably, there are intervals 304b between the plurality of storage areas 304a, each top selected gate tangent line 303 is located in one of the intervals 304b, and the second gate line slot 305 is also located in the interval 304b. More preferably, the second gate line slot 305 also occupies an adjacent portion of the storage area 304a, and the portion of the storage area 304a occupied by the second gate line slot 305 does not have the channel structure 301, so the second gate line slot 305 does not coincide with the channel structure 301.

[0075] In this embodiment, the first gate line slot 302 includes a first gate line cut that perpendicularly penetrates the stack and extends in the lateral (X) direction, and an insulating layer and a conductive layer (not shown) stacked from the outside to the inside in the first gate line cut. The second gate line slot 305 may include one or more second gate line cuts that perpendicularly penetrate the stack and are located between two adjacent first gate line slots 302, and an insulating layer and a conductive layer sequentially filled in the second gate line cut. In some embodiments, the second gate line slot 305 may include one or more second gate line cuts that perpendicularly penetrate the stack and are located between two adjacent first gate line slots 302, and an insulating layer filled in the second gate line cut.

[0076] Please see Figure 6 , Figure 6 This is a top view schematic diagram of the semiconductor device provided in the fourth embodiment of the present invention. The semiconductor device 400 and... Figure 5 The semiconductor device 300 is the same as that in the stack, including a channel structure 401, a first gate line slot 402, a top select gate tangent 403 that divides the block structure 404 into multiple memory regions 404a, and one or more second gate line slots 405 that are vertically through the stack and located between two adjacent first gate line slots 402.

[0077] The difference between the fourth embodiment and the third embodiment is that in this semiconductor device 400, multiple second gate line slots 405 are arranged in multiple columns along the top selected gate tangent line 403. This facilitates the replacement of the interlayer sacrificial layer with the gate layer when the width of the block structure 404 is larger. Preferably, adjacent columns of second gate line slots 405 are staggered in the transverse (X) direction, that is, multiple second gate line slots 405 are not aligned in the Y direction, so that the multiple second gate line slots 405 are evenly distributed in the block structure 404. Furthermore, multiple second gate line slots in the same column are spaced apart along the transverse (X) direction.

[0078] Understandable, Figure 6A block structure 404 has 5 top selection gate tangents 403, 6 memory areas 404a, and 2 columns of second gate slots 405. From left to right, the first column of second gate slots 405 shows only two second gate slots 405, and the second column shows only one second gate slot 405. The number of second gate slots 405 in each column in the horizontal direction (X) is determined by the number of channel structures 401 in the horizontal direction (X). That is, if the memory areas 404a extend further in the horizontal direction (X), there will be more second gate slots 405 in each column.

[0079] In this embodiment, two memory regions 404a are spaced between two adjacent columns of the second gate line slots 405, and two memory regions 404a are spaced between each first gate line slot 402 and an adjacent column of the second gate line slots 405. If the top selected gate tangent 403 is fabricated before the interlayer sacrificial layer replacement process, the top selected gate tangent 403 will affect the etching of the top sacrificial layer of each memory region 404a. Since the first gate line gap 402 and the second gate line gap 405 are both located between two adjacent memory regions 404a, a first gate line gap 402 can replace the interlayer sacrificial layer in the memory regions 404a on both sides with the gate layer, and a column of second gate line gaps 405 can also replace the interlayer sacrificial layer in the memory regions 404a on both sides with the gate layer. Therefore, a first gate line gap 402 and an adjacent column of second gate line gaps 405 can be separated by two memory regions 404a, and two adjacent columns of second gate line gaps 405 can also be separated by two memory regions 404a. That is, a top select gate tangent line 403 is spaced between two adjacent columns of second gate line gaps 405.

[0080] Please see Figure 7 , Figure 7 This is a top view schematic diagram of a semiconductor device provided in a modified embodiment of the fourth embodiment of the present invention. The difference from the fourth embodiment is that the block structure 404 has 9 top select gate cut lines 403 and 10 memory regions 404a, as well as 4 columns of second gate line slots 405.

[0081] The semiconductor device 400 provided in the fourth embodiment of the present invention has multiple rows of second gate line slots 405 distributed along the top select gate tangent line 403, which gives the channel structure 401 better scalability in the Y direction. That is, without affecting the process of replacing the interlayer sacrificial layer with the gate layer, more channel structures 401 and top select gate tangent lines 403 can be added in the Y direction to improve the memory capacity.

[0082] Please see Figure 8 , Figure 8 This is a schematic flowchart illustrating the method for fabricating a semiconductor device according to the fifth embodiment of the present invention. Please also refer to... Figures 9a-9b , Figures 9a-9b This is a top view schematic diagram of the semiconductor device provided in the fifth embodiment of the present invention during the fabrication process. The fabrication method includes steps S1-S5, which can be used to form the above-mentioned… Figure 5 Semiconductor device 300, therefore Figures 9a-9b Continue Figure 5 The structural designation.

[0083] Please see first. Figure 8 Steps S1-S2 and Figure 9a .

[0084] Step S1: Provide a substrate and form a stack on the substrate, the stack comprising alternating stacked interlayer insulating layers and interlayer sacrificial layers.

[0085] Step S2: Form multiple channel structures 301, which vertically penetrate the stack.

[0086] because Figure 9a This is a top-view structural diagram, so the specific structure of the stack is not shown. Step S1, which forms the stack, is the same as in the prior art. Step S2, which forms the plurality of channel structures 301, includes: etching the stack in the vertical direction using a photolithography process to form a plurality of memory areas 304a, and reserving a spacing area 304b between two adjacent memory areas 304a. In this embodiment, during the step of etching the stack to form the channel structure 301, one or more second gate line slot forming areas 304c may also be reserved. The second gate line slot forming area 304c is located in the spacing area 304b and occupies a portion of each of two adjacent memory areas 304a. The second gate line slot forming area 304c does not have the channel structure 301. Each spacing area 304b is used to form a top select gate tangent.

[0087] See Figure 8 Step S3 and Figure 9b .

[0088] Step S3: Form at least two first gate line cutouts 3021 that are perpendicular to the stack and extend in a transverse (X) direction parallel to the substrate, and one or more second gate line cutouts 3051 located between two adjacent first gate line cutouts 3021.

[0089] Specifically, a mask can be used to etch at least two first gate line cutouts 3021 extending laterally (X) to divide the multiple channel structures 301 into multiple block structures 304. Figure 9bOnly one block structure 304 is displayed, while the stack is etched in the second gate line gap forming area 304c to form a second gate line cutout 3051, which is located between two adjacent storage areas 304a.

[0090] Please see Figure 8 Step S4 in the process.

[0091] Step S4: Replace the interlayer sacrificial layer with the gate layer through the first gate line cutout 3021 and the second gate line cutout 3051.

[0092] Specifically, since the interlayer insulating layer and the interlayer sacrificial layer have different etching selectivity, wet etching can be used. The etching solution is poured in from the first gate line cut 3021 and the second gate line cut 3051. Since the first gate line cut 3021 and the second gate line cut 3051 run through the entire stack and are evenly distributed, each interlayer sacrificial layer will be etched. Finally, metal material is poured in from the first gate line cut 3021 and the second gate line cut 3051 to form the gate layer at the location of the interlayer sacrificial layer.

[0093] Please see Figure 8 Step S5 in the process Figure 9b and Figure 5 .

[0094] Step S5: Form a plurality of top selection gate cut lines 303, the plurality of top selection gate cut lines 303 being located between two adjacent first gate line cuts 3021 and extending in the transverse (X) direction.

[0095] In this embodiment, a top select gate tangent 303 is formed by etching the top select gate of the stack in each spacer region 304b. The multiple top select gate tangents 303 divide the channel structure 301 between two adjacent first gate line cuts 3021 into multiple memory regions 304a. Since the second gate line cut 3051 runs through the entire stack, the subsequently formed top select gate tangent 303 cuts a portion of the second gate line cut 3051.

[0096] In this embodiment, after step S4, the preparation method further includes: filling the first gate line cutout 3021 and the second gate line cutout 3051 with an insulating layer and a conductive layer from the outside to the inside to form a first gate line gap 302 and a second gate line gap 305. The first gate line gap 302 and the second gate line gap 305 can serve as an array common source (ACS).

[0097] In some embodiments, the preparation method after step S4 may also include: filling the first gate line cutout 3021 with an insulating layer and a conductive layer from the outside to the inside to form a first gate line gap 302, while filling the second gate line cutout 3051 with only insulating material to form a second gate line gap 305.

[0098] The method for fabricating a semiconductor device 300 provided in the fifth embodiment of the present invention first forms a first gate line cut 3021 and a second gate line cut 3051 to facilitate the replacement of the interlayer sacrificial layer with the gate layer. The top selected gate cut line 303 formed later will not affect the replacement process. Moreover, the replacement process can be carried out normally without too many second gate line cuts 3051. Therefore, the number of second gate line cuts 3051 can be reduced, and the loss of channel structure density caused by the second gate line cuts 3051 is very low.

[0099] Please see Figure 10 , Figure 10 This is a schematic flowchart illustrating the method for fabricating a semiconductor device according to the sixth embodiment of the present invention. Please also refer to... Figures 11a-11c , Figures 11a-11c This is a top view schematic diagram of the semiconductor device provided in the sixth embodiment of the present invention during the fabrication process. The fabrication method includes the following steps S100-S500, which can be used to form the above-mentioned... Figure 6 Semiconductor device 400, therefore Figures 11a-11c Continue Figure 6 The structural designation.

[0100] Please see first. Figure 10 Steps S100-S200 and Figure 11a .

[0101] Step S100: Provide a substrate and form a stack on the substrate, the stack comprising alternately stacked interlayer insulating layers and interlayer sacrificial layers.

[0102] Step S200: Form a plurality of channel structures 401, wherein the plurality of channel structures 401 penetrate the stack vertically.

[0103] The specific preparation method of step S100 is the same as that of step S1 in the fifth embodiment, and the specific preparation method of step S200 is the same as that of step S2 in the fifth embodiment, thereby forming as shown in the figure. Figure 11a The block structure 404 shown includes a plurality of storage areas 404a, a spacing area 404b located between two adjacent storage areas 404a, and one or more second gate line slot forming areas 404c.

[0104] Please see Figure 10 Step S300 and Figure 11b .

[0105] Step S300: Form multiple top selection gate tangents 403 extending in the said transverse (X) direction.

[0106] Specifically, step S300 is the same as step S5 in the fourth embodiment, that is, the top select gate of the stack is etched in the spacer region 404b to form a corresponding top select gate cleavage, and then insulating material is deposited in the top select gate cleavage to form a top select gate cleavage line 403 separating the top select gate, so that the top select gate cleavage line in each memory region 404a can be controlled individually.

[0107] Please see Figure 10 Step S400 and Figure 11c .

[0108] Step S400: Form at least two first gate line cutouts 4021 that are perpendicular to the stack and extend in a lateral (X) direction parallel to the substrate, and one or more second gate line cutouts 4051 located between two adjacent first gate line cutouts 4021, wherein the plurality of top selected gate cutouts 403 are located between two adjacent first gate line cutouts 4021.

[0109] Step S400 is the same as step S3 in the fifth embodiment, thereby forming two first gate line cutouts 4021 on both sides of a block structure 404, and simultaneously etching the stack in the second gate line gap forming region 404c to form second gate line cutouts 4051. The subsequently formed multiple second gate line cutouts 4051 also penetrate the previously formed top selection gate tangent 403, and the multiple top selection gate tangents 403 are located between two adjacent first gate line cutouts 4021.

[0110] Please see Figure 10 Step S500 in the process.

[0111] Step S500: Replace the interlayer sacrificial layer with a gate layer through the first gate line cutout 4021 and the second gate line cutout 4051.

[0112] Step S500 is the same as the preparation method in step S4 of the fifth embodiment, and will not be described again here. Similar to the fifth embodiment, after step S500, the preparation method also includes filling the first gate line cutout 4021 and the second gate line cutout 4051 with material as described in the fifth embodiment, forming a shape as shown in the fifth embodiment. Figure 6 The first grid line slot 402 and the second grid line slot 405 are shown.

[0113] The semiconductor device 400 fabrication method provided in the sixth embodiment of the present invention has a second gate line cut 4051 or a first gate line cut 4021 every other top select gate cut 403. Even if the top select gate cut 403 is formed before the step of etching the interlayer sacrificial layer to form the gate layer, it will not block the etching and replacement of the interlayer sacrificial layer in any memory region 404a. Therefore, this special arrangement of the second gate line cut 4051 makes the fabrication method not require the first gate line cut 4021 and the second gate line cut 4051 to be formed first. In other words, forming the top select gate cut 403 first will not affect the replacement process.

[0114] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized by, include: stack; Multiple channel structures penetrate the stack vertically; At least two first gate line slots penetrate the stack perpendicularly and extend in a lateral direction parallel to the stack, with two adjacent first gate line slots defining a block structure. At least one second gate line slot, perpendicularly penetrating the stack and located between two adjacent first gate line slots; Multiple top-select grid tangents are located between the gaps of two adjacent first grid lines and extend in the lateral direction; The second grid line gap overlaps with the top selected grid tangent.

2. The semiconductor device according to claim 1, wherein The second grid line gap has a circular or rectangular cross-sectional shape parallel to the stack.

3. The semiconductor device of claim 1, wherein Between two adjacent first grid line slots, the second grid line slots are arranged in at least one column along the top selected grid tangent, and a column of second grid line slots includes one or more second grid line slots.

4. The semiconductor device according to claim 3, wherein A top selection grid tangent is provided between the gaps of two adjacent columns of the second grid lines.

5. The semiconductor device of claim 3, wherein Between two adjacent first grid line slots, the plurality of second grid line slots are arranged in a row along the top selected grid tangent.

6. The semiconductor device according to claim 5, characterized in that, The distance from each second grid line slot to the two adjacent first grid line slots is equal.

7. The semiconductor device according to claim 3, characterized in that, Multiple top selection grid tangents are provided between the first grid line slot and an adjacent column of second grid line slots.

8. The semiconductor device according to claim 3, characterized in that, The gaps between the second grid lines in two adjacent columns are staggered in the lateral direction.

9. The semiconductor device according to claim 3, characterized in that, At most one top selection grid tangent is provided between the gaps of two adjacent columns of the second grid lines.

10. The semiconductor device according to claim 3, characterized in that, At most one top selection grid tangent is provided between the first grid line slot and an adjacent column of second grid line slots.

11. The semiconductor device according to claim 3, characterized in that, Multiple second grid line slots in the same column are spaced apart along the lateral direction.

12. The semiconductor device according to claim 1, characterized in that, The multiple top-select gate tangents divide the area between the gaps of two adjacent first gate lines into at least three storage areas.

13. The semiconductor device according to claim 12, characterized in that, The stack includes at least one top select gate, the plurality of top select gate tangents dividing the top select gate between two adjacent first gate line gaps into at least three portions, and the at least three portions are each located in one of the memory regions.

14. The semiconductor device according to claim 12, characterized in that, There is a gap between two adjacent storage areas, each of the top selected gate tangents is located in one of the gaps, and each of the second gate gaps is located in one of the gaps.

15. The semiconductor device according to claim 1, characterized in that, The first gate line slot includes a first gate line cut that extends vertically through the stack and in the lateral direction, and an insulating layer and a conductive layer that are sequentially filled in the first gate line cut.

16. The semiconductor device according to claim 1, characterized in that, The second gate line slot includes a second gate line cut that runs vertically through the stack, and an insulating layer and a conductor layer that are sequentially filled in the second gate line cut.

17. The semiconductor device according to claim 1, characterized in that, The second gate line slot includes a second gate line cut that extends vertically through the stack, and an insulating layer filling the second gate line cut.

18. A method for fabricating a semiconductor device, characterized in that, include: A stack is formed, the stack comprising alternating layers of interlayer insulation and interlayer sacrificial layers; Multiple channel structures are formed, and the multiple channel structures penetrate the stack vertically; At least two first gate line cuts are formed, the at least two first gate line cuts perpendicularly penetrate the stack and extend in a lateral direction parallel to the stack, and two adjacent first gate line cuts define a block structure; At least one second gate line cut is formed, the at least one second gate line cut perpendicularly through the stack and located between two adjacent first gate line cuts; The interlayer sacrificial layer is replaced with a gate layer through the first gate line cut and the second gate line cut; Multiple top selection gate tangents are formed, which perpendicularly penetrate the stack and are located between two adjacent first gate tangents; The second gate line cut overlaps with the top selected gate cut.

19. The method for fabricating a semiconductor device according to claim 18, characterized in that, The second grid cut has a circular or rectangular cross-sectional shape parallel to the stack.

20. The method for fabricating a semiconductor device according to claim 18, characterized in that, Between two adjacent first grid line cuts, the second grid line cuts are arranged in at least one column along the top selected grid tangent, and a column of second grid line cuts includes one or more second grid line cuts.

21. The method for fabricating a semiconductor device according to claim 20, characterized in that, A top selection grid cut is provided between two adjacent columns of the second grid cut.

22. The method for fabricating a semiconductor device according to claim 20, characterized in that, Multiple top selection grid cut lines are provided between the first grid cut and an adjacent column of second grid cuts.

23. The method for fabricating a semiconductor device according to claim 21 or 22, characterized in that, The step of forming multiple top-select gate cut lines is performed after the step of replacing the interlayer sacrificial layer with the gate layer through the first gate cut and the second gate cut.

24. The method for fabricating a semiconductor device according to claim 20, characterized in that, Between two adjacent first grid line cuts, the plurality of second grid line cuts are arranged in a row along the top selected grid tangent.

25. The method for fabricating a semiconductor device according to claim 24, characterized in that, Each second gate line cut is equidistant from the two adjacent first gate line cuts.

26. The method for fabricating a semiconductor device according to claim 20, characterized in that, The second grid line cuts in two adjacent columns are staggered in the lateral direction.

27. The method for fabricating a semiconductor device according to claim 20, characterized in that, Multiple second grid line cuts in the same column are spaced apart along the lateral direction.

28. The method for fabricating a semiconductor device according to claim 20, characterized in that, At most one top selection grid cut is provided between two adjacent columns of the second grid cut.

29. The method for fabricating a semiconductor device according to claim 20, characterized in that, There is at most one top selection grid cut line between the first grid cut and an adjacent column of second grid cut lines.

30. The method for fabricating a semiconductor device according to claim 28 or 29, characterized in that, The step of forming multiple top-select gate cut lines is performed before the step of replacing the interlayer sacrificial layer with the gate layer through the first gate cut and the second gate cut.

31. The method for fabricating a semiconductor device according to claim 18, characterized in that, The steps of forming at least two first gate line cuts and the steps of forming at least one second gate line cut are performed in the same process.

32. The method for fabricating a semiconductor device according to claim 18, characterized in that, The multiple top-select gate tangents divide the area between two adjacent first gate tangents into at least three storage areas.

33. The method for fabricating a semiconductor device according to claim 32, characterized in that, The stack includes at least one top select gate, the plurality of top select gate tangents dividing the top select gate between two adjacent first gate line cuts into at least three portions, and the at least three portions are each located in one of the memory regions.

34. The method for fabricating a semiconductor device according to claim 32, characterized in that, There is a gap between two adjacent storage areas, each of the top selected gate cut lines is located in one of the gaps, and each of the second gate cut lines is located in one of the gaps.

35. The method for fabricating a semiconductor device according to claim 18, characterized in that, After the step of replacing the interlayer sacrificial layer with the gate layer through the first gate line cut and the second gate line cut, the method further includes: sequentially filling the first gate line cut and the second gate line cut with an insulating layer and a conductive layer to form a first gate line gap and a second gate line gap.

36. The method for fabricating a semiconductor device according to claim 18, characterized in that, After the step of replacing the interlayer sacrificial layer with the gate layer through the first gate line cut and the second gate line cut, the method further includes: sequentially filling the first gate line cut with an insulating layer and a conductive layer, and filling the second gate line cut with the insulating layer to form a first gate line gap and a second gate line gap.

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