Display panel and display device

Abstract

The present application describes a display panel and a display device, including: a pixel circuit and a light-emitting element; the pixel circuit includes a data writing module, a driving module and a compensation module; the driving transistor includes a source, a gate, an active layer, a first drain and a second drain, a first driving unit is included between the source and the first drain, a second driving unit is included between the first drain and the second drain, the length of the channel region of the first driving unit is L1, and the length of the channel region of the second driving unit is L2; ​​the data writing module is connected to the source, the compensation module is connected between the gate and the first drain, or the data writing module is connected to the first drain, and the compensation module is connected between the gate and the second drain. The present application is conducive to improving the time required for the display panel to overcome errors when refreshing the screen, reducing flicker problems, and improving display effects.

Description

[0001] This application is a divisional application with the application date of March 16, 2021, application number 202110280448.3, and the name of the invention being “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device comprising the display panel. Background Art

[0003] With the continuous development of display technology, emerging display-related technologies continue to emerge. Self-luminous display panels such as organic light emitting diode (OLED) display panels and micro light emitting diode (Micro LED) display panels are gradually favored by consumers and become a research hotspot.

[0004] In OLED display panels and micro LED display panels, the pixel circuit that provides driving current for the light-emitting element is a crucial element. In the pixel circuit, the driving transistor is one of the key components. The driving transistor plays an important role in generating the driving current. On the one hand, it is required to have good driving capability, and on the other hand, it is required to avoid signal errors when the display panel screen is switched as much as possible, so as to ensure the display effect of the display panel. Therefore, how to reduce the signal error when the display panel screen is switched while ensuring the driving capability of the driving transistor is an urgent problem to be solved in this field. Summary of the invention

[0005] In view of this, the present application provides a display panel and a display device including the display panel, wherein the driving transistor is specially designed to ensure the driving capability of the driving transistor while reducing the signal error caused by the driving transistor when the display panel screen is switched.

[0006] On the one hand, an embodiment of the present application provides a display panel, wherein the display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a data writing module, a driving module and a compensation module; the data writing module is used to selectively provide a data signal to the driving module; the driving module is used to provide a driving current to the light-emitting element, and the driving module includes a driving transistor; the compensation module is used to compensate for the threshold voltage of the driving transistor; the driving transistor includes a source, a gate, an active layer, and a first drain and a second drain, a first driving part is included between the source and the first drain, a second driving part is included between the first drain and the second drain, a channel region of the first driving part has a length of L1, and a channel region of the second driving part has a length of L2; the data writing module is connected to the source, and the compensation module is connected between the gate and the first drain, or the data writing module is connected to the first drain, and the compensation module is connected between the gate and the second drain; wherein,

[0007] L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤ΔVgd2×1 / 2, or,

[0008] L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVsg×1 / 2;

[0009] In the formula, ΔVsd2=|Vs-Vd2|, ΔVsg=|Vs-Vg|, ΔVgd2=|Vg-Vd2|, in the light-emitting stage of the light-emitting element, Vs is the voltage of the source of the driving transistor, Vd2 is the voltage of the second drain of the driving transistor, and Vg is the voltage of the gate of the driving transistor.

[0010] On the other hand, an embodiment of the present application provides another display panel, wherein the display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a data writing module, a driving module and a compensation module; the data writing module is used to selectively provide a data signal to the driving module; the driving module is used to provide a driving current to the light-emitting element, and the driving module includes a driving transistor; the compensation module is used to compensate for the threshold voltage of the driving transistor; the driving transistor includes a source, a gate, an active layer, and a first drain and a second drain, a first driving part is included between the source and the first drain, a second driving part is included between the first drain and the second drain, a length of a channel region of the first driving part is L1, and a length of a channel region of the second driving part is L2; ​​the data writing module is connected to the source, and the compensation module is connected between the gate and the first drain, or the data writing module is connected to the first drain, and the compensation module is connected between the gate and the second drain; wherein, L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤2V, or,

[0011] L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤2V;

[0012] In the formula, ΔVsd2=|Vs-Vd2|, ΔVsg=|Vs-Vg|, ΔVgd2=|Vg-Vd2|, in the light-emitting stage of the light-emitting element, Vs is the voltage of the source of the driving transistor, Vd2 is the voltage of the second drain of the driving transistor, and Vg is the voltage of the gate of the driving transistor.

[0013] On the other hand, an embodiment of the present application provides a display device, including the above-mentioned display panel.

[0014] In a display panel, during the light-emitting stage of a light-emitting element, the voltages between the source, gate and drain of a driving transistor may be such that the voltage difference between the gate and the drain is much greater than the voltage difference between the source and the gate, or the voltage difference between the source and the gate is much greater than the voltage difference between the gate and the drain. In this case, on the side with a larger voltage difference, under the action of a strong electric field, carriers migrate and are easily captured when encountering defects, forming a built-in electric field and polarization. This phenomenon can cause the Vd-Ig curve of the driving transistor to shift, resulting in a deviation in the threshold voltage, which in turn causes the signal written within the initial few frames to have certain errors when the driving transistor rewrites the data signal when the display panel refreshes the screen. This error can only be mitigated by multiple data write frame refreshes, but this can cause flickering and affect the display effect.

[0015] Through the above description, the display panel and display device provided by the present application, by dividing the driving transistor into a first driving part and a second driving part, in the data writing stage, one of the first driving part between the source and the first drain or the second driving part between the first drain and the second drain is not included in the data writing stage, and the voltage difference between the first drain and the gate is set within the range of V0, and V0 is generally set to be less than ΔVgd2 or half of ΔVsg, so that the voltage difference between the first drain and the gate is reduced to within half of the original voltage between the gate and the source or within half of the original voltage between the gate and the second drain, so that the potential difference between the first drain or the source and the gate can be slowed down, and then the threshold voltage offset phenomenon of at least one of the first driving part or the second driving part is weakened, and then one of the first driving part or the second driving part is used to enter the data writing stage, while the other does not participate in the data writing stage, so that the time required for the display panel to overcome the error when refreshing the picture can be better improved, the flicker problem is weakened, and the display effect is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a pixel circuit of a display panel provided in an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of another pixel circuit of a display panel provided in an embodiment of the present application;

[0018] Figure 3 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application;

[0020] Figure 5 is a cross-sectional schematic diagram of a driving transistor provided in an embodiment of the present application;

[0021] Figure 6 is a cross-sectional schematic diagram of another driving transistor provided in an embodiment of the present application;

[0022] Figure 7 It is a relationship diagram between the brightness and refresh frame number of a display panel when refreshing the screen in the prior art;

[0023] Figure 8 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application;

[0024] Fig. 9 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application;

[0025] Fig.10 is a cross-sectional schematic diagram of another driving transistor provided in an embodiment of the present application;

[0026] Fig.11 is a schematic diagram of a top view structure of a driving transistor provided in an embodiment of the present application;

[0027] Fig.12 is a schematic diagram of a top view of another driving transistor provided in an embodiment of the present application;

[0028] Fig.13 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application;

[0029] Fig.14 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application;

[0030] Fig.15 It is a schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0032] It should be noted that specific details are described in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0033] refer to Figure 1-Figure 6 , Figure 1 is a schematic diagram of a pixel circuit of a display panel provided in an embodiment of the present application, Figure 2 is a schematic diagram of another pixel circuit of a display panel provided in an embodiment of the present application, Figure 3 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application. Figure 4 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application. Figure 5 is a cross-sectional schematic diagram of a driving transistor provided in an embodiment of the present application, Figure 6 1 is a cross-sectional schematic diagram of another driving transistor provided in an embodiment of the present application; wherein the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a data writing module 11, a driving module 12 and a compensation module 13; the data writing module 11 is used to selectively provide a data signal to the driving module 12; the driving module 12 is used to provide a driving current to the light-emitting element 20, and the driving module 12 includes a driving transistor T0; the compensation module 13 is used to compensate for the threshold voltage of the driving transistor T0; the driving transistor T0 includes a source 102 (N2 node), a gate 101 (N1 node), an active layer 105, a first drain 103 (N3 node) and a second drain 104 (N4 node), a first driving part T01 is included between the source 102 and the first drain 103, a second driving part T02 is included between the first drain 103 and the second drain 104, the length of the channel region of the first driving part T01 is L1, and the length of the channel region of the second driving part T02 is L2; ​​as shown in FIG. Figure 1 and Figure 2 As shown, the data writing module 11 is connected to the source 102, and the compensation module 13 is connected between the gate 101 and the first drain 103, or, as shown in FIG. Figure 3 and Figure 4As shown, the data writing module 11 is connected to the first drain 103, and the compensation module 13 is connected between the gate 101 and the second drain 104; wherein, L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤ΔVgd2×1 / 2, or, L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVsg×1 / 2; wherein, ΔVsd2=|Vs-Vd2|, ΔVsg=|Vs-Vg|, ΔVgd2=|Vg-Vd2|, in the light emitting stage of the light emitting element 20, Vs is the voltage of the source of the driving transistor, Vd2 is the voltage of the second drain of the driving transistor, and Vg is the voltage of the gate of the driving transistor.

[0034] refer to Figure 5 and Figure 6 In the light-emitting stage of the light-emitting element 20, since the driving transistor T0 is responsible for generating a driving current for the light-emitting element 20 in the light-emitting stage, its gate 101 stores a data signal required for light emission, and the transistor usually works in a non-saturated state. The voltage between the source 102 and the second drain 104 is not equal, and there may be a large voltage difference. At this time, the voltage difference between the gate 101 and the source 102 is generally not equal to the voltage difference between the gate 101 and the second drain 104, and the difference may be large. When the voltage difference between the gate 101 and the source 102 is large, the side with a larger voltage difference will cause the carriers to migrate under the action of a strong electric field due to the larger electric field strength. When encountering defects, they are easily captured, forming a built-in electric field and polarization. This phenomenon will cause the Vd-Ig curve of the driving transistor T0 to shift, resulting in a deviation in the threshold voltage. If the threshold voltage of the driving transistor T0 is Vth, and the deviation is ΔV, then the threshold voltage after the deviation is Vth±ΔV. Here, it should be noted that Figure 5 and Figure 6 The arrows in the middle indicate the density of the electric field lines between the source and the gate, the first drain and the gate, and the second drain and the gate. The density of the electric field lines is merely used to exemplify and illustrate the magnitude of the electric field strength, and the direction of the arrows can be adjusted according to the specific situation.

[0035] refer to Figure 7 , Figure 7It is a relationship diagram between the brightness and refresh frame number of a display panel when the screen is refreshed in the prior art, wherein the ordinate is the brightness of the light-emitting element 20, and the abscissa is the refresh frame number. The starting point in the figure is a screen with extremely small driving current (called a black screen, which is actually also a light-emitting stage, but a light-emitting stage with extremely small light-emitting current). Therefore, the brightness at the starting point is close to 0. When the screen is refreshed, the expected brightness is 450nits. After the first frame of data is refreshed, the brightness first reaches 300nits, and then falls back to a certain extent, failing to reach the expected brightness. Here, as analyzed above, when the screen is switched, because the threshold voltage of the driving transistor in the previous light-emitting cycle is offset, the threshold voltage of the driving transistor deviates to Vth±ΔV. In the data writing stage, the offset of the threshold voltage causes the data signal Vdata written to the gate of the driving transistor to be unstable and unable to reach the accurate value, thereby causing the brightness after the first frame is refreshed to fail to reach the expected brightness. When the second frame data is refreshed, the brightness reaches 450nits, but there is a certain degree of decline. Here, when the second frame data is refreshed, the voltage between the source, gate, and drain of the driving transistor in the light-emitting stage is changed in the data writing stage. Through 2 data writing, the deviation ΔV of the threshold voltage will be gradually improved, making ΔV smaller and smaller, and the threshold voltage tends to be stable. Therefore, when the second frame data is refreshed, the data signal Vdata is more accurate than when the first frame data is refreshed, so that when the second frame data is refreshed, it is closer to the target brightness. When the third frame data is refreshed, as described above, the deviation of the threshold voltage is further improved, ΔV is smaller, the threshold voltage is more stable, the data signal Vdata is written more accurately, and the brightness is closer to the target brightness. After multiple data refreshes, the brightness gradually reaches the target brightness. However, when the number of brightness refresh frames is large, the human eye will perceive the change in brightness, resulting in flickering when the display screen observed by the human eye switches. Therefore, it is necessary to reduce the number of data refresh frames required to achieve the target brightness as much as possible, and the number of data refresh frames is related to the threshold voltage deviation of the driving transistor. The smaller the threshold voltage deviation ΔV, the easier it is for the brightness to reach the target brightness.

[0036] According to the above description, since the voltage difference between the gate 101 and the source 102 is significantly different from the voltage difference between the gate 101 and the second drain 104, it is an important reason for causing the threshold voltage deviation ΔV. Therefore, in the present application, the driving transistor T0 is divided into two parts, the first driving part T01 and the second driving part T02. The part with a larger voltage difference, which causes the threshold voltage deviation and causes unstable data signal writing, is not connected during the data writing stage, and only the part with a smaller voltage difference is connected, so as to maximize the accuracy of the data writing signal.

[0037] Based on the above analysis, the inventors of the present application found that when the light-emitting element 20 is in the light-emitting stage, when the voltage difference between the voltage of the first drain 103 and the voltage of the gate 101 is less than a certain voltage value V0, 0≤V0≤ΔVgd2×1 / 2, or, 0≤V0≤ΔVsg×1 / 2, that is, when the voltage difference between the first drain 103 and the gate 101 is reduced to half of the voltage difference between the gate 101 and the second drain 104, or half of the voltage difference between the gate 101 and the source 102, the part with a larger electric field strength does not participate in the data writing stage, so as to ensure as much as possible that the expected brightness is reached as soon as possible when the screen is refreshed. Therefore, in this embodiment, the driving transistor T0 is divided into two parts: a first driving part T01 and a second driving part T02. The first driving part T01 is a part between the source 102 and the first drain 103, and the second driving part T02 is a part between the first drain 103 and the second drain 104. The length of the channel region of the first driving part T01 is L1, and the length of the channel region of the second driving part is L2.

[0038] When the voltage difference between the voltage of the first drain 103 and the voltage of the gate 101 is less than a certain voltage value V0, that is, when |Vg-Vd1|≤V0, then Vg-V0≤Vd1≤Vg+V0;

[0039] When the first drive unit is selected to participate in the data writing stage, such as Figure 1 and Figure 2 , when the data writing module 11 is connected to the source 102 and the compensation module 13 is connected between the gate 101 and the first drain 103:

[0040] Because |Vs-Vd1|≈|Vs-Vd2|×L1 / (L1+L2);

[0041] When Vs≥Vd1, (Vs-Vg)-V0=Vs-(Vg+V0)≤Vs-Vd1=|Vs-Vd1|≤Vs-(Vg-V0)=(Vs-Vg)+V0;

[0042] When Vs≤Vd1, (Vg-Vs)-V0=Vg-V0-Vs≤Vd1-Vs=|Vs-Vd1|≤Vg-Vs+V0=(Vg-Vs)+V0;

[0043] Because (Vs-Vg)≤|Vs-Vg|, and (Vg-Vs)≤|Vs-Vg|;

[0044] Therefore, |Vs-Vd1|≤|Vs-Vg|+V0;

[0045] That is |Vs-Vd2|×L1 / (L1+L2)≤|Vs-Vg|+V0;

[0046] It is concluded that: L2 / L1≥|Vs-Vd2| / [|Vs-Vg|+V0]-1=ΔVsd2 / (ΔVsg+V0)-1.

[0047] Through the above calculation, it is known that the lengths of L1 and L2 affect the voltage difference between the first drain 103 and the gate 101. When L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, and 0≤V0≤ΔVgd2×1 / 2, it can be ensured that the voltage difference between the gate 101 and the first drain 103 is less than half of the voltage difference between the gate 102 and the second drain 104, thereby avoiding the problem that the voltage difference between the gate 101 and the second drain 104 is too large, resulting in inaccurate data signal input when the screen is refreshed, and the brightness is difficult to reach the expected brightness.

[0048] Similarly, when the second drive unit is selected to participate in the data writing stage, such as Figure 3 and Figure 4 , when the data writing module 11 is connected to the first drain 103 and the compensation module 13 is connected between the gate 101 and the second drain 104:

[0049] Because |Vd2-Vd1|≈|Vs-Vd2|×L2 / (L1+L2);

[0050] When Vd2 ≥ Vd1,

[0051] (Vd2-Vg)-V0≤Vd2-(Vg+V0)≤Vd2-Vd1=|Vd2-Vd1|≤Vd2-(Vg-V0)=(Vd2-Vg)+V0;

[0052] When Vd2≤Vd1,

[0053] (Vg-Vd2)-V0=(Vg-V0)-Vd2≤Vd1-Vd2=|Vd2-Vd1|≤(Vg+V0)-Vd2=(Vg-Vd2)+V0;

[0054] Because (Vd2-Vg)≤|Vg-Vd2|, and (Vg-Vd2)≤|Vg-Vd2|;

[0055] Therefore, |Vd2-Vd1|≤|Vg-Vd2|+V0;

[0056] That is, |Vs-Vd2|×L2 / (L1+L2)≤|Vg-Vd2|+V0;

[0057] It is concluded that: L1 / L2≥|Vs-Vd2| / [|Vg-Vd2|+V0]-1=ΔVsd2 / (ΔVgd2+V0)-1.

[0058] Through the above calculation, it is known that the lengths of L1 and L2 affect the voltage difference between the first drain 103 and the gate 101. When L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, and 0≤V0≤ΔVsg×1 / 2, it can be ensured that the voltage difference between the gate 101 and the first drain 103 is less than half of the voltage difference between the gate 101 and the source 102, thereby avoiding the problem that the voltage difference between the gate 101 and the source 102 is too large, resulting in inaccurate data signal input when the screen is refreshed, and the brightness is difficult to reach the expected brightness.

[0059] The light-emitting stage of the light-emitting element defined in this embodiment is defined from the perspective of the circuit working mechanism. It does not only include the light emitted by the light-emitting element that can be recognized by the human eye, but also includes a black screen with extremely small driving current and very low brightness, which is also within the scope of the light-emitting stage of the light-emitting element.

[0060] In addition, in the present embodiment, in the pixel circuit 10, the N1 node is connected to the gate 101 of the driving transistor, the N2 node is connected to the source 102 of the driving transistor, the N3 node is connected to the first drain 103 of the driving transistor, and the N4 node is connected to the second drain 104 of the driving transistor. In general, the first driving unit T01 and the second driving unit T02 are two parts of the driving transistor T0, which together constitute the driving transistor T0, that is, the driving transistor T0 is still a complete transistor, the gate 101 and the active layer 102 of the driving transistor T0 are both set as a whole, the first drain 103 is connected to the active layer 105, and is a node drawn from the middle of the driving transistor T0, which is used to connect the compensation module 13, and the connection method of the first drain 103 will be analyzed in detail later. In some special cases, if there is a special need, the gate 101 and the active layer 105 of the driving transistor T0 can also be set in blocks as appropriate, but in general, this application mainly focuses on the solution that the driving transistor T0 is a complete transistor.

[0061] Optionally, in this embodiment, if Figure 1 As shown, the driving transistor T0 is a PMOS transistor, wherein the data writing module 11 is connected to the source 102, the compensation module 13 is connected between the gate 101 and the first drain 103, and L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤ΔVgd2×1 / 2, when the driving transistor T0 is a PMOS transistor, in the light emitting stage, the driving transistor T0 is turned on, and the voltage of the gate 101 is lower than the voltage of the source 102, as shown in FIG. Figure 1In the pixel circuit in, in the light emitting stage, the source voltage Vs of the driving transistor T0 is the PVDD signal, the gate voltage Vg is (Vdata-Vth), and the signal of the second drain voltage Vd2 is generally a relatively low voltage, for example, Vs is 4.6V, Vg is 3V, and Vd2 is -2V. At this time, the problem is that the voltage difference ΔVgd2=|Vg-Vd2| between the gate voltage Vg and the second drain voltage Vd2 is large, such as 5V or even larger, while the voltage difference ΔVsg=|Vg-Vs| between the gate voltage Vg and the source voltage Vs is small, such as 1.5V or even smaller, and generally the source voltage Vs is greater than the gate voltage Vg, and the gate voltage Vg is greater than the drain voltage Vd2. In this case, it will lead to the following Figure 5 The problem shown, Figure 5 The arrows in the middle indicate the density of the electric field lines between the source and the gate, the first drain and the gate, and the second drain and the gate. The magnitude of the electric field strength is only exemplarily represented by the density of the electric field lines. Among them, since the voltage difference between the source voltage Vs and the gate voltage Vg is small, the electric field strength between the source and the gate is small, and the voltage difference between the second drain voltage Vd2 and the gate voltage Vg is large, so the electric field strength between the second drain and the gate is large. As mentioned above, the strong electric field between the second drain and the gate is the main reason for the threshold voltage shift of the driving transistor T0. Therefore, for this type of driving transistor, the first driving unit T01 can be selected to participate in the data writing stage, while the second driving unit T02 does not participate in the data writing stage, thereby fully avoiding the threshold voltage shift of the driving transistor T0 caused by the second driving unit T02, which in turn causes the problem of inaccurate data signal writing when the screen is refreshed. In this case, according to the previous analysis, L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤ΔVgd2×1 / 2. At this time, because ΔVgd2 is large, ΔVgd1 is intercepted to be smaller than ΔVgd2×1 / 2, thereby reducing the voltage difference between the gate 101 and the first drain 103 to within half of the voltage difference between the gate 101 and the second drain 104, so that the second driving unit T02 with a larger voltage difference does not participate in the data writing stage.

[0062] Or, optionally, in this embodiment, as Figure 4 As shown, the driving transistor T0 is an NMOS transistor, wherein the data writing module 11 is connected to the first drain 103, the compensation module 13 is connected between the gate 101 and the second drain 104, and L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVsg×1 / 2, when the driving transistor T0 is an NMOS transistor, in the light emitting stage, the driving transistor T0 is turned on, and the voltage of the gate 101 is higher than the voltage of the source 102, as shown in FIG. Figure 4In the pixel circuit in, in the light emitting stage, the second drain voltage Vd2 of the driving transistor T0 is the PVDD signal, the gate voltage Vg is (Vdata+Vth), and the source voltage Vs is a relatively low voltage. For example, the second drain voltage Vd2 is 4.6V, the gate voltage Vg is 4V, and the source voltage is 1V. At this time, the problem is that the voltage difference ΔVgd2=|Vg-Vd2| between the gate voltage Vg and the second drain voltage Vd2 is small, such as 0.6V or even smaller, and the voltage difference ΔVsg=|Vg-Vs| between the gate voltage Vg and the source voltage Vs is large, such as 3V or even larger. In this case, it will lead to the following Figure 6 The problem shown, Figure 6 The arrows in the middle indicate the density of the electric field lines between the source and the gate, the first drain and the gate, and the second drain and the gate. The magnitude of the electric field strength is only exemplarily represented by the density of the electric field lines. Among them, since the voltage difference between the source voltage Vs and the gate voltage Vg is large, the electric field strength between the source and the gate is large. As mentioned above, the strong electric field between the source and the gate is the main reason for the threshold voltage shift of the driving transistor T0. Therefore, for this type of driving transistor, the second driving unit T02 can be selected to participate in the data writing stage, while the first driving unit T01 does not participate in the data writing stage, thereby fully avoiding the threshold voltage shift of the driving transistor T0 caused by the first driving unit T01, which in turn leads to the problem of inaccurate data signal writing when the screen is refreshed. In this case, according to the previous analysis, L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVsg×1 / 2. At this time, because ΔVsg is large, ΔVgd1 is intercepted to be smaller than ΔVsg×1 / 2, thereby reducing the voltage difference between the gate 101 and the first drain 103 to within half of the voltage difference between the gate 101 and the source 102, so that the first driving unit T01 with a larger voltage difference does not participate in the data writing stage.

[0063] In addition, in some cases, such as Figure 3 As shown, the driving transistor T0 is a PMOS transistor, wherein the data writing module 11 is connected to the first drain 103, the compensation module 13 is connected between the gate 101 and the second drain 104, and L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVsg×1 / 2. In this case, during the light emitting stage, the driving transistor T0 may have a smaller difference between ΔVsg and ΔVgd2, or ΔVsg may be greater than ΔVgd2 due to some special designs. At this time, the electric field between the source and the gate is the main reason for the threshold voltage shift of the driving transistor T0. Therefore, for such a PMOS driving transistor, the second driving unit T02 may be selected to participate in the data writing stage, while the first driving unit T01 may not participate in the data writing stage.

[0064] Or, in some cases, such as Figure 2 As shown, the driving transistor T0 is an NMOS transistor, wherein the data writing module 11 is connected to the source 102, the compensation module 13 is connected between the gate 101 and the first drain 103, and L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤ΔVgd2×1 / 2. In this case, during the light emitting stage, the driving transistor T0 may have a smaller difference between ΔVsg and ΔVgd2, or ΔVgd2 may be greater than ΔVsg due to some special designs. At this time, the electric field between the gate and the second drain is the main reason for the threshold voltage shift of the driving transistor T0. Therefore, for such an NMOS driving transistor, the first driving unit T01 may be selected to participate in the data writing stage, while the second driving unit T02 may not participate in the data writing stage.

[0065] Optionally, in this embodiment, the data writing module 11 is connected to the source 102, the compensation module 13 is connected between the gate 101 and the first drain 103, and L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤ΔVgd2×1 / 2, where ΔVsd2≥ΔVsg+V0. In this connection mode, as described above, it is generally because the voltage difference ΔVgd2 between the gate 101 and the second drain 104 is relatively large, and the voltage difference ΔVsg between the gate 101 and the source 102 is relatively small, and the second driving unit T02 is not connected during the data writing stage. Here, setting ΔVsd2≥ΔVsg+V0 can ensure that L2 / L1≥0. Under this premise, the ratio L2 / L1 can also have other limitations, which will be mentioned later.

[0066] Alternatively, the data writing module 11 is connected to the first drain 103, the compensation module 13 is connected between the gate 101 and the second drain 104, and L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVsg×1 / 2, wherein ΔVsd2≥ΔVgd2+V0. In this connection mode, as described above, it is generally because the voltage difference ΔVsg between the gate 101 and the source 102 is relatively large, while the voltage difference ΔVgd2 between the gate 101 and the second drain 104 is relatively small, and the first driving unit T01 is not connected during the data writing stage. Here, setting ΔVsd2≥ΔVgd2+V0 can ensure that L1 / L2≥0. Under this premise, the ratio L1 / L2 can also have other limitations, which will be mentioned later.

[0067] In this embodiment, optionally, the data writing module 11 is connected to the source 102, the compensation module 13 is connected between the gate 101 and the first drain 103, and L2 / L1≥ΔVsd2 / V0-1, 0≤V0≤ΔVgd2×1 / 2; because in the display panel, different light-emitting elements 20 have different requirements for the light-emitting current when emitting light, and the gate potential Vg of the driving transistor T0 of the pixel circuit in the same display panel may be different during the light-emitting stage, and based on the limitation of the process, in order to fully simplify the process, it is generally expected to unify the pixel circuits in the same panel during production, and the overall structure of the driving transistors of different pixel circuits is basically the same. When the Vg requirements are different but the basic structure requirements of the driving transistor are basically the same, the formula L2 / L1≥ΔV sd2 / (ΔVsg+V0)-1 has been further improved for universalization. For PMOS transistors, under this connection mode, the source voltage Vs is generally a PVDD signal, which is a high voltage signal. The gate voltage Vg is generally lower than the source voltage Vs. When Vg is closer to Vs, the driving current is smaller. When Vg≈Vs, a black screen is basically presented, which is reflected in the formula as ΔVsg≥0, ΔVsg+V0≥V0, ΔVsd2 / (ΔVsg+V0)≤ΔVsd2 / V0. Here, the limit case of Vg≈Vs is taken as the standard, and L2 / L1≥ΔVsd2 / V0-1≥ΔVsd2 / (ΔVsg+V0)-1 is limited. In this case, for other cases of Vg≤Vs, the range of L2 / L1 is generally satisfied. For NMOS transistors, the reason is similar. In order to simplify the process and unify the design of driving transistors, Vg is generally greater than Vs. When Vg≈Vs, a black screen is basically displayed. Here, the limit case of Vg≈Vs is taken as the standard, and L2 / L1≥ΔVsd2 / V0-1≥ΔVsd2 / (ΔVsg+V0)-1 is defined. In this case, for other cases where Vg≤Vs, the range of L2 / L1 is generally satisfied. It should be noted that 0≤V0≤ΔVgd2×1 / 2 is defined here, because Vg and Vd2 may be two variables in actual situations, and ΔVgd2 is also a variable. In specific implementation, in order to unify the design of pixel circuits in the same display panel, V0 can be set to a certain value with a smaller value, so that most or all cases fall into the above range as much as possible, which is convenient for the unified design of the panel. The value of V0 will be further introduced later.

[0068] Alternatively, in this embodiment, optionally, the data writing module 11 is connected to the first drain 103, the compensation module 13 is connected between the gate 101 and the second drain 104, and L1 / L2≥ΔVsd2 / V0-1, 0≤V0≤ΔVsg×1 / 2; similar to the above reasons, in order to simplify the process, when selecting L1 / L2, in order to consider the unified design of the driving transistors in the same display panel, the limit value ΔVgd2=0 is taken, and L1 / L2≥ΔVsd2 / V0-1≥ΔVsd2 / (ΔVgd2+V0)-1 is obtained, so that the unified design of the driving transistors in the panel can be realized. At this time, V0 can also be set to a certain value with a smaller value, so that most or all situations fall into the above range as much as possible, which is convenient for the unified design of the panel. The value of V0 will be further introduced later.

[0069] Optionally, in this embodiment, the data writing module 11 is connected to the source 102 , the compensation module 13 is connected between the gate 101 and the first drain 103 , and L2 / L1 ≥ 0.5. As mentioned above, in this connection mode, L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤ΔVgd2×1 / 2, and this connection mode is mostly selected when ΔVgd2≥ΔVsg, because for PMOS transistors, Vd2≤Vg≤Vs, or, for NMOS transistors, Vs≤Vg≤Vd2, then ΔVsd2=ΔVsg+ΔVgd2, and the inventors of the present application found that when ΔVsg≤ΔVgd2≤2×ΔVsg, ΔVsg≥1 / 3×ΔVsd2, for example, Vs is 4.6V, Vd2 is -2V, ΔVsg≥1 / 3×6.6V=2.2V, ΔV gd2≤2 / 3×6.6V=4.4V. In this case, the voltage difference between ΔVsg and Vsd2 is about 2V. The inventors of the present application have found that when the voltage difference between the two is within this range, the electric field strength between the gate 101 and the second drain 104 is still relatively small to a certain extent, and will not cause too much threshold voltage shift. When ΔVgd2≥2×ΔVsg, that is, ΔVgd2≥2 / 3×ΔVsd2, the voltage difference between ΔVgd2 and ΔVsg is more obvious, which will cause a more obvious threshold voltage shift. In order to avoid this phenomenon, in this embodiment, the partial area of ​​ΔVgd2≥2×ΔVsg is not involved in the data writing stage. At this time,

[0070] ΔVsg≤1 / 3×ΔVsd2, ΔVgd2≥2 / 3×ΔVsd2;

[0071] Further define V0≤2 / 3×ΔVsd2×1 / 2≤ΔVgd2×1 / 2;

[0072] Then ΔVsg+V0≤1 / 3×ΔVsd2+2 / 3×ΔVsd2×1 / 2=2 / 3×ΔVsd2;

[0073] It is concluded that L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1≥Vsd2 / (2 / 3×ΔVsd2)-1=0.5.

[0074] In this case, when the voltage difference between the gate voltage and the second drain voltage is large, the portion with a significantly larger voltage difference does not participate in the data writing phase, thereby facilitating the offset of the threshold voltage of the driving transistor.

[0075] Alternatively, in this embodiment, the data writing module 11 is connected to the first drain 103 , the compensation module 13 is connected between the gate 101 and the second drain 104 , and L1 / L2 ≥ 0.5. Similar to the above reasons, in this connection mode, L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVsg×1 / 2, and this connection mode is mostly selected when ΔVsg≥ΔVgd2, because for PMOS transistors, Vd2≤Vg≤Vs, or, for NMOS transistors, Vs≤Vg≤Vd2, then ΔVsd2=ΔVsg+ΔVgd2, and the inventors of the present application found that when ΔVgd2≤ΔVsg≤2×ΔVgd2, ΔVgd2≥1 / 3×ΔVsd2, for example, Vs is -2V, Vd2 is 4.6V, ΔVgd2≥1 / 3×6.6V=2.2 V, ΔVsg≤2 / 3×6.6V=4.4V. In this case, the voltage difference between ΔVsg and Vsd2 is about 2V. The inventors of the present application have found that when the voltage difference between the two is within this range, the electric field strength between the gate 101 and the source 102 is still relatively small to a certain extent, and will not cause too much threshold voltage shift. When ΔVsg≥2×ΔVgd2, that is, ΔVsg≥2 / 3×ΔVsd2, the voltage difference between ΔVsg and ΔVgd2 is more obvious, which will cause a more obvious threshold voltage shift. In order to avoid this phenomenon, in this embodiment, the partial area of ​​ΔVsg≥2×ΔVgd2 is not involved in the data writing stage. At this time,

[0076] ΔVgd2≤1 / 3×ΔVsd2, ΔVsg≥2 / 3×ΔVsd2;

[0077] Further define V0≤2 / 3×ΔVsd2×1 / 2≤ΔVsg×1 / 2;

[0078] Then ΔVgd2+V0≤1 / 3×ΔVsd2+2 / 3×ΔVsd2×1 / 2=2 / 3×ΔVsd2;

[0079] It is concluded that L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1≥Vsd2 / (2 / 3×ΔVsd2)-1=0.5.

[0080] In this case, when the voltage difference between the gate voltage and the source voltage is large, the portion with a significantly larger voltage difference does not participate in the data writing phase, thereby facilitating the offset of the threshold voltage of the driving transistor.

[0081] In addition, optionally, as further described above, in order to make the display panel uniformly manufactured for the driving transistor and simplify the process, it is concluded that the data writing module 11 is connected to the source 102, the compensation module 13 is connected between the gate 101 and the first drain 103, and L2 / L1≥ΔVsd2 / V0-1, 0≤V0≤ΔVgd2×1 / 2. Combined with the previous content, in the case of V0≤2 / 3×ΔVsd2×1 / 2=1 / 3×ΔVsd2, ΔVsd2 / V0≥ΔVsd2 / (1 / 3×ΔVsd2)=3, L2 / L1≥ΔVsd2 / V0-1≥2. This situation can make the part of the driving transistor with a significantly larger voltage difference not participate in the data writing stage, while being conducive to the unified design of the panel and can better simplify the process. For specific reasons, please refer to the description above.

[0082] Or, optionally, further as described above, in order to make the display panel uniformly manufactured driving transistors and simplify the process, it is concluded that the data writing module 11 is connected to the first drain 103, the compensation module 13 is connected between the gate 101 and the second drain 104, and L1 / L2≥ΔVsd2 / V0-1, 0≤V0≤ΔVsg×1 / 2. Combined with the previous content, in the case of V0≤2 / 3×ΔVsd2×1 / 2=1 / 3×ΔVsd2, ΔVsd2 / V0≥ΔVsd2 / (1 / 3×ΔVsd2)=3, L1 / L2≥ΔVsd2 / V0-1≥2. This situation makes the part with a significantly larger voltage difference of the driving transistor not participate in the data writing stage, which is conducive to the unified design of the panel and can better simplify the process. The specific reasons are described in the above.

[0083] In addition, optionally, in the present embodiment, in order to ensure that the voltage difference ΔVgd1 between the gate voltage Vg and the first drain voltage Vd1 is further reduced, the range of V0 can be further narrowed. Here, V0≤ΔVgd2×1 / 3, or V0≤ΔVsg×1 / 3, is limited to fully reduce the voltage difference ΔVgd1 between the gate voltage Vg and the first drain voltage Vd1, thereby ensuring the accuracy of data signal writing when the screen is refreshed as much as possible.

[0084] Furthermore, the inventor of the present application discovered that Figure 1-Figure 4For the pixel circuit in, the voltage difference ΔVgd1 between the gate 101 and the first drain 103 is generally set within 2V, so the voltage difference between them is small, the electric field strength is weak, and it will not cause great interference to the data signal when the screen is refreshed. Therefore, in this embodiment, 0≤V0≤2V is set to ensure that ΔVgd1 is within a smaller voltage range, thereby improving the accuracy of data signal writing when the screen is refreshed and ensuring the display effect. Under this premise, V0 can also be further narrowed to 0≤V0≤1.5V, 0≤V0≤1V, 0≤V0≤0.5V, etc. Specifically, V0 can be one of 2V, 1.8V, 1.5V, 1.2V, 1.0V, 0.8V, 0.6V, 0.4V, 0.2V, 0V, etc. In the specific use process, a reasonable V0 value can be selected according to the specific situation.

[0085] refer to Figure 8-Figure 10 , Figure 8 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application. Fig. 9 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application. Fig.10It is a cross-sectional schematic diagram of another driving transistor provided in an embodiment of the present application, wherein the source node 102 of the driving transistor T0 includes a first source 1021 and a second source 1022, a third driving unit T03 is included between the first source 1021 and the second source 1022, a data writing module 11 is connected to the second source 1022, and a compensation module 13 is connected between the gate 101 and the first drain 103. In the aforementioned embodiments, the processing method when one of ΔVsg and ΔVgd2 is greater than the other and the voltage difference is large to a certain extent is shown. On this basis, the present embodiment further considers that the driving transistor satisfies the condition: the voltage difference ΔVs2g between the second source 1021 and the gate 101 = |Vs2-Vg|≤V0, or satisfies the condition: the voltage difference ΔVgd1 between the first drain 103 and the gate 101 = |Vg-Vd1|≤V0, or both of these conditions are met, and then the first driving unit T01 participates in the data writing stage, while the second driving unit T02 and the third driving unit T03 that may produce a large voltage difference do not participate in the data writing stage, so that the first driving unit T01 has a smaller voltage difference, thereby improving the accuracy of data signal writing as much as possible and avoiding brightness flickering during the screen refresh process. At this time, according to the previous analysis, if ΔVs2g≤V0 is required, then L3 / (L1+L2)≥ΔVs1d2 / (ΔVgd2+V0)-1, 0≤V0≤ΔVs1g×1 / 2, where ΔVs1d2=|Vs1-Vd2|. At this time, consider the L1+L2 part as one part, and then according to the analysis process above, we can get this formula. If ΔVgd1≤V0 is required, then L2 / (L1+L3)≥ΔVs1d2 / (ΔVs1g+V0)-1, 0≤V0≤ΔVgd2×1 / 2, where ΔVs1d2=|Vs1-Vd2|, ΔVs1g=|Vs1-Vg|. At this time, consider the L3+L1 part as one part, and then according to the analysis process above, we can get this formula. It should be noted that Fig.10 The intensity of the electric field and the density of the electric field lines are only shown as examples, and the direction of the arrows can be adjusted according to specific circumstances.

[0086] Optionally, based on the above description, when ΔVs2g≤V1 and ΔVgd1≤V1, the above conditions need to be met at the same time, then it can be concluded that L3 / (L1+L2)≥ΔVs1d2 / (ΔVgd2+V1)-1, and L2 / (L1+L3)≥ΔVs1d2 / (ΔVs1g+V1)-1, where V1 is set to a certain value to facilitate the unified definition of ΔVs2g and ΔVgd1. According to the above description, the inventors of the present application found that when 0≤V1≤2V, a large voltage difference can be avoided between the gate 101 and the second source 1022, and between the gate 101 and the first drain 103, so that the threshold voltage of the first driving unit T01 is sufficiently stable, thereby fully avoiding the flickering problem when the screen is refreshed. Under this premise, V1 can also be further narrowed to 0≤V1≤1.5V, 0≤V1≤1V, 0≤V1≤0.5V, etc. Specifically, V1 can be one of 2V, 1.8V, 1.5V, 1.2V, 1.0V, 0.8V, 0.6V, 0.4V, 0.2V, 0V, etc. In specific use, a reasonable V1 value can be selected according to the specific situation.

[0087] So far, the above description is about the relationship between the lengths of the channel regions and the related voltage differences among the first driving part T01, the second driving part T02 and the third driving part T03. Hereinafter, the structure of the driving transistor T0 after being arranged as above will be described.

[0088] refer to Fig.11 , Fig.11 1 is a schematic diagram of a top view structure of a driving transistor provided by an embodiment of the present application, wherein the channel region 106 of the active layer 105 of the driving transistor T0 includes a first section 1061 and a second section 1062, and a first point 200 located between the first section 1061 and the second section 1062, the first drain 103 is connected to the first point 200, the first section 1061 is located in the first driving part T01, and the second section 1062 is located in the second driving part T02; the gate 101 includes a first side surface 1011, and the first side surface 1011 is the side surface of the gate 101 closest to the first point 200; wherein, in the first section 1061, at least a part of the region is at a distance from the first side surface 1011 of the gate 101 greater than a distance from the first point 200 to the first side surface 1011; or in the second section 1062, at least a part of the region is at a distance from the first side surface 1011 of the gate 101 greater than a distance from the first point 200 to the first side surface 1011.

[0089] In the present application, the setting of the first drain 103 needs to consider ΔVgd1, and ΔVgd1 is related to the ratio of L1 and L2, that is, the change of L1 or L2 will cause the change of ΔVgd1. As described above, L1 and L2 are designed according to certain requirements. Therefore, in order to avoid unnecessary voltage changes when the first node 200 is connected to the first drain 103, the length of the channel region between the first node 200 and the first drain 102 needs to be small enough, and even no channel region is required between the two. In this case, the first node 200 needs to extend out of at least one side of the gate 101, or at least extend to a side very close to the gate 101, and this side is defined as The first side surface 1011 is provided. At this time, the distance between the first point 200 and the first side surface 1011 is 0, or is small enough to facilitate connection with the first drain 103. The first point 200 is located between the first section 1061 and the second section 1062. The first section 1061 and the second section 1062 need to have respective lengths L1 and L2, and the channel region 106 must overlap with the gate. Therefore, in order to ensure L1 and L2, at least one of the first section 1061 and the second section 1062 needs to be detoured from the first side surface 1011, and after passing through the lengths L1 and L2, it is detoured out of the coverage of the gate 101. In particular, in order to consider the process factors, when the gate 101 is made into a rectangle, this design is very necessary. Fig.11 What is shown is a situation where the distance between the second section 1062 and the first side 1011 in at least a partial area is greater than the distance between the first point 200 and the first side 1011. In other embodiments, the first section 1061 may also be set to have a situation where the distance between the first section 1061 and the first side 1011 in at least a partial area is greater than the distance between the first point 200 and the first side 1011.

[0090] In addition, optionally, in the present embodiment, the gate 101 also includes a second side 1012, the second side 1011 is connected to the second side 1012, the first side 1011 and the second side 1012 are the two sides of the gate 101 closest to the first point 200; wherein, in the first section 1061, at least a partial area has a distance from the first side 1011 of the gate 101 greater than the distance between the first point 200 and the first side 1011; and / or, in the second section 1062, at least a partial area has a distance from the second side 1062 of the gate 101 greater than the distance between the first point 200 and the second side 1062.

[0091] like Fig.11As shown, the first side surface 1061 and the second side surface 1062 are the two sides of the gate 101 that are closest to the first point 200. As mentioned above, in order to ensure the accuracy of the voltage of the first drain 103, the first point 200 needs to be close enough to the side surface of the gate 101 to facilitate the extraction of the first drain 103. However, on the other hand, the lengths of the first section 1061 and the second section 1062 also need to be ensured. Therefore, at least one of the first section 1061 and the second section 1062 may need to be bypassed, or both may need to be bypassed. Therefore, the distance between at least a part of the first section 1061 and the first side surface 1061 is greater than the distance between the first point 200 and the first side surface 1061, and / or, the distance between at least a part of the second section 1062 and the second side surface 1062 of the gate 101 is greater than the distance between the first point 200 and the second side surface 1062.

[0092] Additionally, optionally, refer to Fig.12 , Fig.12 It is a schematic diagram of a top view structure of another driving transistor provided in an embodiment of the present application, wherein the first point 200 and the gate 101 do not overlap with each other. In this case, the first point 200 does not constitute part of the channel region, and is connected to the first drain 103 after extension, which has little effect on the voltage of the first drain 103, which is beneficial to the division of the first driving unit T01 and the second driving unit T02 according to voltage in the present application.

[0093] Optional, such as Fig.11As shown, the first point 200 and the gate 101 at least partially overlap each other, and an auxiliary channel region 201 is included between the first point 200 and the first drain 103. The length of the auxiliary channel region 201 is L0, 0≤L0≤V0×(L1+L2) / (10×Vsd2). In the present embodiment, as described above, the voltage value of the first drain 103 is obtained through comprehensive calculation. Therefore, it is required that the voltage loss when the first point 200 is connected to the first drain 103 is as small as possible. If the first point 200 is set on the outside of the gate 101, that is, the first point 200 and the gate 101 do not overlap, it will cause the combined area of ​​the active layer 105 and the gate 101 on the panel to increase, which is not conducive to improving the PPI of the panel. Therefore, in some cases, the first point 200 is set to at least partially overlap with the gate to save the total area occupied by the active layer 105 and the gate 101. In this case, in order to avoid the voltage loss caused by passing through the auxiliary channel region 201 when the first point 200 is connected to the first drain 103, it is necessary to reduce the length of the auxiliary channel region 201 as much as possible. According to the above calculation, in the light-emitting stage, the voltage of the first point 200 is Vd1, which is transmitted to the first point 200. When the error generated is set to ΔV1, the voltage of the first drain 103 can be Vd1'=Vd1±ΔV1. The main limitation in this application is ΔVgd1≤V0. In order to ensure the voltage of the first drain 103, ΔVgd1'≤V0 is also required, that is, |Vg-Vd1±ΔV1|≤V0, ΔVgd1±ΔV1≤V0. The inventor of this application found that when ΔV1 / V0≤1 / 10, that is, ΔV 1 is at least within the range of 1 / 10 times of V0, the auxiliary channel region 201 has little effect on the voltage of the first drain 103. On this basis, it can be further defined that ΔV1 / V0≤1 / 10, ΔV1 / V0≤1 / 15, ΔV1 / V0≤1 / 20, ΔV1 / V0≤1 / 30, etc., so as to fully ensure the accuracy of the voltage of the first drain 103 and ensure that the voltage between the gate 101 and the first drain 103 is less than V0. At this time,

[0094] Because L0 / L1≈ΔV1 / ΔVsd1, ΔV1 / ΔVsd1≤V0×1 / 10 / ΔVsd1;

[0095] Then L0 / L1≤V0×1 / 10 / ΔVsd1, and ΔVsd1≈ΔVsd2×L1 / (L1+L2);

[0096] Then L0 / L1≤V0×1 / 10×(L1+L2) / L1 / ΔVsd2;

[0097] Then 0≤L0≤V0×(L1+L2) / (10×Vsd2).

[0098] When L0 meets this condition, the influence of the auxiliary channel region 201 on the voltage of the first drain 103 and on ΔVgd1 can be avoided as much as possible. On this basis, as shown above, it can also be concluded that 0≤L0≤V0×(L1+L2) / (15×Vsd2), 0≤L0≤V0×(L1+L2) / (20×Vsd2) and 0≤L0≤V0×(L1+L2) / (30×Vsd2), etc., and the specific situation depends on specific needs.

[0099] In addition, referring to the above definition: V0≤2 / 3×ΔVsd2×1 / 2=1 / 3×ΔVsd2;

[0100] Combined with the above: 0≤L0≤V0×(L1+L2) / (10×Vsd2), we can conclude that:

[0101] 0≤L0≤(L1+L2) / 30.

[0102] Therefore, the accuracy of the first drain 103 and ΔVgd1 is fully guaranteed.

[0103] In addition, in this embodiment, optionally, reference Fig.11 and Fig.12 , the data writing module 11 is connected to the source 102, the compensation module 13 is connected between the gate 101 and the first drain 103, and the width of the channel region of the first driving part T01 is smaller than the width of the channel region of the second driving part T02; or,

[0104] The data writing module 11 is connected to the first drain 103 , the compensation module 13 is connected between the gate 101 and the second drain 104 , and the width of the channel region of the first driving part T01 is greater than the width of the channel region of the second driving part T02 .

[0105] The above definition is that the width of the channel region of the part participating in the data writing stage is less than the width of the channel region of the part not participating in the data writing stage. The inventor of the present application found that when the length and electric field strength of the channel region are constant, the larger the width of the channel region, the larger the area, so that the electric field strength per unit area is smaller, that is, the electric field density is smaller. Combined with the analysis above, the threshold voltage drift of the driving transistor is related to the electric field strength per unit area to some extent. When the electric field strength between the gate and the second drain or the gate and the source is large, the drift of the threshold voltage is also more serious. Therefore, in this embodiment, the channel region of the driving part that does not participate in the data writing stage is appropriately widened, which is conducive to reducing the offset of the threshold voltage. Therefore, when the first driving part T01 participates in the data writing stage and the second driving part T02 does not participate in the data writing stage, the width of the channel region of the second driving part T02 can be appropriately widened; and when the first driving part T01 does not participate in the data writing stage and the second driving part T02 participates in the data writing stage, the width of the channel region of the first driving part T01 can be appropriately widened.

[0106] refer to Figure 1-Figure 12 In this embodiment, one end of the data writing module 11 is connected to the data signal end for receiving the data signal Vdata, the other end is connected to the driving module 12, and the control end is connected to the first scanning signal line S1 for receiving the first scanning signal; one end of the compensation module 13 is connected to the gate 101 of the driving transistor T0, the other end is connected to the first drain 103 or the second drain 104 of the driving transistor T0, and the control end is connected to the second scanning signal line S2 for receiving the second scanning signal. Optionally, the data writing module 11 may include a first transistor T1, the source of the first transistor T1 is connected to the data signal end, the drain is connected to the driving transistor T0, and the gate is connected to the first scanning signal line S1.

[0107] In addition, in the present embodiment, the pixel circuit further includes a light emitting control module 14, which is used to selectively allow the light emitting element 20 to enter the light emitting stage; the light emitting control module 14 includes a first light emitting control module 141 and a second light emitting control module 142, one end of the first light emitting control module 141 is connected to the first power signal end for receiving the first power signal PVDD, the other end is connected to the driving module 12, and the control end is connected to the light emitting control signal line for receiving the light emitting control signal EM; one end of the second light emitting control module 142 is connected to the driving module 12, the other end is connected to the light emitting element 20, and the control end is connected to the light emitting control signal line for receiving the light emitting control signal EM. Here, the light emitting control signal EM is a general term, and in some embodiments, the light emitting control signal EM received by the first light emitting module 141 and the light emitting control signal EM received by the second light emitting module 142 may be the same, and in other embodiments, the light emitting control signal EM received by the first light emitting module 141 and the light emitting control signal EM received by the second light emitting module 142 may also be different. The first light-emitting control module 141 may include a third transistor T3, the source of the third transistor T3 is connected to the first power signal terminal, the drain is connected to the driving transistor T0, and the gate is connected to the light-emitting control signal line; the second light-emitting module 142 may include a fourth transistor T4, the source of the fourth transistor T4 can be connected to the driving transistor T0, the drain can be connected to the light-emitting element 20, and the gate can be connected to the light-emitting control signal line.

[0108] In the data writing stage, the first scanning signal S1 controls the data writing module 11 to turn on, and the data signal Vdata is written into the source 102 (N2 node) of the driving transistor T0 through the data writing module 11, the driving transistor T0 is turned on, and the data signal Vdata is written into the first drain 103 (N3 node) through the first driving unit T01, and the second scanning signal S2 controls the compensation module 13 to turn on, and the data signal Vdata is written into the gate 101 (N1 node) of the driving transistor T0 through the compensation module 13; in the light emitting stage of the light emitting element 20, the light emitting control signal EM controls the light emitting module 14 to turn on, the driving transistor T0 is turned on, the driving transistor T0 generates a driving current, and controls the light emitting element 20 to emit light.

[0109] In addition, if Figure 1-Figure 12As shown, in this embodiment, the pixel circuit 10 further includes an initialization module 15 and a reset module 16, one end of the initialization module 15 is connected to the initialization signal end for receiving the initialization signal Vini, the other end is connected to the light emitting element 20, and the control end is connected to the fourth scanning line S4 for receiving the fourth scanning signal, and the initialization signal 15 is used to provide the initialization signal Vini to the light emitting element 20 in the initialization stage, so as to initialize the voltage of the light emitting element 20. The initialization module 15 may include a fifth transistor T5, the source of the fifth transistor T5 is connected to the initialization signal end, the drain is connected to the light emitting element 20, and the gate is connected to the fourth scanning signal line S4.

[0110] The connection mode of the reset module 16 can be as follows Figure 1 As shown, one end is connected to the reset signal end for receiving the reset signal Vref, the other end is connected to the gate 101 (N1 node) of the driving transistor T0, and the control end is connected to the third scanning signal line S3 for receiving the third scanning signal. In the reset stage, the third scanning signal line S3 controls the reset module 16 to turn on, and the reset module 16 provides a reset signal to the gate 101 of the driving transistor T0. The reset module 16 may include a sixth transistor T6, the source of the sixth transistor T6 is connected to the reset signal end, the drain is connected to the gate of the driving transistor T0, and the gate is connected to the second scanning signal line S2. The connection method of the reset module 16 can also be as follows Figure 2 As shown, one end is connected to the reset signal end for receiving the reset signal Vref, the other end is connected to the first drain 103 (N3) node, the control end is connected to the third scan signal line S3 for receiving the third scan signal, in the reset stage, the third scan signal line S3 controls the reset module 16 to turn on, the second scan signal line S2 controls the compensation module 13 to turn on, and the reset signal Vref is written into the gate of the driving transistor T0 for reset. At this time, the source of the sixth transistor T6 is connected to the reset signal end, the drain is connected to the first drain 103 (N3) node of the driving transistor, and the gate is connected to the third scan signal line S3.

[0111] Optional, reference Fig.13 and Fig.14 , Fig.13 is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application. Fig.14This is a schematic diagram of a pixel circuit of another display panel provided in an embodiment of the present application, wherein the pixel circuit 10 includes a bias adjustment module 17, one end of the bias adjustment module 17 is connected to the bias adjustment signal end for receiving the bias adjustment signal, the other end is connected to the second drain 104 (N4 node) of the driving transistor T0, and the control end is connected to the bias control signal line S5 for receiving the bias control signal; the working process of the pixel circuit includes a bias adjustment stage, in the bias adjustment stage, the bias adjustment module 17 is turned on, the compensation module 13 is turned off, and the bias adjustment signal is transmitted to the second drain of the driving transistor T0. Because in the light-emitting stage, the voltage difference between the voltage of the second drain and the voltage of the gate may be large, resulting in a large electric field strength of the second driving unit. In this embodiment, in order to further improve this problem, a bias adjustment module 17 is connected to the second drain 104. The bias adjustment module 17 is used to provide a bias adjustment signal to the second drain 104 in the bias adjustment stage, reduce the voltage difference between the second drain and the gate, or reverse the direction of the electric field between the second drain and the gate, thereby offsetting the problem of threshold voltage drift of the driving transistor caused by the electric field problem between the gate and the second drain in the light-emitting stage.

[0112] Optionally, the bias adjustment module 17 may include a seventh transistor T7, wherein the source of the first transistor T7 is connected to the bias adjustment signal terminal, the drain is connected to the second drain 104 (node ​​N4) of the driving transistor T0, and the gate is connected to the bias control signal line S5.

[0113] Optional, such as Fig.13 As shown, the driving transistor T0 is a PMOS transistor, and the bias adjustment signal is a constant high voltage signal VH. Because when the driving transistor is a PMOS transistor, in the light-emitting stage, the source voltage of the driving transistor is generally higher, followed by the gate, and then the second drain. The voltage of the second drain is usually lower. In order to offset the threshold voltage offset problem caused by the lower voltage of the second drain, the bias adjustment signal can be set to a constant high voltage signal VH, so that in the bias adjustment stage, the electric field strength between the second drain and the gate can be adjusted or even offset as quickly as possible. Fig.14 As shown, the driving transistor T0 is an NMOS transistor, and the bias adjustment signal is a constant low voltage signal VL. Because when the driving transistor is an NMOS transistor, in the light-emitting stage, the source voltage of the driving transistor is generally low, followed by the gate, and then the second drain. The voltage of the second drain is usually high. In order to offset the threshold voltage offset problem caused by the high voltage of the second drain, the bias adjustment signal can be set to a constant low voltage signal VL, so that in the bias adjustment stage, the electric field strength between the second drain and the gate can be adjusted or even offset as quickly as possible.

[0114] Another aspect of the present application provides another display panel, wherein the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a data writing module 11, a driving module 12 and a compensation module 13; the data writing module 11 is used to selectively provide a data signal to the driving module 12; the driving module 12 is used to provide a driving current to the light-emitting element 20, and the driving module 12 includes a driving transistor T0; the compensation module 13 is used to compensate for the threshold voltage of the driving transistor T0; the driving transistor T0 includes a source 102, a gate 101, an active layer 105 and a first drain 1 03 and the second drain 104, a first driving unit T01 is included between the source 102 and the first drain 103, a second driving unit T02 is included between the first drain 103 and the second drain 104, the length of the channel region of the first driving unit T01 is L1, and the length of the channel region of the second driving unit T02 is L2; ​​the data writing module 11 is connected to the source 102, and the compensation module 13 is connected between the gate 101 and the first drain 103, or the data writing module 11 is connected to the first drain 103, and the compensation module 13 is connected between the gate 101 and the second drain 104; wherein,

[0115] L2 / L1≥ΔVsd2 / (ΔVsg+V0)-1, 0≤V0≤2V, or,

[0116] L1 / L2≥ΔVsd2 / (ΔVgd2+V0)-1, 0≤V0≤2V;

[0117] In the formula, ΔVsd2=|Vs-Vd2|, ΔVsg=|Vs-Vg|, ΔVgd2=|Vg-Vd2|, in the light-emitting stage of the light-emitting element, Vs is the voltage of the source of the driving transistor, Vd2 is the voltage of the second drain of the driving transistor, and Vg is the voltage of the gate of the driving transistor.

[0118] In this embodiment, it is limited to 0≤V0≤2V, that is, for the pixel circuit in this application, when 0≤ΔVgd1≤2V, the electric field strength between the gate 101 and the first drain 103 can be basically reduced to a certain extent, so that the threshold voltage deviation ΔV of the driving transistor T0 caused by it can be controlled within 100mV as much as possible, thereby avoiding the threshold voltage offset from having a greater impact on the data writing stage and avoiding the flicker problem.

[0119] Under this premise, V0 can also be further narrowed to 0≤V0≤1.5V, 0≤V0≤1V, 0≤V0≤0.5V, etc. Specifically, V0 can be one of 2V, 1.8V, 1.5V, 1.2V, 1.0V, 0.8V, 0.6V, 0.4V, 0.2V, 0V, etc. In specific use, a reasonable V0 value can be selected according to the specific situation.

[0120] In addition, other implementations can refer to the implementations mentioned above, and can all be applied here, and will not be repeated here.

[0121] Another aspect of the present application provides a display device, referring to Fig.15 , Fig.15 It is a schematic diagram of a display device provided in an embodiment of the present application, wherein the display device 2 displays a panel 1, and the display panel 1 includes the display panels described in all the aforementioned embodiments. The display device 2 can be one of a variety of display devices such as a television, a notebook, a mobile phone, a smart wearable display device, etc., and this embodiment does not make any special limitation on this.

[0122] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Pixel circuit and light emitting element; The pixel circuit includes a driving module, and the driving module includes a driving transistor; The driving transistor includes a source, a gate, an active layer, a first drain and a second drain, a first driving unit is included between the source and the first drain, and a second driving unit is included between the first drain and the second drain; wherein, The channel region of the active layer includes a first segment and a second segment, and a first point located between the first segment and the second segment, the first drain is connected to the first point, the first segment is located in the first driving part, and the second segment is located in the second driving part; wherein, The gate includes a first side, the first side being the side of the gate closest to the first position; the first section and / or the second section needs to be detoured, wherein, In the first section, at least a part of the region is at a distance from the first side surface of the gate that is greater than a distance between the first site and the first side surface; and / or, In the second section, at least a portion of the region is at a distance from the first side surface of the gate that is greater than a distance between the first site and the first side surface.

2. The display panel according to claim 1, characterized in that: The gate further includes a second side surface, the second side surface is connected to the first side surface, and the first side surface and the second side surface are two sides of the gate closest to the first position; wherein, In the first section, at least a part of the region is at a distance from the second side of the gate that is greater than a distance between the first site and the second side; and / or, In the second section, at least a part of the region is at a distance from the second side surface of the gate that is greater than a distance between the first site and the second side surface.

3. The display panel according to claim 1, characterized in that: The first site does not overlap with the gate.

4. The display panel according to claim 1, characterized in that: The first site and the gate at least partially overlap each other.

5. The display panel according to claim 1, characterized in that: The pixel circuit includes a data writing module and a compensation module; The data writing module is connected to the source of the driving transistor, and the compensation module is connected between the gate and the first drain of the driving transistor; or, The data writing module is connected to the first drain of the driving transistor, and the compensation module is connected between the gate and the second drain of the driving transistor.

6. The display panel according to claim 1, characterized in that: The length of the channel region of the first driving part is L1, and the length of the channel region of the second driving part is L2; An auxiliary channel region is included between the first site and the first drain, and a length of the auxiliary channel region is L0, wherein 0≤L0≤(L1+L2) / 30.

7. The display panel according to claim 1, characterized in that: The driving transistor is a PMOS transistor or an NMOS transistor.

8. A display device, characterized in that: A display panel comprising any one of claims 1 to 7.

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