A signal processing circuit and method for improving AD resolution

Abstract

The application provides a signal processing circuit and method for improving AD resolution, which comprises a signal processing unit connected between a sensor and an AD analog-digital converter, the unit being a four-pole operational amplifier circuit composed of four operational amplifiers, the non-inverting input terminals of the first, second, third and fourth operational amplifiers are connected to Ui, the inverting input terminal of the first operational amplifier is connected to 3 / 4Ur, the first inverting input terminal of the second operational amplifier is connected to 1 / 2Ur, the second inverting input terminal of the second operational amplifier is connected to node b, the first inverting input terminal of the third operational amplifier is connected to 1 / 4Ur, the second inverting input terminal of the third operational amplifier is connected to node d, the third inverting input terminal of the third operational amplifier is connected to node c, the first inverting input terminal of the fourth operational amplifier is connected to node e, the second inverting input terminal of the fourth operational amplifier is connected to node d, and the third inverting input terminal of the fourth operational amplifier is connected to node c. The application solves the problems of low tube conversion rate, high cost and tight supply in the prior art, realizes high-resolution and high-precision AD sampling, and reduces the cost.

Description

Technical Field

[0001] This invention relates to the field of electronic power technology, and more specifically to a signal processing circuit for improving AD resolution and a method for applying the circuit. Background Technology

[0002] In intelligent systems that process analog signals, analog signals must first be converted into digital signals, thus requiring analog-to-digital converters (ADCs). Currently, high-speed, high-resolution ADCs are expensive and in short supply. Furthermore, these converters are almost monopolized by a few foreign companies, resulting in order cycles of a year or even longer, causing significant inconvenience for users.

[0003] like Figure 1 As shown, a signal with a peak value of Umax is typically amplified N times by an operational amplifier to reach full scale before undergoing AD conversion via the first channel of a 16-bit analog-to-digital converter (ADC). It is then processed by an unprocessed unit. With increasing bit depth of the selected ADC chip, not only does the conversion rate decrease, but the cost also increases significantly.

[0004] Currently, multi-channel low-resolution converters are not only mature and inexpensive, but also readily available. If these converters can be used to improve resolution through simple transformations, users can not only reduce costs but also escape the current predicament of not being able to buy them, which has significant practical implications. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide a signal processing circuit and its control method for improving AD resolution. The system and method solve the problems of low tube conversion rate, high cost and tight supply in the prior art, realize high-resolution and high-precision AD sampling, and reduce costs.

[0006] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0007] A signal processing circuit for improving analog-to-digital (AD) resolution includes: a signal processing unit connected between a sensor and an AD converter; the signal processing unit is a quadrupole operational amplifier circuit composed of four operational amplifiers; the AD converter is a 14-bit AD converter; the non-inverting inputs of the first, second, third, and fourth operational amplifiers are all connected to Ui; the inverting input of the first operational amplifier is connected to 3 / 4Ur; the inverting input of the second operational amplifier is divided into two inverting inputs; the first inverting input of the second operational amplifier is connected to 1 / 2Ur; and the second inverting input of the second operational amplifier is connected to... At node b, the inverting input of the third op-amp is divided into three inverting inputs. The first inverting input of the third op-amp is connected to 1 / 4Ur, the second inverting input of the third op-amp is connected to node d, and the third inverting input of the third op-amp is connected to node c. The inverting input of the fourth op-amp is also divided into three inverting inputs. The first inverting input of the fourth op-amp is connected to node e, the second inverting input of the fourth op-amp is connected to node d, and the third inverting input of the fourth op-amp is connected to node c. The output of the first op-amp is connected to node a, the output of the second op-amp is connected to node f, and the output of the third op-amp is connected to node e.

[0008] A further scheme is that node a is connected to node b, node b is connected to node c, node f is connected to node d, node a is connected to the first conversion channel of the AD converter, node f is connected to the second conversion channel of the AD converter, node e is connected to the third conversion channel of the AD converter, and the output of the fourth operational amplifier is connected to the fourth conversion channel of the AD converter.

[0009] A further proposed solution is to connect a resistor R2 to the non-inverting input of the first op-amp, a resistor R3 to the inverting input of the first op-amp, and a resistor R3 between the non-inverting input and the output of the first op-amp. One end of the resistor R2 is the sampling signal input, and the other end of the resistor R3 is connected to 3 / 4Ur.

[0010] A further proposed solution is to connect a resistor R22 to the non-inverting input of the second op-amp, a resistor R23 to the first inverting input of the second op-amp, a resistor R24 ​​to the second inverting input of the second op-amp, a resistor R21 to the non-inverting input and output of the second op-amp, one end of resistor R22 to the sampling signal input, and one end of resistor R23 to 1 / 2Ur.

[0011] A further proposed solution is to connect resistor R32 to the non-inverting input of the third op-amp, resistor R33 to the first inverting input of the third op-amp, resistor R34 to the second inverting input of the third op-amp, resistor R35 to the third inverting input of the third op-amp, and resistor R31 to the non-inverting input and output of the third op-amp. One end of resistor R32 is the sampling signal input, and one end of resistor R33 is connected to 1 / 4Ur.

[0012] A further proposed solution is to connect resistor R42 to the non-inverting input of the fourth op-amp, resistor R43 to the first inverting input of the fourth op-amp, resistor R44 to the second inverting input of the fourth op-amp, resistor R45 to the third inverting input of the fourth op-amp, resistor R41 to the non-inverting input and output of the fourth op-amp, and one end of resistor R42 to the sampling signal input.

[0013] A signal processing method for improving AD resolution is provided. This method is applied to a signal processing circuit for improving AD resolution, and includes: setting the desired sampling resolution; dividing the peak signal Umax into four equal parts based on voltage levels, with waveforms of signals Udc, Ucb, Uba, and Uao respectively; setting a reference voltage value Ur, where Ur corresponds to the peak signal Umax; amplifying signals Udc, Ucb, Uba, and Uao by a factor of K using four operational amplifiers, so that the waveform of each signal segment is amplified to the amplitude of the peak signal Umax; and then amplifying the four signal waveforms further. After being multiplied by N, the data is transmitted to the four conversion channels of the n-bit AD converter for sampling and AD conversion. The sampled AD values ​​from the n-bit AD converter are then transmitted to a microprocessor for processing. The microprocessor adds the sampling results at the same time and divides them by K to calculate the AD conversion result. The difference between the sampled AD value from the n-bit AD converter and the reference voltage value Ur is checked to see if it is within the effective error range ΔV. If the difference is within the effective error range, the AD sampled value from the n-bit AD converter is determined to be valid. The n-bit AD converter is a 14-bit AD converter.

[0014] A further approach is to divide the peak signal Umax into four equal parts based on voltage levels, including:

[0015] The input signal Ui is subtracted by 3 / 4Ur by the op-amp to obtain the signal Udc, which is expressed as formula (1):

[0016] Udc=Ui-3 / 4Ur (1)

[0017] The input signal Ui is obtained by subtracting 1 / 2Ur and Udc from the input signal Ui through an operational amplifier, which is expressed as formula (2):

[0018] Ucb=Ui-1 / 2Ur-Udc (2)

[0019] The input signal Ui is obtained by subtracting 1 / 4 Ur, Udc, Ucb and Uao from the input signal Ui through an operational amplifier, which is expressed as formula (3):

[0020] Uba = Ui - 1 / 4 Ur - Udc - Ucb - Uao;

[0021] The input signal Ui is obtained by subtracting Udc, Ucb and Uao from the input signal Ui through an operational amplifier, and is expressed as formula (4):

[0022] Uao = Ui - Udc - Ucb - Uao;

[0023] The voltage divisions 3 / 4Ur, 1 / 2Ur, and 1 / 4Ur of each reference voltage are obtained by voltage division using precision resistors set in each operational amplifier, and then by voltage followers composed of operational amplifiers.

[0024] A further approach involves setting the required sampling resolution, i.e., determining the value of (ΔV·K), where ΔV is the effective error range and K is the differential amplification factor. The value of K is determined by the resistance values ​​of the resistors in each operational amplifier. The sampling signal is loaded after the reference voltage value Ur, and the sampling signal and the reference voltage value Ur are respectively connected to a quadrupole operational amplifier circuit. Then, the AD converter samples and converts the signal output by the quadrupole operational amplifier circuit, and transmits the obtained settable high-resolution, high-precision AD sampling value to the microprocessor. In this approach, the error between the input signal and the reference voltage value is amplified by a factor of K by the quadrupole operational amplifier circuit before the high-resolution sampling and conversion data is achieved by the n-bit AD converter.

[0025] A further approach involves coupling a microprocessor to an n-bit analog-to-digital converter (ADC), receiving sampled AD values ​​from the ADC, and providing a resolution control signal based on the sampled AD values ​​to introduce an offset into the sensor input signal, thereby enabling the ADC to provide digital values ​​at a given resolution. The ADC is configured to operate within a fixed resolution region that can accommodate the entire specified operating range of the sensor, and the A / D converter 18 is configured to provide its output at the optimal resolution.

[0026] Therefore, compared with the prior art, the present invention utilizes currently inexpensive and high-precision operational amplifiers to cut and amplify waveforms in segments, and converts them separately by different channels of the AD converter. Finally, the complete waveform is synthesized by a microprocessor, thereby enabling high-resolution and high-precision AD sampling to be achieved using a low-bit AD converter, thus reducing costs.

[0027] Furthermore, this invention divides the original waveform into four equal parts, each of which retains the original resolution, thus increasing the resolution by a factor of four. This means that a 14-bit AD converter achieves the effect of a 16-bit AD converter. Therefore, the sampling circuit and algorithm for high-speed, high-resolution, and high-precision AD sampling based on the low-bit AD converter provided by this invention are simple and easy to implement. Moreover, without increasing costs, they improve detection accuracy, facilitating more precise control.

[0028] Furthermore, the quadrupole operational amplifier circuit of this invention can also achieve high-precision detection of weak signals. It is not only simple to implement, but also low in cost. This invention only uses four inexpensive precision resistors and eight operational amplifiers, which can greatly save costs compared with the existing out-of-stock and expensive 16-bit AD converters.

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of a common amplification and processing circuit for an existing AD signal conversion circuit.

[0031] Figure 2 This is a circuit schematic diagram of an embodiment of a signal processing circuit for improving AD resolution according to the present invention.

[0032] Figure 3 This is a circuit schematic diagram involving waveform processing in an embodiment of a signal processing circuit for improving AD resolution according to the present invention.

[0033] Figure 4 This is a schematic diagram of an embodiment of a signal processing circuit for improving AD resolution according to the present invention. Detailed Implementation

[0034] An embodiment of a signal processing circuit for improving AD resolution:

[0035] See Figures 2 to 4 A signal processing circuit for improving AD resolution includes: a signal processing unit connected between a sensor 1 and an AD analog-to-digital converter 3; the signal processing unit is a quadrupole operational amplifier circuit 2 composed of four operational amplifiers; the AD analog-to-digital converter 3 is a 14-bit AD analog-to-digital converter; the non-inverting inputs of the first operational amplifier U1, the second operational amplifier U2, the third operational amplifier U3, and the fourth operational amplifier U4 are all connected to Ui; the inverting input of the first operational amplifier U1 is connected to 3 / 4Ur; the inverting input of the second operational amplifier U2 is divided into two inverting inputs; the first inverting input of the second operational amplifier U2 is connected to 1 / 2Ur, and the second inverting input of the second operational amplifier U2 is connected to... At node b, the inverting input of the third operational amplifier U3 is divided into three inverting inputs. The first inverting input of the third operational amplifier U3 is connected to 1 / 4Ur, the second inverting input of the third operational amplifier U3 is connected to node d, and the third inverting input of the third operational amplifier U3 is connected to node c. The inverting input of the fourth operational amplifier U4 is divided into three inverting inputs. The first inverting input of the fourth operational amplifier U4 is connected to node e, the second inverting input of the fourth operational amplifier U4 is connected to node d, and the third inverting input of the fourth operational amplifier U4 is connected to node c. The output of the first operational amplifier U1 is connected to node a, the output of the second operational amplifier U2 is connected to node f, and the output of the third operational amplifier U3 is connected to node e.

[0036] In this embodiment, node a is connected to node b, node b is connected to node c, node f is connected to node d, node a is connected to the first conversion channel of the AD analog-to-digital converter 3, node f is connected to the second conversion channel of the AD analog-to-digital converter 3, node e is connected to the third conversion channel of the AD analog-to-digital converter 3, and the output terminal of the fourth operational amplifier U4 is connected to the fourth conversion channel of the AD analog-to-digital converter 3.

[0037] In this embodiment, the non-inverting input terminal of the first operational amplifier U1 is connected to a resistor R2, the inverting input terminal of the first operational amplifier U1 is connected to a resistor R3, and a resistor R3 is connected between the non-inverting input terminal and the output terminal of the first operational amplifier U1. One end of the resistor R2 is the sampling signal input terminal, and one end of the resistor R3 is connected to 3 / 4Ur.

[0038] In this embodiment, the non-inverting input of the second operational amplifier U2 is connected to a resistor R22, the first inverting input of the second operational amplifier U2 is connected to a resistor R23, the second inverting input of the second operational amplifier U2 is connected to a resistor R24, a resistor R21 is connected between the non-inverting input and the output of the second operational amplifier U2, one end of the resistor R22 is the sampling signal input, and one end of the resistor R23 is connected to 1 / 2Ur.

[0039] In this embodiment, the non-inverting input of the third operational amplifier U3 is connected to a resistor R32, the first inverting input of the third operational amplifier U3 is connected to a resistor R33, the second inverting input of the third operational amplifier U3 is connected to a resistor R34, the third inverting input of the third operational amplifier U3 is connected to a resistor R35, a resistor R31 is connected between the non-inverting input and the output of the third operational amplifier U3, one end of the resistor R32 is the sampling signal input, and one end of the resistor R33 is connected to 1 / 4Ur.

[0040] In this embodiment, the non-inverting input of the fourth operational amplifier U4 is connected to a resistor R42, the first inverting input of the fourth operational amplifier U4 is connected to a resistor R43, the second inverting input of the fourth operational amplifier U4 is connected to a resistor R44, the third inverting input of the fourth operational amplifier U4 is connected to a resistor R45, a resistor R41 is connected between the non-inverting input and the output of the fourth operational amplifier U4, and one end of the resistor R42 is the sampling signal input terminal.

[0041] Furthermore, the signal processing circuit also includes a keyboard circuit 5 and a display circuit 6. The resolution of the AD analog-to-digital converter 3 can be set through the keyboard circuit 5, and the calculation results can be displayed through the display circuit 6.

[0042] An embodiment of a signal processing method for improving AD resolution:

[0043] A signal processing method for improving AD resolution, wherein the method is applied to the aforementioned signal processing circuit for improving AD resolution, the method comprising:

[0044] Set the desired sampling resolution.

[0045] The peak signal Umax is divided into four equal parts according to the voltage level, and their waveforms are signals Udc, Ucb, Uba and Uao, respectively.

[0046] Let the reference voltage value be Ur, and the value of Ur correspond to the peak signal Umax.

[0047] Signals Udc, Ucb, Uba, and Uao are amplified by K times by four operational amplifiers, so that the waveform of each signal segment is amplified to the amplitude of the peak signal Umax. Then, the four signal waveforms are amplified by N times and transmitted to the four conversion channels of an n-bit AD converter for sampling and AD conversion.

[0048] The sampled AD value from the n-bit AD converter is transmitted to the microprocessor 4 for processing. The microprocessor 4 adds the sampling results at the same time and divides them by K to calculate the AD conversion result. The difference between the sampled AD value of the n-bit AD converter and the reference voltage value Ur is checked to see if it is within the effective error range ΔV. If the difference is within the effective error range, the AD sampled value sampled by the n-bit AD converter is determined to be valid. The n-bit AD converter is a 14-bit AD converter.

[0049] If the difference exceeds the error range, the AD sampled value sampled by the n-bit AD analog-to-digital converter is invalid. At this time, the difference between the AD sampled value and the reference voltage value Ur is compared and the sampling signal is quickly fed back and adjusted until the difference between the AD sampled value sampled by the n-bit AD analog-to-digital converter and the reference voltage value Ur enters the effective error range ΔV, thus realizing measurement sampling.

[0050] In this embodiment, the peak signal Umax is divided into four equal parts according to voltage levels, including:

[0051] The input signal Ui is subtracted by 3 / 4Ur by the op-amp to obtain the signal Udc, which is expressed as formula (1):

[0052] Udc=Ui-3 / 4Ur (1)

[0053] The input signal Ui is obtained by subtracting 1 / 2Ur and Udc from the input signal Ui through an operational amplifier, which is expressed as formula (2):

[0054] Ucb=Ui-1 / 2Ur-Udc (2)

[0055] The input signal Ui is obtained by subtracting 1 / 4 Ur, Udc, Ucb and Uao from the input signal Ui through an operational amplifier, which is expressed as formula (3):

[0056] Uba = Ui - 1 / 4 Ur - Udc - Ucb - Uao;

[0057] The input signal Ui is obtained by subtracting Udc, Ucb and Uao from the input signal Ui through an operational amplifier, and is expressed as formula (4):

[0058] Uao = Ui - Udc - Ucb - Uao;

[0059] The voltage divisions 3 / 4Ur, 1 / 2Ur, and 1 / 4Ur of each reference voltage are obtained by voltage division using precision resistors set in each operational amplifier, and then by voltage followers composed of operational amplifiers.

[0060] In this embodiment, the required sampling resolution is set, i.e., the value of (△V·K) is determined, where △V is the effective error range and K is the differential amplification factor. The value of K is determined by the resistance value of the resistor in each operational amplifier. The sampling signal is loaded after the reference voltage value Ur, and the sampling signal and the reference voltage value Ur are respectively connected to the quadrupole operational amplifier circuit 2. Then, the AD analog-to-digital converter 3 samples and converts the signal output by the quadrupole operational amplifier circuit 2, and transmits the obtained settable high-resolution and high-precision AD sampling value to the microprocessor 4.

[0061] In this process, the error between the input signal and the reference voltage value is amplified by a factor of K by a quadrupole operational amplifier circuit 2, and then the high-resolution sampling and conversion data is achieved by an n-bit AD analog-to-digital converter, where K is 4 and n is 14.

[0062] In this embodiment, the microprocessor 4 is coupled to an n-bit AD converter, receives the sampled AD value from the n-bit AD converter, and provides a resolution control signal based on the sampled AD value to introduce an offset into the input signal of the sensor 1, so that the n-bit AD converter provides a digital value at a given resolution.

[0063] The n-bit analog-to-digital converter is configured to operate in a fixed resolution region that can accommodate the entire specified operating range of sensor 1, and the analog-to-digital converter 3 is configured to provide its output at the optimal resolution.

[0064] Specifically, this embodiment will Figure 1 The peak signal of the signal source is evenly divided into four parts according to the voltage level, and the waveforms are Udc, Ucb, Uba and Uao respectively; let the reference voltage of AD be Ur, and the value of Ur corresponds to the peak value of the waveform Umax.

[0065] The segmented signal is obtained as follows:

[0066] For example, Udc can be obtained by subtracting 3 / 4Ur from the input signal using an op-amp subtractor, i.e., Ui - 3 / 4Ur.

[0067] Similarly, we can obtain the following from the op-amp subtractor: Ucb = Ui - 1 / 2 Ur - Udc; Uba = Ui - 1 / 4 Ur - Udc - Ucb - Uao; Uao = Ui - Udc - Ucb - Uao.

[0068] The above signals are amplified by four times by four operational amplifiers, so that the waveform of each segment is amplified to the peak value Umax. These four waveforms are then amplified by N times and sent to the four conversion channels of the A / D converter 3 for A / D conversion. Afterwards, the microprocessor 4 adds the sampling results at the same time and divides by 4 to obtain the signal. Figure 1 The result of the 16-bit AD conversion.

[0069] The process of amplifying by N times can be amplified together in the op-amp that amplifies by 4 times, that is, amplified by 4N times.

[0070] In this embodiment, the keyboard circuit 5 and the display circuit 6 are required to set the required resolution. The resolution of the AD analog-to-digital converter 3 can be set through the keyboard circuit 5. After a certain resolution is set, the logic switching is realized through the microprocessor 4, the quadrupole operational amplifier circuit 2, the AD analog-to-digital converter 3, the digital potentiometer and the analog switch switching circuit. Finally, the calculation result is displayed through the display circuit 6.

[0071] For example, based on this application, to achieve a 16-bit A / D conversion function, the 16-bit resolution is set through the keyboard circuit 5, which is two bits more than the resolution of a 14-bit automatic analog-to-digital converter. This requires dividing the reference voltage into 2^2 = 4 levels, and the amplification factor of the amplifier circuit is required to be 4 times.

[0072] Similarly, as long as the relationship is satisfied, where n is the number of bits of resolution to be increased based on the 10-bit AD analog-to-digital converter 3, the voltage divider level of the reference voltage (input signal) is adjusted by adjusting the digital potentiometer. The level is determined by the level logic circuit detection and sent to the microprocessor 4 for judgment, and finally the microprocessor 4 controls the digital potentiometer to adjust.

[0073] Therefore, compared with the prior art, the present invention utilizes the currently inexpensive and high-precision operational amplifier to perform waveform cutting and segmented amplification, and converts them separately by different channels of the AD analog-to-digital converter 3. Finally, the complete waveform is synthesized by the microprocessor 4, thereby enabling high-resolution and high-precision AD sampling to be achieved using the low-bit AD analog-to-digital converter 3, thus reducing costs.

[0074] Furthermore, this invention divides the original waveform into four equal parts, each of which retains the original resolution, thus increasing the resolution by a factor of four. This means that a 14-bit AD converter achieves the effect of a 16-bit AD converter. Therefore, the sampling circuit and algorithm for high-speed, high-resolution, and high-precision AD sampling based on the low-bit AD converter 3 provided by this invention are simple and easy to implement. Moreover, without increasing costs, they improve detection accuracy, facilitating more precise control.

[0075] Furthermore, the quadrupole operational amplifier circuit 2 of the present invention can also achieve high-precision detection of weak signals, which is not only simple to implement but also low in cost. The present invention only uses four inexpensive precision resistors and eight operational amplifiers, which can greatly save costs compared with the existing out-of-stock and expensive 16-bit AD converters.

[0076] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A signal processing circuit for improving AD resolution, characterized in that, include: The signal processing unit, connected between the sensor and the analog-to-digital converter (ADC), is a quadrupole operational amplifier circuit composed of four operational amplifiers. The ADC is a 14-bit ADC. The non-inverting inputs of the first, second, third, and fourth operational amplifiers are all connected to Ui. The inverting input of the first operational amplifier is connected to 3 / 4Ur. The inverting input of the second operational amplifier is divided into two paths. The first inverting input of the second operational amplifier is connected to 1 / 2Ur, and the second inverting input of the second operational amplifier is connected to node b. The inverting input of the third operational amplifier... The phase input terminal is divided into three inverting inputs. The first inverting input of the third op-amp is connected to 1 / 4Ur, the second inverting input of the third op-amp is connected to node d, and the third inverting input of the third op-amp is connected to node c. The inverting input terminal of the fourth op-amp is divided into three inverting inputs. The first inverting input of the fourth op-amp is connected to node e, the second inverting input of the fourth op-amp is connected to node d, and the third inverting input of the fourth op-amp is connected to node c. The output terminal of the first op-amp is connected to node a, the output terminal of the second op-amp is connected to node f, and the output terminal of the third op-amp is connected to node e. Node a is connected to node b, node b is connected to node c, node f is connected to node d, node a is connected to the first conversion channel of the AD converter, node f is connected to the second conversion channel of the AD converter, node e is connected to the third conversion channel of the AD converter, and the output of the fourth operational amplifier is connected to the fourth conversion channel of the AD converter.

2. The circuit according to claim 1, characterized in that: The non-inverting input of the first op-amp is connected to a resistor R2, the inverting input of the first op-amp is connected to a resistor R3, and a resistor R3 is connected between the non-inverting input and the output of the first op-amp. One end of resistor R2 is the sampling signal input terminal, and one end of resistor R3 is connected to 3 / 4Ur.

3. The circuit according to claim 2, characterized in that: The non-inverting input of the second op-amp is connected to resistor R22, the first inverting input of the second op-amp is connected to resistor R23, the second inverting input of the second op-amp is connected to resistor R24, and resistor R21 is connected between the non-inverting input and the output of the second op-amp. One end of resistor R22 is the sampling signal input terminal, and one end of resistor R23 is connected to 1 / 2Ur.

4. The circuit according to claim 3, characterized in that: The non-inverting input of the third op-amp is connected to resistor R32, the first inverting input of the third op-amp is connected to resistor R33, the second inverting input of the third op-amp is connected to resistor R34, the third inverting input of the third op-amp is connected to resistor R35, and resistor R31 is connected between the non-inverting input and the output of the third op-amp. One end of resistor R32 is the sampling signal input terminal, and one end of resistor R33 is connected to 1 / 4Ur.

5. The circuit according to claim 3, characterized in that: The non-inverting input of the fourth op-amp is connected to resistor R42, the first inverting input of the fourth op-amp is connected to resistor R43, the second inverting input of the fourth op-amp is connected to resistor R44, the third inverting input of the fourth op-amp is connected to resistor R45, and resistor R41 is connected between the non-inverting input and the output of the fourth op-amp. One end of resistor R42 is the sampling signal input terminal.

6. A signal processing method for improving AD resolution, characterized in that, This method is applied to a signal processing circuit for improving AD resolution as described in any one of claims 1 to 5 for signal processing, the method comprising: Set the desired sampling resolution; The peak signal Umax is divided into four equal parts according to the voltage level, and their waveforms are signals Udc, Ucb, Uba and Uao, respectively. Let the reference voltage value be Ur, and the value of Ur correspond to the peak signal Umax; Signals Udc, Ucb, Uba, and Uao are amplified by K times by four operational amplifiers, so that the waveform of each signal segment is amplified to the amplitude of the peak signal Umax. Then, the four signal waveforms are amplified by N times and transmitted to the four conversion channels of the n-bit AD converter for sampling and AD conversion. The sampled AD values ​​from the n-bit AD converter are transmitted to the microprocessor for processing. The microprocessor adds the sampling results at the same time and divides them by K to calculate the AD conversion result. The difference between the sampled AD value of the n-bit AD converter and the reference voltage value Ur is checked to see if it is within the effective error range ΔV. If the difference is within the effective error range, the AD sampled value sampled by the n-bit AD converter is determined to be valid. The n-bit AD converter is a 14-bit AD converter.

7. The method according to claim 6, characterized in that: The peak signal Umax is divided into four equal parts according to voltage levels, including: The input signal Ui is subtracted by 3 / 4Ur by the op-amp to obtain the signal Udc, which is expressed as formula (1): Udc=Ui-3 / 4Ur(1) The input signal Ui is obtained by subtracting 1 / 2Ur and Udc from the input signal Ui through an operational amplifier, which is expressed as formula (2): Ucb=Ui-1 / 2Ur-Udc(2) The input signal Ui is obtained by subtracting 1 / 4 Ur, Udc, Ucb and Uao from the input signal Ui through an operational amplifier, which is expressed as formula (3): Uba = Ui - 1 / 4Ur - Udc - Ucb - Uao; The input signal Ui is obtained by subtracting Udc, Ucb and Uao from the input signal Ui through an operational amplifier, and is expressed as formula (4): Uao = Ui - Udc - Ucb - Uao; The voltage divisions 3 / 4Ur, 1 / 2Ur, and 1 / 4Ur of each reference voltage are obtained by voltage division using precision resistors set in each operational amplifier, and then by voltage followers composed of operational amplifiers.

8. The method according to claim 6, characterized in that: Set the required sampling resolution, i.e. determine the value of (△V·K), where △V is the effective error range and K is the differential amplification factor. The value of K is determined by the resistance value of the resistor in each operational amplifier. After the reference voltage value Ur is applied, the sampling signal is loaded, and the sampling signal and the reference voltage value Ur are respectively connected to the quadrupole operational amplifier circuit. Then, the AD converter samples and converts the signal output by the quadrupole operational amplifier circuit, and transmits the obtained settable high-resolution and high-precision AD sampling value to the microprocessor. Specifically, the error between the input signal and the reference voltage value is amplified by a factor of K through a quadrupole operational amplifier circuit, and then the data is sampled and converted at high resolution by an n-bit AD converter.

9. The method according to claim 6, characterized in that: The microprocessor is coupled to an n-bit AD converter, receives the sampled AD values ​​from the n-bit AD converter, and provides a resolution control signal based on the sampled AD values ​​to introduce an offset into the sensor input signal, so that the n-bit AD converter provides digital values ​​at a given resolution. The n-bit AD analog-to-digital converter is configured to operate in a fixed resolution region that can accommodate the entire specified operating range of the sensor, and the A / D converter 18 is configured to provide its output at the optimal resolution.

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