Solid-state imaging device

Abstract

The solid-state imaging device has 2×2 pixel units in which global shutter common pixels are adjacently arranged. The global shutter common pixels are reversed upside down relative to the global shutter common pixels and are adjacently arranged with a 1 / 2 pixel pitch shifted in the row and column directions.

Description

Technical Field

[0001] One embodiment of the present invention relates to a solid-state imaging device that performs a global shutter operation corresponding to a moving image. Background Art

[0002] In the past, various solid-state imaging devices using global shutter pixels have been developed. As a technology related to this, there is an invention disclosed in International Publication No. 2018 / 173793.

[0003] International Publication No. 2018 / 173793 relates to a solid-state imaging element used when multiple pixels arranged in an oblique direction share an FD (floating diffusion) and other elements. The solid-state imaging element comprises: a pixel array in which a shared pixel group is arranged in an oblique direction, and the shared pixel group is composed of multiple pixels that share at least the FD; and a vertical signal line that is wired in a zigzag manner avoiding the photoelectric conversion part of each pixel constituting the shared pixel group, and the vertical signal line is arranged to be close to other vertical signal lines at the connection part with the shared pixel group. Summary of the invention

[0004] Technical Problems to be Solved by the Invention

[0005] In the solid-state imaging element disclosed in International Publication No. 2018 / 173793, the resolution is improved by tilting the common pixel group shared by two pixels in the oblique direction and arranging them at a 1 / 2 pixel pitch in both the horizontal and vertical directions. Furthermore, by crossing the configuration of two adjacent signal output lines, a pixel configuration with good symmetry and no loss of sensitivity characteristics is achieved.

[0006] However, since the shared pixel group is in an oblique direction, there are problems such as an increase in the number of rows to be read and a decrease in the frame rate.

[0007] An object of one aspect of the present invention is to reduce the number of read lines and realize a solid-state imaging device with a high frame rate.

[0008] Technical solutions for solving technical problems

[0009] In order to solve the above-mentioned problem, a solid-state imaging device of one embodiment of the present invention is configured with a plurality of 2×2 pixel units, wherein global shutter shared pixels are adjacently configured in the 2×2 pixel units, and a plurality of adjacent 2×2 pixel units are configured with a 2-pixel period in the column direction and a 1-pixel period in the row direction, wherein in the 2×2 pixel units, a first global shutter shared pixel and a second global shutter shared pixel are adjacently configured with a 1 / 2 pixel pitch offset in the row direction and the column direction, respectively, wherein the second global shutter shared pixel is configured by inverting the same layout as the first global shutter shared pixel in the column direction, and the first global shutter shared pixel and the second global shutter shared pixel are each A pair of unit pixels are arranged relative to each other in the column direction, and the first global shutter shared pixel and the second global shutter shared pixel share: a floating diffusion portion, which stores charges; a signal charge detection portion, which generates a pixel signal according to the charges stored in the floating diffusion portion; and a signal charge reset portion, which discharges the charges stored in the floating diffusion portion, and the pair of unit pixels respectively include: a photodiode portion, which performs photoelectric conversion on a light signal and stores charges; a first charge transfer portion, which transfers the charges stored in the photodiode portion; a charge storage portion, which stores the charges transferred by the first charge transfer portion; and a second charge transfer portion, which transfers the charges stored in the charge storage portion to the floating diffusion portion.

[0010] Beneficial Effects

[0011] According to one aspect of the present invention, it is possible to provide a solid-state imaging device that reduces the number of read lines and achieves a high frame rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a planar layout diagram of a unit pixel of a solid-state imaging device according to an embodiment of the present invention.

[0013] Figure 2 It is a planar layout diagram of a global shutter shared pixel of a solid-state imaging device according to an embodiment of the present invention.

[0014] Figure 3 It is a diagram showing a circuit configuration of a global shutter shared pixel of a solid-state imaging device according to an embodiment of the present invention.

[0015] Figure 4 It is a planar layout diagram of a global shutter 2×2 pixel unit of a solid-state imaging device according to an embodiment of the present invention.

[0016] Figure 5 It is a plan layout diagram of a solid-state imaging device according to an embodiment of the present invention.

[0017] Figure 6 is Figure 5In the planar layout of the solid-state imaging device according to the embodiment of the present invention, a row readout drive wiring connected to the second charge transfer section is added with a bold line.

[0018] Figure 7 is Figure 5 In the planar layout of the solid-state imaging device according to the embodiment of the present invention shown in FIG. 1 , a driving wiring connected to a row selection transistor and a driving wiring connected to a reset transistor are added with bold lines.

[0019] Figure 8 It is a diagram for explaining a method of reading pixel signals of a solid-state imaging device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Hereinafter, an embodiment of the present invention will be described in detail. In addition, for the convenience of description, the same reference numerals are given to the same components, and the names and functions thereof are also the same. Therefore, the detailed description thereof will not be repeated.

[0021] <Planar Layout of Unit Pixel of Solid-State Imaging Device>

[0022] Figure 1 1 is a planar layout diagram of a unit pixel of a solid-state imaging device according to an embodiment of the present invention. The unit pixel 100 includes: a photodiode portion PD; a first charge transfer portion TRX, which is adjacent to the photodiode portion PD and covered by a first gate electrode; a charge storage portion (not shown), which is adjacent to the first charge transfer portion TRX in a direction different from the photodiode portion PD; and a second charge transfer portion TRG, which is covered by a second gate electrode adjacent to the charge storage portion in a direction different from the first charge transfer portion TRX.

[0023] The unit pixel 100 also includes: a floating diffusion portion FD of the first conductive semiconductor region, which is adjacent to the second charge transfer portion TRG in a direction different from the charge storage portion; a third charge transfer portion OFG, which is covered by a third gate electrode, and the third gate electrode is adjacent to the photodiode portion PD in a direction different from the first charge transfer portion TRX; and an overflow drain portion, which is adjacent to the third charge transfer portion OFG in a direction different from the photodiode portion PD and is connected to the power supply voltage VDD.

[0024] <Planar Layout of Global Shutter Shared Pixels of Solid-State Imaging Device>

[0025] Figure 2 FIG. 1 is a planar layout diagram of a global shutter shared pixel of a solid-state imaging device according to an embodiment of the present invention. The connection wiring of the floating diffusion portion FD is indicated by a bold line. Figure 2As shown, the global shutter common pixel first connects two unit pixels 100 - 1 and 100 - 2 via a floating diffusion portion FD, and is arranged opposite to each other in the column direction (the vertical direction in the figure).

[0026] Furthermore, the two unit pixels 100-1 and 100-2 share a signal charge detection unit and a reset transistor (signal charge reset unit) RST, wherein the signal charge detection unit is composed of a source follower transistor SF and a row selection transistor SEL, and the gate electrode is connected to the floating diffusion unit FD and the source follower transistor SF through the wiring in the unit pixel 100-2 shown by the bold line; the source portion of the unit pixel 100-2 is connected to the floating diffusion unit FD and the reset transistor RST through the wiring in the unit pixel 100-2 shown by the same bold line, and its drain portion is connected to the reset transistor RST and the power supply voltage VDD. In addition, the pixel pitch between the unit pixels 100-1 and 100-2 is a.

[0027] Figure 3 1 is a diagram showing the circuit configuration of global shutter shared pixels 100-1 and 100-2 of a solid-state imaging device according to an embodiment of the present invention. The global shutter shared pixels 100-1 and 100-2 include first charge transfer units TRX1 and TRX2, second charge transfer units TRG1 and TRG2, overflow gates (third charge transfer units) OFG1 and OFG2, photodiode units PD1 and PD2, charge storage units MEMS1 and MEMS2, floating diffusion units FD, reset transistors RST, source follower transistors SF, and row selection transistors SEL.

[0028] The photodiode PD1 functions as a photoelectric converter that converts incident light into electric charges by photoelectric conversion and stores them. The photodiode PD1 has an anode terminal connected to the ground and a cathode terminal connected to the first charge transfer unit TRX1 and the overflow gate (third charge transfer unit) OFG1.

[0029] The first charge transfer unit TRX1 is driven by a first transfer signal (not shown). When the first charge transfer unit TRX1 is turned on, the charge stored in the photodiode unit PD1 is transferred to the charge storage unit MEMS1. The charge transfer from the photodiode unit PD1 to the charge storage unit MEMS1 is performed at approximately the same time in all the unit pixels of the solid-state imaging element, and the charge is transferred simultaneously in all the unit pixels. The charge storage unit MEMS1 stores the charge transferred from the photodiode unit PD1.

[0030] The second charge transfer portion TRG1 is driven by a row read drive signal described later. When the second charge transfer portion TRG1 is turned on, the charges stored in the charge holding portion MEM1 are transferred to the floating diffusion portion FD.

[0031] The overflow gate OFG1 is driven by a discharge signal (not shown). When the overflow gate OFG1 is turned on, the charge stored in the photodiode portion PD1 is discharged to the power supply wiring VDD. In addition, the overflow gate OFG1 has a function of overflowing the charge from the photodiode portion PD1 to the power supply wiring VDD when a charge greater than the saturation charge amount of the photodiode portion PD1 is generated by photoelectric conversion.

[0032] Likewise, the photodiode section PD2 functions as a photoelectric conversion unit that converts incident light into charges by photoelectric conversion and stores the charges. The anode terminal of the photodiode section PD2 is grounded, and the cathode terminal is connected to the first charge transfer section TRX2 and the overflow gate (third charge transfer section) OFG2.

[0033] The first charge transfer unit TRX2 is driven by a first transfer signal not shown. When the first charge transfer unit TRX2 is turned on, the charge stored in the photodiode unit PD2 is transferred to the charge storage unit MEMS2. The charge transfer from the photodiode unit PD2 to the charge storage unit MEMS2 is performed at approximately the same time in all unit pixels of the solid-state imaging element, and the charge is transferred simultaneously in all unit pixels. The charge storage unit MEMS2 stores the charge transferred from the photodiode unit PD2.

[0034] The second charge transfer portion TRG2 is driven by a row read drive signal described later. When the second charge transfer portion TRG2 is turned on, the charges stored in the charge holding portion MEM2 are transferred to the floating diffusion portion FD.

[0035] The overflow gate OFG2 is driven by a discharge signal (not shown). When the overflow gate OFG2 is turned on, the charge stored in the photodiode portion PD2 is discharged to the power supply wiring VDD. In addition, the overflow gate OFG2 has a function of causing the charge to overflow from the photodiode portion PD2 to the power supply wiring VDD when a charge greater than the saturation charge amount of the photodiode portion PD2 is generated by photoelectric conversion.

[0036] The source follower transistor SF outputs a pixel signal of a level corresponding to the charge stored in the floating diffusion portion FD to the vertical signal line VSL via the row selection transistor SEL. That is, by connecting the floating diffusion portion FD to the gate electrode of the source follower transistor SF, the floating diffusion portion FD and the source follower transistor SF function as a conversion portion that converts the charge generated in the photodiode portion PD1 or PD2 into a pixel signal of a level corresponding to the charge.

[0037] The row selection transistor SEL is driven by a row selection signal described later. When the row selection transistor SEL is turned on, the pixel signal output from the source follower transistor SF can be output to the vertical signal line VSL. The source follower transistor SF and the row selection transistor SEL function as a signal charge detection unit.

[0038] The reset transistor RST is driven by a row reset signal (RST signal) described later. When the reset transistor RST is turned on, the charge accumulated in the floating diffusion FD is discharged to the power supply wiring VDD, and the floating diffusion FD is reset.

[0039] The floating diffusion FD is a first conductive semiconductor region having a predetermined storage capacitor connected to the gate electrode of the source follower transistor SF, and the floating diffusion FD stores the charge transferred from the charge storage portion. In addition, the floating diffusion FD, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL are shared by the two unit pixels 100-1 and 100-2.

[0040] <Planar layout diagram of a global shutter 2×2 pixel unit of a solid-state imaging device>

[0041] Figure 4 1 is a planar layout diagram of a global shutter 2×2 pixel unit of a solid-state imaging device according to an embodiment of the present invention. The connection wiring of the floating diffusion FD is indicated by a bold line. In addition, the unit pixels 100-11 and 100-21 constitute one global shutter shared pixel, and the unit pixels 100-12 and 100-22 constitute another global shutter shared pixel.

[0042] Global shutter 2×2 pixel unit relative to Figure 2 The global shutter shared pixels (100-1, 100-2) shown are identical global shutter shared pixels that are inverted in the column direction (vertical direction) and are adjacently arranged with a shift of a / 2 relative to the pixel pitch a in the row and column directions.

[0043] like Figure 4 As shown, the VDD of the overflow drain portion of the overflow gate OFG11 adjacent to the upper photodiode PD11 of the global shutter shared pixel (100-11, 100-21) on the left is shared with the VDD connected to the drain terminal of the reset transistor RST2 of the global shutter shared pixel (100-12, 100-22) on the right.

[0044] <Plane Layout of Solid-State Imaging Device>

[0045] Figure 51 is a plan view of a solid-state imaging device 1 according to an embodiment of the present invention. The connection wiring of the floating diffusion portion FD is indicated by a bold line. The solid-state imaging device of this embodiment is configured by arranging a plurality of pixels at a period of two pixels in the column direction and at a period of one pixel in the row direction. Figure 3 The global shutter shown is composed of 2×2 units.

[0046] like Figure 5 As shown, for example, the VDD of the overflow gate OFG21 adjacent to the photodiode PD21 on the lower side of the global shutter shared pixel (100-11, 100-21) on the upper left side is shared with the VDD connected to the drain portion of the source follower transistor SF22 of the global shutter shared pixel (100-32, 100-42) on the lower right side. In addition, other global shutter shared pixels are configured and connected in the same manner.

[0047] exist Figure 5 In the embodiment, a global shutter 2×2 pixel unit is composed of global shutter shared pixels (100-13, 100-23) and global shutter shared pixels (100-14, 100-24). In addition, a global shutter 2×2 pixel unit is composed of global shutter shared pixels (100-31, 100-41) and global shutter shared pixels (100-32, 100-42). Similarly, a global shutter 2×2 pixel unit is composed of global shutter shared pixels (100-33, 100-43) and global shutter shared pixels (100-34, 100-44).

[0048] <Row Readout Drive Wiring of Solid-State Imaging Device>

[0049] Figure 6 is Figure 5 In the planar layout of the solid-state imaging device 1 according to the embodiment of the present invention, a row read drive wiring connected to the second charge transfer unit TRG is added with a bold line. The row read drive wirings TRG1 to TRG4 are wired in a zigzag manner at the boundary of each global shutter common pixel arranged in the column direction, and the second charge transfer unit TRG on the upper side of each global shutter common pixel is connected by the same row read drive wiring (TRG1, TRG3), and the second charge transfer unit TRG on the lower side is connected by the same row read drive wiring (TRG2, TRG4).

[0050] <Drive Wiring Connected to Row Select Transistor SEL of Solid-State Imaging Device and Drive Wiring Connected to Reset Transistor RST>

[0051] Figure 7 is Figure 5In the planar layout of the solid-state imaging device according to the embodiment of the present invention shown in FIG. 1 , a driving wiring connected to the row selection transistor SEL and a driving wiring connected to the reset transistor RST are added with bold lines.

[0052] The driving wiring (row selection signal) SEL1 is connected to the row selection transistors SEL11, SEL12, SEL13, and SEL14. Although they are different wirings in the pixel array, they are connected via a pixel peripheral circuit portion (not shown) and are supplied with the same waveform.

[0053] The drive wiring SEL2 is connected to row selection transistors SEL21, SEL22, SEL23, and SEL24. Although it is a different wiring in the pixel array, it is connected through a pixel peripheral circuit portion (not shown) similarly to the row selection signal SEL1, and the same waveform is supplied.

[0054] The driving wiring (row reset signal) RST1 is connected to the reset transistors RST11, RST12, RST13, and RST14. Although they are different wirings in the pixel array, they are connected via a pixel peripheral circuit portion (not shown) and are supplied with the same waveform.

[0055] The driving wiring RST2 is connected to the reset transistors RST21, RST22, RST23, and RST24. Although it is a different wiring in the pixel array, it is connected through a pixel peripheral circuit portion (not shown) similarly to the row reset signal RST1, and the same waveform is supplied.

[0056] The drive wirings SEL1, SEL2, RST1, and RST2 are arranged in a zigzag pattern at the boundary of each global shutter common pixel. The drive wirings SEL1 and RST1 are connected to each global shutter common pixel through two wirings, but in the case of Figure 7 In the case where the wiring is arranged on the upper side of the global shutter common pixel as shown, and in the case where the wiring is arranged on the lower side, the arrangement order in the column direction is opposite.

[0057] Figure 8 1 is a diagram for explaining a method of reading pixel signals of the solid-state imaging device 1 according to an embodiment of the present invention. Figure 8 As shown in FIG. 1 , by reading pixel signals from unit pixels arranged in a zigzag pattern, the number of reading times can be halved compared to the conventional technology. Therefore, it is possible to operate at a high frame rate and read at a high speed.

[0058] As described above, according to the solid-state imaging device in this embodiment, the two unit pixels 100-1 and 100-2 are connected by the floating diffusion FD and arranged opposite to each other in the column direction (up and down direction of the figure) as a global shutter common pixel. In addition, the second charge transfer unit TRG on the upper side of the global shutter common pixel is connected by a row reading drive wiring, and the second charge transfer unit TRG on the lower side is connected by another row reading drive wiring. As a result, the number of read rows can be reduced, and a high frame rate can be achieved.

[0059] The frame rate (the time required to read one screen) is calculated by multiplying the read time per line (AD conversion time per line) by the number of lines to be read. Therefore, even if the number of pixels is the same, the frame rate only doubles when the number of lines to be read is halved.

[0060] In addition, the VDD of the overflow drain portion of the overflow gate OFG11 adjacent to the photodiode PD11 on the upper side of the global shutter shared pixel (100-11, 100-21) is shared with the VDD of the drain terminal of the reset transistor RST2 connected to the global shutter shared pixel (100-12, 100-22). Therefore, the configuration of the global shutter shared pixel (100-11, 100-21) and the global shutter shared pixel (100-12, 100-22) can be effectively performed, and the characteristics of the photodiode portion and the charge storage portion can be maintained.

[0061] In addition, the VDD of the overflow gate OFG21 adjacent to the photodiode PD21 on the lower side of the global shutter shared pixel (100-11, 100-21) and the VDD connected to the drain portion of the source follower transistor SF22 of the global shutter shared pixel (100-32, 100-42) are shared. Therefore, the configuration of the global shutter shared pixel (100-11, 100-21) and the global shutter shared pixel (100-32, 100-42) can be effectively performed, and the characteristics of the photodiode portion and the charge holding portion can be maintained.

[0062] The sensitivity characteristics and saturation charge amount of the solid-state imaging element depend on the area of ​​the photodiode section PD. In addition, the saturation charge amount of the global shutter pixel depends on the area of ​​the charge storage section MEMS. Therefore, by efficiently performing the configuration, even if an oblique pixel configuration is performed, the areas of the photodiode section PD and the charge storage section MEMS can be maintained, and the same characteristics can be maintained with the usual pixel arrangement.

[0063] Furthermore, by making the layout of each unit pixel the same and the layout of each global shutter common pixel the same, various characteristics such as sensitivity, saturation charge amount, dark noise characteristics, and charge transfer characteristics of each pixel can be made uniform.

[0064] Furthermore, row selection transistors SEL11, SEL12, SEL13, and SEL14 are connected to a drive wiring (row selection signal) SEL1, and the drive wiring connected to row selection transistors SEL11 and SEL13 and the drive wiring connected to row selection transistors SEL12 and SEL14 are different wirings. Therefore, the wiring of row selection signal SEL1 can be performed efficiently.

[0065] Furthermore, the drive wiring (row reset signal) RST1 is connected to the reset transistors RST11, RST12, RST13, and RST14, and the drive wiring connected to the reset transistors RST11 and RST13 and the drive wiring connected to the reset transistors RST12 and RST14 are different wirings. Therefore, the row reset signal RST1 can be efficiently wired.

[0066] In addition, the drive wirings SEL1 and RST1 are connected to each global shutter common pixel through two wirings, but the arrangement order in the column direction is opposite when the wiring is on the upper side of the global shutter common pixel and when the wiring is on the lower side. Therefore, the row selection signal SEL1 and the row reset signal RST1 can be efficiently wired.

[0067] <Conclusion>

[0068] The solid-state imaging device involved in mode 1 of the present invention is configured with a plurality of 2×2 pixel units, global shutter shared pixels are adjacently configured in the 2×2 pixel units, a plurality of adjacent 2×2 pixel units are configured with a 2-pixel period in the column direction and a 1-pixel period in the row direction, and in the 2×2 pixel units, a first global shutter shared pixel and a second global shutter shared pixel are adjacently configured with a 1 / 2 pixel pitch offset in the row direction and the column direction, respectively, wherein the second global shutter shared pixel is configured by inverting the same layout as the first global shutter shared pixel in the column direction, and the first global shutter shared pixel and the second global shutter shared pixel are each arranged in the column direction. A pair of unit pixels are arranged relative to each other in the direction, and the first global shutter shared pixel and the second global shutter shared pixel share: a floating diffusion portion, which stores charges; a signal charge detection portion, which generates a pixel signal according to the charges stored in the floating diffusion portion; and a signal charge reset portion, which discharges the charges stored in the floating diffusion portion, and the pair of unit pixels respectively include: a photodiode portion, which performs photoelectric conversion on the light signal and stores charges; a first charge transfer portion, which transfers the charges stored in the photodiode portion; a charge storage portion, which stores the charges transferred by the first charge transfer portion; and a second charge transfer portion, which transfers the charges stored in the charge storage portion to the floating diffusion portion.

[0069] According to the above configuration, the number of lines to be read can be reduced, and a high frame rate can be achieved.

[0070] In the solid-state imaging device involved in mode 2 of the present invention, in the above-mentioned mode 1, the second charge transfer unit of the unit pixel on the upper side within the first global shutter shared pixel and the second charge transfer unit of the unit pixel on the upper side within the second global shutter shared pixel are driven by the first row reading drive signal, and the second charge transfer unit of the unit pixel on the lower side of the first global shutter shared pixel and the second charge transfer unit of the unit pixel on the lower side of the second global shutter shared pixel are driven by the second row reading drive signal.

[0071] According to the above configuration, the number of lines to be read can be reduced, and a high frame rate can be achieved.

[0072] In the solid-state imaging device involved in mode 3 of the present invention, in the above-mentioned mode 1 or 2, the unit pixel also has a third charge transfer unit, which discharges a charge greater than the saturation charge of the photodiode unit, and the overflow drain unit of the third charge transfer unit of the unit pixel in the first global shutter shared pixel and the drain unit of the signal charge reset unit in the second global shutter shared pixel are composed of the same first semiconductor region.

[0073] According to the above configuration, the configuration of the first global shutter common pixel and the second global shutter common pixel can be efficiently performed, and the characteristics of the photodiode portion and the charge holding portion can be maintained.

[0074] In the solid-state imaging device involved in mode 4 of the present invention, in the above-mentioned mode 1 or 2, the unit pixel also has a third charge transfer unit, which discharges a charge greater than the saturation charge of the photodiode unit, and the overflow drain unit of the third charge transfer unit of the unit pixel in the first global shutter shared pixel and the drain unit of the signal charge detection unit in the second global shutter shared pixel are composed of the same first semiconductor region.

[0075] According to the above configuration, the configuration of the first global shutter common pixel and the second global shutter common pixel can be efficiently performed, and the characteristics of the photodiode portion and the charge holding portion can be maintained.

[0076] In the solid-state imaging device involved in mode 5 of the present invention, in any of the above-mentioned modes 1 to 4, the row selection signal connected to the signal charge detection unit in the first global shutter shared pixel and the row selection signal connected to the signal charge detection unit in the second global shutter shared pixel have the same signal waveform and are connected through different wirings.

[0077] According to the above configuration, the row selection signal can be efficiently wired.

[0078] In the solid-state imaging device according to mode 6 of the present invention, in the above-mentioned mode 5, the row reset signal connected to the signal charge reset portion in the first global shutter shared pixel and the row reset signal connected to the signal charge reset portion in the second global shutter shared pixel have the same signal waveform and are connected by different wirings.

[0079] According to the above configuration, the row reset signal can be efficiently wired.

[0080] In the solid-state imaging device according to mode 7 of the present invention, in mode 6, the wiring arrangement of the row selection signal and the row reset signal connected to the first global shutter common pixel is opposite to the wiring arrangement of the row selection signal and the row reset signal connected to the second global shutter common pixel.

[0081] According to the above configuration, the row selection signal and the row reset signal can be efficiently wired.

[0082] The present invention is not limited to the above-mentioned embodiments, and various changes can be made within the scope of the claims. The embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Moreover, new technical features can be formed by combining the technical methods disclosed in each embodiment.

Claims

1. A solid-state imaging device, characterized in that: A plurality of 2×2 pixel units are configured, wherein global shutter shared pixels are adjacently configured in the 2×2 pixel units. A plurality of adjacent 2×2 pixel units are arranged at a 2-pixel period in the column direction and at a 1-pixel period in the row direction, In the 2×2 pixel unit, the first global shutter shared pixel and the second global shutter shared pixel are adjacently arranged with a 1 / 2 pixel pitch staggered in the row direction and the column direction, respectively, wherein the second global shutter shared pixel is a reverse arrangement of the same layout as the first global shutter shared pixel in the column direction, The first global shutter shared pixel and the second global shutter shared pixel each configure a pair of unit pixels opposite to each other in a column direction, and the first global shutter shared pixel and the second global shutter shared pixel share: a floating diffusion that stores charge; a signal charge detection unit that generates a pixel signal according to the charge stored in the floating diffusion unit; and The signal charge reset unit discharges the charge stored in the floating diffusion unit. The pair of unit pixels respectively include: The photodiode part converts the light signal into photoelectricity and stores the charge; a first charge transfer section that transfers charges stored in the photodiode section; a charge holding portion that holds the charge transferred by the first charge transfer portion; and a second charge transfer section that transfers the charge stored in the charge storage section to the floating diffusion section, The second charge transfer section of the upper unit pixel in the first global shutter shared pixel and the second charge transfer section of the upper unit pixel in the second global shutter shared pixel are driven by a first row reading drive signal, The second charge transfer portion of the unit pixel on the lower side of the first global shutter sharing pixel and the second charge transfer portion of the unit pixel on the lower side of the second global shutter sharing pixel are driven by a second row readout driving signal.

2. The solid-state imaging device according to claim 1, wherein: The unit pixel further includes a third charge transfer unit that discharges a charge larger than a saturation charge amount of the photodiode unit. An overflow drain portion of the third charge transfer portion of the unit pixel in the first global shutter common pixel and a drain portion of the signal charge resetting portion in the second global shutter common pixel are formed of the same first semiconductor region.

3. The solid-state imaging device according to claim 1, wherein The unit pixel further includes a third charge transfer unit that discharges a charge larger than a saturation charge amount of the photodiode unit. An overflow drain portion of the third charge transfer portion of the unit pixel in the first global shutter common pixel and a drain portion of the signal charge detection portion in the second global shutter common pixel are formed of the same first semiconductor region.

4. The solid-state imaging device according to claim 1, wherein The row selection signal connected to the signal charge detection section in the first global shutter shared pixel and the row selection signal connected to the signal charge detection section in the second global shutter shared pixel have the same signal waveform and are connected through different wirings.

5. The solid-state imaging device according to claim 4, wherein: A row reset signal connected to the signal charge reset section in the first global shutter sharing pixel and a row reset signal connected to the signal charge reset section in the second global shutter sharing pixel have the same signal waveform and are connected by different wirings.

6. The solid-state imaging device according to claim 5, wherein: The wiring arrangement of the row selection signal and the row reset signal connected to the first global shutter common pixel is opposite to the wiring arrangement of the row selection signal and the row reset signal connected to the second global shutter common pixel.

Images