An LED driving system and an LED driving circuit

Abstract

The present invention discloses an LED driving system and an LED driving circuit. The LED driving system includes a first and a second LED driving circuit, and both the first and the second LED driving circuit include a first state detection circuit, a second state detection circuit and a first feedback control circuit. The first state detection circuit is coupled to a plurality of LED lamp strings to receive a plurality of blanking detection voltages and generate at least one first state signal. The second state detection circuit receives a downstream feedback signal and generates at least one second state signal. The first feedback control circuit generates a first feedback control signal based on at least one first state signal and at least one second state signal. The second state detection circuit of the first LED driving circuit is coupled to the first feedback control circuit of the second LED driving circuit to receive the first feedback control signal generated by the second LED driving circuit as the downstream feedback signal of the first LED driving circuit.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and in particular, to an LED driving system and an LED driving circuit. Background Art

[0002] In LED driving applications, such as dynamic tail lights, daytime running lights, and / or fog lights, a large number of LED strings are often required for lighting. However, a typical LED driving chip can only drive a few LED strings. In this case, multiple LED driving chips are usually required to drive the required number of LED strings. Therefore, the problem of how to control an LED driving system to drive a large number of LED strings to meet the lighting requirements needs to be solved urgently. Summary of the Invention

[0003] Aiming at the problems existing in the prior art, the purpose of the present invention is to provide an LED driving system and an LED driving circuit that can effectively drive a large number of LED strings.

[0004] According to an embodiment of the present invention, an LED driving circuit is proposed for driving a plurality of LED strings, where each LED string has a first end for receiving a bias voltage and a second end for providing a clearance detection voltage. The LED driving circuit includes: a first state detection circuit, coupled to the plurality of LED strings to receive a plurality of clearance detection voltages, and generating at least one first state signal based on the plurality of clearance detection voltages; a second state detection circuit, receiving a downstream feedback signal, and generating at least one second state signal based on the downstream feedback signal, where at least one second state signal is used to indicate whether a downstream LED driving circuit is coupled to the LED driving circuit, and when the downstream LED driving circuit is coupled to the LED driving circuit, indicating the state of the downstream LED driving circuit; and a first feedback control circuit, generating a first feedback control signal based on the at least one first state signal and the at least one second state signal, where the first feedback control signal is used to indicate the state of the LED driving circuit.

[0005] According to another embodiment of the present invention, an LED driving circuit is proposed for driving a plurality of LED strings, where each LED string has a first end for receiving a bias voltage and a second end for providing a clearance detection voltage. The LED driving circuit includes: a state detection circuit, receiving a plurality of clearance detection voltages and a downstream feedback signal, and generating at least one state signal based on the plurality of clearance detection voltages and the downstream feedback signal; a first feedback control circuit, generating a first feedback control signal based on the at least one state signal; a second feedback control circuit, generating a second feedback control signal based on the at least one state signal; and a selection circuit, receiving a mode signal, and selecting the first feedback control signal or the second feedback control signal as a feedback control signal based on the mode signal.

[0006] According to another embodiment of the present invention, an LED driving system includes: a first LED driving unit; and a second LED driving unit, wherein both the first LED driving unit and the second LED driving unit include an LED driving circuit, and each LED driving circuit drives a plurality of LED lamp strings respectively. Each LED lamp string has a first end for receiving a bias voltage and a second end for providing a clearance detection voltage. The LED driving circuit includes: a first state detection circuit coupled to the plurality of LED lamp strings to receive a plurality of clearance detection voltages and generate at least one first state signal based on the plurality of clearance detection voltages; a second state detection circuit for receiving a downstream feedback signal and generating at least one second state signal based on the downstream feedback signal; and a first feedback control circuit for generating a first feedback control signal based on the at least one first state signal and the at least one second state signal; wherein the second state detection circuit of the first LED driving unit is coupled to the first feedback control circuit of the second LED driving unit to receive the first feedback control signal of the second LED driving unit as the downstream feedback signal of the first LED driving unit.

[0007] According to an embodiment of the present invention, the LED driving system and the LED driving circuit can drive a large number of LED lamp strings simultaneously to meet the lighting requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 LED driving circuit 100 according to an embodiment of the present invention;

[0009] Figure 2 First state detection circuit 200 according to an embodiment of the present invention;

[0010] Figure 3 Second state detection circuit 300 according to an embodiment of the present invention;

[0011] Figure 4 Logic circuit 400 according to an embodiment of the present invention;

[0012] Figure 5 Second feedback control circuit 500 according to an embodiment of the present invention;

[0013] Figure 6 Modulation circuit 600 according to an embodiment of the present invention;

[0014] Figure 7 First feedback control circuit 700 according to an embodiment of the present invention;

[0015] Figure 8 LED driving system 800 according to an embodiment of the present invention;

[0016] Figure 9 Selection circuit 900 according to an embodiment of the present invention. Detailed implementation

[0017] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described here are only for illustrative purposes and do not limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the present invention.

[0018] Throughout the specification, references to "an embodiment", "embodiments", "an example", or "examples" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the phrases "in an embodiment", "in embodiments", "an example", or "examples" appearing throughout the specification are not necessarily all referring to the same embodiment or example. Additionally, the specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as "directly connected to" or "directly coupled to" another element, no intervening elements are present. Like reference numerals indicate like elements. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0019] In the present invention, unless otherwise clearly specified in the text, the plural form does not exclude a singular reference. For example, "a plurality of LED light strings" may include only one LED light string, and "a plurality of LED lights" may include only one LED light.

[0020] Figure 1 LED driving circuit 100 according to an embodiment of the present invention. As Figure 1 shown, the LED driving circuit 100 is used to drive an LED array ALED having a plurality of LED light strings SLED1 to SLEDN, where i is an integer from 1 to N and N is an integer greater than or equal to 1. Each LED light string SLEDi (i = 1, 2,..., N) includes a plurality of light emitting diodes LEDi1 to LEDiM whose first ends (such as anodes) and second ends (such as cathodes) are interconnected with each other, where M is an integer greater than or equal to 1. As Figure 1As shown, the first end of LEDi1 receives the bias voltage VBIAS as the input voltage, and the second end of LEDiM provides the blanking detection voltage VLEDi. The LED driving circuit 100 can adjust the current flowing through each LED string SLEDi and maintain the current at an expected value.

[0021] In Figure 1 In the embodiment shown, the LED driving circuit 100 includes a state detection circuit 101 and a first feedback control circuit 102. The state detection circuit 101 is coupled to the LED array ALED to receive a plurality of blanking detection voltages VLED1 to VLEDN, and also receives a downstream feedback signal VFBI, and generates at least one state signal ST based on the plurality of blanking detection voltages VLED1 to VLEDN and the downstream feedback signal VFBI.

[0022] In one embodiment, the downstream feedback signal VFBI is used to indicate whether there is a downstream LED driving circuit coupled to the LED driving circuit 100, and when the downstream LED driving circuit is coupled to the LED driving circuit 100, it indicates the state of the downstream LED driving circuit. In one embodiment, the downstream LED driving circuit and the LED driving circuit 100 have the same structure, that is, the components of the downstream LED driving circuit and the connection relationships between the components are the same as those of the LED driving circuit 100.

[0023] The first feedback control circuit 102 is coupled to the state detection circuit 101 to receive at least one state signal ST, and generates a first feedback control signal VFBO1 according to the at least one state signal ST. In one embodiment, the first feedback control signal VFBO1 is used to indicate the state of the LED driving circuit 100.

[0024] In the following embodiments, for convenience of description, the plurality of LED strings SLED1 to SLEDN driven by the LED driving circuit 100 are defined as the first group of LED strings, and the plurality of LED strings driven by the downstream LED driving circuit are defined as the second group of LED strings. The bias voltage VBIAS provided to the first group of LED strings is defined as the first bias voltage, and the bias voltage provided to the second group of LED strings is defined as the second bias voltage. The voltage required to drive the first group of LED strings to meet the requirement that the current flowing through each of the first group of LED strings is maintained at a first expected value is defined as the first required voltage, and the voltage required to drive the second group of LED strings to meet the requirement that the current flowing through each of the second group of LED strings is maintained at a second expected value is defined as the second required voltage.

[0025] In one embodiment, the states of the LED driving circuit 100 include: 1) State 1: The first bias voltage VBIAS is greater than the first required voltage, and at the same time, the bias voltage supplied to the second group of LED strings is also greater than the second required voltage; 2) State 2: The first bias voltage VBIAS is exactly close to or suitable for the first required voltage, and at the same time, the bias voltage supplied to the second group of LED strings is also exactly suitable for or close to the second required voltage; and 3) State 3: The first bias voltage VBIAS is less than the first required voltage, or the second bias voltage is less than the second required voltage. The above descriptions of the three states of the LED driving circuit 100 also apply to the downstream LED driving circuit. In one embodiment, the downstream LED driving circuit includes one or more LED driving circuits having the same structure as the LED driving circuit 100.

[0026] In one embodiment, when the states of the LED driving circuit 100 and the downstream LED driving circuit are the same, the first feedback control signal VFBO1 and the downstream feedback signal VFBI have the same value.

[0027] In one embodiment, the LED driving circuit 100 further includes a second feedback control circuit 103 and a selection circuit 104. The second feedback control circuit 103 is coupled to the state detection circuit 101 to receive at least one state signal ST, and generates a second feedback control signal VFBO2 based on the at least one state detection signal ST.

[0028] The selection circuit 104 receives the mode signal MODE, and selects the first feedback control signal VFBO1 or the second feedback control signal VFBO2 as the feedback control signal VFBO of the LED driving circuit 100 based on the mode signal MODE.

[0029] In one embodiment, the mode signal MODE has a first mode and a second mode. Among them, when the mode signal MODE is grounded, it indicates that it has the first mode, and the selection circuit 104 selects the second feedback control signal VFBO2 as the feedback control signal VFBO, and the LED driving circuit 100 is set as the main LED driving circuit; when the mode signal MODE is coupled to the supply voltage, it indicates that it has the second mode, and the selection circuit 104 selects the first feedback control signal VFBO1 as the feedback control signal VFBO, and the LED driving circuit 100 is set as the slave LED driving circuit.

[0030] Figure 9Selection circuit 900 according to an embodiment of the present invention. Selection circuit 900 has switches SS1 and SS2, both of which have a first end, a second end, and a control end. The first end of switch SS1 receives the first feedback control signal VFBO1, and the control end receives the mode signal MODE. The first end of switch SS2 receives the second feedback control signal VFBO2, and the control end receives the reverse mode signal having a level opposite to that of the mode signal MODE. The second ends of switches SS1 and SS2 are coupled together to provide the feedback control signal VFBO. When the mode signal MODE is in the first mode, switch SS1 is turned off and switch SS2 is turned on to select the second feedback control signal VFBO2 as the feedback control signal VFBO; when the mode signal MODE is in the second mode, switch SS1 is turned on and switch SS2 is turned off to select the first feedback control signal VFBO1 as the feedback control signal VFBO. In one embodiment, both switches SS1 and SS2 are N-type MOSFETs.

[0031] Continuing as Figure 1 shown, the status detection circuit 101 includes a first status detection circuit 111 and a second status detection circuit 112. The first status detection circuit 111 is coupled to the LED array ALED to receive a plurality of blanking detection voltages VLED1~VLEDN, and generates at least one first status signal S based on the plurality of blanking detection voltages VLED1~VLEDN. The second status detection circuit 112 receives the downstream feedback signal VFBI, and generates at least one second status signal D based on the downstream feedback signal VFBI. Further, the status detection circuit 101 generates at least one status signal ST based on at least one first status signal S and at least one second status signal D.

[0032] In one embodiment, the first status detection circuit 111 receives a plurality of blanking detection voltages VLED1~VLEDN, a first blanking threshold voltage VTHL, and a second blanking threshold voltage VTHH, and compares each blanking detection voltage VLEDi with the first blanking threshold voltage VTHL and the second blanking threshold voltage VTHH respectively, and generates at least one first status signal S according to the comparison result. In another embodiment, the second status detection circuit 112 receives the downstream feedback signal VFBI, a first downstream threshold voltage VTH1, and a second downstream threshold voltage VTH2, and compares the downstream feedback signal VFBI with the first downstream threshold voltage VTH1 and the second downstream threshold voltage VTH2 respectively, and generates at least one second status signal D according to the comparison result.

[0033] In one embodiment, at least one first status signal S includes a first upward status signal UP_S and a first downward status signal DOWN_S. Among them, the first status detection circuit 111 compares each clearance detection voltage VLEDi with the first clearance threshold voltage VTHL respectively to generate the first upward status signal UP_S; and compares each clearance detection voltage VLEDi with the second clearance threshold voltage VTHH respectively to generate the first downward status signal DOWN_S. In one embodiment, when any one of the clearance detection voltages VLEDi is less than the first clearance threshold voltage VTHL, the first upward status signal UP_S is logically valid; when each clearance detection voltage VLEDi is greater than the second clearance threshold voltage VTHH, the first downward status signal DOWN_S is logically valid; when each clearance detection voltage VLEDi is between the first clearance threshold voltage VTHL and the second clearance threshold voltage VTHH, both the first upward status signal UP_S and the first downward status signal DOWN_S are logically invalid.

[0034] In another embodiment, at least one second status signal D includes a second upward status signal UP_D and a second downward status signal DOWN_D. Among them, the second status detection circuit 112 compares the downstream feedback signal VFBI with the first downstream threshold voltage VTH1 to generate the second upward status signal UP_D; and compares the downstream feedback signal VFBI with the second downstream threshold voltage VTH2 to generate the second downward status signal DOWN_D. In one embodiment, when the downstream feedback signal VFBI is greater than the first downstream threshold voltage VTH1, the second upward status signal UP_D is logically valid; when the downstream feedback signal VFBI is less than the second downstream threshold voltage VTH2, the second downward status signal DOWN_D is logically valid; when the downstream feedback signal VFBI is between the first downstream threshold voltage VTH1 and the second downstream threshold voltage VTH2, both the second upward status signal UP_D and the second downward status signal DOWN_D are logically invalid.

[0035] Figure 2 A first status detection circuit 200 according to an embodiment of the present invention. The first status detection circuit 200 includes an upward status detection circuit 201 and a downward status detection circuit 202. The upward status detection circuit 201 receives a plurality of clearance detection voltages VLED1 to VLEDN and the first clearance threshold voltage VTHL, and compares each clearance detection voltage VLEDi with the first clearance threshold voltage VTHL respectively to generate the first upward status signal UP_S. When any one of the clearance detection voltages VLEDi is less than the first clearance threshold voltage VTHL, the first upward status signal UP_S is logically valid (such as logic "1"); when each clearance detection voltage VLEDi is not less than the first clearance threshold voltage VTHL, the first upward status signal UP_S is logically invalid (such as logic "0").

[0036] As shown Figure 2 in FIG. [FIGURE REFERENCE], the upward state detection circuit 201 includes a plurality of first comparators CMPL1 to CMPLN, a plurality of first flip-flops FFL1 to FFLN, and an OR gate circuit OR. Each first comparator CMPLi has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the corresponding blanking detection voltage VLEDi, and the second input terminal receives the first blanking threshold voltage VTHL. In one embodiment, the first input terminal of the first comparator CMPLi is the inverting input terminal, and the second input terminal is the non-inverting input terminal. The first comparator CMPLi compares the blanking detection voltage VLEDi with the first blanking threshold voltage VTHL and provides a first comparison signal SCMPLi at the output terminal. When the blanking detection voltage VLEDi is less than the first blanking threshold voltage VTHL, the first comparison signal SCMPLi is logically valid (such as logic "1"); when the blanking detection voltage VLEDi is not less than the first blanking threshold voltage VTHL, the first comparison signal SCMPLi is logically invalid (such as logic "0").

[0037] Each first flip-flop FFLi has a first input terminal DLi and an output terminal QLi. The first input terminal DLi is coupled to the corresponding first comparator CMPLi to receive the first comparison signal SCMPLi and generates a first trigger signal SQLi at the output terminal DLi according to the first comparison signal SCMPLi at the first input terminal DLi. As shown Figure 2 in FIG. [FIGURE REFERENCE], the first flip-flop FFLi further has a second input terminal CKLi to receive the clock signal SCKi. During operation, when the clock signal SCKi is valid (such as changing from logic "1" to logic "0"), the first flip-flop FFLi samples and holds the first comparison signal SCMPLi and outputs the sampled and held signal as the first trigger signal SQLi. Therefore, when the sampled and held first comparison signal SCMPLi is logically valid, the first trigger signal SQLi is logically valid; when the sampled and held first comparison signal SCMPLi is logically invalid, the first trigger signal SQLi is logically invalid. In one embodiment, the clock signal SCKi is a pulse width modulation signal used to adjust the current flowing through the LED string SLEDi to achieve PWM dimming.

[0038] The OR gate circuit OR has a plurality of input terminals and an output terminal. The plurality of input terminals are respectively coupled to the plurality of first flip-flops FFL1 to FFLN to receive the plurality of first trigger signals SQL1 to SQLN and generate a first upward state signal UP_S at the output terminal according to the plurality of first trigger signals SQL1 to SQLN. Specifically, when any one of the first trigger signals SQLi is logically valid, the first upward state signal UP_S is logically valid; when all the first trigger signals are logically invalid, the first upward state signal UP_S is logically invalid.

[0039] In Figure 2 In the illustrated embodiment, the downward state detection circuit 202 receives a plurality of blanking detection voltages VLED1 to VLEDN and a second blanking threshold voltage VTHH, and compares each blanking detection voltage VLEDi with the second blanking threshold voltage VTHH to generate a first downward state signal DOWN_S. Specifically, when each blanking detection voltage VLEDi is greater than the second blanking threshold voltage VTHH, the first downward state signal DOWN_S is logically valid (such as logic "1"); when any one of the blanking detection voltages VLEDi is not greater than the second blanking threshold voltage VTHH, the first downward state signal DOWN_S is logically invalid (such as logic "0").

[0040] The downward state detection circuit 202 includes a plurality of second comparators CMPH1 to CMPHN, a plurality of inverters INV1 to INV, a plurality of second flip-flops FFH1 to FFHN, and an AND gate circuit AND. Each second comparator CMPHi has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the corresponding blanking detection voltage VLEDi, and the second input terminal receives the second blanking threshold voltage VTHH. In one embodiment, the first input terminal of the second comparator CMPHi is an inverting input terminal, and the second input terminal is a non-inverting input terminal. The second comparator CMPHi compares the blanking detection voltage VLEDi with the second blanking threshold voltage VTHH, and provides a second comparison signal SCMPHi at the output terminal, wherein when the blanking detection voltage VLEDi is greater than the second blanking threshold voltage VTHH, the second comparison signal SCMPHi is logically valid (such as logic "0"); when the blanking detection voltage VLEDi is not greater than the second blanking threshold voltage VTHH, the second comparison signal SCMPHi is logically invalid (such as logic "1").

[0041] Each inverter INVi has an input terminal and an output terminal, wherein the input terminal is coupled to the corresponding second comparator CMPHi to receive the second comparison signal SCMPHi, and inverts the second comparison signal SCMPHi, and provides an inverted comparison signal SCMPHi' at the output terminal. When the second comparison signal SCMPHi is logically valid, the inverted comparison signal SCMPHi' is logically valid (such as logic "1"); when the second comparison signal SCMPHi is logically invalid, the inverted comparison signal SCMPHi' is logically invalid (such as logic "0").

[0042] Each second flip-flop FFHi has a first input terminal DHi and an output terminal QHi, wherein the first input terminal DHi is coupled to the corresponding inverter INVi to receive the inverted comparison signal SCMPHi', and generates a second trigger signal SQHi according to the inverted comparison signal SCMPHi'. As Figure 2As shown, the second flip-flop FFHi also has a second input terminal CKHi for receiving a clock signal SCKi. When the clock signal SCKi is logically valid, the second flip-flop FFHi samples and holds the inverted comparison signal SCMPHi′, and outputs the sampled and held signal as the second trigger signal SQHi. Therefore, when the sampled and held inverted comparison signal SCMPHi′ is logically valid, the second trigger signal SQHi is logically valid; when the sampled and held inverted comparison signal SCMPHi′ is logically invalid, the second trigger signal SQHi is logically invalid.

[0043] The AND gate circuit AND has a plurality of input terminals and an output terminal, wherein the plurality of input terminals are respectively coupled to a plurality of second flip-flops FFH1 to FFHN to receive a plurality of second trigger signals SQH1 to SQHN, and generate a first down state signal DOWN_S according to the plurality of second trigger signals SQH1 to SQHN. Specifically, when each second trigger signal SQHi is logically valid, the first down state signal DOWN_S is logically valid; when any one of the second trigger signals SQHi is logically invalid, the first down state signal DOWN_S is logically invalid.

[0044] Those of ordinary skill in the art can understand that the first state detection circuit 200 is merely an exemplary illustration and does not limit the present invention in any way. In another embodiment, Figure 1 the first state detection circuit 200 shown can adopt a structure different from Figure 2 that shown. For example, Figure 2 the plurality of first comparators CMPL1 to CMPLN and the plurality of second comparators CMPH1 to CMPHN in can be replaced by only a string of comparators CMP1 to CMPN, wherein each comparator CMPi has a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal receives the corresponding clearance detection voltage VLEDi, the second input terminal receives the first clearance threshold voltage VTHL, and the third input terminal receives the second clearance threshold voltage VTHH. The comparator CMPi compares the clearance detection voltage VLEDi with the first clearance threshold voltage VTHL and the second clearance threshold voltage VTHH respectively, and generates a comparison signal. Subsequently, the comparison signal is fed into a downstream circuit to generate a first up state signal UP_S and a first down state signal DOWN_S.

[0045] Figure 3The second state detection circuit 300 according to an embodiment of the present invention. The second state detection circuit 300 includes a first comparator CMP1 and a second comparator CMP2. The first comparator CMP1 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a downstream feedback signal VFBI, and the second input terminal receives a first downstream threshold voltage VTH1. In one embodiment, the first input terminal is the non-inverting terminal, and the second input terminal is the inverting terminal. The first comparator CMP1 compares the downstream feedback signal VFBI with the first downstream threshold voltage VTH1 to generate a first comparison signal SCMP1, wherein when the downstream feedback signal VFBI is greater than the first downstream threshold voltage VTH1, the first comparison signal SCMP1 is logically valid (such as logic "1"); when the downstream feedback signal VFBI is less than the first downstream threshold voltage VTH1, the first comparison signal SCMP1 is logically invalid (such as logic "0").

[0046] The second comparator CMP2 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a downstream feedback signal VFBI, and the second input terminal receives a second downstream threshold voltage VTH2. In one embodiment, the first input terminal is the inverting terminal, and the second input terminal is the non-inverting terminal. The second comparator CMP2 compares the downstream feedback signal VFBI with the second downstream threshold voltage VTH2 to generate a second comparison signal SCMP2, wherein when the downstream feedback signal VFBI is less than the second downstream threshold voltage VTH2, the second comparison signal SCMP2 is logically valid (such as logic "1"); when the downstream feedback signal VFBI is greater than the second downstream threshold voltage VTH2, the second comparison signal SCMP2 is logically invalid (such as logic "0").

[0047] The second state detection circuit 300 further includes a first flip-flop FF1 and a second flip-flop FF2. The first flip-flop FF1 has a first input terminal D1 and an output terminal Q1, wherein the first input terminal D1 receives the first comparison signal SCMP1, and the first flip-flop FF1 generates a second upward state signal UP_D according to the first comparison signal SCMP1. The first flip-flop FF1 further has a second input terminal CK1 to receive a clock signal SCK1. When the clock signal SCK1 is valid (such as changing from logic "1" to logic "0"), the first flip-flop FF1 samples and holds the first comparison signal SCMP1, and outputs the sampled and held signal as the second upward state signal UP_D. Therefore, when the sampled and held first comparison signal SCMP1 is logically valid, the second upward state signal UP_D is logically valid (such as logic "1"); when the sampled and held first comparison signal SCMP1 is logically invalid, the second upward state signal UP_D is logically invalid (such as logic "0"). In one embodiment, the clock signal SCK1 is a pulse width modulation signal used to adjust the current flowing through the LED string SLEDi to achieve PWM dimming.

[0048] The second flip-flop FF2 has a first input terminal D2 and an output terminal Q2. The first input terminal D2 receives a second comparison signal SCMP2. The second flip-flop FF2 generates a second down state signal DOWN_D according to the second comparison signal SCMP2. The second flip-flop FF2 further has a second input terminal CK2 to receive a clock signal SCK2. When the clock signal SCK2 is valid (such as changing from logic "1" to logic "0"), the second flip-flop FF2 samples and holds the second comparison signal SCMP2, and outputs the sampled and held signal as the second down state signal DOWN_D. Therefore, when the sampled and held second comparison signal SCMP2 is logically valid, the second down state signal DOWN_D is logically valid (such as logic "1"); when the sampled and held second comparison signal SCMP2 is logically invalid, the second down state signal DOWN_D is logically invalid (such as logic "0").

[0049] In one embodiment, at least one first state signal S includes a first up state signal UP_S and a first down state signal DOWN_S, at least one second state signal D includes a second up state signal UP_D and a second down state signal DOWN_D, and at least one state signal ST includes an up state signal UP and a down state signal DOWN. The state detection circuit 101 generates an up state signal UP according to the first up state signal UP_S and the second up state signal UP_D, and generates a down state signal DOWN according to the first down state signal DOWN_S and the second down state signal DOWN_D. When any one of the blanking detection voltages VLEDi is less than the first blanking threshold voltage VTHL or the downstream feedback signal VFBI is greater than the first downstream threshold voltage VTH1, the up state signal UP is logically valid; when each blanking detection voltage VLEDi is greater than the second blanking threshold voltage VTHH and the downstream feedback signal VFBI is less than the second downstream threshold voltage VTH2, the down state signal DOWN is logically valid; when each blanking detection voltage VLEDi is between the first blanking threshold voltage VTHL and the second blanking threshold voltage VTHH and the downstream feedback signal VFBI is between the first downstream threshold voltage VIH1 and the second downstream threshold voltage VTH2, both the up state signal UP and the down state signal DOWN are logically invalid. The first feedback control circuit 102 generates a first feedback control signal VFBO1 according to the up state signal UP and the down state signal DOWN.

[0050] Continue Figure 1, the status detection circuit 101 further includes a logic circuit 113. The logic circuit 113 is coupled to the first status detection circuit 111 to receive the first upward status signal UP_S and the first downward status signal DOWN_S, and at the same time is coupled to the second status detection circuit 112 to receive the second upward status signal UP_D and the second downward status signal DOWN_D. The logic circuit 113 generates an upward status signal UP according to the first upward status signal UP_S and the second upward status signal UP_D, and generates a downward status signal DOWN according to the first downward status signal DOWN_S and the second downward status signal DOWN_D.

[0051] Figure 4 is a logic circuit 400 according to an embodiment of the present invention. The logic circuit 400 includes an OR gate circuit ORL and an AND gate circuit ANDL. The first input terminal of the OR gate circuit ORL receives the first upward status signal UP_S, and the second input terminal receives the second upward status signal UP_D. The OR gate circuit ORL provides an upward status signal UP according to the first upward status signal UP_S and the second upward status signal UP_D. The first input terminal of the AND gate circuit ANDL receives the first downward status signal DOWN_S, and the second input terminal receives the second downward status signal DOWN_D. The AND gate circuit ANDL provides a downward status signal DOWN according to the first downward status signal DOWN_S and the second downward status signal DOWN_D.

[0052] Figure 5 is a second feedback control circuit 500 according to an embodiment of the present invention. As Figure 5 shown, the second feedback control circuit 500 includes a counting circuit 501, a modulation circuit 502, and a buffer BUF.

[0053] The counting circuit 501 receives the upward status signal UP and the downward status signal DOWN, and generates a counting signal CT according to the upward status signal UP and the downward status signal DOWN. Specifically, according to the upward status signal UP and the downward status signal DOWN, the counting signal CT can count in the first direction, count in the second direction, or remain unchanged, where the second direction is opposite to the first direction.

[0054] Those of ordinary skill in the art can understand that in one embodiment, the first direction is the direction in which the counting signal CT counts and increases, and the second direction is the direction in which the counting signal CT counts and decreases. In another embodiment, the first direction is the direction in which the counting signal CT counts and decreases, and the second direction is the direction in which the counting signal CT counts and increases. In one embodiment, the counting signal CT is a digital signal.

[0055] The modulation circuit 502 is coupled to the counting circuit 501 to receive the counting signal CT, and generates a modulation signal MOD according to the counting signal CT, where the modulation signal MOD changes with the change of the counting signal CT. Specifically, according to the counting signal CT, the modulation signal MOD can increase, decrease, or remain unchanged. In one embodiment, the modulation signal MOD is a voltage signal.

[0056] The buffer BUF has a first input terminal, a second input terminal, and an output terminal, where the first input terminal is coupled to the modulation circuit 502 to receive the modulation signal MOD, the output terminal is coupled to the second input terminal, and generates a buffer signal SB according to the modulation signal MOD. In one embodiment, the first input terminal is the non-inverting input terminal, and the second input terminal is the inverting input terminal. In Figure 5 the illustrated embodiment, the second feedback control signal VFBO2 is the buffer signal SB itself without any processing. In another embodiment, the buffer signal SB is further processed to generate the second feedback control signal VFBO2.

[0057] During operation, when any one of the blanking detection voltages VLEDi is less than the first blanking threshold voltage VTHL or the downstream feedback signal VFBI is greater than the first downstream threshold voltage VTH1, the up state signal UP is logically valid (such as logic "1"); when each blanking detection voltage VLEDi is greater than the second blanking threshold voltage VTHH and the downstream feedback signal VFBI is less than the second downstream threshold voltage VTH2, the down state signal DOWN is logically valid; when each blanking detection voltage VLEDi is between the first blanking threshold voltage VTHL and the second blanking threshold voltage VTHH, and the downstream feedback signal VFBI is between the first downstream threshold voltage VTH1 and the second downstream threshold voltage VTH2, both the up state signal UP and the down state signal DOWN are logically invalid. When the up state signal UP is logically valid, the counting signal CT counts in the first direction (such as counting up); when the down state signal DOWN is logically valid, the counting signal CT counts in the second direction (such as counting down); when both the up state signal UP and the down state signal DOWN are logically invalid, the counting signal CT remains unchanged. When the counting signal CT counts in the first direction, the modulation signal MOD decreases; when the counting signal CT counts in the second direction, the modulation signal MOD increases; when the counting signal CT remains unchanged, the modulation signal MOD also remains unchanged.

[0058] Table 1 shows the counting circuit 112T according to an embodiment of the present invention. The counting circuit 112T receives an up state signal UP and a down state signal DOWN, and generates a count signal CT according to the up state signal UP and the down state signal DOWN. The count signal CT is data D[L-1] to D[0] with L bits, where L is an integer greater than 0. Specifically, when the up state signal UP is logically valid, the counting circuit 112T adds 1 to the data D[L-1] to D[0] based on the current state. Conversely, when the down state signal DOWN is logically valid, the counting circuit 112T subtracts 1 from the data D[L-1] to D[0] based on the current state. When both the up state signal UP and the down state signal DOWN are logically invalid, the counting circuit 112T keeps the data D[L-1] to D[0] unchanged. For example, when L = 8, as shown in Table 1, the counting circuit 112T includes 256 states S1 to S256. Assume that the current state of the counting circuit 112T is S2, that is, the count signal CT is 00000001. When the up state signal UP is logically valid, the counting circuit 112T adds 1 to the data, that is, the count signal CT increases to 00000010; when the down state signal DOWN is logically valid, the counting circuit 112T subtracts 1 from the data, that is, the count signal CT decreases to 00000000; when both the up state signal UP and the down state signal DOWN are logically invalid, the count signal CT remains 00000001 unchanged. In addition, the counting circuit 112T also receives a count clock signal. When the count clock signal is logically valid (such as changing from logic "0" to logic "1"), if the up state signal UP is logically valid, the counting circuit 112T adds 1 to the data D[L-1] to D[0]; if the down state signal DOWN is logically valid, the counting circuit 112T subtracts 1 from the data D[L-1] to D[0].

[0059] Table 1

[0060] Status D[L-1] D[6] D[5] …… …… D[2] D[1] D[0] S1 0 0 0 0 0 0 0 0 S2 0 0 0 0 0 0 0 1 S3 0 0 0 0 0 0 1 0 …… …… …… …… …… …… …… …… …… S255 0 1 1 1 1 1 1 1 S256 1 1 1 1 1 1 1 1

[0061] Figure 6 is the modulation circuit 600 according to an embodiment of the present invention. As Figure 6As shown, modulation circuit 600 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first end and a second end, and the first end receives a supply voltage VCC. In one embodiment, the supply voltage VCC is a bias voltage VBIAS. The second resistor R2 has a first end and a second end, and the first end of the second resistor R2 is coupled to the second end of the first resistor R1 and provides a modulation signal MOD, and the second end of the second resistor R2 is coupled to a reference ground GND. The resistance value of the second resistor R2 is controlled by a count signal CT. In one embodiment, when the count signal CT counts in a first direction, the resistance value of the second resistor R2 decreases; when the count signal CT counts in a second direction, the resistance value of the second resistor R2 increases; when the count signal CT remains unchanged, the resistance value of the second resistor R2 also remains unchanged. In one embodiment, the second resistor R2 includes a plurality of resistors and a plurality of switches, and the count signal CT can control the plurality of switches to enable and disable the corresponding resistors to change the resistance value of the second resistor R2.

[0062] Figure 7 A first feedback control circuit 700 according to an embodiment of the present invention. As Figure 7 shown, the first feedback control circuit 700 includes a first switch S1, a second switch S2, and resistors R3, R4. The first switch S1 has a first end, a second end, and a control end, and the first end is coupled to the first end of R3, the second end is coupled to the second end of R3, and the control end receives an upward state signal UP. The second switch S2 has a first end, a second end, and a control end, and the first end is coupled to the first end of R4, the second end is coupled to the second end of R4, and the control end receives a downward state signal DOWN. Both the resistors R3 and R4 have a first end and a second end, the first end of R3 receives a supply voltage VDD, the first end of R4 is coupled to the second end of R3 to provide a first feedback control signal VFBO1, and the second end of R4 is coupled to a reference ground GND.

[0063] During operation, when any one of the blanking detection voltages VLEDi is less than the first blanking threshold voltage VTHL or the downstream feedback signal VFBI is greater than the first downstream threshold voltage VTH1, the upward status signal UP is logically valid (e.g., logic "1"), and the downward status signal DOWN is logically invalid (e.g., logic "0"). The first switch S1 is turned on, and the second switch S2 is turned off. The first feedback control signal VFBO1 is equal to the supply voltage VDD. When each blanking detection voltage VLEDi is greater than the second blanking threshold voltage VTHH and the downstream feedback signal VFBI is less than the second downstream threshold voltage VTH2, the upward status signal UP is logically invalid (e.g., logic "0"), and the downward status signal DOWN is logically valid (e.g., logic "1"). The first switch S1 is turned off, and the second switch S2 is turned on. The first feedback control signal VFBO1 is equal to the reference ground. When each blanking detection voltage VLEDi is between the first blanking threshold voltage VTHL and the second blanking threshold voltage VTHH and the downstream feedback signal VFBI is between the first downstream threshold voltage VTH1 and the second downstream threshold voltage VTH2, both the upward status signal UP and the downward status signal DOWN are logically invalid. Both the first switch S1 and the second switch S2 are turned off, and the first feedback control signal VFBO1 = VDD×R4 / (R3+R4). In one embodiment, the resistances of resistors R3 and R4 are equal, so the first feedback control signal VFBO1 = VDD / 2.

[0064] Figure 8 An LED driving system 800 according to an embodiment of the present invention. The LED driving system 800 includes a plurality of LED driving circuits CLED1 to CLEDP, where k is an integer from 1 to P, and P is an integer greater than 1. As Figure 8 shown, each LED driving circuit CLEDk (k = 1, 2,..., P) is used to drive an LED array ALEDk. As previously described, the LED array ALEDk receives a bias voltage VBIAS and provides a plurality of blanking detection voltages VLEDk1 to VLEDkN.

[0065] In Figure 8 the embodiment of, the LED driving circuit CLEDk may include some or all of the functions and / or architectures of the LED driving circuit shown in the above embodiment. As Figure 8As shown, the LED driver circuit CLEDk receives the downstream feedback signal VFBIk and provides a feedback control signal VFBOCk. The LED driver circuits CLED1 to CLED(P-1) are respectively coupled to the LED driver circuits CLED2 to CLEDP, so as to receive the corresponding feedback control signals VFBOC2 to VFBOCP as the downstream feedback signals VFBI1 to VFBI(P-1). Specifically, the second state detection circuits of the LED driver circuits CLED1 to CLED(P-1) are respectively coupled to the first feedback control circuits of the LED driver circuits CLED2 to CLEDP to receive the corresponding first feedback control signals as the downstream feedback signals VFBI1 to VFBI(P-1).

[0066] As Figure 8 shown, the LED driver circuit CLED1 serves as the main driver circuit and is coupled to the voltage converter 801, where the voltage converter 801 generates a bias voltage VBIAS according to the feedback control signal VFBOC1 and uses the bias voltage VBIAS to supply power to a plurality of LED arrays ALED1 to ALEDP. In the driver circuit CLED1, the selection circuit 104 receives a mode signal MODE1 having a first mode and selects the second feedback control signal VFBO2 as its feedback control signal VFBOC1 according to the mode signal MODE1. The other LED driver circuits CLED2 to CLEDP serve as slave driver circuits. The selection circuit 104 receives mode signals MODE2 to MODEP having a second mode and selects the first feedback control signal VFBO1 as the feedback control signals VFBOC2 to VFBOCP according to the mode signals MODE2 to MODEP, and provides the feedback control signals VFBOC2 to VFBOCP to the upstream LED driver circuits CLED1 to CLED(P-1) respectively.

[0067] In one embodiment, the first feedback control signals VFBO1 generated by the LED driver circuits CLED1 to CLEDP are used to indicate the states of the LED driver circuits CLED1 to CLEDP. In another embodiment, the downstream feedback signals VFBI1 to VFBI(P-1) received by the LED driver circuits CLED1 to CLED(P-1) are used to indicate whether the corresponding downstream LED driver circuits CLED2 to CLEDP are coupled to the LED driver circuits CLED1 to CLED(P-1), and when the corresponding downstream LED driver circuits CLED2 to CLEDP are coupled to the LED driver circuits CLED1 to CLED(P-1), further indicate the states of the downstream LED driver circuits CLED2 to CLEDP. As Figure 8As shown, the LED driving circuit CLEDP is the last slave LED driving circuit of the LED driving system 800. The received downstream feedback signal VFBIP is coupled to the reference ground, which is used to indicate that no downstream LED driving circuit is coupled to the LED driving circuit CLEDP.

[0068] Next, the working principle of the LED driving system 800 will be described. In the LED driving circuit CLEDP, the received downstream feedback signal VFBIP is coupled to the reference ground (such as 0V), which is less than the second downstream threshold voltage (such as 0.3V). Therefore, the second up state signal UP_D is logically invalid, and the second down state signal DOWN_D is logically valid. At this time, the up state signal UP is determined by the first up state signal UP_S, and the down state signal DOWN is determined by the first down state signal DOWN_S. When any one of the blanking detection voltages VLEDPi is less than the first blanking threshold voltage VTHL, the first up state signal UP_S is logically valid, and the first down state signal DOWN_S is logically invalid. Therefore, the up state signal UP is logically valid, and the down state signal DOWN is logically invalid. The mode signal MODEP is in the second mode, and the LED driving circuit CLEDP selects the first feedback control signal VFBO1 as the feedback control signal VFBOCP. In the first feedback control circuit, the first switch S1 is turned on, and the second switch S2 is turned off. Therefore, the first feedback control signal VFBO1, that is, the feedback control signal VFBOCP, is equal to the supply voltage VDD. The LED driving circuit CLED(P-1) receives this feedback control signal VFBOCP as the downstream feedback signal VFBI(P-1). In the LED driving circuit CLED(P-1), regardless of whether the blanking detection voltage VLED(P-1)i is less than the first blanking threshold voltage VTHL, since the downstream feedback signal VFBI(P-1) is greater than the first downstream threshold voltage VTH1 (such as 0.75V), it can be obtained that the second up state signal UP_D is logically valid, and the second down state signal DOWN_S is logically invalid. Then the up state signal UP is logically valid, and the down state signal DOWN is logically invalid. As a result, the feedback control signal VFBOC(P-1) is also equal to the supply voltage VDD. The working principles of the LED driving circuits CLED2 to CLED(P-2) are similar to that of CLED(P-1), and it can be deduced that the feedback control signal VFBOC2 is equal to the supply voltage VDD. In the LED driving circuit CLED1, the received downstream feedback signal VFBI1, that is, the feedback control signal VFBOC2, is greater than the first downstream threshold voltage VTH1, and the up state signal UP is logically valid. Therefore, the feedback control signal VFBOC1 decreases, and the bias voltage VBIAS increases to an appropriate value, so that each blanking detection voltage VLEDPi in the LED array ALEDP is not less than the first blanking threshold voltage VTHL.

[0069] Similarly, when any one of the multiple blanking detection voltages of the LED arrays ALED1 to ALEDP is less than the first blanking threshold voltage VTHL, the first upward state signal UP_S of the corresponding LED driving circuit CLEDi is logically valid, and the first downward state signal DOWN_S is logically invalid. Therefore, the upward state signal UP is logically valid, and the downward state signal DOWN is logically invalid. From this, it can be deduced that the feedback control signal VFBOC2 is equal to the supply voltage VDD. In the LED driving circuit CLED1, the downstream feedback signal VFBI1 it receives, that is, the feedback control signal VFBOC2 is greater than the first downstream threshold voltage VTH1, and the upward state signal UP is logically valid. Thus, the feedback control signal VFBOC1 decreases, and the bias voltage VBIAS increases to an appropriate value to supply power to the LED arrays ALED1 to ALEDP.

[0070] When each of the multiple blanking detection voltages of the LED arrays ALED1 to ALEDP is greater than the second blanking threshold voltage VTHH, the first upward state signal UP_S of the corresponding LED driving circuit CLEDi is logically invalid, and the first downward state signal DOWN_S is logically valid. Consequently, the upward state signal UP is logically invalid, and the downward state signal DOWN is logically valid. It can be deduced that the feedback control signal VFBOC2 is equal to the reference ground GND. In the LED driving circuit CLED1, the downstream feedback signal VFBI1 it receives, that is, the feedback control signal VFBOC2 is less than the second downstream threshold voltage VTH2, and the downward state signal DOWN is logically valid. Thus, the feedback control signal VFBOC1 increases, and the bias voltage VBIAS decreases to an appropriate value to supply power to the LED arrays ALED1 to ALEDP.

[0071] When each of the multiple blanking detection voltages of the LED arrays ALED1 to ALEDP is between the first blanking threshold voltage VTHL and the second blanking threshold voltage VTHH, both the first upward state signal UP_S and the first downward state signal DOWN_S of the corresponding LED driving circuit CLEDi are logically invalid, and the second upward state signal UP_D and the second downward state signal DOWN_D are also logically invalid. Therefore, both the upward state signal UP and the downward state signal DOWN are logically invalid. It can be deduced that the feedback control signal VFBOC2 is also equal to VDD / 2. In the LED driving circuit CLED1, the downstream feedback signal VFBI1 it receives, that is, the feedback control signal VFBOC2 is equal to VDD / 2, and both the upward state signal UP and the downward state signal DOWN are logically invalid. The feedback control signal VFBOC1 remains unchanged. Therefore, the bias voltage VBIAS also remains unchanged to supply power to the LED arrays ALED1 to ALEDP.

[0072] The LED driving system of the present invention has a master-slave structure. The downstream LED driving circuit sequentially transmits its status to the upstream LED driving circuit until it reaches the first LED driving circuit CLED1. This driving scheme takes into account the status of all LED driving circuits and can adjust the bias voltage VBIAS to the desired value to power a large number of LED strings. The LED driving system of the present invention has a simple structure and high efficiency.

[0073] While the invention has been described with reference to several exemplary embodiments, it is to be understood that the terms used are illustrative and exemplary terms, rather than limiting. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above-described embodiments are not limited to any of the foregoing details, but rather should be construed broadly within the spirit and scope defined by the appended claims, and therefore all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. An LED driving circuit for driving a plurality of LED strings, wherein each LED string has a first end for receiving a bias voltage and a second end for providing a blanking detection voltage, and the LED driving circuit includes: A first state detection circuit coupled to the plurality of LED strings to receive a plurality of blanking detection voltages and generating at least one first state signal based on the plurality of blanking detection voltages; A second state detection circuit receiving a downstream feedback signal and generating at least one second state signal based on the downstream feedback signal, wherein the downstream feedback signal is used to indicate whether there is a downstream LED driving circuit coupled to the LED driving circuit and, when a downstream LED driving circuit is coupled to the LED driving circuit, indicates the state of the downstream LED driving circuit; And A first feedback control circuit generating a first feedback control signal based on the at least one first state signal and the at least one second state signal, wherein the first feedback control signal is used to indicate the state of the LED driving circuit; Wherein The downstream LED driving circuit has the same structure as the LED driving circuit.

2. The LED driving circuit according to claim 1, wherein: When any one of the plurality of blanking detection voltages is less than a first blanking threshold voltage or the downstream feedback signal is greater than a first downstream threshold voltage, the first feedback control signal has a first value; When each of the plurality of blanking detection voltages is greater than a second blanking threshold voltage and the downstream feedback signal is less than a second downstream threshold voltage, the first feedback control signal has a second value; And When each of the plurality of blanking detection voltages is between the first blanking threshold voltage and the second blanking threshold voltage and the downstream feedback signal is between the first downstream threshold voltage and the second downstream threshold voltage, the first feedback control signal has a third value.

3. The LED driving circuit according to claim 1, wherein: The at least one first state signal includes a first upward state signal and a first downward state signal. The first state detection circuit compares each of the plurality of blanking detection voltages with the first blanking threshold voltage to generate the first upward state signal, and compares each of the plurality of blanking detection voltages with the second blanking threshold voltage to generate the first downward state signal; The at least one second state signal includes a second upward state signal and a second downward state signal. The second state detection circuit compares the downstream feedback signal with the first downstream threshold voltage to generate the second upward state signal, and compares the downstream feedback signal with the second downstream threshold voltage to generate the second downward state signal; And Wherein the first feedback control circuit generates the first feedback control signal based on the first upward state signal, the first downward state signal, the second upward state signal, and the second downward state signal.

4. The LED driving circuit according to claim 3, wherein the first feedback control circuit includes: A first resistor having a first end and a second end, wherein the first end receives a supply voltage; A second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second end of the first resistor to provide the first feedback control signal, and the second end of the second resistor is coupled to a reference ground; A first switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled to the first terminal of a first resistor, the second terminal of the first switch is coupled to the second terminal of the first resistor, and the control terminal is controlled by a first upward state signal and a second upward state signal; and A second switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first resistor, the second terminal of the second switch is coupled to a reference ground, and the control terminal is controlled by a first downward state signal and a second downward state signal.

5. The LED driving circuit according to claim 3, further comprising a logic circuit, wherein the logic circuit includes: An OR gate circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to a first state detection circuit to receive the first upward state signal, the second input terminal is coupled to a second state detection circuit to receive the second upward state signal, and the OR gate circuit generates an upward state signal based on the first upward state signal and the second upward state signal; An AND gate circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to a first state detection circuit to receive the first downward state signal, the second input terminal is coupled to a second state detection circuit to receive the second downward state signal, and the AND gate circuit generates a downward state signal based on the first downward state signal and the second downward state signal; and wherein the first feedback control circuit generates the first feedback control signal based on the upward state signal and the downward state signal.

6. The LED driving circuit according to claim 1, wherein when the downstream LED driving circuit has the same state as the LED driving circuit, the downstream feedback signal has the same value as the first feedback control signal.

7. An LED driving circuit for driving a plurality of LED strings, wherein each LED string has a first terminal for receiving a bias voltage and a second terminal for providing a clearance detection voltage, and the LED driving circuit includes: A first state detection circuit that receives a plurality of clearance detection voltages and generates at least one first state signal based on the plurality of clearance detection voltages; A second state detection circuit that receives a downstream feedback signal and generates at least one second state signal based on the downstream feedback signal, wherein the downstream feedback signal is used to indicate whether there is a downstream LED driving circuit coupled to the LED driving circuit and, when a downstream LED driving circuit is coupled to the LED driving circuit, indicates the state of the downstream LED driving circuit; A first feedback control circuit that generates a first feedback control signal based on the at least one first state signal and the at least one second state signal, wherein the first feedback control signal is used to indicate the state of the LED driving circuit; A second feedback control circuit that generates a second feedback control signal based on the at least one first state signal and the at least one second state signal; and A selection circuit that receives a mode signal and selects the first feedback control signal or the second feedback control signal as the feedback control signal based on the mode signal.

8. The LED driving circuit according to claim 7, wherein the at least one first status signal includes a first upward status signal and a first downward status signal, and the at least one second status signal includes a second upward status signal and a second downward status signal, wherein: The first status detection circuit receives a plurality of blanking detection voltages, a first blanking threshold voltage, and a second blanking threshold voltage, compares each of the plurality of blanking detection voltages with the first blanking threshold voltage to generate a first upward status signal, and compares each of the plurality of blanking detection voltages with the second blanking threshold voltage to generate a first downward status signal; The second status detection circuit receives a downstream feedback signal, a first downstream threshold voltage, and a second downstream threshold voltage, compares the downstream feedback signal with the first downstream threshold voltage to generate a second upward status signal, and compares the downstream feedback signal with the second downstream threshold voltage to generate a second downward status signal; and wherein based on the first upward status signal, the first downward status signal, the second upward status signal, and the second downward status signal, the first feedback control circuit and the second feedback control circuit respectively generate a first feedback control signal and a second feedback control signal.

9. The LED driving circuit according to claim 8, further comprising a logic circuit, wherein the logic circuit includes: An OR gate circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the first status detection circuit to receive the first upward status signal, the second input terminal is coupled to the second status detection circuit to receive the second upward status signal, and the OR gate circuit generates an upward status signal based on the first upward status signal and the second upward status signal; An AND gate circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the first status detection circuit to receive the first downward status signal, the second input terminal is coupled to the second status detection circuit to receive the second downward status signal, and the AND gate circuit generates a downward status signal based on the first downward status signal and the second downward status signal; and wherein based on the upward status signal and the downward status signal, the first feedback control circuit and the second feedback control circuit respectively generate a first feedback control signal and a second feedback control signal.

10. The LED driving circuit according to claim 7, wherein when the mode signal has a first mode, the selection circuit selects the second feedback control signal as the feedback control signal, and the LED driving circuit is coupled to a voltage converter and provides the feedback control signal to the voltage converter to adjust the bias voltage.

11. The LED driving circuit according to claim 7, wherein when the mode signal has a second mode, the selection circuit selects the first feedback control signal as the feedback control signal, and the LED driving circuit is coupled to an upstream LED driving circuit and provides the feedback control signal to the upstream LED driving circuit.

12. The LED driving circuit according to claim 7, wherein: when any one of the plurality of blanking detection voltages is less than the first blanking threshold voltage or the downstream feedback signal is greater than the first downstream threshold voltage, the first feedback control signal has a first value; When each of the plurality of blanking detection voltages is greater than the second blanking threshold voltage and the downstream feedback signal is less than the second downstream threshold voltage, the first feedback control signal has a second value; and When each of the plurality of blanking detection voltages is between the first blanking threshold voltage and the second blanking threshold voltage and the downstream feedback signal is between the first downstream threshold voltage and the second downstream threshold voltage, the first feedback control signal has a third value.

13. The LED driving circuit according to claim 7, wherein the first feedback control circuit comprises: a first resistor having a first end and a second end, wherein the first end receives a supply voltage; a second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the second end of the first resistor to provide the first feedback control signal, and the second end of the second resistor is coupled to a reference ground; a first switch having a first end, a second end and a control end, wherein the first end of the first switch is coupled to the first end of the first resistor, the second end of the first switch is coupled to the second end of the first resistor, and the control end is controlled by the at least one first status signal and the at least one second status signal; and a second switch having a first end, a second end and a control end, wherein the first end of the second switch is coupled to the second end of the first resistor, the second end of the second switch is coupled to a reference ground, and the control end is controlled by the at least one first status signal and the at least one second status signal.

14. The LED driving circuit according to claim 7, wherein the second feedback control circuit comprises: a counting circuit that generates a counting signal based on the at least one first status signal and the at least one second status signal, wherein the counting signal counts in a first direction, counts in a second direction opposite to the first direction, or remains unchanged; a modulation circuit that generates a modulation signal based on the counting signal; and a buffer having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the modulation circuit to receive the modulation signal, the output terminal is coupled to the second input terminal and provides a buffer signal, and the second feedback control signal is generated based on the buffer signal.

15. An LED driving system, comprising: a first LED driving unit; and a second LED driving unit, wherein both the first LED driving unit and the second LED driving unit include an LED driving circuit, wherein each LED driving circuit drives a plurality of LED lamp strings respectively, and each LED lamp string has a first end receiving a bias voltage and a second end providing a blanking detection voltage, and the LED driving circuit comprises: a first status detection circuit coupled to the plurality of LED lamp strings to receive a plurality of blanking detection voltages and generating at least one first status signal based on the plurality of blanking detection voltages; a second status detection circuit that receives a downstream feedback signal and generates at least one second status signal based on the downstream feedback signal, wherein the downstream feedback signal is used to indicate whether a downstream LED driving circuit is coupled to the LED driving circuit and, when a downstream LED driving circuit is coupled to the LED driving circuit, indicates the status of the downstream LED driving circuit; and A first feedback control circuit generates a first feedback control signal based on the at least one first status signal and the at least one second status signal, wherein the first feedback control signal is used to indicate the status of the LED driving circuit; Wherein the second status detection circuit of the first LED driving unit is coupled to the first feedback control circuit of the second LED driving unit to receive the first feedback control signal of the second LED driving unit as the downstream feedback signal of the first LED driving unit.

16. The LED driving system according to claim 15, wherein the downstream feedback signal received by the first LED driving unit is used to indicate the status of the second LED driving unit.

17. The LED driving system according to claim 15, wherein: When any one of the multiple blanking detection voltages received by the second LED driving unit is less than the first blanking threshold voltage, or when the downstream feedback signal it receives is greater than the first downstream threshold voltage, the first feedback control signal generated by the second LED driving unit has a first value; When each of the multiple blanking detection voltages received by the second LED driving unit is greater than the second blanking threshold voltage, and the downstream feedback signal it receives is less than the second downstream threshold voltage, the first feedback control signal generated by the second LED driving unit has a second value; and When each of the multiple blanking detection voltages received by the second LED driving unit is between the first blanking threshold voltage and the second blanking threshold voltage, and the downstream feedback signal it receives is between the first downstream threshold voltage and the second downstream threshold voltage, the first feedback control signal generated by the second LED driving unit has a third value.

18. The LED driving system according to claim 15, wherein: The at least one first status signal includes a first upward status signal and a first downward status signal. The first status detection circuit compares each of the multiple blanking detection voltages with the first blanking threshold voltage to generate the first upward status signal, and compares each of the multiple blanking detection voltages with the second blanking threshold voltage to generate the first downward status signal; The at least one second status signal includes a second upward status signal and a second downward status signal. The second status detection circuit compares the downstream feedback signal with the first downstream threshold voltage to generate the second upward status signal, and compares the downstream feedback signal with the second downstream threshold voltage to generate the second downward status signal; And Wherein the first feedback control circuit generates the first feedback control signal based on the first upward status signal, the first downward status signal, the second upward status signal, and the second downward status signal.

19. The LED driving system according to claim 18, wherein the LED driving circuit further includes a logic circuit, and the logic circuit includes: An OR gate circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the first status detection circuit to receive the first upward status signal, the second input terminal is coupled to the second status detection circuit to receive the second upward status signal, and the OR gate circuit generates an upward status signal based on the first upward status signal and the second upward status signal; An AND gate circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to a first state detection circuit to receive a first downward state signal, and the second input terminal is coupled to a second state detection circuit to receive a second downward state signal. The AND gate circuit generates a downward state signal based on the first downward state signal and the second downward state signal; and wherein the first feedback control circuit generates a first feedback control signal based on the upward state signal and the downward state signal.

20. The LED driving system according to claim 15, wherein the LED driving circuit further comprises: a second feedback control circuit that generates a second feedback control signal based on the at least one first state signal and the at least one second state signal; and a selection circuit that receives a mode signal and selects the first feedback control signal or the second feedback control signal as the feedback control signal based on the mode signal.

21. The LED driving system according to claim 20, wherein the first LED driving unit is coupled to a voltage converter to receive a bias voltage, and the first LED driving unit provides the second feedback control signal to the voltage converter to adjust the bias voltage.

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