A data analysis method, system, medium, and electronic device

Abstract

The application provides a data analysis method, system, medium and electronic equipment. The method comprises: acquiring at least one group of detection data of a wafer to be analyzed; for any one group of detection data, identifying the wafer to be analyzed according to a corresponding detection standard to generate a defect identification map of the wafer to be analyzed; performing a superposition operation on each defect identification map to generate a comprehensive defect map of the wafer to be analyzed, and performing data analysis on the wafer to be analyzed according to the comprehensive defect map. The technical scheme of the application can integrate the detection data of each process section, clearly show the evolution of defects and process problems, and provide effective data support for process improvement and equipment monitoring.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a data analysis method, system, computer-readable medium, computer program product, and electronic device. Background Technology

[0002] During the online wafer inspection process, due to the different production processes, the generated inspection data is distributed in various independent workshops. Moreover, the generated inspection data is scattered and in different forms, making it inconvenient to conduct overall analysis and process improvement. Summary of the Invention

[0003] The embodiments of this application provide a data analysis method, system, computer-readable medium, computer program product, and electronic device, which can at least to some extent integrate the detection data of each process stage, clarify the evolution of defects and process problems, and provide effective data support for process improvement and equipment monitoring.

[0004] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0005] According to one aspect of the embodiments of this application, a data analysis method is provided, the method comprising: acquiring at least one set of inspection data of a wafer to be analyzed; for any set of inspection data, identifying the wafer to be analyzed according to a corresponding inspection standard to generate a defect identification map of the wafer to be analyzed; performing an overlay operation on the defect identification maps to generate a comprehensive defect map of the wafer to be analyzed; and performing data analysis on the wafer to be analyzed based on the comprehensive defect map.

[0006] In some embodiments of this application, obtaining at least one set of test data for the wafer to be analyzed includes: collecting test output data from different testing machines for the wafer to be analyzed to obtain at least one set of test data.

[0007] In some embodiments of this application, the step of identifying the wafer to be analyzed according to the corresponding detection standard for any set of detection data includes: generating a mesh map of the wafer to be analyzed; and identifying the mesh map according to the corresponding detection standard for any set of detection data.

[0008] In some embodiments of this application, based on the foregoing scheme, the step of marking the mesh map according to the corresponding detection standard for any set of detection data includes: for any set of detection data, determining the location of the defect in the wafer to be analyzed according to the corresponding detection standard; mapping the location of the defect in the wafer to be analyzed onto the mesh map, and marking the mesh with the defect.

[0009] In some embodiments of this application, the overlay operation of each defect identification image includes: assigning a corresponding fill color to each defect identification image, the fill color being used to fill the identified grids in each defect identification image, and adjusting the transparency of the unidentified grids to 100%; determining the positive direction of each defect identification image and the center position of the wafer in each defect identification image; and overlaying each defect identification image on the same layer according to the positive direction of each defect identification image and the center position of the wafer in each defect identification image.

[0010] In some embodiments of this application, the step of performing data analysis on the wafer to be analyzed based on the comprehensive defect map includes: analyzing the defect distribution of the wafer to be analyzed based on the comprehensive defect map, and generating a quality analysis report for the wafer to be analyzed.

[0011] In some embodiments of this application, after acquiring at least one set of detection data for the wafer to be analyzed, the method further includes: storing each set of detection data in a database.

[0012] According to one aspect of this application, a data analysis system is provided, the system comprising: a data proxy module for acquiring at least one set of inspection data for a wafer to be analyzed; a data normalization module for identifying the wafer to be analyzed based on a corresponding inspection standard for any set of inspection data, generating a defect identification map of the wafer to be analyzed; and an overlay analysis module for performing an overlay operation on the various defect identification maps to generate a comprehensive defect map of the wafer to be analyzed, and performing data analysis on the wafer to be analyzed based on the comprehensive defect map.

[0013] According to one aspect of this application, a computer-readable storage medium is provided, wherein at least one piece of program code is stored therein, the at least one piece of program code being loaded and executed by a processor to perform the operations performed by the data analysis method described herein.

[0014] According to one aspect of this application, an electronic device is provided, including a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, the one or more programs including instructions for performing the data analysis method as described.

[0015] In some embodiments of this application, the technical solutions can simultaneously acquire detection data from different process stages of the wafer to be analyzed. Then, according to the corresponding detection standards, the wafer to be analyzed is marked. A comprehensive defect map of the wafer to be analyzed is generated through overlay operations. The degree of defects generated in different process stages of the wafer can be analyzed based on the comprehensive defect map. Finally, the production quality of the wafer to be analyzed can be comprehensively judged. To a certain extent, the detection data of each process stage can be integrated, the evolution of defects and process problems can be clarified, and effective data support can be provided for process improvement and equipment monitoring.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0018] Figure 1 A simplified flowchart of a data analysis method according to an embodiment of this application is shown;

[0019] Figure 2 A simplified flowchart of a data analysis method according to an embodiment of this application is shown;

[0020] Figure 3 A mesh diagram of a wafer to be analyzed according to an embodiment of this application is shown;

[0021] Figure 4 A simplified flowchart of a data analysis method according to an embodiment of this application is shown;

[0022] Figure 5 A uniformly processed mesh diagram of a wafer to be analyzed according to an embodiment of this application is shown;

[0023] Figure 6 A defect identification diagram corresponding to the COW of a wafer to be analyzed according to an embodiment of this application is shown;

[0024] Figure 7 A defect identification diagram corresponding to the EPI of the wafer to be analyzed according to an embodiment of this application is shown;

[0025] Figure 8 This paper shows a defect identification diagram corresponding to the COTZ of a wafer to be analyzed according to an embodiment of the present application;

[0026] Figure 9 A comprehensive defect map of a wafer to be analyzed according to one embodiment of this application is shown;

[0027] Figure 10 A quality analysis report of a wafer to be analyzed according to an embodiment of this application is shown;

[0028] Figure 11 A block diagram of a data analysis system according to an embodiment of this application is shown;

[0029] Figure 12 A block diagram of a data analysis system according to an embodiment of this application is shown;

[0030] Figure 13 A schematic diagram of the structure of a computer system suitable for implementing the electronic device of the present application is shown. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0035] It should be noted that "multiple" in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0036] Please see Figure 1 .

[0037] Figure 1 A simplified flowchart of a data analysis method according to an embodiment of this application is shown, as follows: Figure 1 As shown, the method may include steps S101-S103:

[0038] Step S101: Obtain at least one set of detection data for the wafer to be analyzed.

[0039] Step S102: For any set of test data, mark the wafer to be analyzed according to the corresponding test standard and generate a defect marking map of the wafer to be analyzed.

[0040] Step S103: Perform an overlay operation on each defect identifier map to generate a comprehensive defect map of the wafer to be analyzed, and perform data analysis on the wafer to be analyzed based on the comprehensive defect map.

[0041] In this application, detection data from different process stages of the wafer to be analyzed can be acquired simultaneously. Then, the wafer to be analyzed is marked according to the corresponding detection standards. A comprehensive defect map of the wafer to be analyzed is generated through overlay operation. The degree of defects generated by the wafer in different process stages can be analyzed based on the comprehensive defect map. Finally, the production quality of the wafer to be analyzed can be comprehensively judged. To a certain extent, the detection data of each process stage can be integrated, the evolution of defects and process problems can be clarified, and effective data support can be provided for process improvement and equipment monitoring.

[0042] In this application, the method for obtaining at least one set of test data for the wafer to be analyzed may include: collecting test output data of different testing machines for the wafer to be analyzed, and obtaining at least one set of test data.

[0043] In this application, obtaining at least one set of inspection data for the wafer to be analyzed may include inspection data from inspection equipment such as epitaxial defect inspection system (EPI), chip surface defect inspection system (COTZ), and chip appearance inspection system (COW).

[0044] In this application, the epitaxial defect detection system (EPI) can detect epitaxial defects in the wafer to be analyzed. The types of epitaxial defects that can be detected may include: impurity defects, ring-shaped defects, granular defects, scratch defects, fogging defects, and other epitaxial defects.

[0045] In this application, the chip surface defect detection system (COTZ) can detect surface defects of the wafer to be analyzed. The surface defects that can be detected may include: electrode defects, polysilicon defects, epitaxial defects, light-emitting area contamination, residual gold in the light-emitting area, ITO shedding, mesa residual gold, etc. The above defects need to be cleaned or repaired in a targeted manner.

[0046] In this application, the chip appearance inspection system (COW) can detect appearance defects of the wafer to be analyzed. The appearance defects that can be detected may include: wafer grid defects, wafer mesa abnormalities, scratches, dirt, black spots and other appearance defects.

[0047] The detection standards can be used to determine whether the wafer to be analyzed has the above-mentioned defect types, and the location of the defects can be located. However, the location is only based on the coordinate data corresponding to the coordinate system established by the wafer to be analyzed, and the distribution of each defect cannot be displayed intuitively.

[0048] In this application, the test data are distributed across various independent workshops according to different production processes, resulting in scattered and inconsistent data that is inconvenient for comprehensive analysis and process improvement. Therefore, DataX can be introduced to collect and manage the data from each group.

[0049] It should be noted that DataX, mentioned in this application, is a widely used offline data synchronization tool / platform within Alibaba Group, enabling efficient data synchronization between various heterogeneous data sources, including MySQL, SQL Server, Oracle, PostgreSQL, HDFS, Hive, HBase, OTS, and ODPS. DataX's advantages are significant: First, deployment is extremely simple; data synchronization can be performed on either physical machines or virtual machines as long as the network is accessible, greatly facilitating implementation and freeing users from the limitations of standard data synchronization product deployments. Second, it is an open-source product with virtually no cost.

[0050] Please see Figures 2 to 3 .

[0051] Figure 2 A simplified flowchart of a data analysis method according to an embodiment of this application is shown, as follows: Figure 2 As shown, the method for identifying the wafer to be analyzed according to the corresponding detection standard may include steps S201-S202:

[0052] Step S201: Generate a mesh diagram of the wafer to be analyzed.

[0053] Step S202: For any set of detection data, mark the grid diagram according to the corresponding detection standard.

[0054] In this application, for any set of test data, the location of the defect in the wafer to be analyzed can be determined according to the corresponding test standard; the location of the defect in the wafer to be analyzed can be mapped onto the mesh diagram, and the mesh with the defect can be marked.

[0055] In this application, the wafer to be analyzed is prone to unavoidable quality defects during the manufacturing process. To pinpoint the location of these defects, a mesh map can be generated for the wafer. Inspection data can be compared across each mesh; if the inspection data exceeds or fails to meet the inspection standards, the corresponding mesh can be identified.

[0056] In this application, the quality defects can be those detected by the epitaxial defect detection system (EPI), the chip surface defect detection system (COTZ), and the chip appearance inspection system (COW). The defects detected by the three detection systems can correspond to a variety of quality defects.

[0057] In this application, a set of different colors can be used to identify a quality defect. Grids that do not meet the detection standards are identified by one color, and grids that meet the detection standards are identified by another color. After the above operation, the location and extent of the quality defect on the wafer to be analyzed can be clearly shown on a grid diagram to facilitate subsequent data analysis.

[0058] For example, Figure 3 A mesh diagram of a wafer to be analyzed according to an embodiment of this application is shown. If, by comparing the test data with the test standards, scratches are found on mesh 301 and the corresponding test data does not meet the test standards, mesh 301 can be marked in black, while the remaining meshes that meet the test standards are marked in white. Therefore, the marked mesh diagram can intuitively display the specific location of the scratched defect meshes, thereby determining whether the wafer to be analyzed meets the factory requirements based on the distribution of scratch defects, or formulating a repair plan based on the specific location of the scratched defect meshes, facilitating targeted repair of mesh 301.

[0059] In this application, for the same defect, different grids can be identified with different shades of the same main color according to the severity of the defect.

[0060] In this application, only one type of quality defect can be analyzed on the wafer to be analyzed. For example, only the epitaxial defects detected by the epitaxial defect detection system (EPI) can be identified by the corresponding mesh map.

[0061] For meshes with impurities or defects, the corresponding meshes can be marked in blue;

[0062] For meshes exhibiting circular defects, the corresponding mesh can be marked in orange;

[0063] For meshes with granular defects, the corresponding mesh identifiers can be marked as light green, green, and dark green, respectively, according to the degree of defect, from high to low.

[0064] For grids with scratches or defects, the corresponding grids can be marked in yellow;

[0065] For grids with atomization defects, the corresponding grid labels can be marked as dark purple, purple, and light purple respectively, according to the degree of defect, from high to low.

[0066] The remaining grids without defects can be marked as gray.

[0067] Please see Figure 4 .

[0068] Figure 4 A simplified flowchart of a data analysis method according to an embodiment of this application is shown, as follows: Figure 4 As shown, the method for overlaying various defect identification images may include steps S401-S403:

[0069] Step S401: Assign a corresponding fill color to each defect identification image. The fill color is used to fill the identified grid in each defect identification image, and the transparency of the unidentified grid is adjusted to 100%.

[0070] Step S402: Determine the positive direction of each defect identification map and the center position of the wafer in each defect identification map.

[0071] Step S403: According to the positive direction of each defect identification image and the center position of the wafer in each defect identification image, stack the defect identification images on the same layer.

[0072] In this application, a set of different colors can be used to fill in a quality defect. Grids exceeding the detection standard are marked with one color, and grids not meeting the detection standard are marked with another color. After performing the above operation, the location and extent of the quality defect in the wafer to be analyzed can be clearly shown on a grid diagram, facilitating subsequent data analysis. Different colors need to be used for different detection data to clearly represent the differences between various quality defects.

[0073] In this application, at least one defect identification image filled with color can be superimposed on the same layer. After determining the position and positive direction, grids at the same position can be overlapped, so the distribution of at least one quality defect can be shown on one layer.

[0074] In this application, the transparency of the unmarked grids in each defect identification map can be adjusted to 100% to prevent color obscuring after overlay operation, which would seriously affect the accuracy of the composite defect map.

[0075] In this application, because defect data obtained through different detection systems often exhibit significant differences, and the corresponding generated defect identification maps are also prone to discrepancies, normalization processing can be performed on different defect identification maps to unify their grid size and grid position. Furthermore, to ensure that the defect identification results do not deviate significantly after overlay operations, the defect identification map with the smallest unit grid can be used as a baseline, and the grids of the remaining defect identification maps can be re-divided and repositioned. The already identified grids will be transformed into multiple smaller grids as they are divided, and the defect identification will also be divided accordingly, while their specific locations remain unchanged, thus not affecting the specific distribution of defects.

[0076] In this application, at least two defect identification images can be overlaid. For example, the overlay operation can be performed only on defect identification images generated by EPI and COW.

[0077] EPI data normalization processing: Generate coordinate constraints, generate EPI mesh diagram and perform corresponding defect identification;

[0078] COW data normalization processing: Generate COW mesh diagram and perform corresponding defect identification;

[0079] Data integration: Based on the grid size of the two defect identification maps, coordinate relationships are established, and the positions of each grid are divided, and then an overlay operation is performed.

[0080] For example, overlay operations can be performed only on the defect identification maps generated by COTZ and COW: In this application, because the formats of the detection data generated by COTZ and COW are similar, the two systems can share the same basic mesh map in actual operation. Therefore, it is only necessary to convert the data of the two systems and generate the corresponding defect mesh map to perform the overlay operation without having to reset the mesh size or mesh position.

[0081] Therefore, in this application, the defect identification maps of COTZ and COW can be overlaid first, and then the defect identification map corresponding to EPI can be overlaid, which can reduce the operation of resetting the mesh size or mesh position.

[0082] In this application, if a grid contains multiple different types of defects, the grid can be divided into multiple sub-grids based on the types of defects, and the colors corresponding to the different types of defects can be used to identify them.

[0083] For example, please see Figures 5 to 8 , Figure 5 A mesh diagram of a uniformly processed wafer to be analyzed according to an embodiment of this application is shown. Figure 6 This illustration shows a defect identification diagram corresponding to the COW of a wafer to be analyzed according to an embodiment of this application, such as... Figure 6 As shown, dirt defects appeared in meshes 601 and 602. Figure 7 This illustration shows a defect identification diagram corresponding to the EPI of the wafer to be analyzed according to one embodiment of this application, such as... Figure 7 As shown, grid 701 has a scratch defect. Figure 8 This paper shows a defect identification diagram corresponding to the COTZ of a wafer to be analyzed according to an embodiment of the present application, such as... Figure 8 As shown, ITO detachment defects occurred in meshes 801, 802, and 803.

[0084] Figures 6-8 All have been based on the unified processed grid diagram, i.e. Figure 5 Adjust the grid size and grid position to meet the requirements of the overlay operation.

[0085] Please see Figure 9 , Figure 9 A comprehensive defect map of a wafer to be analyzed according to one embodiment of this application is shown. As shown in the figures, Figure 9 for Figures 6 to 7 The composite defect map generated after stacking them on the same layer, with meshes 901 and 902 corresponding to each other. Figure 6 Mesh 601 and 602 show dirt defects, and mesh 903 corresponds to... Figure 7 The grids 701, 904, 905, and 906 that show scratch defects correspond to respectively Figure 8 Mesh 801, mesh 802, and mesh 803 show ITO detachment defects.

[0086] In this application, the method for performing data analysis on the wafer to be analyzed based on the comprehensive defect map may include: analyzing the defect distribution of the wafer to be analyzed based on the comprehensive defect map, and generating a quality analysis report for the wafer to be analyzed.

[0087] In this application, the generated comprehensive defect map can intuitively present the distribution of different types of defects on a wafer. Based on the data provided by the comprehensive defect map, the process segments where different types of defects occur can be analyzed. The impact of different types of defects on the wafer's outgoing quality can be analyzed, as can the proportion of different types of defects on the entire wafer. The proportion of a certain type of defect among all defects can also be analyzed. This can be used to determine whether the current wafer needs to undergo a repair process, whether the current wafer meets the outgoing requirements, and whether it can proceed to the next production process.

[0088] For example, Figure 10 A quality analysis report of a wafer to be analyzed according to an embodiment of this application is shown, such as... Figure 10 As shown, 1001 is the display area for basic information of the wafer to be analyzed, including wafer number, production time, and various inspection times. 1002 is the display area for the comprehensive defect map of the wafer to be analyzed, used to display the comprehensive defect map. The comprehensive defect map is displayed as a color image, allowing technicians to visually view the distribution of different types of defects. 1003 is the display area for defect distribution information of the wafer to be analyzed. In 1003, the distribution of different defects can be recorded or displayed: defect color, i.e., the color corresponding to 1002; defect quantity, i.e., the number of grids where the current defect occurs; defect ratio, which can be either the proportion of the current defect grid to all grids or the proportion of the current defect grid to all defect grids.

[0089] In 1003, the corresponding production process segment for the defect type can also be displayed. Therefore, technicians can not only analyze the production quality of wafers by relying on quality analysis reports, but also quickly find the process segment corresponding to serious defects and intervene to make adjustments as soon as possible.

[0090] The generated quality analysis reports can comprehensively assess the production quality of the wafers under analysis. To a certain extent, they can integrate the detection data from each process stage, clarify the evolution of defects and process problems, and provide effective data support for process improvement and equipment monitoring.

[0091] In this application, after obtaining at least one set of detection data for the wafer to be analyzed, the method may further include: storing each set of detection data in a database for later use in subsequent operations.

[0092] In this application, the test data of each group can be stored in a database according to different process flows. The test data can be the raw data detected by the testing system, the defect identification map corresponding to each group of test data, or the comprehensive defect map of the wafer to be analyzed. This allows technicians to easily access the data and adjust the production process according to the data in the database.

[0093] An embodiment of the apparatus of this application will now be described with reference to the accompanying drawings.

[0094] Please see Figure 11 .

[0095] Figure 11 A block diagram of a data analysis system according to an embodiment of this application is shown, such as Figure 11 As shown, the system includes: a data proxy module 1101, a data normalization module 1102, and an overlay graph analysis module 1103.

[0096] The specific configuration of the system can be as follows: a data proxy module 1101, used to acquire at least one set of inspection data for the wafer to be analyzed; a data normalization module 1102, used to identify the wafer to be analyzed according to the corresponding inspection standard for any set of inspection data, and generate a defect identification map of the wafer to be analyzed; and an overlay analysis module 1103, used to perform overlay operations on the various defect identification maps to generate a comprehensive defect map of the wafer to be analyzed, and perform data analysis on the wafer to be analyzed based on the comprehensive defect map.

[0097] For example, Figure 12 A block diagram of a data analysis system according to an embodiment of this application is shown, such as Figure 12 As shown, the data analysis system may include a data agent module (Agent), a data normalization module (Data Normalization), a database module (DB), a data storage module (Storage Server), a data mining module (Data Mining), an overlay analysis module (OverlayAnalysis), a virtual yield module (Virtual Yield), a statistical analysis module (Statistical Analysis), and a data analysis module (Data Analysis).

[0098] Please see Figure 13 .

[0099] Figure 13 A schematic diagram of the structure of a computer system suitable for implementing the electronic device of the present application is shown.

[0100] It should be noted that, Figure 13 The computer system 1300 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0101] like Figure 13As shown, the computer system 1300 includes a Central Processing Unit (CPU) 1301, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 1302 or programs loaded from storage portion 1308 into Random Access Memory (RAM) 1303, such as performing the methods described in the above embodiments. Various programs and data required for system operation are also stored in RAM 1303. The CPU 1301, ROM 1302, and RAM 1303 are interconnected via bus 1304. An Input / Output (I / O) interface 1305 is also connected to bus 1304.

[0102] The following components are connected to I / O interface 1305: an input section 1306 including a keyboard, mouse, etc.; an output section 1307 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1308 including a hard disk, etc.; and a communication section 1309 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 1309 performs communication processing via a network such as the Internet. A drive 1310 is also connected to I / O interface 1305 as needed. Removable media 1311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1310 as needed so that computer programs read from them can be installed into storage section 1308 as needed.

[0103] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1309, and / or installed from removable medium 1311. When the computer program is executed by central processing unit (CPU) 1301, it performs various functions defined in the system of this application.

[0104] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0105] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0106] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0107] In another aspect, this application also provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the data analysis method described in the above embodiments.

[0108] In another aspect, this application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to implement the data analysis method described in the above embodiments.

[0109] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0110] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the method according to the embodiments of this application.

[0111] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0112] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A data analysis method, characterized by, The method comprises: acquiring at least one set of detection data of a wafer to be analyzed; for any one set of detection data, identifying the wafer to be analyzed according to the corresponding detection standard to generate a defect identification map of the wafer to be analyzed; superimposing each defect identification map to generate a comprehensive defect map of the wafer to be analyzed, and performing data analysis on the wafer to be analyzed according to the comprehensive defect map; the method comprises: generating a grid map of the wafer to be analyzed; for any one set of detection data, identifying the grid map according to the corresponding detection standard; the method comprises: for any one set of detection data, judging the position of the wafer to be analyzed where defects occur according to the corresponding detection standard; mapping the position of the wafer to be analyzed where defects occur to the grid map to identify the grid where defects occur; the method comprises: allocating a corresponding fill color to each defect identification map, the fill color being used to fill the identified grid in each defect identification map, and adjusting the transparency of the grid not identified to 100; taking the defect identification map with the smallest unit grid as the reference, and repositioning the grid of the remaining defect identification maps; determining the positive direction of each defect identification map and the center position of the wafer in each defect identification map; stacking each defect identification map in the same layer according to the positive direction of each defect identification map and the center position of the wafer in each defect identification map.

2. The method of claim 1, wherein, The method comprises: collecting detection output data of different detection machines for the wafer to be analyzed to obtain at least one set of detection data.

3. The method of claim 1, wherein, The method comprises: analyzing the defect distribution of the wafer to be analyzed according to the comprehensive defect map to generate a quality analysis report for the wafer to be analyzed.

4. The method of claim 1, wherein, After acquiring at least one set of detection data of the wafer to be analyzed, the method further comprises: saving each set of detection data in a database.

5. A data analysis system, characterized by, The system comprises: a data agent module used to acquire at least one set of detection data of a wafer to be analyzed; a data normalization module used to identify the wafer to be analyzed according to the corresponding detection standard for any one set of detection data to generate a defect identification map of the wafer to be analyzed; the data normalization module is also used to generate a grid map of the wafer to be analyzed; for any one set of detection data, identifying the grid map according to the corresponding detection standard; for any one set of detection data, judging the position of the wafer to be analyzed where defects occur according to the corresponding detection standard; mapping the position of the wafer to be analyzed where defects occur to the grid map to identify the grid where defects occur; The overlay analysis module is configured to perform overlay operation on each defect identification map to generate a comprehensive defect map of the wafer to be analyzed, and perform data analysis on the wafer to be analyzed according to the comprehensive defect map. The overlay analysis module is further configured to assign a corresponding fill color to each defect identification map, fill the identified grid in each defect identification map with the fill color, adjust the transparency of the un-identified grid to 100, take the defect identification map with the smallest unit grid as a reference, and re-locate the grid of the remaining defect identification maps. Determine the positive direction of each defect identification map and the center position of the wafer in each defect identification map. Overlay each defect identification map on the same layer according to the positive direction of each defect identification map and the center position of the wafer in each defect identification map.

6. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program code, and the at least one program code is loaded and executed by the processor to implement the operations performed by the data analysis method according to any one of claims 1 to 4.

7. An electronic device, comprising: A memory and one or more programs are included, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs contain instructions for performing the data analysis method according to any one of claims 1 to 4.

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