Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a non-folding area and a folding area, wherein the non-folding area is arranged adjacent to the folding area, and the display panel is folded with reference to the folding area; and the display panel includes multiple data lines, multiple gate lines, and multiple gate drive units; the multiple data lines extend in the column direction, and the multiple gate lines extend in the row direction. The gate lines and the data lines intersect to define the area where the sub-pixels are located. The multiple gate drive units are arranged in sequence along the column direction, and the gate drive units are connected to the corresponding gate lines, and the gate lines are connected to the pixel drive circuits of the sub-pixels. Based on this, by arranging some components of the gate drive units located in the folding area in the non-folding area, the number of components in the folding area is appropriately reduced, thereby reducing stress concentration in the folding area, thereby reducing the possibility of electrical changes in the folding area circuit and circuit line breakage, and thus improving the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Foldable, portable display devices are an important development direction for future display devices. However, in current related technologies, when a display device is folded, stress concentration is high in the folding area, causing electrical changes in the circuits in the folding area and even breaking circuit traces, thus affecting the display quality in the folding area and even the entire display panel. Summary of the Invention

[0003] The present invention provides a display panel and a display device to reduce stress concentration in a folding area, thereby reducing the possibility of electrical changes in circuits in the folding area and circuit wiring breakage, and improving the display effect of the display panel.

[0004] According to one aspect of the present invention, there is provided a display panel including a non-folding area and a folding area, characterized in that it comprises:

[0005] A plurality of data lines extending along a column direction;

[0006] A plurality of gate lines extend along a row direction; the gate lines intersect with the data lines to define an area where a sub-pixel is located;

[0007] A plurality of gate driving units are sequentially arranged along a column direction; the gate driving units are connected to corresponding gate lines, and the gate lines are electrically connected to pixel driving circuits of sub-pixels;

[0008] The non-folding area is adjacent to the folding area, the display panel is folded with reference to the folding area, and some components of the gate driving unit located in the folding area are arranged in the non-folding area.

[0009] Optionally, the non-folding area includes a device setting area and a device reserved area;

[0010] The device reserved area is located between the device setting area and the folding area, the components of the gate driving unit located in the non-folding area are set in the device setting area, and some components of the gate driving unit located in the folding area are set in the device reserved area.

[0011] Optionally, the gate driving unit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is located in the non-folding area, and the second gate driving unit is located in the folding area.

[0012] Optionally, the first gate driving units are arranged at equal intervals in a direction from the non-folding area away from the adjacent folding area;

[0013] Preferably, the distance between two adjacent first gate driving units increases gradually from the direction where the non-folding area departs from the adjacent folding area.

[0014] Optionally, in the same non-folding area, the arrangement of components of the first gate driving unit that is relatively close to the adjacent folding area is different from the arrangement of components of the first gate driving unit that is relatively far from the same folding area;

[0015] Preferably, the components of the first gate driving unit relatively close to the folding area are arranged in m rows, and the components of the first gate driving unit relatively far from the folding area are arranged in n rows; wherein m and n are both positive integers and m<n;

[0016] Preferably, in the first gate driving unit relatively close to the folding area, the spacing between two adjacent components is a first spacing; in the first gate driving unit relatively far from the folding area, the spacing between two adjacent components is a second spacing; wherein the first spacing is smaller than the second spacing;

[0017] Preferably, the display panel includes a display area and a non-display area, and the sub-pixels are located in the display area; the components of the sub-pixels that are relatively close to the folding area and relatively close to the non-display area are arranged at non-equal intervals; some components of the first gate driving unit that are relatively close to the folding area are located in the display area.

[0018] Optionally, a folding axis is defined in the folding area;

[0019] The components of the second gate driving unit located in the folding area are arranged at equal intervals;

[0020] Preferably, in the folding area, the distance between two adjacent second gate driving units tends to decrease from the direction from the folding axis to the non-folding area;

[0021] Preferably, in the folding area, the distance between two adjacent components tends to decrease in the direction from the folding axis to the non-folding area, and the components are components of the second gate driving unit.

[0022] Optionally, the second gate driving unit includes a plurality of thin film transistors; the size of the thin film transistors of the second gate driving unit in the non-folding area is larger than the size of the thin film transistors of the second gate driving unit in the folding area;

[0023] Preferably, the second gate driving unit includes a plurality of capacitors, and at least one capacitor of the second gate driving unit is disposed in the non-folding area.

[0024] Optionally, the gate driving unit includes:

[0025] Scanning the first transistor, scanning the second transistor, scanning the third transistor, scanning the fourth transistor, scanning the fifth transistor, scanning the sixth transistor, scanning the seventh transistor, scanning the eighth transistor, scanning the first capacitor, and scanning the second capacitor;

[0026] The first end of the scanning first transistor is connected to the first enable signal, the second end of the scanning first transistor is connected to the first end of the scanning second transistor, and the control end of the scanning first transistor is connected to the first clock signal;

[0027] The second end of the second scanning transistor is connected to the first end of the third scanning transistor, and the control end of the second scanning transistor is connected to the second clock signal;

[0028] The second end of the third scanning transistor is connected to the first potential signal, and the control end of the third scanning transistor is connected to the first end of the fourth scanning transistor;

[0029] The second end of the fourth scanning transistor is connected to the first clock signal, and the control end of the fourth scanning transistor is connected to the second end of the first scanning transistor;

[0030] The first end of the fifth scanning transistor is connected to the first end of the fourth scanning transistor, the second end of the fifth scanning transistor is connected to the second potential signal, and the control end of the fifth scanning transistor is connected to the first clock signal;

[0031] The control end of the sixth scanning transistor is connected to the first end of the fifth scanning transistor, the first end of the sixth scanning transistor is connected to the first potential signal, and the second end of the sixth scanning transistor is connected to the output end of the gate driving unit;

[0032] A first end of the scanning seventh transistor is connected to the output end of the gate driving unit, a second end of the scanning seventh transistor is connected to the second clock signal, and a control end of the scanning seventh transistor is connected to the first end of the scanning eighth transistor;

[0033] The second end of the eighth scanning transistor is connected to the control end of the fourth scanning transistor, and the control end of the eighth scanning transistor is connected to the second potential signal;

[0034] The first scanning capacitor is connected between the control terminal and the first terminal of the sixth scanning transistor;

[0035] The second scanning capacitor is connected between the control terminal and the first terminal of the seventh scanning transistor;

[0036] The sixth scanning transistor, the seventh scanning transistor, the first scanning capacitor and the second scanning capacitor are arranged in the non-folding area.

[0037] Optionally, the gate driving unit includes:

[0038] a first light-emitting control transistor, a second light-emitting control transistor, a third light-emitting control transistor, a fourth light-emitting control transistor, a fifth light-emitting control transistor, a sixth light-emitting control transistor, a seventh light-emitting control transistor, an eighth light-emitting control transistor, a ninth light-emitting control transistor, a tenth light-emitting control transistor, a first light-emitting control capacitor, a second light-emitting control capacitor, and a third light-emitting control capacitor;

[0039] The first terminal of the first light-emitting control transistor is connected to the second enable signal, the second terminal of the first light-emitting control transistor is connected to the control terminal of the second light-emitting control transistor, and the control terminal of the first light-emitting control transistor is connected to the third clock signal;

[0040] The first end of the second light-emitting control transistor is connected to the first clock signal, and the second end of the second light-emitting control transistor is connected to the first end of the third light-emitting control transistor;

[0041] The second terminal of the third light-emitting control transistor is connected to the fourth potential signal, and the control terminal of the third light-emitting control transistor is connected to the third clock signal;

[0042] The control end of the fourth light-emitting control transistor is connected to the first end of the third light-emitting control transistor, the first end of the fourth light-emitting control transistor is connected to the third potential signal, and the second end of the fourth light-emitting control transistor is connected to the first end of the fifth light-emitting control transistor;

[0043] The second end of the fifth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, and the control end of the fifth light-emitting control transistor is connected to the fourth clock signal;

[0044] The control end of the sixth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, the first end of the sixth light-emitting control transistor is connected to the third potential signal, and the second end of the sixth light-emitting control transistor is connected to the first end of the seventh light-emitting control transistor;

[0045] The second end of the seventh light-emitting control transistor is connected to the first end of the eighth light-emitting control transistor, and the control end of the seventh light-emitting control transistor is connected to the fourth clock signal;

[0046] The second end of the eighth light-emitting control transistor is connected to the fourth clock signal, and the control end of the eighth light-emitting control transistor is connected to the first end of the third light-emitting control transistor;

[0047] A first end of the ninth light-emitting control transistor is connected to the third potential signal, a second end of the ninth light-emitting control transistor is connected to the output end of the gate driving unit, and a control end of the ninth light-emitting control transistor is connected to the second end of the sixth light-emitting control transistor;

[0048] A first end of the tenth light-emitting control transistor is connected to the output end of the gate driving unit, a second end of the tenth light-emitting control transistor is connected to the fourth potential signal, and a control end of the tenth light-emitting control transistor is connected to the second end of the first light-emitting control transistor;

[0049] The first light-emitting control capacitor is connected between the first terminal and the control terminal of the eighth light-emitting control transistor;

[0050] A first end of the second light-emitting control capacitor is connected to the control end of the tenth light-emitting control transistor, and a second end of the light-emitting control capacitor is connected to the fourth clock signal;

[0051] The third light-emitting control capacitor is connected between the control terminal and the first terminal of the ninth light-emitting control transistor;

[0052] Among them, the eighth light-emitting control transistor, the ninth light-emitting control transistor, the tenth light-emitting control transistor, the first light-emitting control capacitor, the second light-emitting control capacitor and the third light-emitting control capacitor are arranged in the non-folding area.

[0053] Optionally, the display panel further includes a clock line, a potential line and an enable line;

[0054] Each of the gate driving units is connected to the clock line, and each of the gate driving units is connected to the potential line; the enable line is used to provide a start signal to the gate driving unit; wherein, the clock line, the potential line and / or the enable line located between two adjacent gate driving units in the folding area are arranged at an angle in the plane where the display panel is located.

[0055] According to another aspect of the present invention, a display device is provided, characterized by comprising the display panel as described in the above aspect.

[0056] The technical solution of an embodiment of the present invention is as follows: a display panel includes a non-folding area and a folding area, wherein the non-folding area is arranged adjacent to the folding area, and the display panel is folded with reference to the folding area; and the display panel includes multiple data lines, multiple gate lines, and multiple gate driving units; the multiple data lines extend in the column direction, and the multiple gate lines extend in the row direction. The intersection of the gate lines and the data lines defines the area where the sub-pixels are located. The multiple gate driving units are arranged in sequence along the column direction, and the gate driving units are connected to corresponding gate lines, and the gate lines are connected to corresponding sub-pixels. Based on this, by disposing some components of the gate driving units located in the folding area in the non-folding area, the number of components in the folding area is appropriately reduced, thereby reducing stress concentration in the folding area, thereby reducing the possibility of electrical changes in the circuit in the folding area and circuit wiring breakage, and thus improving the display effect of the display panel.

[0057] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 This is a schematic structural diagram of a display panel in the related art;

[0060] Figure 2 is a schematic structural diagram of another display panel in the related art;

[0061] Figure 3 is a schematic structural diagram of another display panel in the related art;

[0062] Figure 4 This is a schematic structural diagram of a display device in the related art;

[0063] Figure 5 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0064] Figure 6 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0065] Figure 7 This is a schematic diagram of the arrangement of components of a first gate driving unit provided by an embodiment of the present invention;

[0066] Figure 8 This is a schematic diagram of another arrangement of components of a first gate driving unit provided by an embodiment of the present invention;

[0067] Figure 9 This is a schematic diagram of another arrangement of components of a first gate driving unit provided by an embodiment of the present invention;

[0068] Figure 10 is a structural diagram of a second gate driving unit provided by an embodiment of the present invention;

[0069] Figure 11 is a structural diagram of another second gate driving unit provided by an embodiment of the present invention;

[0070] Figure 12 yes Figure 5 A partial enlarged view of the display panel shown;

[0071] Figure 13 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0072] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0073] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0074] As mentioned in the background, in current related technologies, when a display device is folded, stress concentration in the folding area is significant, causing changes in the electrical properties of the circuits in the folding area and even breaking of the circuit traces. After extensive research, the inventors have discovered the following specific reasons:

[0075] Figure 1 This is a schematic diagram of the structure of a display panel in the related art. Figure 1 The display panel includes a first non-folding area 12_1, a second non-folding area 12_2 and a folding area 11, wherein the folding area 11 is located between the first non-folding area 12_1 and the second non-folding area 12_2; the display panel includes gate lines 14, data lines 15 and a gate driving unit 13, wherein the gate lines 14 and the data lines 15 intersect to define the area where the sub-pixels are located, the gate lines 14 are connected to the corresponding sub-pixels, and the gate driving unit 13 is connected to the corresponding gate lines 14. Figure 1 Because the gate drive unit 13 is provided in the folding region 11, when the display panel is folded relative to the folding region 11, the gate drive unit 13 in the folding region 11 will bend, causing a greater stress concentration in the folding region 11. As the number of folds increases, the gate drive unit 13 in the folding region 11 is more likely to suffer from damaging fatigue, resulting in component damage and breakage of the wiring 16 between the gate drive units 13, that is, causing component failure in the folding region 11. When components fail, signals cannot be transmitted normally, which affects the display quality of the folding region 11 and, in severe cases, the display quality of the entire display panel.

[0076] Figure 2 This is a schematic diagram of the structure of another display panel in the related art. Figure 2 The display panel includes a non-folding area 22 and a folding area 21. The non-folding area 22 includes multiple first gate lines 24_1, multiple first data lines 25_1, multiple first sub-pixels, and multiple first gate driving units 23_1. The first gate lines 24_1 are connected to corresponding first sub-pixels, the first data lines 25_1 are connected to corresponding first sub-pixels, and the first gate driving units 23_1 are connected to corresponding first gate lines 24_1. The first gate lines 24_1 extend along the row direction x, and the first data lines 25_1 extend along the column direction y. The folding area 21 includes a plurality of second gate lines 24_2, a plurality of second data lines 25_2, a plurality of second sub-pixels, and a plurality of second gate driving units 23_2. The second gate lines 24_2 are connected to corresponding second sub-pixels, the second data lines 25_2 are connected to corresponding second sub-pixels, and the second gate driving units 23_2 are connected to corresponding second gate lines 24_2. The second gate lines 24_2 extend along the column direction y, and the second data lines 25_2 extend along the row direction x. Figure 2By designing the first gate driver unit 23_1 in the non-folding area 22 and the second gate driver unit 23_2 in the folding area 21 independently, the second gate driver unit 23_2 is protected from being affected by the bending of the display panel. However, this design still does not substantially reduce stress concentration in the folding area, and designing independent gate driver units in the non-folding area 22 and the folding area 21 can easily cause a split screen display.

[0077] Figure 3 This is a schematic diagram of the structure of another display panel in the related art. Figure 3 The display panel includes a first non-folding area 32_1, a second non-folding area 32_2 and a folding area 31. The folding area 31 is located between the first non-folding area 32_1 and the second non-folding area 32_2. The display panel includes a plurality of gate lines 35, a plurality of data lines 34, a plurality of first data pins 36_1 and a plurality of second data pins 36_2. The gate lines 35 pass through the first non-folding area 32_1, the folding area 31 and the second non-folding area 32_2 in sequence. The data lines 34 include a first data line 34_1 located in the first non-folding area 32_1 and a second data line 34_2 located in the second non-folding area 32_2. The first data line 34_1 is connected to the first data pin 36_1 located in the first non-folding area 32_1, and the second data line 34_2 is connected to the second data pin 36_2 located in the second non-folding area 32_2. The gate lines 35 extend along the column direction y, and the data lines 34 extend along the row direction x. Continue to refer to Figure 3 By aligning the extension direction of the data lines 34 with the folding axis KK', bending of the data lines 34 is avoided. Furthermore, because the gate lines 35 span the first non-folding region 32_1, the folding region 31, and the second non-folding region 32_2, scanning signals can be provided from both sides of the gate lines 35. However, while this design avoids the need to locate the gate drive unit 33 in the folding region 31, thereby preventing multiple bending of the gate drive unit in the folding region 31, the placement of the first data pins 36_1 and the second data pins 36_2 in the first non-folding region 32_1 and the second non-folding region 32_2, respectively, causes the flexible circuit board (not shown) connecting the first data pins 36_1 and the second data pins 36_2 to bend multiple times. This transfers the bending problem of the gate drive unit in the folding region 31 to the flexible circuit board, leaving the technical problem unresolved. Furthermore, the two binding regions can easily cause a split screen display.

[0078] Figure 4 This is a schematic diagram of the structure of a display device in the related art. Figure 4The display device includes a substrate 40, a plurality of gate lines, a plurality of data lines and a plurality of gate drivers 43. The gate driver 43 includes a plurality of gate driving blocks. The gate driving blocks are connected to corresponding gate lines. The gate lines extend along the row direction x and the data lines extend along the column direction y. Figure 4 The substrate 40 defines a fold line QQ' and a fold portion 41. By not placing the gate driver 43 on the fold line QQ', that is, not placing the gate driver 43 on the fold portion 41, and thus not placing devices such as thin-film transistors with overlapping electrodes on the fold portion 41, the gate driver 43 is not directly affected even if the display device is repeatedly folded. However, this design, because all gate driver blocks are placed in the non-folding area 42, results in a larger border in the non-folding area 42, which in turn results in a larger border in the display device.

[0079] In view of this, an embodiment of the present invention provides a display panel and a display device to specifically solve the technical problem of large stress concentration in the folding area, reduce the possibility of electrical changes in the circuit in the folding area and circuit wiring breakage, thereby improving the display effect of the display panel. At the same time, a narrow bezel design is achieved and a split screen display is avoided.

[0080] Figure 5 Schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 5 The display panel includes a non-folding area 52 and a folding area 51, and the display panel includes: a plurality of data lines 55 extending along the column direction y; a plurality of gate lines 54 extending along the row direction x; the gate lines 54 and the data lines 55 intersect to define the area where the sub-pixels are located; a plurality of gate driving units are arranged in sequence along the column direction y; the gate driving units 53 are connected to the corresponding gate lines 54, and the gate lines 54 are connected to the corresponding sub-pixels (specifically, the gate lines 54 can be electrically connected to the pixel driving circuits of the sub-pixels); wherein the non-folding area 52 is adjacent to the folding area 51, and the display panel is folded with reference to the folding area 51, and some components of the gate driving unit 53 located in the folding area 51 are arranged in the non-folding area 52.

[0081] Specifically, the display panel may be a flexible foldable display panel, and the display panel may have at least two non-folding areas 52 and at least one folding area 51, wherein the folding area 51 is located between two adjacent non-folding areas 52. Each folding area 51 defines a folding axis PP', and the display panel may be folded or bent (curved) along the folding axis within the folding area 51, so that the plane curvature of the display panel in the folding area 51 is not zero. Figure 5 exemplarily illustrates that the display panel has two non-folding areas 52 (ie, a first non-folding area 52_1 and a second non-folding area 52_2) and a folding area 51 (defined with a folding axis PP'), and the folding area 51 is located between the first non-folding area 52_1 and the second non-folding area 52_2.

[0082] Subpixels (not shown) are arranged within the area defined by the intersection of the data lines 55 and the gate lines 54. Multiple subpixels are arranged in an array within the display panel, covering the first non-folding area 52_1, the folding area 51, and the second non-folding area 52_2. The subpixels may include light-emitting elements and pixel drive circuits (referred to as pixel circuits). The light-emitting elements are connected to the pixel circuits, which are configured to drive the connected light-emitting elements to emit light according to drive signals, including data signals, scan signals, and initialization signals. The light-emitting elements are, for example, light-emitting diodes (LEDs).

[0083] The data signal is provided by the data line 55. The scan signal is provided by the gate line 54; the scan signal can be used as a scan signal Scan to drive switching transistors such as the data writing transistor and the initialization transistor, or as a light-emitting control signal EM to drive the light-emitting control transistor. Here, the data writing transistor refers to a switching transistor in the pixel circuit used to transmit a data signal to the storage capacitor, the initialization transistor is a switching transistor used to transmit an initialization signal to the gate of the driving transistor and / or the anode of the light-emitting element, and the light-emitting control transistor is a switching transistor used to control the light-emitting stage of the light-emitting element.

[0084] The driver in the display panel includes a data driver unit (not shown in the figure) and a gate driver unit 53. The data driver unit is connected to the corresponding data line 55 and is used to generate a data signal. The gate driver unit 53 is connected to the corresponding gate line 54 and is used to generate a scan signal. Each gate driver unit 53 can be used as a shift register, and multiple cascaded gate driver units 53 constitute multiple cascaded shift registers. The input end of the first-level gate driver unit 53 is connected to the start signal. The gate driver unit 53 can shift the start signal from its own output end according to the received clock signal and output it. The output is the scan signal. The input end of the next-level gate driver unit 53 can be connected to the output end of the previous-level gate driver unit 53.

[0085] Multiple gate drive units 53 are arranged sequentially along the column direction y around the periphery of the subpixel array. Gate drive units 53 are provided in the first non-folding area 52_1, the folding area 51, and the second non-folding area 52_2. Each gate drive unit 53 may include multiple components, i.e., multiple components electrically connected to form a gate drive unit 53. Components such as thin film transistors or capacitors may be formed. A thin film transistor may be formed by stacking an active layer and multiple metal film layers, while a capacitor may be formed by stacking multiple metal film layers.

[0086] As can be seen, when the display panel is folded with reference to the folding area 51, the gate drive unit 53 in the folding area 51 is bent because the gate drive unit 53 is provided in the folding area 51. The active layer and metal film layer constituting the components in the gate drive unit 53 are relatively hard, and generally the gate drive unit 53 contains a large number of components, which are densely arranged. Therefore, the stress concentration in the folding area 51 is relatively large. As the number of folding increases, the gate drive unit 53 in the folding area 51 is prone to damaging fatigue, resulting in damage to the components of the gate drive unit 53 and breakage of the wiring between the gate drive units 53. The wiring between the units 53 includes, but is not limited to, an enable line for providing a start signal, a clock line for providing a clock signal, and a potential line for providing a potential signal; the potential signal can be, for example, a potential signal with a relatively high voltage or a potential signal with a relatively low voltage.

[0087] In this regard, in the technical solution of this embodiment, some components of the gate driver unit 53 located in the folding area 51 are disposed in the non-folding area 52. For example, some components of the gate driver unit 53 located in the folding area 51 are disposed in the first non-folding area 52_1 and / or the second non-folding area 52_2, thereby appropriately reducing the number of components in the folding area 51. With fewer components in the folding area 51, the volume of the active layer and metal film layer in the folding area 51 is smaller, and the density of the component arrangement can be lower, thereby reducing stress concentration in the folding area 51. This embodiment thus reduces stress concentration in the folding area 51, thereby reducing the possibility of damage to components of the gate driver unit 53 in the folding area 51 and the possibility of broken wiring between units, allowing the gate driver unit 53 in the folding area 51 to generate and transmit signals normally and operate normally. This embodiment thus improves the stability, reliability, and display effect of the folding area 51 and the display panel.

[0088] At the same time, due to the technical solution of this embodiment, only part of the components of the gate driving unit 53 located in the folding area 51 are arranged in the non-folding area 52. If the folding area 51 is provided with multiple gate driving units 53, only part of the components of each gate driving unit 53 in the folding area 51 are arranged in the non-folding area 52. The area of ​​the non-folding area 52 occupied is very small, so compared with Figure 4 and Figure 3 The solution shown reduces the frame of the non-folding area 52, thereby reducing the frame of the display device and achieving a narrow frame design. Moreover, since the area occupied by the non-folding area 52 is very small, it is possible to avoid making large movements, changes, and adjustments to the arrangement of the gate drive units 53 in the non-folding area 52, thereby increasing the reliability of the non-folding area 52 and thus increasing the reliability of the display panel. Figure 3 and Figure 2The illustrated horizontal / vertical screen design avoids split-screen display, further enhancing the display quality. Furthermore, the technical solution of this embodiment reduces stress concentration in the folding region 51 by reducing the number of components in the folding region 51, while also softening the folding region 51, thereby improving the bending performance of the folding region 51 and thereby increasing the service life and reliability of the display panel.

[0089] Continue to refer Figure 5 As an embodiment of the present invention, optionally, the non-folding area 52 includes a device setting area 56 and a device reserved area 57; the device reserved area 57 is located between the device setting area 56 and the folding area 51; the components of the gate driving unit 53 located in the non-folding area 52 are set in the device setting area 56, and some components of the gate driving unit 53 located in the folding area 51 are set in the device reserved area 57; wherein the device setting area 56 and the device reserved area 57 are both located at the periphery of the sub-pixel array.

[0090] Specifically, the technical solution of this embodiment uses the non-folding area 52 as the area for arranging the gate driver unit 53, leaving a small area for arranging some components of the gate driver unit 53 of the folding area 51. The vacated small area is the device reserved area 57, and the unvacated area is the device setting area 56. The device setting area 56 is used to arrange the gate driver unit 53 of the non-folding area 52, and the device reserved area 57 is used to arrange some components of the gate driver unit 53 of the folding area 51. That is, the components in the gate driver unit 53 of the folding area 51 that need to be moved to the non-folding area 52 can be arranged in the device reserved area 57. The device reserved area 57 is set between the device setting area 56 and the non-folding area 52, so that the components moved from the gate driving unit 53 in the folding area 51 to the non-folding area 52 can be set nearby, so as to shorten the wiring length between the components in the gate driving unit 53 in the folding area 51 as much as possible, and shorten the wiring length between the folding area 51 and the non-folding area 52. This can not only reduce the IR-Drop (IR voltage drop) on the wiring, but also simplify the wiring around the sub-pixel array, thereby improving the reliability of the display panel.

[0091] For example, continue to refer to Figure 5The first non-folding area 52_1 may include a first device placement area 56_1 and a first device reserved area 57_1, and / or the second non-folding area 52_2 may include a second device placement area 56_2 and a second device reserved area 57_2. The first device placement area 56_1 is used to place the gate driver unit 53 of the first non-folding area 52_1, and the second device placement area 56_2 is used to place the gate driver unit 53 of the second non-folding area 52_2. The first device reserved area 57_1 is located between the first device placement area 56_1 and the folding area 51, and the second device reserved area 57_2 is located between the second device placement area 56_2 and the folding area 51. Components in the gate driver unit 53 of the folding area 51 that need to be moved to the non-folding area 52 can be placed in the first device reserved area 57_1 and / or the second device reserved area 57_2.

[0092] In the embodiment of the present invention, there are many ways to set the device setting area and the device reserved area in the non-folding area. The following is an exemplary description of several of them, but it does not limit the present invention. Among them, the gate driving unit 53 includes a first gate driving unit 53_1 and a second gate driving unit 53_2. The first gate driving unit 53_1 is set in the non-folding area 52, and the second gate driving unit 53_2 is set in the folding area 51. Figure 5 As shown in the figure, the first gate driving unit 53_1 is arranged in the first non-folding area 52_1 and the second non-folding area 52_2; the direction in which the non-folding area 52 deviates from the adjacent folding area 51 includes the direction in which the first non-folding area 52_1 deviates from the folding area 51, and the direction in which the second non-folding area 52_2 deviates from the folding area 51.

[0093] Continue to refer Figure 5 Optionally, in one embodiment of the present invention, the first gate driving units 53_1 are arranged at equal intervals in a direction from the non-folding area 52 away from the adjacent folding area 51 .

[0094] Specifically, in this embodiment, in the first non-folding area 52_1, the first gate driving units 53_1 are arranged at equal intervals in the direction from the first non-folding area 52_1 away from the folding area 51, and in the second non-folding area 52_2, the first gate driving units 53_1 are arranged at equal intervals in the direction from the second non-folding area 52_2 away from the folding area 51; thereby, the first device reserved area 57_1 is obtained by translating all the first gate driving units 53_1 in the first non-folding area 52_1 as a whole in the direction away from the folding area 51, and the second device reserved area 57_2 is obtained by translating all the first gate driving units 53_1 in the second non-folding area 52_2 as a whole in the direction away from the folding area 51.

[0095] Moreover, since in this embodiment only some components of the second gate driving unit 53_2 are arranged in the first non-folding area 52_1 or the second non-folding area 52_2, the first device reserved area 57_1 and the second device reserved area 57_2 do not need to be too large, and thus all the first gate driving units 53_1 do not need to be translated as a whole for too much distance in the non-folding area 52. Based on this, this embodiment achieves a narrow frame design while reducing stress concentration in the folding area 51.

[0096] refer to Figure 6 , Figure 6 This is a schematic structural diagram of another display panel provided by an embodiment of the present invention. In another embodiment of the present invention, optionally, as the non-folding area 52 moves away from the adjacent folding area 51, the distance between two adjacent first gate driving units 53_1 tends to increase (that is, the distance between two adjacent first gate driving units 53_1 increases sequentially).

[0097] For example, in the first non-folding area 52_1, the distance between two adjacent first gate driving units 53_1 tends to increase as the first non-folding area 52_1 deviates from the folding area 51, and in the second non-folding area 52_2, the distance between two adjacent first gate driving units 53_1 tends to increase as the second non-folding area 52_2 deviates from the folding area 51; thereby, the first device reserved area 57_1 is obtained by reducing the distance between two adjacent first gate driving units 53_1 in the first non-folding area 52_1 close to the folding area 51, and the second device reserved area 57_2 is obtained by reducing the distance between two adjacent first gate driving units 53_1 in the second non-folding area 52_2 close to the folding area 51. That is to say, by “pushing together” the first gate driving units 53_1 in the first non-folding area 52_1 along the column direction y so that they are compactly arranged in the column direction y, a small area is left in the first non-folding area 52_1 as the first device reserved area 57_1, and by “pushing together” the first gate driving units 53_1 in the second non-folding area 52_2 along the column direction y so that they are compactly arranged in the column direction y, a small area is left in the second non-folding area 52_2 as the second device reserved area 57_2.

[0098] Since the device reserved area 57 is located between the device placement area 56 and the folding area 51, the spacing between two adjacent first gate driving units 53_1 within the non-folding area 52 near the folding area 51 can be preferentially compressed and reduced to leave a small area for the device reserved area 57. Furthermore, since this embodiment only places some components of the second gate driving unit 53_2 in the area vacated by the first gate driving unit 53_1 in the non-folding area 52 (i.e., in the vacated device reserved area), without occupying any other area, the non-folding area 52 will not be enlarged. Consequently, this embodiment achieves a narrow bezel design while reducing stress concentration in the folding area 51.

[0099] Figure 7 1 is a schematic diagram of the arrangement of components of a first gate driving unit provided by an embodiment of the present invention. Figure 8 Schematic diagram of another arrangement of components of the first gate drive unit provided by an embodiment of the present invention. In another embodiment of the present invention, optionally, in the same non-folding area 52, the arrangement of the components D of the first gate drive unit that are relatively close to the adjacent folding area 51 (see Figure 8 ), and the arrangement of the components D of the first gate drive unit relatively far from the same folding area 51 (see Figure 7 ) is different, accordingly, a device reserved area 57 can also be reserved in the non-folding area 52.

[0100] Continue to refer Figure 7 and Figure 8 In another embodiment of the present invention, optionally, in the same non-folding area 52, the components of the first gate driving unit relatively close to the folding area 51 are arranged in m rows, and the components of the first gate driving unit relatively far from the folding area 51 are arranged in n rows; wherein m and n are both positive integers and m<n, Figure 7 The first gate driving unit can be Figure 6 The first gate driving unit 53_106 of the first non-folding area 52_1 (relatively far from the folding area 51), Figure 8 The first gate unit can be Figure 6 The first gate driving unit 53_101 of the first non-folding area 52_1 (relatively close to the folding area 51) is configured.

[0101] Specifically, the gate driver units 53 in a typical display panel have the same structure, meaning they contain the same types and numbers of components. Within the same non-folding region 52, the components of the first gate driver units 53_1 that are relatively far from the folding region 51 are arranged in n rows, while the components of the first gate driver units 53_1 that are relatively close to the folding region 51 are arranged in m rows. Consequently, the device reserved area 57 is created by placing fewer components of the first gate driver units 53_1 near the folding region 51 in the non-folding region 52 in the column direction y and more in the row direction x, thereby leaving a small area within the non-folding region 52 as the device reserved area 57. For example, the components of the first gate driver unit 53_101 and the components of the first gate driver unit 53_106 in the first non-folding area 52_1 were originally arranged in 4 rows and 3 columns. However, by arranging the components of the first gate driver unit 53_101 in 3 rows and 4 columns, a small area within the first non-folding area 52_1 is reserved as the first device area 57_1. Furthermore, since only some components of the second gate driver unit 53_2 are arranged in the first non-folding area 52_1 or the second non-folding area 52_2 in this embodiment, the first device area 57_1 and the second device area 57_2 do not need to be large. Consequently, there is no need to arrange a large number of components of the first gate driver unit 53_1 in the column direction y and a large number in the row direction x. Consequently, this embodiment achieves a narrow frame design while reducing stress concentration in the folding area 51.

[0102] Continue to refer Figure 7 and Figure 8 In another embodiment of the present invention, optionally, in the same non-folding area 52, in the first gate driving unit 53_101 relatively close to the folding area 51, the spacing between two adjacent components D is a first spacing L1; in the first gate driving unit 53_106 relatively far from the folding area 51, the spacing between two adjacent components D is a second spacing L2; the first spacing L1 is smaller than the second spacing L2.

[0103] Specifically, the distance between two adjacent components D in the first gate driving unit 53_1 which is relatively close to the folding area 51 is set to be smaller, which is not only conducive to vacating the device reserved area 57, but also helps to basically not cause the frame to increase during the process of vacating the device reserved area 57, thereby achieving a narrow frame design while reducing stress concentration in the folding area 51.

[0104] Figure 9 FIG. 1 is a schematic diagram of another arrangement of components of a first gate drive unit provided by an embodiment of the present invention. Figure 6 and Figure 9In another embodiment of the present invention, optionally, the display panel includes a display area AA and a non-display area NAA, and the sub-pixels are located in the display area AA; in the same non-folding area 52, the sub-pixels that are relatively close to the folding area 51 and relatively close to the non-display area NAA have their components arranged at non-equal intervals; some components of the first gate driving unit 53_1 that are relatively close to the folding area 51 are located in the display area AA.

[0105] Specifically, the components of the pixel circuits within sub-pixels relatively close to the folding area 51 and relatively close to the non-display area NAA may be arranged at unequal intervals, so that the components in the pixel circuits are "crowded" along the column direction y or the row direction x. This allows a small area relatively close to the folding area 51 and relatively close to the non-display area NAA to be used to place some components of the first gate driver unit 53_1, thereby allowing a small area in the non-folding area 52 to be used as a device reserved area 57. Since this embodiment squeezes some components of the first gate driver unit 53_1 into the display area AA, thereby freeing up the device reserved area 57 in the non-folding area 52, it does not cause an increase in the bezel. Based on this, this embodiment achieves a narrow bezel design while reducing stress concentration in the folding area 51.

[0106] Based on any of the above technical solutions, in the embodiment of the present invention, there are multiple ways to arrange the components of the second gate driving unit 53_2 located in the folding area 51. Several of them are exemplarily described below, but are not intended to limit the present invention.

[0107] In one embodiment of the present invention, optionally, the components of the second gate driving unit 53_2 located in the folding area 51 are arranged at equal intervals, that is, the components of the second gate driving unit 53_2 located in the folding area 51 are evenly distributed in the folding area 51, thereby further reducing the stress concentration in the folding area 51, and further softening the folding area 51, thereby improving the bending performance of the folding area 51.

[0108] In another embodiment of the present invention, optionally, in the folding region 51, the spacing between two adjacent second gate driving units 53_2 decreases as viewed from the folding axis PP' toward the non-folding region 52. That is, as viewed from the folding axis PP' toward the non-folding region 52, the spacing between two adjacent second gate driving units 53_2 farther from the folding axis PP' is relatively smaller, while the spacing between two adjacent second gate driving units 53_2 closer to the folding axis PP' is relatively larger. In other words, the second gate driving units 53_2 are more sparsely arranged in the region closer to the folding axis PP', thereby further reducing stress concentration in the folding region 51.

[0109] In another embodiment of the present invention, optionally, in the folding region 51, the spacing between two adjacent components, as viewed from the folding axis PP' toward the non-folding region 52, decreases, where the components are components of the second gate drive unit 53_2. That is, in the folding region 51, as viewed from the folding axis PP' toward the non-folding region 52, the spacing between two adjacent components farther from the folding axis PP' is relatively smaller, while the spacing between two adjacent components closer to the folding axis PP' is relatively larger. In other words, the components in the region closer to the folding axis PP' are more sparsely arranged and less clustered, thereby further reducing stress concentration in the folding region 51.

[0110] In the embodiment of the present invention, any components of the second gate driving unit 53_2 may be disposed in the non-folding area 52, and this embodiment does not specifically limit this. For example, based on the layout design of the first gate driving unit 53_1 and the second gate driving unit 53_2 in the display panel, a portion of the components of the second gate driving unit 53_2 may be selected and disposed in the non-folding area 52, with the premise that the layout design is substantially not adversely affected and the wiring is simplified.

[0111] In one embodiment of the present invention, optionally, the second gate driving unit 53_2 includes multiple thin film transistors; wherein the size of the thin film transistor of the second gate driving unit 53_2 arranged in the non-folding area 52 is larger than the size of the thin film transistor of the second gate driving unit 53_2 arranged in the folding area 51.

[0112] Specifically, among the multiple thin-film transistors typically included in the second gate driver unit 53_2, some are relatively small, while others are relatively large. The relatively large thin-film transistors experience relatively greater stress concentration. Moving the relatively large thin-film transistors from the folding region 51 to the non-folding region 52 not only significantly reduces stress concentration in the large thin-film transistors, protecting them from damage or electrical changes, but also effectively reduces the total component volume within the folding region 51, thereby effectively reducing stress concentration in the folding region 51, effectively softening the folding region 51, and improving the bending performance of the folding region 51. Furthermore, by specifically designing the components of the second gate driver unit 53_2 located in the folding region 51 to be relatively small, stress concentration in the folding region 51 can be further reduced, softening the folding region 51, and improving the bending performance of the folding region 51.

[0113] In another embodiment of the present invention, optionally, the second gate driving unit 53_2 further includes a plurality of capacitors; wherein at least one capacitor of the second gate driving unit 53_2 is disposed in the non-folding area 52 .

[0114] Specifically, the capacitors in the second gate driver unit 53_2 are generally used to ensure that the second gate driver unit 53_2 stably outputs scan signals. If the capacitors are damaged or electrically altered due to bending, it will more easily affect the normal operation of the second gate driver unit 53_2, thereby affecting the display of the folding area 51 and even the entire display panel. Accordingly, placing the capacitors of the second gate driver unit 53_2 in the non-folding area 52 not only avoids stress concentration on the capacitors and protects them from damage or electrical changes, but also effectively reduces the total component volume within the folding area 51, thereby effectively reducing stress concentration in the folding area 51, and effectively softening the folding area 51, improving the bending performance of the folding area 51.

[0115] As an embodiment of the present invention, optionally, the second gate driving unit 53_2 includes an 8T2C structure to output the scan signal Scan. Figure 10 is a structural diagram of a second gate driving unit provided by an embodiment of the present invention. For example, referring to Figure 10 The second gate driving unit 53_2 having an 8T2C structure includes:

[0116] Scan the first transistor T1, scan the second transistor T2, scan the third transistor T3, scan the fourth transistor T4, scan the fifth transistor T5, scan the sixth transistor T6, scan the seventh transistor T7, scan the eighth transistor T8, scan the first capacitor C1 and scan the second capacitor C2;

[0117] The first end of the scanning first transistor T1 is connected to the first enable signal SIN, the second end of the scanning first transistor T1 is connected to the first end of the scanning second transistor T2, and the control end of the scanning first transistor T1 is connected to the first clock signal SCK1;

[0118] The second end of the second scanning transistor T2 is connected to the first end of the third scanning transistor T3, and the control end of the second scanning transistor T2 is connected to the second clock signal SCK2;

[0119] The second end of the third scanning transistor T3 is connected to the first potential signal VGH1, and the control end of the third scanning transistor T3 is connected to the first end of the fourth scanning transistor T4;

[0120] The second end of the fourth scanning transistor T4 is connected to the first clock signal SCK1, and the control end of the fourth scanning transistor T4 is connected to the second end of the first scanning transistor T1;

[0121] A first end of the fifth scanning transistor T5 is connected to the first end of the fourth scanning transistor T4 , a second end of the fifth scanning transistor T5 is connected to the second potential signal VGL1 , and a control end of the fifth scanning transistor T5 is connected to the first clock signal SCK1 ;

[0122] The control end of the sixth scanning transistor T6 is connected to the first end of the fifth scanning transistor T5, the first end of the sixth scanning transistor T6 is connected to the first potential signal VGH1, and the second end of the sixth scanning transistor T6 is connected to the output end of the gate driving unit;

[0123] A first end of the scanning seventh transistor T7 is connected to the output end of the gate driving unit, a second end of the scanning seventh transistor T7 is connected to the second clock signal SCK2, and a control end of the scanning seventh transistor T7 is connected to the first end of the scanning eighth transistor T8;

[0124] The second end of the eighth scanning transistor T8 is connected to the control end of the fourth scanning transistor T4 , and the control end of the eighth scanning transistor T8 is connected to the second potential signal VGL1 ;

[0125] The first scanning capacitor C1 is connected between the control terminal and the first terminal of the sixth scanning transistor T6;

[0126] The second scanning capacitor C2 is connected between the control terminal and the first terminal of the seventh scanning transistor T7;

[0127] Among them, the sixth scanning transistor T6 and the seventh scanning transistor T7 are transistors used by the gate driving unit to output the scanning signal Scan, and their sizes are generally larger than other scanning transistors. Therefore, the sixth scanning transistor T6 and the seventh scanning transistor T7 can be set in the non-folding area 52; the first scanning capacitor C1 and the second scanning capacitor C2 are used to ensure that the gate unit outputs a stable scanning signal Scan, so the first scanning capacitor C1 and the second scanning capacitor C2 can be set in the non-folding area 52.

[0128] As another embodiment of the present invention, optionally, the second gate driving unit 53_2 includes: a 10T3C structure to output the light emitting control signal EM. Figure 11 is a structural diagram of another second gate driving unit provided by an embodiment of the present invention. For example, referring to Figure 11 The second gate driving unit 53_2 having a 10T3C structure includes:

[0129] a first light-emitting control transistor M1, a second light-emitting control transistor M2, a third light-emitting control transistor M3, a fourth light-emitting control transistor M4, a fifth light-emitting control transistor M5, a sixth light-emitting control transistor M6, a seventh light-emitting control transistor M7, an eighth light-emitting control transistor M8, a ninth light-emitting control transistor M9, a tenth light-emitting control transistor M10, a first light-emitting control capacitor C3, a second light-emitting control capacitor C4, and a third light-emitting control capacitor C5;

[0130] The first end of the first light-emitting control transistor M1 is connected to the second enable signal EIN, the second end of the first light-emitting control transistor M1 is connected to the control end of the second light-emitting control transistor M2, and the control end of the first light-emitting control transistor M1 is connected to the third clock signal ECK1;

[0131] A first end of the second light-emitting control transistor M2 is connected to the first clock signal SCK1, and a second end of the second light-emitting control transistor M2 is connected to a first end of the third light-emitting control transistor M3;

[0132] The second end of the third light-emitting control transistor M3 is connected to the fourth potential signal VGL2, and the control end of the third light-emitting control transistor M3 is connected to the third clock signal ECK1;

[0133] The control end of the fourth light-emitting control transistor M4 is connected to the first end of the third light-emitting control transistor M3, the first end of the fourth light-emitting control transistor M4 is connected to the third potential signal VGH2, and the second end of the fourth light-emitting control transistor M4 is connected to the first end of the fifth light-emitting control transistor M5;

[0134] The second end of the fifth light-emitting control transistor M5 is connected to the second end of the first light-emitting control transistor M1 , and the control end of the fifth light-emitting control transistor M5 is connected to the fourth clock signal ECK2 ;

[0135] The control end of the sixth light-emitting control transistor M6 is connected to the second end of the first light-emitting control transistor M1, the first end of the sixth light-emitting control transistor M6 is connected to the third potential signal VGH2, and the second end of the sixth light-emitting control transistor M6 is connected to the first end of the seventh light-emitting control transistor M7;

[0136] The second end of the seventh light-emitting control transistor M7 is connected to the first end of the eighth light-emitting control transistor M8, and the control end of the seventh light-emitting control transistor M7 is connected to the fourth clock signal ECK2;

[0137] The second end of the eighth light-emitting control transistor M8 is connected to the fourth clock signal ECK2, and the control end of the eighth light-emitting control transistor M8 is connected to the first end of the third light-emitting control transistor M3;

[0138] A first end of the ninth light-emitting control transistor M9 is connected to the third potential signal VGH2, a second end of the ninth light-emitting control transistor M9 is connected to the output end of the gate driving unit, and a control end of the ninth light-emitting control transistor M9 is connected to the second end of the sixth light-emitting control transistor M6;

[0139] A first end of the tenth light-emitting control transistor M10 is connected to the output end of the gate driving unit, a second end of the tenth light-emitting control transistor M10 is connected to the fourth potential signal VGL2, and a control end of the tenth light-emitting control transistor M10 is connected to the second end of the first light-emitting control transistor M1;

[0140] The first light-emitting control capacitor C3 is connected between the first terminal and the control terminal of the eighth light-emitting control transistor M8;

[0141] A first end of the second light-emitting control capacitor C4 is connected to the control end of the tenth light-emitting control transistor M10 , and a second end of the light-emitting control capacitor is connected to the fourth clock signal ECK2 ;

[0142] The third light-emitting control capacitor C5 is connected between the control terminal and the first terminal of the ninth light-emitting control transistor M9;

[0143] Among them, the eighth light-emitting control transistor M8, the ninth light-emitting control transistor M9 and the tenth light-emitting control transistor M10 are generally larger in size than other light-emitting control transistors, so the eighth light-emitting control transistor M8, the ninth light-emitting control transistor M9 and the tenth light-emitting control transistor M10 can be set in the non-folding area 52; the first light-emitting control capacitor C3, the second light-emitting control capacitor C4 and the third light-emitting control capacitor C5 are used to ensure that the gate unit outputs a stable light-emitting control signal EM, so the first light-emitting control capacitor C3, the second light-emitting control capacitor C4 and the third light-emitting control capacitor C5 can be set in the non-folding area 52.

[0144] It should be noted that the 8T2C or 10T3C structure of the second gate driver unit 53_2 provided in this embodiment is provided as an example only. The second gate driver unit 53_2 may also have other structures, which are not specifically limited in this embodiment. Furthermore, the first gate driver unit 53_1 and the second gate driver unit 53_2 may have the same structure. Furthermore, the display panel may simultaneously include a second gate driver unit 53_2 with an 8T2C structure to output the scan signal Scan and a second gate driver unit 53_2 with a 10T3C structure to output the emission control signal EM. The second gate driver unit 53_2 with a 10T3C structure may be disposed peripherally to the second gate driver unit 53_2 with an 8T2C structure.

[0145] Figure 12 yes Figure 5 The partial enlarged view of the display panel shown in FIG. 1 is based on any of the above embodiments and is combined with Figure 5 and Figure 12Optionally, the display panel further includes a clock line 58, a potential line 59 and an enable line (not shown in the figure); each gate driving unit 53 is connected to the clock line 58, and each gate driving unit 53 is connected to the potential line 59; the clock line 58 is used to provide a clock signal, the potential line 59 is used to provide a potential signal, and the enable line is used to provide a start signal to the gate driving unit 53; wherein, the clock line 58, the potential line 59 and / or the enable line located between two adjacent gate driving units 53 in the folding area 51 are arranged at an angle in the plane where the display panel is located, thereby further reducing the stress concentration in the folding area 51, further softening the folding area 51, and improving the bending performance of the folding area 51.

[0146] Figure 13 Schematic diagram of a display device according to an embodiment of the present invention. Figure 13 The present invention also provides a display device, comprising the display panel of any of the above embodiments. The display device and display panel provided by the present invention are based on the same inventive concept and can achieve the same technical effects. The repeated contents will not be repeated here.

[0147] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel comprising a non-folding area and a folding area, characterized in that: include: A plurality of data lines extending along a column direction; A plurality of gate lines extending along a row direction; The gate line and the data line intersect to define an area where a sub-pixel is located; A plurality of gate driving units are sequentially arranged along a column direction; the gate driving units are connected to corresponding gate lines, and the gate lines are electrically connected to pixel driving circuits that drive the sub-pixels; The non-folding area is adjacent to the folding area, and some components of the gate driving unit located in the folding area are arranged in the non-folding area; The gate driving unit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is located in the non-folding area, and the second gate driving unit is located in the folding area; The second gate driving unit includes a plurality of thin film transistors; the size of the thin film transistors of the second gate driving unit in the non-folding area is larger than the size of the thin film transistors of the second gate driving unit in the folding area; The second gate driving unit includes a plurality of capacitors, and at least one capacitor of the second gate driving unit is disposed in the non-folding area.

2. The display panel according to claim 1, wherein: The non-folding area includes a device setting area and a device reserved area; The device reserved area is located between the device setting area and the folding area, the components of the gate driving unit located in the non-folding area are set in the device setting area, and some components of the gate driving unit located in the folding area are set in the device reserved area.

3. The display panel according to claim 2, wherein: The first gate driving units are arranged at equal intervals in a direction from the non-folding area away from the adjacent folding area.

4. The display panel according to claim 3, wherein: From the direction where the non-folding area is away from the adjacent folding area, the distance between two adjacent first gate driving units increases successively.

5. The display panel according to claim 4, wherein: In the same non-folding area, the arrangement of components of the first gate driving unit that is relatively close to the adjacent folding area is different from the arrangement of components of the first gate driving unit that is relatively far from the same folding area.

6. The display panel according to claim 5, wherein: The components of the first gate driving unit relatively close to the folding area are arranged in m rows, and the components of the first gate driving unit relatively far from the folding area are arranged in n rows; wherein m and n are both positive integers and m<n.

7. The display panel according to claim 6, wherein: In the first gate driving unit relatively close to the folding area, the spacing between two adjacent components is a first spacing; in the first gate driving unit relatively far from the folding area, the spacing between two adjacent components is a second spacing; wherein the first spacing is smaller than the second spacing.

8. The display panel according to claim 7, wherein: The display panel includes a display area and a non-display area, and the sub-pixels are located in the display area; the components of the sub-pixels that are relatively close to the folding area and relatively close to the non-display area are arranged at non-equidistant intervals; some components of the first gate driving unit that are relatively close to the folding area are located in the display area.

9. The display panel according to claim 1, wherein: A folding axis is defined in the folding area; The components of the second gate driving unit located in the folding area are arranged at equal intervals.

10. The display panel according to claim 9, wherein: In the folding area, from the folding axis toward the non-folding area, the distance between two adjacent second gate driving units tends to decrease.

11. The display panel according to claim 10, wherein: In the folding area, from the folding axis to the direction of the non-folding area, the distance between two adjacent components tends to decrease, and the components are components of the second gate driving unit.

12. The display panel according to claim 1, wherein The gate driving unit includes: Scanning the first transistor, scanning the second transistor, scanning the third transistor, scanning the fourth transistor, scanning the fifth transistor, scanning the sixth transistor, scanning the seventh transistor, scanning the eighth transistor, scanning the first capacitor, and scanning the second capacitor; The first end of the scanning first transistor is connected to the first enable signal, the second end of the scanning first transistor is connected to the first end of the scanning second transistor, and the control end of the scanning first transistor is connected to the first clock signal; The second end of the second scanning transistor is connected to the first end of the third scanning transistor, and the control end of the second scanning transistor is connected to the second clock signal; The second end of the third scanning transistor is connected to the first potential signal, and the control end of the third scanning transistor is connected to the first end of the fourth scanning transistor; The second end of the fourth scanning transistor is connected to the first clock signal, and the control end of the fourth scanning transistor is connected to the second end of the first scanning transistor; The first end of the fifth scanning transistor is connected to the first end of the fourth scanning transistor, the second end of the fifth scanning transistor is connected to the second potential signal, and the control end of the fifth scanning transistor is connected to the first clock signal; The control end of the sixth scanning transistor is connected to the first end of the fifth scanning transistor, the first end of the sixth scanning transistor is connected to the first potential signal, and the second end of the sixth scanning transistor is connected to the output end of the gate driving unit; A first end of the scanning seventh transistor is connected to the output end of the gate driving unit, a second end of the scanning seventh transistor is connected to the second clock signal, and a control end of the scanning seventh transistor is connected to the first end of the scanning eighth transistor; The second end of the eighth scanning transistor is connected to the control end of the fourth scanning transistor, and the control end of the eighth scanning transistor is connected to the second potential signal; The first scanning capacitor is connected between the control terminal and the first terminal of the sixth scanning transistor; The second scanning capacitor is connected between the control terminal and the first terminal of the seventh scanning transistor; The sixth scanning transistor, the seventh scanning transistor, the first scanning capacitor and the second scanning capacitor are arranged in the non-folding area.

13. The display panel according to claim 1, wherein The gate driving unit includes: a first light-emitting control transistor, a second light-emitting control transistor, a third light-emitting control transistor, a fourth light-emitting control transistor, a fifth light-emitting control transistor, a sixth light-emitting control transistor, a seventh light-emitting control transistor, an eighth light-emitting control transistor, a ninth light-emitting control transistor, a tenth light-emitting control transistor, a first light-emitting control capacitor, a second light-emitting control capacitor, and a third light-emitting control capacitor; The first terminal of the first light-emitting control transistor is connected to the second enable signal, the second terminal of the first light-emitting control transistor is connected to the control terminal of the second light-emitting control transistor, and the control terminal of the first light-emitting control transistor is connected to the third clock signal; The first end of the second light-emitting control transistor is connected to the first clock signal, and the second end of the second light-emitting control transistor is connected to the first end of the third light-emitting control transistor; The second terminal of the third light-emitting control transistor is connected to the fourth potential signal, and the control terminal of the third light-emitting control transistor is connected to the third clock signal; The control end of the fourth light-emitting control transistor is connected to the first end of the third light-emitting control transistor, the first end of the fourth light-emitting control transistor is connected to the third potential signal, and the second end of the fourth light-emitting control transistor is connected to the first end of the fifth light-emitting control transistor; The second end of the fifth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, and the control end of the fifth light-emitting control transistor is connected to the fourth clock signal; The control end of the sixth light-emitting control transistor is connected to the second end of the first light-emitting control transistor, the first end of the sixth light-emitting control transistor is connected to the third potential signal, and the second end of the sixth light-emitting control transistor is connected to the first end of the seventh light-emitting control transistor; The second end of the seventh light-emitting control transistor is connected to the first end of the eighth light-emitting control transistor, and the control end of the seventh light-emitting control transistor is connected to the fourth clock signal; The second end of the eighth light-emitting control transistor is connected to the fourth clock signal, and the control end of the eighth light-emitting control transistor is connected to the first end of the third light-emitting control transistor; A first end of the ninth light-emitting control transistor is connected to the third potential signal, a second end of the ninth light-emitting control transistor is connected to the output end of the gate driving unit, and a control end of the ninth light-emitting control transistor is connected to the second end of the sixth light-emitting control transistor; A first end of the tenth light-emitting control transistor is connected to the output end of the gate driving unit, a second end of the tenth light-emitting control transistor is connected to the fourth potential signal, and a control end of the tenth light-emitting control transistor is connected to the second end of the first light-emitting control transistor; The first light-emitting control capacitor is connected between the first terminal and the control terminal of the eighth light-emitting control transistor; A first end of the second light-emitting control capacitor is connected to the control end of the tenth light-emitting control transistor, and a second end of the light-emitting control capacitor is connected to the fourth clock signal; The third light-emitting control capacitor is connected between the control terminal and the first terminal of the ninth light-emitting control transistor; Among them, the eighth light-emitting control transistor, the ninth light-emitting control transistor, the tenth light-emitting control transistor, the first light-emitting control capacitor, the second light-emitting control capacitor and the third light-emitting control capacitor are arranged in the non-folding area.

14. The display panel according to claim 1, wherein The display panel further includes a clock line, a potential line and an enable line; Each of the gate driving units is connected to the clock line, and each of the gate driving units is connected to the potential line; the enable line is used to provide a start signal to the gate driving unit; wherein, the clock line, the potential line and / or the enable line located between two adjacent gate driving units in the folding area are arranged at an angle in the plane where the display panel is located.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

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