Driving circuit, driving method, driving module and display device

Abstract

The present invention provides a driving circuit, a driving method, a driving module and a display device. The driving circuit includes a first node control circuit, a second node control circuit, a control node control circuit and an output circuit; the first node control circuit controls the potential of the first node; the control node control circuit controls the potential of the control node according to the second clock signal under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage, and controls the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal to maintain the potential of the control node; the second node control circuit controls the potential of the second node; the output circuit controls the drive signal output terminal to output the drive signal under the control of the potential of the first node and the potential of the second node. The present invention can realize that the pulse width of the drive signal outputted by it is adjustable, and can be applied to forward scanning and reverse scanning.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module and a display device. Background Art

[0002] In recent years, with the advancement of smart display technology, organic light emitting diode (OLED) has become one of the hot topics in the current display research field. As display panels become thinner and borders narrower, the optimization design of display panels has become increasingly severe.

[0003] The related driving circuit cannot realize the adjustable pulse width of the driving signal outputted by it, and cannot be applied to forward scanning and reverse scanning at the same time. Summary of the invention

[0004] In one aspect, an embodiment of the present invention provides a driving circuit, including a first node control circuit, a second node control circuit, a control node control circuit, and an output circuit;

[0005] The first node control circuit is used to control the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the first scan control signal provided by the first scan control terminal, the first clock signal provided by the first clock signal terminal and the second scan control signal provided by the second scan control terminal;

[0006] The control node control circuit is used to control the potential of the control node according to the second clock signal provided by the second clock signal terminal under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage, and to control the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal, and to maintain the potential of the control node;

[0007] The second node control circuit is electrically connected to the first node, the second node, the connection node, the control node, the first clock signal terminal and the second voltage terminal respectively, and is used to control the connection or disconnection between the second node and the second voltage terminal under the control of the potential of the first node, control the connection or disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node, and control the connection or disconnection between the connection node and the second node under the control of the first clock signal;

[0008] The output circuit is electrically connected to the first node, the second node, the first voltage terminal, the second voltage terminal and the drive signal output terminal, respectively, and is used to control the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node, and to control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0009] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first energy storage circuit and a second energy storage circuit;

[0010] The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output end, and is used to control the potential of the first node according to the drive signal output by the drive signal output end;

[0011] The second energy storage circuit is electrically connected to the second node, and is used to maintain the potential of the second node.

[0012] Optionally, the first node control circuit is electrically connected to the first node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the first control voltage terminal under the control of a first scan control signal provided by the first scan control terminal and a first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the first node and the second control voltage terminal under the control of a second scan control signal provided by the second scan control terminal and the first clock signal;

[0013] The control node control circuit is electrically connected to the control node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the second clock signal terminal under the control of the first scan control signal and the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the control node and the second clock signal terminal under the control of the second scan control signal and the second control voltage provided by the second control voltage terminal, and to control the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal.

[0014] Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0015] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first control voltage terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;

[0016] The control electrode of the second transistor is electrically connected to the first scan control terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0017] The control electrode of the third transistor is electrically connected to the second scan control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0018] A control electrode of the fourth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the second control voltage terminal.

[0019] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first leakage prevention circuit;

[0020] The first leakage prevention circuit is electrically connected to the first node, the first voltage terminal, the second electrode of the first transistor and the second electrode of the third transistor, respectively, and is used to control the connection between the first voltage terminal and the second electrode of the first transistor, and to control the connection between the first voltage terminal and the second electrode of the third transistor under the control of the potential of the first node.

[0021] Optionally, the control node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a storage capacitor;

[0022] The control electrode of the fifth transistor is electrically connected to the first control voltage terminal, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor;

[0023] The control electrode of the sixth transistor is electrically connected to the first scan control terminal, and the second electrode of the sixth transistor is electrically connected to the control node;

[0024] The control electrode of the seventh transistor is electrically connected to the second scan control terminal, the first electrode of the seventh transistor is electrically connected to the control node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;

[0025] The control electrode of the eighth transistor is electrically connected to the second control voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second clock signal terminal;

[0026] The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the control node;

[0027] A first end of the storage capacitor is electrically connected to the control node, and a second end of the storage capacitor is electrically connected to the connection node.

[0028] Optionally, the second node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0029] The control electrode of the tenth transistor is electrically connected to the control node, the first electrode of the tenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the connection node;

[0030] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the connection node, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0031] The control electrode of the twelfth transistor and the control electrode of the thirteenth transistor are both electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second voltage terminal, the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the second electrode of the thirteenth transistor is electrically connected to the second node.

[0032] Optionally, the output circuit includes a first output transistor and a second output transistor;

[0033] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal;

[0034] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the second voltage terminal.

[0035] Optionally, the output circuit includes a first output transistor, a second output transistor and a third output transistor;

[0036] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal;

[0037] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first electrode of the third output transistor;

[0038] A control electrode of the third output transistor is electrically connected to the second node, and a second electrode of the third output transistor is electrically connected to the second voltage terminal.

[0039] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a second leakage prevention circuit;

[0040] The second anti-leakage circuit is electrically connected to the drive signal output terminal, the first voltage terminal and the second electrode of the second output transistor respectively, and is used to control the connection between the first voltage terminal and the second electrode of the second output transistor under the control of the drive signal provided by the drive signal output terminal.

[0041] Optionally, the first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor;

[0042] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the drive signal output terminal;

[0043] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the second voltage end.

[0044] Optionally, the first leakage prevention circuit includes a fourteenth transistor;

[0045] The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the second electrode of the first transistor and the second electrode of the third transistor.

[0046] Optionally, the second leakage prevention circuit includes a fifteenth transistor;

[0047] The control electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, the first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second electrode of the second output transistor.

[0048] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a driving output terminal, an output resistor and an output capacitor;

[0049] The first end of the output resistor is electrically connected to the drive signal output terminal; the second end of the output resistor is electrically connected to the drive output terminal; the first end of the output capacitor is electrically connected to the second end of the output resistor, and the second end of the output capacitor is grounded; or,

[0050] The driving circuit further includes a driving output terminal, M output resistors and M output capacitors, where M is an integer greater than 1;

[0051] A first end of a first output resistor is electrically connected to the drive signal output terminal, and a second end of an Mth output resistor is electrically connected to the drive output terminal;

[0052] The first end of the m-th output resistor is electrically connected to the second end of the m-1-th output resistor; m is an integer less than or equal to M and greater than 1;

[0053] A first end of a first output capacitor is electrically connected to a second end of the first output resistor, and a second end of the first output capacitor is grounded;

[0054] A first end of the mth output capacitor is electrically connected to a second end of the mth output resistor, and a second end of the mth output capacitor is grounded.

[0055] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method includes:

[0056] The first node control circuit controls the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the first scan control signal, the first clock signal and the second scan control signal;

[0057] The control node control circuit controls the potential of the control node under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage according to the second clock signal provided by the second clock signal terminal, and controls the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal;

[0058] The second node control circuit controls the connection or disconnection between the second node and the second voltage terminal under the control of the potential of the first node, controls the potential of the connection node according to the potential of the control node, and controls the connection or disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection or disconnection between the connection node and the second node under the control of the first clock signal;

[0059] The output circuit controls the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0060] Optionally, the driving circuit further includes a first energy storage circuit and a second energy storage circuit; when the driving circuit performs forward scanning, the first scanning control terminal provides a third voltage signal, and the second scanning control terminal provides a fourth voltage signal, and the driving cycle includes a first forward scanning stage, a second forward scanning stage, a third forward scanning stage, and a fourth forward scanning stage which are successively arranged;

[0061] The driving method comprises: when the driving circuit performs forward scanning,

[0062] In the first positive scanning stage, the first clock signal terminal provides a sixth voltage signal, and the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node;

[0063] In the second forward scanning stage, the first control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the first control voltage and the first scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the first control voltage terminal under the control of the first scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

[0064] In the third positive scanning stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal; the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; and the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node;

[0065] In the fourth positive scan stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The first node control circuit controls the connection between the first node and the first control voltage terminal under the control of the first scan control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0066] Optionally, the driving circuit further includes a first energy storage circuit and a second energy storage circuit; when the driving circuit performs reverse scanning, the first scanning control terminal provides a fourth voltage signal, the second scanning control terminal provides a third voltage signal, and the driving cycle includes a first reverse scanning stage, a second reverse scanning stage, a third reverse scanning stage and a fourth reverse scanning stage which are arranged in sequence; the driving method includes: when the driving circuit performs reverse scanning,

[0067] In the first reverse scanning stage, the first clock signal terminal provides a sixth voltage signal, and the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node;

[0068] In the second reverse scanning stage, the second control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the second control voltage and the second scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

[0069] In the third reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal; the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node;

[0070] In the fourth reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The first node control circuit controls the connection between the first node and the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0071] In a third aspect, an embodiment of the present invention provides a driving module, comprising a plurality of stages of the above-mentioned driving circuits;

[0072] The first control voltage terminal of the first stage driving circuit is electrically connected to the starting voltage terminal;

[0073] The first control voltage terminal of the a-th level driving circuit is electrically connected to the driving signal output terminal of the a-1-th level driving circuit;

[0074] The second control voltage terminal of the b-th level driving circuit is electrically connected to the driving signal output terminal of the b+1-th level driving circuit;

[0075] a is an integer greater than 1, and b is a positive integer.

[0076] In a fourth aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned driving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0078] Figure 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0079] Figure 3is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0080] Figure 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0081] Figure 5 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0082] Figure 6 The present invention Figure 5 A first working timing diagram of at least one embodiment of the driving circuit shown;

[0083] Figure 7 The present invention Figure 5 A second operation timing diagram of at least one embodiment of the driving circuit shown;

[0084] Figure 8 The present invention Figure 5 A third operation timing diagram of at least one embodiment of the driving circuit shown;

[0085] Fig. 9 The present invention Figure 5 A fourth operation timing diagram of at least one embodiment of the driving circuit shown;

[0086] Fig.10 It is a schematic diagram of each driving signal output terminal outputting corresponding driving signals in sequence from top to bottom when the driving module according to at least one embodiment of the present invention performs forward scanning;

[0087] Fig.11 It is a schematic diagram of each driving signal output terminal outputting corresponding driving signals in sequence from bottom to top when the driving module according to at least one embodiment of the present invention performs forward scanning;

[0088] Fig.12 It is a schematic diagram of each driving signal output terminal outputting corresponding driving signals in sequence from top to bottom when the driving module according to at least one embodiment of the present invention performs forward scanning;

[0089] Fig.13A is a schematic diagram of each driving signal output terminal outputting corresponding driving signals in sequence from bottom to top when the driving module according to at least one embodiment of the present invention performs reverse scanning;

[0090] Fig. 13B is a schematic diagram of each driving signal output terminal outputting corresponding driving signals in sequence from bottom to top when the driving module according to at least one embodiment of the present invention performs reverse scanning;

[0091] Fig.14 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0092] Fig.15 It is a connection diagram of the minimum repeating unit of odd and even rows;

[0093] Fig.16 is a structural diagram of a driving module according to at least one embodiment of the present invention;

[0094] Fig.17 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0095] Fig.18 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0096] Fig.19 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0097] Fig. 20 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0098] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0099] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0100] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0101] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0102] like Figure 1 As shown, the driving circuit according to at least one embodiment of the present invention includes a first node control circuit 11, a second node control circuit 12, a control node control circuit 13 and an output circuit 14;

[0103] The first node control circuit 11 is electrically connected to the first scan control terminal CN, the first clock signal terminal XCK, the second scan control terminal CNB, the first control voltage terminal STU, the second control voltage terminal STD and the first node Q respectively, and is used to control the potential of the first node Q according to the first control voltage provided by the first control voltage terminal STU and the second control voltage provided by the second control voltage terminal STD under the control of the first scan control signal provided by the first scan control terminal CN, the first clock signal provided by the first clock signal terminal XCK and the second scan control signal provided by the second scan control terminal CNB;

[0104] The control node control circuit 13 is electrically connected to the first scan control terminal CN, the first control voltage terminal STU, the second scan control terminal CNB, the second control voltage terminal STD, the second clock signal terminal CK, the control node QP and the first voltage terminal V1 respectively, and is used to control the potential of the control node QP according to the second clock signal provided by the second clock signal terminal CK under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage, and to control the connection or disconnection between the control node QP and the first voltage terminal V1 under the control of the second clock signal, and to maintain the potential of the control node QP;

[0105] The second node control circuit 12 is electrically connected to the first node Q, the second node QB, the connection node J1, the control node QP, the first clock signal terminal XCK and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the second node QB and the second voltage terminal V2 under the control of the potential of the first node Q, control the connection or disconnection between the first clock signal terminal XCK and the connection node J1 under the control of the potential of the control node QP, and control the connection or disconnection between the connection node J1 and the second node QB under the control of the first clock signal;

[0106] The output circuit 14 is electrically connected to the first node Q, the second node QB, the first voltage terminal V1, the second voltage terminal V2 and the drive signal output terminal GN, respectively, and is used to control the connection or disconnection between the drive signal output terminal GN and the first voltage terminal V1 under the control of the potential of the first node Q, and to control the connection or disconnection between the drive signal output terminal GN and the second voltage terminal V2 under the control of the potential of the second node QB.

[0107] The driving circuit described in the embodiment of the present invention can achieve adjustable pulse width of the driving signal outputted by the driving circuit, and can be applied to forward scanning and reverse scanning.

[0108] The driving circuit described in the embodiment of the present invention can be used to provide a compensation control signal for a compensation transistor in an internal compensation pixel circuit, and can also be used to provide a light emission control signal for a light emission control transistor in an external compensation pixel circuit, but is not limited thereto.

[0109] In at least one embodiment of the present invention, the first voltage terminal V1 may be a high voltage terminal, and the second voltage terminal V2 may be a low voltage terminal, but the present invention is not limited thereto.

[0110] Figure 1 At least one embodiment of the driving circuit shown may be an N-th stage driving circuit, and the driving signal output terminal GN may be an N-th stage driving signal output terminal, where N is a positive integer.

[0111] In at least one embodiment of the present invention, the first node control circuit is electrically connected to the first node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the first control voltage terminal under the control of the first scan control signal provided by the first scan control terminal and the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the first node and the second control voltage terminal under the control of the second scan control signal provided by the second scan control terminal and the first clock signal;

[0112] The control node control circuit is electrically connected to the control node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the second clock signal terminal under the control of the first scan control signal and the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the control node and the second clock signal terminal under the control of the second scan control signal and the second control voltage provided by the second control voltage terminal, and to control the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal.

[0113] The present invention Figure 1 When at least one embodiment of the driving circuit shown is in operation, the first node control circuit 11 controls the connection or disconnection between the first node Q and the first control voltage terminal STU under the control of the first scan control signal provided by the first scan control terminal CN and the first clock signal provided by the first clock signal terminal, and controls the connection or disconnection between the first node Q and the second control voltage terminal STD under the control of the second scan control signal provided by the second scan control terminal CNB and the first clock signal;

[0114] The control node control circuit 13 controls the connection or disconnection between the control node QP and the second clock signal terminal CK under the control of the first scan control signal and the first control voltage provided by the first control voltage terminal STU, and controls the connection or disconnection between the control node QP and the second clock signal terminal CK under the control of the second scan control signal and the second control voltage provided by the second control voltage terminal STD, and controls the connection or disconnection between the control node QP and the first voltage terminal V1 under the control of the second clock signal provided by the second clock signal terminal CK.

[0115] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a first energy storage circuit 21 and a second energy storage circuit 22;

[0116] The first end of the first energy storage circuit 21 is electrically connected to the first node Q, and the second end of the first energy storage circuit 21 is electrically connected to the drive signal output terminal GN, and is used to control the potential of the first node Q according to the drive signal output by the drive signal output terminal GN;

[0117] The second energy storage circuit 22 is electrically connected to the second node QB, and is used to maintain the potential of the second node QB.

[0118] In at least one embodiment of the present invention, the third voltage signal may be a high voltage signal, and the fourth voltage signal may be a low voltage signal, but the present invention is not limited thereto.

[0119] The present invention Figure 2 At least one embodiment of the driving circuit shown is in operation. When the driving circuit performs forward scanning, the first scanning control terminal CN provides a high voltage signal, and the second scanning control terminal CNB provides a low voltage signal. The driving cycle includes a first forward scanning stage, a second forward scanning stage, a third forward scanning stage, and a fourth forward scanning stage which are successively arranged.

[0120] The driving method comprises: when the driving circuit performs forward scanning,

[0121] In the first forward scanning stage, the first clock signal terminal XCK provides a sixth voltage signal, and the second node control circuit 12 controls the connection node J1 and the second node QB to be disconnected under the control of the first clock signal; the first energy storage circuit 21 maintains the potential of the first node Q, and the second energy storage circuit 22 maintains the potential of the second node QB;

[0122] In the second forward scanning stage, the first control voltage terminal STU provides a fifth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, and the second clock signal terminal CK provides a sixth voltage signal. The control node control circuit 13 controls the second clock signal terminal CK to be connected to the control node QP under the control of the first control voltage and the first scanning control signal; the second node control circuit 12 controls the first clock signal terminal XCK to be disconnected from the connection node J1 under the control of the potential of the control node QP; the first node control circuit 11 controls the first node Q to be connected to the first control voltage terminal STU under the control of the first scanning control signal and the first clock signal; the output circuit 14 controls the drive signal output terminal GN to be connected to the first voltage terminal V1 under the control of the potential of the first node Q;

[0123] In the third positive scanning stage, the first control voltage terminal STU provides a sixth voltage signal, the first clock signal terminal XCK provides a sixth voltage signal, and the second clock signal terminal CK provides a fifth voltage signal. The control node control circuit 13 controls the control node QP to be connected to the first voltage terminal V1 under the control of the second clock signal; the second node control circuit 12 controls the connection node J1 to be disconnected from the second node QB under the control of the first clock signal; the first energy storage circuit 21 maintains the potential of the first node Q; the output circuit 14 controls the drive signal output terminal GN to be connected to the first voltage terminal V1 under the control of the potential of the first node Q;

[0124] In the fourth positive scan stage, the first control voltage terminal STU provides a sixth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, and the second clock signal terminal CK provides a sixth voltage signal. The first node control circuit 11 controls the connection between the first node Q and the first control voltage terminal STU under the control of the first scan control signal and the first clock signal; the control node control circuit 13 maintains the potential of the control node QP; the second node control circuit 12 controls the connection between the first clock signal terminal XCK and the connection node J1 under the control of the potential of the control node QP, and controls the connection between the connection node J1 and the second node QB under the control of the first clock signal; the output circuit 14 controls the connection between the drive signal output terminal GN and the second voltage terminal V2 under the control of the potential of the second node QB.

[0125] In at least one embodiment of the present invention, the fifth voltage signal may be a high voltage signal, and the sixth voltage signal may be a low voltage signal, but the present invention is not limited thereto.

[0126] The present invention Figure 2At least one embodiment of the driving circuit shown in the figure is in operation. When the driving circuit performs reverse scanning, the first scanning control terminal CN provides a low voltage signal, and the second scanning control terminal CNB provides a high voltage signal. The driving cycle includes a first reverse scanning stage, a second reverse scanning stage, a third reverse scanning stage, and a fourth reverse scanning stage which are arranged in sequence. When the driving circuit performs reverse scanning,

[0127] In the first reverse scanning stage, the first clock signal terminal XCK provides a sixth voltage signal, and the second node control circuit 12 controls the connection node J1 and the second node QB to be disconnected under the control of the first clock signal; the first energy storage circuit 21 maintains the potential of the first node Q, and the second energy storage circuit 22 maintains the potential of the second node QB;

[0128] In the second reverse scanning stage, the second control voltage terminal STD provides a fifth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, and the second clock signal terminal CK provides a sixth voltage signal. The control node control circuit 13 controls the second clock signal terminal CK to be connected to the control node QP under the control of the second control voltage and the second scanning control signal; the second node control circuit 12 controls the first clock signal terminal XCK to be disconnected from the connection node J1 under the control of the potential of the control node QP; the first node control circuit 11 controls the first node Q to be connected to the second control voltage terminal STD under the control of the second scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal GN to be connected to the first voltage terminal V1 under the control of the potential of the first node Q;

[0129] In the third reverse scanning stage, the second control voltage terminal STD provides a sixth voltage signal, the first clock signal terminal XCK provides a sixth voltage signal, and the second clock signal terminal CK provides a fifth voltage signal. The control node control circuit 13 controls the control node QP to be connected to the first voltage terminal V1 under the control of the second clock signal; the second node control circuit 12 controls the connection node J1 to be disconnected from the second node QB under the control of the first clock signal; the first energy storage circuit 21 maintains the potential of the first node Q; the output circuit 14 controls the drive signal output terminal GN to be connected to the first voltage terminal V1 under the control of the potential of the first node Q;

[0130] In the fourth reverse scanning stage, the second control voltage terminal STD provides a sixth voltage signal, the first clock signal terminal XCK provides a fifth voltage signal, and the second clock signal terminal CK provides a sixth voltage signal. The first node control circuit 11 controls the connection between the first node Q and the second control voltage terminal STD under the control of the second scanning control signal and the first clock signal; the control node control circuit 13 maintains the potential of the control node QP; the second node control circuit 12 controls the connection between the first clock signal terminal XCK and the connection node J1 under the control of the potential of the control node QP, and controls the connection between the connection node J1 and the second node QB under the control of the first clock signal; the output circuit 14 controls the connection between the drive signal output terminal GN and the second voltage terminal V2 under the control of the potential of the second node QB.

[0131] Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor;

[0132] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first control voltage terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;

[0133] The control electrode of the second transistor is electrically connected to the first scan control terminal, and the second electrode of the second transistor is electrically connected to the first node;

[0134] The control electrode of the third transistor is electrically connected to the second scan control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0135] A control electrode of the fourth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the second control voltage terminal.

[0136] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the first node control circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0137] The gate of the first transistor T1 is electrically connected to the first clock signal terminal XCK, the source of the first transistor T1 is electrically connected to the first control voltage terminal STU, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2;

[0138] The gate of the second transistor T2 is electrically connected to the first scan control terminal CN, and the drain of the second transistor T2 is electrically connected to the first node Q;

[0139] The gate of the third transistor T3 is electrically connected to the second scan control terminal CNB, the source of the third transistor T3 is electrically connected to the first node Q, and the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4;

[0140] A gate of the fourth transistor T4 is electrically connected to the first clock signal terminal XCK, and a drain of the fourth transistor T4 is electrically connected to the second control voltage terminal STD.

[0141] The driving circuit described in at least one embodiment of the present invention further includes a first leakage prevention circuit;

[0142] The first leakage prevention circuit is electrically connected to the first node, the first voltage terminal, the second electrode of the first transistor and the second electrode of the third transistor, respectively, and is used to control the connection between the first voltage terminal and the second electrode of the first transistor, and to control the connection between the first voltage terminal and the second electrode of the third transistor under the control of the potential of the first node.

[0143] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a first leakage prevention circuit 41;

[0144] The first leakage prevention circuit 41 is electrically connected to the first node Q, the high voltage terminal VGH, the drain of the first transistor T1 and the drain of the third transistor T3, respectively, and is used to control the connection between the high voltage terminal VGH and the drain of the first transistor T1 and the connection between the high voltage terminal VGH and the drain of the third transistor T3 under the control of the potential of the first node Q.

[0145] The present invention Figure 4 When at least one embodiment of the driving circuit shown is in operation, when the potential of the first node Q is a high voltage, the first leakage prevention circuit 41, under the control of the potential of the first node Q, controls the first voltage terminal V1 to be connected to the drain of the first transistor T1, and controls the first voltage terminal V1 to be connected to the drain of the third transistor T3, provides a high voltage signal to the middle node of the first transistor T1 and the second transistor T2, and provides a high voltage signal to the middle node of the third transistor T3 and the fourth transistor T4, prevents the first node Q from leaking to the first control voltage terminal STU and the second control voltage terminal STD, and is beneficial to maintaining the potential of the first node Q.

[0146] Optionally, the control node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a storage capacitor;

[0147] The control electrode of the fifth transistor is electrically connected to the first control voltage terminal, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor;

[0148] The control electrode of the sixth transistor is electrically connected to the first scan control terminal, and the second electrode of the sixth transistor is electrically connected to the control node;

[0149] The control electrode of the seventh transistor is electrically connected to the second scan control terminal, the first electrode of the seventh transistor is electrically connected to the control node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor;

[0150] The control electrode of the eighth transistor is electrically connected to the second control voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second clock signal terminal;

[0151] The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the control node;

[0152] A first end of the storage capacitor is electrically connected to the control node, and a second end of the storage capacitor is electrically connected to the connection node.

[0153] Optionally, the second node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0154] The control electrode of the tenth transistor is electrically connected to the control node, the first electrode of the tenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the connection node;

[0155] The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the connection node, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0156] The control electrode of the twelfth transistor and the control electrode of the thirteenth transistor are both electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second voltage terminal, the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the second electrode of the thirteenth transistor is electrically connected to the second node.

[0157] Optionally, the output circuit includes a first output transistor and a second output transistor;

[0158] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal;

[0159] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the second voltage terminal.

[0160] Optionally, the output circuit includes a first output transistor, a second output transistor and a third output transistor;

[0161] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal;

[0162] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first electrode of the third output transistor;

[0163] A control electrode of the third output transistor is electrically connected to the second node, and a second electrode of the third output transistor is electrically connected to the second voltage terminal.

[0164] Optionally, the first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor;

[0165] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the drive signal output terminal;

[0166] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the second voltage end.

[0167] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the control node control circuit 13 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a storage capacitor C0;

[0168] The gate of the fifth transistor T5 is electrically connected to the first control voltage terminal STU, the source of the fifth transistor T5 is electrically connected to the second clock signal terminal CK, and the drain of the fifth transistor T5 is electrically connected to the source of the sixth transistor T6;

[0169] The gate of the sixth transistor T6 is electrically connected to the first scan control terminal CN, and the drain of the sixth transistor T6 is electrically connected to the control node QP;

[0170] The gate of the seventh transistor T7 is electrically connected to the second scan control terminal CNB, the source of the seventh transistor T7 is electrically connected to the control node QP, and the drain of the seventh transistor T7 is electrically connected to the source of the eighth transistor T8;

[0171] The gate of the eighth transistor T8 is electrically connected to the second control voltage terminal STD, and the drain of the eighth transistor T8 is electrically connected to the second clock signal terminal CK;

[0172] The gate of the ninth transistor T9 is electrically connected to the second clock signal terminal CK, the source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and the drain of the ninth transistor T9 is electrically connected to the control node QP;

[0173] The first end of the storage capacitor C0 is electrically connected to the control node QP, and the second end of the storage capacitor C0 is electrically connected to the connection node J1;

[0174] The second node control circuit 12 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13;

[0175] The gate of the tenth transistor T10 is electrically connected to the control node QP, the source of the tenth transistor T10 is electrically connected to the first clock signal terminal XCK, and the drain of the tenth transistor T10 is electrically connected to the connection node J1;

[0176] The gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal XCK, the source of the eleventh transistor T11 is electrically connected to the connection node J1, and the drain of the eleventh transistor T11 is electrically connected to the second node QB;

[0177] The gate of the twelfth transistor T12 and the gate of the thirteenth transistor T13 are both electrically connected to the first node Q, the source of the twelfth transistor T12 is electrically connected to the low voltage terminal VGL, the drain of the twelfth transistor T12 is electrically connected to the source of the thirteenth transistor T13; the drain of the thirteenth transistor T13 is electrically connected to the second node QB;

[0178] The output circuit 14 includes a first output transistor TO1 and a second output transistor TO2;

[0179] The gate of the first output transistor TO1 is electrically connected to the first node Q, the source of the first output transistor TO1 is electrically connected to the high voltage terminal VGH, and the drain of the first output transistor TO1 is electrically connected to the drive signal output terminal GN;

[0180] The gate of the second output transistor TO2 is electrically connected to the second node QB, the source of the second output transistor TO2 is electrically connected to the drive signal output terminal GN, and the source of the second output transistor TO2 is electrically connected to the low voltage terminal VGL;

[0181] The first energy storage circuit includes a first capacitor C1; the second energy storage circuit includes a second capacitor C2;

[0182] The first end of the first capacitor C1 is electrically connected to the first node Q, and the second end of the first capacitor C1 is electrically connected to the driving signal output terminal GN;

[0183] A first end of the second capacitor C2 is electrically connected to the second node QB, and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.

[0184] In the present invention, Figure 5 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0185] The present invention Figure 5 When at least one embodiment of the driving circuit shown is in operation, when CN provides a high voltage signal and CNB provides a low voltage signal, the driving circuit performs forward scanning in conjunction with the first control voltage provided by STU; when CN provides a high voltage signal and CNB provides a low voltage signal, the driving circuit performs reverse scanning in conjunction with the second control voltage provided by STD; wherein the first control voltage and the second control voltage can be combined into one voltage signal.

[0186] The present invention Figure 5 At least one embodiment of the driving circuit shown in the figure is in operation.

[0187] When performing forward scanning, when the pulse width of the first control voltage provided by STU changes, the pulse width of the driving signal output by GN will also change accordingly;

[0188] During reverse scanning, when the pulse width of the second control voltage provided by STD changes, the pulse width of the driving signal output by GN will also change accordingly.

[0189] like Figure 6 As shown, the present invention Figure 5 In at least one embodiment of the driving circuit shown, when performing forward scanning, CN provides a high voltage signal and CNB provides a low voltage signal; the driving cycle includes a first forward scanning stage S11, a second forward scanning stage S12, a first interval stage S01, a third forward scanning stage S13, a second interval stage S02 and a fourth forward scanning stage S14 which are successively arranged;

[0190] In the first forward scanning stage S11, XCK provides a low voltage signal, T11 is turned off, so as to control the disconnection between the connection node J1 and the second node QB; C1 maintains the potential of the first node Q, and C2 maintains the potential of the second node QB;

[0191] In the first positive scan stage S11, CK provides a high voltage signal, STU provides a high voltage signal, T9 is turned on, T5 and T6 are turned on, so that the potential of QP is a high voltage, and T10 is turned on; then CK provides a low voltage signal, T9 is turned off, the potential of QP is a low voltage, T10 is turned off, and T11 is turned off;

[0192] In the second positive scan stage S12, CK provides a low voltage signal, XCK provides a high voltage signal, STU provides a high voltage signal, STD provides a low voltage signal, T1 and T2 are turned on, and the first node Q is controlled to be connected with STU. At this time, the potential of the first node Q is a high voltage; since T5 and T6 are continuously turned on, the potential of QP is a low voltage, T10 is turned off, T12 and T13 are both turned on, the potential of the second node QB is a low voltage, TO1 is turned on, TO2 is turned off, and GN outputs a high voltage signal;

[0193] In the first interval phase S01, CK provides a low voltage signal, XCK provides a low voltage signal, STU provides a low voltage signal, T1 is turned off, C1 maintains the potential of the first node Q as a high voltage, C2 maintains the potential of the second node QB as a low voltage, TO1 is turned on, TO2 is turned off, and GN continues to output a high voltage signal;

[0194] In the third forward scanning stage S13, CK provides a high voltage signal, XCK provides a low voltage signal, STU provides a low voltage signal, T9 is turned on, the potential of QP is a high voltage, T10 is turned on, T11 is turned off, the potential of the second node QB is maintained at a low voltage, TO2 is turned off, T1 and T4 are turned off, the potential of the first node Q is maintained at a high voltage, TO1 is turned on, and GN outputs a high voltage signal;

[0195] In the second interval phase S02, CK provides a low voltage signal, XCK provides a low voltage signal, T9 is closed, the potential of the control node QP is maintained at a high level, T10 is opened, T11 is closed, and the potential of the second node QB is maintained at a low voltage; TO2 is closed, T1 and T4 are closed, the potential of the first node Q is maintained at a high voltage, TO1 is opened, and GN outputs a high voltage signal;

[0196] In the fourth forward scan stage S14, CK provides a low voltage signal, XCK provides a high voltage signal, STU provides a low voltage signal, T1 is turned on, T2 is turned on, and the potential of the first node Q is set to a low voltage by discharging, T5 is turned off, T9 is turned off, T7 is turned off, and the potential of the control node QP is maintained at a high voltage, T10 is turned on, T11 is turned on, the potential of the second node QB is a high voltage, TO1 is turned off, TO2 is turned on, GN outputs a low voltage signal, and then scans step by step to the end of the last level.

[0197] like Figure 7 As shown, including Figure 5 The driving module of at least one embodiment of the driving circuit shown may include a 12-level driving circuit;

[0198] The first-level drive signal output terminal is labeled G1, the second-level drive signal output terminal is labeled G2, the third-level drive signal output terminal is labeled G3, the fourth-level drive signal output terminal is labeled G4, the fifth-level drive signal output terminal is labeled G5, the sixth-level drive signal output terminal is labeled G6, the seventh-level drive signal output terminal is labeled G7, the eighth-level drive signal output terminal is labeled G8, the ninth-level drive signal output terminal is labeled G9, the tenth-level drive signal output terminal is labeled G10, the eleventh-level drive signal output terminal is labeled G11, and the twelfth-level drive signal output terminal is labeled G12.

[0199] like Figure 8 As shown, the present invention Figure 5 In at least one embodiment of the driving circuit shown, when performing forward scanning, CN provides a low voltage signal and CNB provides a high voltage signal; the driving cycle includes a first reverse scanning stage S21, a second reverse scanning stage S22, a third interval stage S03, a third reverse scanning stage S23, a fourth interval stage S04 and a fourth reverse scanning stage S24 which are arranged in sequence;

[0200] In the first reverse scanning stage S21, XCK provides a low voltage signal, T11 is turned off, so as to control the disconnection between the connection node J1 and the second node QB; C1 maintains the potential of the first node Q, and C2 maintains the potential of the second node QB;

[0201] In the first reverse scan stage S21, CK provides a high voltage signal, STD provides a high voltage signal, T9 is turned on, T7 and T8 are turned on, so that the potential of the control node QP is a high voltage, and T10 is turned on; then CK provides a low voltage signal, T9 is turned off, the potential of the control node QP is a low voltage, T10 is turned off, and T11 is turned off;

[0202] In the second reverse scanning stage S22, CK provides a low voltage signal, XCK provides a high voltage signal, STD provides a high voltage signal, STU provides a low voltage signal, T3 and T4 are turned on, and the first node Q is controlled to be connected with STD. At this time, the potential of the first node Q is a high voltage; since T7 and T8 are continuously turned on, the potential of the control node QP is a low voltage, T10 is turned off, T12 and T13 are both turned on, the potential of the second node QB is a low voltage, TO1 is turned on, TO2 is turned off, and GN outputs a high voltage signal;

[0203] In the third interval stage S03, CK provides a low voltage signal, XCK provides a low voltage signal, STD provides a low voltage signal, T1 is turned off, C1 maintains the potential of the first node Q as a high voltage, C2 maintains the potential of the second node QB as a low voltage, TO1 is turned on, TO2 is turned off, and GN continues to output a high voltage signal;

[0204] In the third reverse scan stage S23, CK provides a high voltage signal, XCK provides a low voltage signal, STD provides a low voltage signal, T9 is turned on, the potential of the control node QP is a high voltage, T10 is turned on, T11 is turned off, the potential of the second node QB is maintained at a low voltage, TO2 is turned off, T1 and T4 are turned off, the potential of the first node Q is maintained at a high voltage, TO1 is turned on, and GN outputs a high voltage signal;

[0205] In the third interval stage S03, CK provides a low voltage signal, XCK provides a low voltage signal, T9 is closed, the potential of the control node QP is maintained at a high level, T10 is opened, T11 is closed, and the potential of the second node QB is maintained at a low voltage; TO2 is closed, T1 and T4 are closed, the potential of the first node Q is maintained at a high voltage, TO1 is opened, and GN outputs a high voltage signal;

[0206] In the fourth reverse scan stage S24, CK provides a low voltage signal, XCK provides a high voltage signal, STD provides a low voltage signal, T3 is turned on, T4 is turned on, and the potential of the first node Q is set to a low voltage by discharging, T6 is turned off, T9 is turned off, T8 is turned off, and the potential of the control node QP is maintained at a high voltage, T10 is turned on, T11 is turned on, the potential of the second node QB is a high voltage, TO1 is turned off, TO2 is turned on, and GN outputs a low voltage signal.

[0207] like Fig. 9 As shown, including Figure 5The driving module of at least one embodiment of the driving circuit shown may include a 12-level driving circuit;

[0208] The first-level drive signal output terminal is labeled G1, the second-level drive signal output terminal is labeled G2, the third-level drive signal output terminal is labeled G3, the fourth-level drive signal output terminal is labeled G4, the fifth-level drive signal output terminal is labeled G5, the sixth-level drive signal output terminal is labeled G6, the seventh-level drive signal output terminal is labeled G7, the eighth-level drive signal output terminal is labeled G8, the ninth-level drive signal output terminal is labeled G9, the tenth-level drive signal output terminal is labeled G10, the eleventh-level drive signal output terminal is labeled G11, and the twelfth-level drive signal output terminal is labeled G12.

[0209] When including Figure 5 When the driving module of at least one embodiment of the driving circuit shown includes a 24-level driving circuit,

[0210] like Fig.10 As shown, when the driving module performs forward scanning, each driving signal output terminal outputs corresponding driving signals in sequence from top to bottom;

[0211] like Fig.11 As shown, when the driving module performs forward scanning, each driving signal output terminal outputs the corresponding driving signal in sequence from bottom to top.

[0212] exist Fig.10 and Fig.11 , the first-level drive signal output terminal is labeled G1, the second-level drive signal output terminal is labeled G2, the third-level drive signal output terminal is labeled G3, the fourth-level drive signal output terminal is labeled G4, the eleventh-level drive signal output terminal is labeled G11, the twelfth-level drive signal output terminal is labeled G12, the thirteenth-level drive signal output terminal is labeled G13, the fourteenth-level drive signal output terminal is labeled G14, the fifteenth-level drive signal output terminal is labeled G15, the sixteenth-level drive signal output terminal is labeled G16, the seventeenth-level drive signal output terminal is labeled G17, the eighteenth-level drive signal output terminal is labeled G18, the eighteenth-level drive signal output terminal is labeled G19, and the nineteenth-level drive signal output terminal is labeled G20.

[0213] When including Figure 5 When the driving module of at least one embodiment of the driving circuit shown includes a 12-level driving circuit,

[0214] like Fig.12As shown, when the driving module performs forward scanning, each driving signal output terminal sequentially outputs corresponding driving signals from top to bottom, and the forward scanning pulse width is 1 clock cycle;

[0215] like Fig.13A As shown, when the driving module performs reverse scanning, each driving signal output terminal sequentially outputs corresponding driving signals from bottom to top, and the reverse scanning pulse width is 1 clock cycle;

[0216] like Fig. 13B As shown, when the driving module performs reverse scanning, each driving signal output terminal sequentially outputs corresponding driving signals from bottom to top, and the reverse scanning pulse width is 4 clock cycles. Fig.12 , Fig.13A and Fig. 13B , the one labeled G1 is the first-stage drive signal output terminal, the one labeled G2 is the second-stage drive signal output terminal, the one labeled G3 is the third-stage drive signal output terminal, the one labeled G10 is the tenth-stage drive signal output terminal, the one labeled G11 is the eleventh-stage drive signal output terminal, and the one labeled G12 is the twelfth-stage drive signal output terminal.

[0217] The driving circuit described in at least one embodiment of the present invention further includes a driving output terminal, an output resistor and an output capacitor;

[0218] The first end of the output resistor is electrically connected to the drive signal output terminal; the second end of the output resistor is electrically connected to the drive output terminal; the first end of the output capacitor is electrically connected to the second end of the output resistor, and the second end of the output capacitor is grounded; or,

[0219] The driving circuit further includes a driving output terminal, M output resistors and M output capacitors, where M is an integer greater than 1;

[0220] A first end of a first output resistor is electrically connected to the drive signal output terminal, and a second end of an Mth output resistor is electrically connected to the drive output terminal;

[0221] The first end of the m-th output resistor is electrically connected to the second end of the m-1-th output resistor; m is an integer less than or equal to M and greater than 1;

[0222] A first end of a first output capacitor is electrically connected to a second end of the first output resistor, and a second end of the first output capacitor is grounded;

[0223] A first end of the mth output capacitor is electrically connected to a second end of the mth output resistor, and a second end of the mth output capacitor is grounded.

[0224] In a specific implementation, when the driving circuit described in at least one embodiment of the present invention further includes a driving output terminal, the driving signal output terminal is used for cascading, and the driving output terminal is used to provide a driving signal for a corresponding transistor in the pixel circuit.

[0225] like Fig.14 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown in FIG. 1 , the driving circuit according to at least one embodiment of the present invention further includes a driving output terminal ON, a first output resistor R1, a second output resistor R2, a third output resistor R3, a fourth output resistor R4, a fifth output resistor R5, a first output capacitor C01, a second output capacitor C02, a third output capacitor C03, a fourth output capacitor C04 and a fifth output capacitor C05;

[0226] A first end of R1 is electrically connected to GN, and a second end of R1 is electrically connected to a first end of R2;

[0227] The second end of R2 is electrically connected to the first end of R3, and the second end of R3 is electrically connected to the first end of R4;

[0228] The second end of R4 is electrically connected to the first end of R5, and the second end of R5 is electrically connected to the driving output end ON;

[0229] The first end of C01 is electrically connected to the second end of R1, and the second end of C01 is electrically connected to the ground;

[0230] The first end of C02 is electrically connected to the second end of R2, and the second end of C02 is electrically connected to the ground;

[0231] The first end of C03 is electrically connected to the second end of R3, and the second end of C03 is electrically connected to the ground;

[0232] The first end of C04 is electrically connected to the second end of R4, and the second end of C04 is electrically connected to the ground;

[0233] A first end of C05 is electrically connected to the second end of R1, and a second end of C05 is electrically connected to the ground.

[0234] Fig.15 It is a connection diagram of the minimum repeating unit of odd and even rows.

[0235] exist Fig.14 In at least one embodiment of the driving circuit shown, ON is the Nth stage driving output terminal, and N is a positive integer.

[0236] exist Fig.15 In the figure, the circuit diagram of the Nth stage driving circuit is denoted by 151, and the circuit diagram of the N+1th stage driving circuit is denoted by 152.

[0237] exist Fig.15Among them, the one labeled GN is the Nth level drive signal output terminal, GN+1 is the N+1th level drive signal output terminal, ON is the Nth level drive output terminal, and ON+1 is the N+1th level drive output terminal;

[0238] The second control voltage terminal of the Nth stage driving circuit 151 is electrically connected to GN+1;

[0239] The first control voltage terminal of the (N+1)th stage driving circuit 152 is electrically connected to GN.

[0240] Fig.16 is a structural diagram of a driving module according to at least one embodiment of the present invention.

[0241] like Fig.16 As shown, the driving module described in at least one embodiment of the present invention includes a first-stage driving circuit GOA1, a second-stage driving circuit GOA2, a third-stage driving circuit GOA3, an N-2-stage driving circuit GOAN-2, an N-1-stage driving circuit GOAN-1 and an N-stage driving circuit GOAN;

[0242] exist Fig.16 In at least one embodiment shown, N is greater than 4;

[0243] exist Fig.16 , the terminal labeled XCK is the first clock signal terminal, the terminal labeled CK is the second clock signal terminal, the terminal labeled CN is the first scan control terminal, and the terminal labeled CNB is the second scan control terminal;

[0244] The terminal labeled STV1 is a first starting voltage terminal, the terminal labeled STV2 is a second starting voltage terminal, the terminal labeled VGH is a high voltage terminal, and the terminal labeled VGL is a low voltage terminal;

[0245] The one labeled G1 is the first-stage drive signal output terminal, and the one labeled O1 is the first-stage drive output terminal;

[0246] The one labeled G2 is the second-stage drive signal output terminal, and the one labeled O2 is the second-stage drive output terminal;

[0247] The one labeled G3 is the third-level drive signal output terminal, and the one labeled O3 is the third-level drive output terminal;

[0248] The one labeled GN-2 is the N-2-th level drive signal output terminal, and the one labeled O N-2 is the N-2-th level drive output terminal;

[0249] The one labeled GN-1 is the N-1th level drive signal output terminal, and the one labeled ON-1 is the N-1th level drive output terminal;

[0250] The one labeled GN is the Nth level drive signal output terminal, and the one labeled ON is the Nth level drive output terminal;

[0251] The first control voltage terminal of GOA1 is electrically connected to the first starting voltage terminal STV1, and the second control voltage terminal of GOA1 is electrically connected to G2;

[0252] A first control voltage terminal of GOA2 is electrically connected to G1, and a second control voltage terminal of GOA2 is electrically connected to G3;

[0253] A first control voltage terminal of GOA3 is electrically connected to G2;

[0254] The second control voltage terminal of GOAN-2 is electrically connected to GN-1;

[0255] The first control voltage terminal of GOAN-1 is electrically connected to GN-2, and the second control voltage terminal of GOAN-1 is electrically connected to GN;

[0256] The first control voltage terminal of GOAN is electrically connected to GN-1, and the second control voltage terminal of GOAN is electrically connected to the second starting voltage terminal STV2.

[0257] Optionally, the output circuit includes a first output transistor, a second output transistor and a third output transistor;

[0258] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal;

[0259] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first electrode of the third output transistor;

[0260] A control electrode of the third output transistor is electrically connected to the second node, and a second electrode of the third output transistor is electrically connected to the second voltage terminal.

[0261] The driving circuit described in at least one embodiment of the present invention further includes a second leakage prevention circuit;

[0262] The second anti-leakage circuit is electrically connected to the drive signal output terminal, the first voltage terminal and the second electrode of the second output transistor respectively, and is used to control the connection between the first voltage terminal and the second electrode of the second output transistor under the control of the drive signal provided by the drive signal output terminal.

[0263] Optionally, the first leakage prevention circuit includes a fourteenth transistor;

[0264] The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the second electrode of the first transistor and the second electrode of the third transistor.

[0265] Optionally, the second leakage prevention circuit includes a fifteenth transistor;

[0266] The control electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, the first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second electrode of the second output transistor.

[0267] The present invention Fig.17 At least one embodiment of the driving circuit shown in FIG. Figure 5 The differences of at least one embodiment of the driving circuit shown are as follows:

[0268] The output circuit 14 includes a first output transistor TO1, a second output transistor TO2 and a third output transistor TO3;

[0269] The gate of the first output transistor TO1 is electrically connected to the first node Q, the source of the first output transistor TO1 is electrically connected to the high voltage terminal VGH, and the drain of the first output transistor TO1 is electrically connected to the drive signal output terminal GN;

[0270] The gate of the second output transistor TO2 is electrically connected to the second node QB, the source of the second output transistor TO2 is electrically connected to the drive signal output terminal GN, and the drain of the second output transistor TO2 is electrically connected to the source of the third output transistor TO3;

[0271] A gate of the third output transistor TO3 is electrically connected to the second node QB, and a drain of the third output transistor TO3 is electrically connected to the low voltage terminal VGL.

[0272] In the present invention, Fig.17 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0273] like Fig.18 As shown, in Fig.17 Based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes a second leakage prevention circuit 181;

[0274] The second anti-leakage circuit 181 is electrically connected to the drive signal output terminal GN, the high voltage terminal VGH and the drain of the second output transistor TO2, respectively, and is used to control the connection between the high voltage terminal VGH and the drain of the second output transistor TO2 under the control of the drive signal provided by the drive signal output terminal GN.

[0275] The present invention Fig.18 When at least one embodiment of the driving circuit shown is in operation, when GN outputs a high voltage signal, the second leakage prevention circuit 181 controls the connection between the high voltage terminal VGH and the drain of the second output transistor TO2, so that the potential of the drain of the second output transistor TO2 is a high voltage, preventing GN from leaking to the low voltage terminal VGL.

[0276] like Fig.19 As shown, in Fig.18 In at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of the present invention further includes a first leakage prevention circuit 41;

[0277] The first anti-leakage circuit 41 includes a fourteenth transistor T14;

[0278] The gate of the fourteenth transistor T14 is electrically connected to the first node Q, the source of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGH, and the drain of the fourteenth transistor T14 is electrically connected to the drain of the first transistor T1 and the drain of the third transistor T3;

[0279] The second anti-leakage circuit 181 includes a fifteenth transistor T15;

[0280] A gate of the fifteenth transistor T15 is electrically connected to the driving signal output terminal GN, a source of the fifteenth transistor T15 is electrically connected to the high voltage terminal VGH, and a drain of the fifteenth transistor T15 is electrically connected to a drain of the second output transistor TO2.

[0281] exist Fig.19 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but the present invention is not limited thereto.

[0282] like Fig. 20 As shown, in Fig.19 Based on at least one embodiment of the driving circuit shown in FIG. 1 , the driving circuit according to at least one embodiment of the present invention further includes a driving output terminal ON, a first output resistor R1, a second output resistor R2, a third output resistor R3, a fourth output resistor R4, a fifth output resistor R5, a first output capacitor C01, a second output capacitor C02, a third output capacitor C03, a fourth output capacitor C04 and a fifth output capacitor C05;

[0283] A first end of R1 is electrically connected to GN, and a second end of R1 is electrically connected to a first end of R2;

[0284] The second end of R2 is electrically connected to the first end of R3, and the second end of R3 is electrically connected to the first end of R4;

[0285] The second end of R4 is electrically connected to the first end of R5, and the second end of R5 is electrically connected to the driving output end ON;

[0286] The first end of C01 is electrically connected to the second end of R1, and the second end of C01 is electrically connected to the ground;

[0287] The first end of C02 is electrically connected to the second end of R2, and the second end of C02 is electrically connected to the ground;

[0288] The first end of C03 is electrically connected to the second end of R3, and the second end of C03 is electrically connected to the ground;

[0289] The first end of C04 is electrically connected to the second end of R4, and the second end of C04 is electrically connected to the ground;

[0290] A first end of C05 is electrically connected to the second end of R1, and a second end of C05 is electrically connected to the ground.

[0291] The driving method described in the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method includes:

[0292] The first node control circuit controls the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the first scan control signal, the first clock signal and the second scan control signal;

[0293] The control node control circuit controls the potential of the control node under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage according to the second clock signal provided by the second clock signal terminal, and controls the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal;

[0294] The second node control circuit controls the connection or disconnection between the second node and the second voltage terminal under the control of the potential of the first node, controls the potential of the connection node according to the potential of the control node, and controls the connection or disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection or disconnection between the connection node and the second node under the control of the first clock signal;

[0295] The output circuit controls the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0296] In at least one embodiment of the present invention, the driving circuit further includes a first energy storage circuit and a second energy storage circuit; when the driving circuit performs forward scanning, the first scanning control terminal provides a third voltage signal, and the second scanning control terminal provides a fourth voltage signal, and the driving cycle includes a first forward scanning stage, a second forward scanning stage, a third forward scanning stage, and a fourth forward scanning stage which are successively arranged;

[0297] The driving method comprises: when the driving circuit performs forward scanning,

[0298] In the first positive scanning stage, the first clock signal terminal provides a sixth voltage signal, and the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node;

[0299] In the second forward scanning stage, the first control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the first control voltage and the first scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the first control voltage terminal under the control of the first scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

[0300] In the third positive scanning stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal; the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; and the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node;

[0301] In the fourth positive scan stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The first node control circuit controls the connection between the first node and the first control voltage terminal under the control of the first scan control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0302] In at least one embodiment of the present invention, the driving circuit further includes a first energy storage circuit and a second energy storage circuit; when the driving circuit performs reverse scanning, the first scanning control terminal provides a fourth voltage signal, the second scanning control terminal provides a third voltage signal, and the driving cycle includes a first reverse scanning stage, a second reverse scanning stage, a third reverse scanning stage and a fourth reverse scanning stage which are arranged in sequence; the driving method includes: when the driving circuit performs reverse scanning,

[0303] In the first reverse scanning stage, the second control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a sixth voltage signal, the second clock signal terminal provides a fifth voltage signal, and the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node;

[0304] In the second reverse scanning stage, the second control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the second control voltage and the second scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node;

[0305] In the third reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal; the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node;

[0306] In the fourth reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The first node control circuit controls the connection between the first node and the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

[0307] The driving module described in the embodiment of the present invention includes multiple stages of the above-mentioned driving circuits;

[0308] The first control voltage terminal of the first stage driving circuit is electrically connected to the starting voltage terminal;

[0309] The first control voltage terminal of the a-th level driving circuit is electrically connected to the driving signal output terminal of the a-1-th level driving circuit;

[0310] The second control voltage terminal of the b-th level driving circuit is electrically connected to the driving signal output terminal of the b+1-th level driving circuit;

[0311] a is an integer greater than 1, and b is a positive integer.

[0312] The display device described in the embodiment of the present invention includes the above-mentioned driving circuit.

[0313] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0314] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: including a first node control circuit, a second node control circuit, a control node control circuit and an output circuit; The first node control circuit is used to control the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the first scan control signal provided by the first scan control terminal, the first clock signal provided by the first clock signal terminal and the second scan control signal provided by the second scan control terminal; The control node control circuit is used to control the potential of the control node according to the second clock signal provided by the second clock signal terminal under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage, and to control the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal, and to maintain the potential of the control node; The second node control circuit is electrically connected to the first node, the second node, the connection node, the control node, the first clock signal terminal and the second voltage terminal respectively, and is used to control the connection or disconnection between the second node and the second voltage terminal under the control of the potential of the first node, control the connection or disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node, and control the connection or disconnection between the connection node and the second node under the control of the first clock signal; The output circuit is electrically connected to the first node, the second node, the first voltage terminal, the second voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node, and control the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node; The driving circuit also includes a first energy storage circuit and a second energy storage circuit; The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the drive signal output end, and is used to control the potential of the first node according to the drive signal output by the drive signal output end; The second energy storage circuit is electrically connected to the second node and is used to maintain the potential of the second node; When the driving circuit performs forward scanning, the driving cycle includes a first forward scanning stage, a second forward scanning stage, a third forward scanning stage and a fourth forward scanning stage which are arranged in sequence; The second node control circuit is used for controlling the disconnection between the connection node and the second node under the control of the first clock signal during the first positive scanning phase; The first energy storage circuit is used to maintain the potential of the first node in the first positive scanning stage, and the second energy storage circuit is used to maintain the potential of the second node in the first positive scanning stage; The control node control circuit is used for controlling the connection between the second clock signal terminal and the control node under the control of the first control voltage and the first scanning control signal in the second forward scanning stage; The second node control circuit is used for controlling the disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node in the second positive scanning phase; The first node control circuit is used for controlling the connection between the first node and the first control voltage terminal under the control of the first scanning control signal and the first clock signal in the second forward scanning stage; The output circuit is used for controlling the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node in the second positive scanning stage; The control node control circuit is used to control the connection between the control node and the first voltage terminal under the control of the second clock signal in the third positive scanning stage; the second node control circuit is used to control the disconnection between the connection node and the second node under the control of the first clock signal in the third positive scanning stage; The first energy storage circuit is used for maintaining the potential of the first node in the third positive scanning stage; The output circuit is used for controlling the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node in the third forward scanning stage; The first node control circuit is used for controlling the connection between the first node and the first control voltage terminal under the control of the first scanning control signal and the first clock signal in the fourth positive scanning stage; the control node control circuit is used for maintaining the potential of the control node in the fourth positive scanning stage; The second node control circuit is used for controlling the connection between the first clock signal terminal and the connection node under the control of the potential of the control node in the fourth positive scanning stage, and controlling the connection between the connection node and the second node under the control of the first clock signal; The output circuit is used to control the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node in the fourth positive scanning stage.

2. The driving circuit according to claim 1, characterized in that: The first node control circuit is electrically connected to the first node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal and the first clock signal terminal, respectively, and is used to control the connection or disconnection between the first node and the first control voltage terminal under the control of the first scan control signal provided by the first scan control terminal and the first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the first node and the second control voltage terminal under the control of the second scan control signal provided by the second scan control terminal and the first clock signal; The control node control circuit is electrically connected to the control node, the first control voltage terminal, the second control voltage terminal, the first scan control terminal, the second scan control terminal, the second clock signal terminal and the first voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the second clock signal terminal under the control of the first scan control signal and the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the control node and the second clock signal terminal under the control of the second scan control signal and the second control voltage provided by the second control voltage terminal, and to control the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal.

3. The driving circuit according to claim 2, characterized in that: The first node control circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first control voltage terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor; The control electrode of the second transistor is electrically connected to the first scan control terminal, and the second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the second scan control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; A control electrode of the fourth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fourth transistor is electrically connected to the second control voltage terminal.

4. The driving circuit according to claim 3, characterized in that: Also included is a first leakage prevention circuit; The first leakage prevention circuit is electrically connected to the first node, the first voltage terminal, the second electrode of the first transistor and the second electrode of the third transistor, respectively, and is used to control the connection between the first voltage terminal and the second electrode of the first transistor, and to control the connection between the first voltage terminal and the second electrode of the third transistor under the control of the potential of the first node.

5. The driving circuit according to claim 2, characterized in that: The control node control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a storage capacitor; The control electrode of the fifth transistor is electrically connected to the first control voltage terminal, the first electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor; The control electrode of the sixth transistor is electrically connected to the first scan control terminal, and the second electrode of the sixth transistor is electrically connected to the control node; The control electrode of the seventh transistor is electrically connected to the second scan control terminal, the first electrode of the seventh transistor is electrically connected to the control node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; The control electrode of the eighth transistor is electrically connected to the second control voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second clock signal terminal; The control electrode of the ninth transistor is electrically connected to the second clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the control node; A first end of the storage capacitor is electrically connected to the control node, and a second end of the storage capacitor is electrically connected to the connection node.

6. The driving circuit according to any one of claims 1 to 5, characterized in that: The second node control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The control electrode of the tenth transistor is electrically connected to the control node, the first electrode of the tenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the connection node; The control electrode of the eleventh transistor is electrically connected to the first clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the connection node, and the second electrode of the eleventh transistor is electrically connected to the second node; The control electrode of the twelfth transistor and the control electrode of the thirteenth transistor are both electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second voltage terminal, the second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor; the second electrode of the thirteenth transistor is electrically connected to the second node.

7. The driving circuit according to any one of claims 1 to 5, characterized in that: The output circuit includes a first output transistor and a second output transistor; The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal; The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the second voltage terminal.

8. The driving circuit according to any one of claims 1 to 5, characterized in that: The output circuit includes a first output transistor, a second output transistor and a third output transistor; The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first voltage terminal, and the second electrode of the first output transistor is electrically connected to the drive signal output terminal; The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first electrode of the third output transistor; A control electrode of the third output transistor is electrically connected to the second node, and a second electrode of the third output transistor is electrically connected to the second voltage terminal.

9. The driving circuit according to claim 8, characterized in that: Also comprising a second leakage prevention circuit; The second anti-leakage circuit is electrically connected to the drive signal output terminal, the first voltage terminal and the second electrode of the second output transistor respectively, and is used to control the connection between the first voltage terminal and the second electrode of the second output transistor under the control of the drive signal provided by the drive signal output terminal.

10. The driving circuit according to any one of claims 1 to 5, characterized in that: The first energy storage circuit includes a first capacitor; the second energy storage circuit includes a second capacitor; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the drive signal output terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the second voltage end.

11. The driving circuit according to claim 4, characterized in that: The first leakage prevention circuit includes a fourteenth transistor; The control electrode of the fourteenth transistor is electrically connected to the first node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the second electrode of the first transistor and the second electrode of the third transistor.

12. The driving circuit according to claim 9, characterized in that: The second leakage prevention circuit includes a fifteenth transistor; The control electrode of the fifteenth transistor is electrically connected to the drive signal output terminal, the first electrode of the fifteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifteenth transistor is electrically connected to the second electrode of the second output transistor.

13. The driving circuit according to any one of claims 1 to 5, characterized in that: It also includes a driver output terminal, an output resistor, and an output capacitor; The first end of the output resistor is electrically connected to the drive signal output terminal; the second end of the output resistor is electrically connected to the drive output terminal; the first end of the output capacitor is electrically connected to the second end of the output resistor, and the second end of the output capacitor is grounded; or, The driving circuit further includes a driving output terminal, M output resistors and M output capacitors, where M is an integer greater than 1; A first end of a first output resistor is electrically connected to the drive signal output terminal, and a second end of an Mth output resistor is electrically connected to the drive output terminal; The first end of the mth output resistor is electrically connected to the second end of the m-1th output resistor; m is an integer less than or equal to M and greater than 1; A first end of a first output capacitor is electrically connected to a second end of the first output resistor, and a second end of the first output capacitor is grounded; A first end of the mth output capacitor is electrically connected to a second end of the mth output resistor, and a second end of the mth output capacitor is grounded.

14. A driving method, applied to the driving circuit according to any one of claims 1 to 13, characterized in that: The driving method comprises: The first node control circuit controls the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the first scan control signal, the first clock signal and the second scan control signal; The control node control circuit controls the potential of the control node under the control of the first scan control signal, the first control voltage, the second scan control signal and the second control voltage according to the second clock signal provided by the second clock signal terminal, and controls the connection or disconnection between the control node and the first voltage terminal under the control of the second clock signal; The second node control circuit controls the connection or disconnection between the second node and the second voltage terminal under the control of the potential of the first node, controls the potential of the connection node according to the potential of the control node, and controls the connection or disconnection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection or disconnection between the connection node and the second node under the control of the first clock signal; The output circuit controls the connection or disconnection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node; The driving circuit also includes a first energy storage circuit and a second energy storage circuit; when the driving circuit performs forward scanning, the driving cycle includes a first forward scanning stage, a second forward scanning stage, a third forward scanning stage and a fourth forward scanning stage which are arranged in sequence; The driving method comprises: when the driving circuit performs forward scanning, In the first positive scanning stage, the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node; In the second forward scanning stage, the control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the first control voltage and the first scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the first control voltage terminal under the control of the first scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node; In the third positive scanning stage, the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node; In the fourth positive scan stage, the first node control circuit controls the connection between the first node and the first control voltage terminal under the control of the first scan control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

15. The driving method according to claim 14, characterized in that: When the driving circuit performs reverse scanning, the first scanning control terminal provides a fourth voltage signal, the second scanning control terminal provides a third voltage signal, and the driving cycle includes a first reverse scanning stage, a second reverse scanning stage, a third reverse scanning stage and a fourth reverse scanning stage which are arranged in sequence; the driving method includes: when the driving circuit performs reverse scanning, In the first reverse scanning stage, the first clock signal terminal provides a sixth voltage signal, and the second node control circuit controls the connection node and the second node to be disconnected under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node, and the second energy storage circuit maintains the potential of the second node; In the second reverse scanning stage, the second control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The control node control circuit controls the second clock signal terminal to be connected to the control node under the control of the second control voltage and the second scanning control signal; the second node control circuit controls the first clock signal terminal to be disconnected from the connection node under the control of the potential of the control node; the first node control circuit controls the first node to be connected to the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the output circuit controls the drive signal output terminal to be connected to the first voltage terminal under the control of the potential of the first node; In the third reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal; the control node control circuit controls the connection between the control node and the first voltage terminal under the control of the second clock signal; the second node control circuit controls the disconnection between the connection node and the second node under the control of the first clock signal; the first energy storage circuit maintains the potential of the first node; the output circuit controls the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the first node; In the fourth reverse scanning stage, the second control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal. The first node control circuit controls the connection between the first node and the second control voltage terminal under the control of the second scanning control signal and the first clock signal; the control node control circuit maintains the potential of the control node; the second node control circuit controls the connection between the first clock signal terminal and the connection node under the control of the potential of the control node, and controls the connection between the connection node and the second node under the control of the first clock signal; the output circuit controls the connection between the drive signal output terminal and the second voltage terminal under the control of the potential of the second node.

16. The driving method according to claim 14, characterized in that: Also includes: When the driving circuit performs forward scanning, the first scanning control terminal provides a third voltage signal, and the second scanning control terminal provides a fourth voltage signal; The driving method comprises: when the driving circuit performs forward scanning, In the first positive scanning stage, the first clock signal terminal provides a sixth voltage signal; In the second forward scanning stage, the first control voltage terminal provides a fifth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal; In the third positive scanning stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a sixth voltage signal, and the second clock signal terminal provides a fifth voltage signal; In the fourth positive scanning stage, the first control voltage terminal provides a sixth voltage signal, the first clock signal terminal provides a fifth voltage signal, and the second clock signal terminal provides a sixth voltage signal.

17. A driving module, characterized in that: A driving circuit comprising a plurality of stages as claimed in any one of claims 1 to 13; The first control voltage terminal of the first stage driving circuit is electrically connected to the starting voltage terminal; The first control voltage terminal of the a-th level driving circuit is electrically connected to the driving signal output terminal of the a-1-th level driving circuit; The second control voltage terminal of the b-th level driving circuit is electrically connected to the driving signal output terminal of the b+1-th level driving circuit; a is an integer greater than 1, and b is a positive integer.

18. A display device, characterized in that: Comprising the driving module as claimed in claim 17.

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