Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display, which is used for reducing the voltage drop of a cathode and improving the brightness uniformity of the display panel. The display panel comprises a substrate, an auxiliary electrode, a connecting part, a light-emitting layer and a cathode layer. The connecting part comprises a first connecting pattern, a second connecting pattern and a third connecting pattern, the first connecting pattern is electrically connected with the auxiliary electrode, and the edge of the second connecting pattern is inwardly recessed relative to the edge of the third connecting pattern. The light-emitting layer comprises a first light-emitting pattern and a second light-emitting pattern, the first light-emitting pattern is located around the second light-emitting pattern and is separated from the second light-emitting pattern, and the second light-emitting pattern is located on the side of the third connecting pattern away from the substrate. The cathode layer passes through the gap between the first light-emitting pattern and the second light-emitting pattern and is electrically contacted with at least one of the first connecting pattern, the second connecting pattern and the third connecting pattern. The display panel provided by the application is applied to the display device and realizes picture display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Compared to passively emitting liquid crystal displays (LCDs), self-emitting organic light-emitting diode displays (OLEDs) have advantages such as fast response, high contrast, and wide viewing angle, and are easy to implement in flexible display applications, thus they are widely used.

[0003] OLED displays emit light in two ways: top-emitting and bottom-emitting. Top-emitting OLED displays require the use of transparent or semi-transparent cathodes. In medium-sized and large-sized OLED displays, the high resistance of transparent electrodes and the thin uniformity of semi-transparent cathodes can easily lead to a large cathode voltage drop (IR Drop), ultimately resulting in poor brightness uniformity of the display panel.

[0004] How to reduce the voltage drop of the cathode and improve the brightness uniformity of the display panel has become one of the main research problems for those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display panel and display device for reducing the voltage drop of the cathode, improving the brightness uniformity of the display panel, and enhancing the display effect of the display panel.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] On one hand, a display panel is provided. The display panel includes a substrate, an auxiliary electrode, a connecting portion, a light-emitting layer, and a cathode layer. The auxiliary electrode is located on the substrate. The connecting portion is located on the side of the auxiliary electrode away from the substrate; the connecting portion includes a first connecting pattern, a second connecting pattern, and a third connecting pattern sequentially stacked in a direction away from the substrate, the first connecting pattern being electrically connected to the auxiliary electrode, and the edge of the second connecting pattern being recessed relative to the edge of the third connecting pattern. The light-emitting layer includes a first light-emitting pattern and a second light-emitting pattern, the first light-emitting pattern being located around and separated from the second light-emitting pattern, and the second light-emitting pattern being located on the side of the third connecting pattern away from the substrate. The cathode layer is located on the side of the light-emitting layer away from the substrate, the cathode layer passing through the gap between the first light-emitting pattern and the second light-emitting pattern, and making electrical contact with at least one of the first connecting pattern, the second connecting pattern, and the third connecting pattern.

[0008] In some embodiments, the orthographic projection of the third connection pattern on the substrate is located inside the orthographic projection of the first connection pattern on the substrate, and there is a gap between the boundary of the orthographic projection of the third connection pattern on the substrate and the boundary of the orthographic projection of the first connection pattern on the substrate.

[0009] In some embodiments, the display panel further includes a circuit structure layer located between the connection portion and the substrate, the circuit structure layer including a semiconductor layer, a gate layer and a source / drain electrode layer; the auxiliary electrode is located in at least one of the semiconductor layer, the gate layer and the source / drain electrode layer.

[0010] In some embodiments, the cathode layer includes a first contact portion and a second contact portion, wherein the first contact portion is located on the side of the first luminescent pattern away from the substrate; and the second contact portion is located on the side of the second luminescent pattern away from the substrate.

[0011] In some embodiments, there is a gap between the second connecting pattern and the first emitting pattern, exposing a portion of the surface of the first connecting pattern; the first contact portion is electrically contacted with the side of the first emitting pattern near the second connecting pattern and the exposed surface of the first connecting pattern; and / or, the first contact portion is electrically contacted with the side of the second connecting pattern.

[0012] In some embodiments, the second contact portion covers the side of the second luminescent pattern near the first luminescent pattern and is in electrical contact with the side of the third connecting pattern.

[0013] In some embodiments, the first contact portion and the second contact portion are separated from each other.

[0014] In some embodiments, the display panel further includes a planarization layer located between the connection portion and the auxiliary electrode; the planarization layer includes a first through-hole that exposes the auxiliary electrode; the first connection pattern contacts the auxiliary electrode through the first through-hole.

[0015] In some embodiments, the first via includes a first port and a second port, the first port being farther away from the substrate than the second port, and the size of the first port being larger than the size of the second port; the wall of the first via is inclined relative to the plane of the substrate, and the edge of the second connection pattern extends to the wall of the first via.

[0016] In some implementations, the cathode layer includes a first contact portion and a second contact portion that are separated from each other, with the edges of the first contact portion and the second contact portion close to each other located on the wall of the first through hole.

[0017] In some embodiments, the display panel further includes a passivation layer located between the planarization layer and the auxiliary electrode; the passivation layer includes a second via that exposes at least a portion of the surface of the auxiliary electrode; the second via communicates with the first via; and the first connection pattern contacts the auxiliary electrode through the first via and the second via.

[0018] In some embodiments, the orthogonal projection of the second via on the substrate lies within the orthogonal projection of the auxiliary electrode on the substrate.

[0019] In some embodiments, the orthographic projection of the second via on the substrate is located inside the orthographic projection of the second port of the first via on the substrate, and there is a gap between the boundary of the orthographic projection of the second via on the substrate and the boundary of the orthographic projection of the second port on the substrate.

[0020] In some embodiments, the orthographic projection of the second via on the substrate is rectangular, and the orthographic projection of the second port of the first via on the substrate is rectangular.

[0021] In some embodiments, the display panel further includes a pixel defining layer located on the side of the connection portion away from the substrate; the pixel defining layer includes a third via that exposes a portion of the surface of the first connection pattern away from the substrate, as well as the sides of the second connection pattern and the third connection pattern; wherein the light-emitting layer contacts the first connection pattern and the third connection pattern through the third via.

[0022] In some embodiments, the display panel further includes an anode layer located between the light-emitting layer and the auxiliary electrode; the connection portion is located on the anode layer; the anode layer further includes an anode, and the pixel defining layer further includes a pixel opening that exposes a portion of the surface of the anode; the pixel opening is offset from the third through-hole.

[0023] In some embodiments, the display panel further includes a planarization layer, wherein the planarization layer includes a first via, the orthographic projection of a first port of the first via on the substrate is located inside the orthographic projection of the third via on the substrate, and there is a gap between the boundary of the orthographic projection of the first port on the substrate and the boundary of the orthographic projection of the third via on the substrate.

[0024] In some embodiments, the display panel includes a plurality of sub-pixels, the plurality of sub-pixels being arranged in multiple rows along a first direction and in multiple columns along a second direction; the first direction intersects the second direction; the display panel includes a plurality of auxiliary electrodes; at least one auxiliary electrode extends along the first direction and is located between two adjacent rows of sub-pixels; and / or, at least one auxiliary electrode extends along the second direction and is located between two adjacent columns of sub-pixels.

[0025] In some embodiments, a first connection pattern is provided where one of the auxiliary electrodes connects to a plurality of the connection portions.

[0026] On the other hand, a display device is provided. The display device includes a display panel as described in any of the above embodiments.

[0027] The display panel and display device provided in this disclosure have the following beneficial effects:

[0028] In the display panel provided in this embodiment, the connecting portion includes a first connecting pattern, a second connecting pattern, and a third connecting pattern. The edge of the second connecting pattern is recessed relative to the edge of the third connecting pattern. So that after the connecting portion is formed, when the light-emitting layer is formed, the light-emitting layer is broken at the edge of the third connecting pattern of the connecting portion, forming a second light-emitting pattern located on the side of the third connecting pattern away from the substrate, and a first light-emitting pattern located around the second light-emitting pattern.

[0029] In this way, the subsequently formed cathode layer can pass through the gap between the first and second light-emitting patterns and make electrical contact with at least one of the first, second, and third connecting patterns. That is, the cathode layer can be electrically connected to the connecting portion, achieving parallel connection with the connecting portion. At the same time, the first connecting pattern of the connecting portion is electrically connected to the auxiliary electrode, so that the cathode layer can be electrically connected to the auxiliary electrode. The cathode layer and the auxiliary electrode form a parallel structure, thereby reducing the resistance of the cathode layer, reducing the voltage drop on the cathode layer, improving the display effect of the display panel, and enhancing the brightness uniformity of the display panel.

[0030] The beneficial effects that the display device provided in this disclosure can achieve are the same as those that the display panel provided in the above-mentioned technical solutions can achieve, and will not be repeated here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0032] Figure 1 This is a structural diagram of a display panel according to some embodiments;

[0033] Figure 2 This is a top view of a connection portion according to some embodiments;

[0034] Figure 3A This is a top view of another connection according to some embodiments;

[0035] Figure 3B This is a top view of another connection according to some embodiments;

[0036] Figure 4 This is a structural diagram of the overlap between a cathode layer and a connecting portion according to some embodiments;

[0037] Figure 5 This is a structural diagram of another overlap between the cathode layer and the connecting portion according to some embodiments;

[0038] Figure 6 for Figure 1 A magnified view of the CC region;

[0039] Figure 7A This is a structural diagram of another display panel according to some embodiments;

[0040] Figure 7B This is a structural diagram of another display panel according to some embodiments;

[0041] Figure 8 This is a circuit structure diagram of a pixel circuit according to some embodiments;

[0042] Figure 9 This is a layout diagram of a display panel according to some embodiments;

[0043] Figure 10 This is a top view of yet another connection according to some embodiments;

[0044] Figure 11 This is a top view of yet another connection according to some embodiments;

[0045] Figure 12 This is a structural diagram of another display panel according to some embodiments;

[0046] Figure 13 This is a structural diagram of yet another display panel according to some embodiments;

[0047] Figure 14 This is a flowchart of a method for manufacturing a display panel according to some embodiments;

[0048] Figure 15 This is a structural diagram of a display device according to some embodiments. Detailed Implementation

[0049] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0052] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0053] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B, and C.

[0054] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0055] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0056] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0057] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0058] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0059] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0060] like Figure 1 As shown, some embodiments of this disclosure provide a display panel 100, which includes a substrate 10, an auxiliary electrode 20, a connecting portion 30, a light-emitting layer 40, and a cathode layer 50.

[0061] The substrate 10 can be a flexible substrate, and the material of the substrate 10 may include, for example, polyimide (PI). Alternatively, the substrate 10 can be a rigid substrate, and the material of the substrate 10 may include, for example, glass.

[0062] The auxiliary electrode 20 is located on the substrate 10. For example, the material of the auxiliary electrode 20 can be a metal, such as aluminum, copper, molybdenum, etc.

[0063] The connection portion 30 is located on the side of the auxiliary electrode 20 away from the substrate 10. The connection portion 30 includes a first connection pattern 31, a second connection pattern 32 and a third connection pattern 33 stacked sequentially in a direction away from the substrate 10. The first connection pattern 31 is electrically connected to the auxiliary electrode 20, and the edge of the second connection pattern 32 is recessed relative to the edge of the third connection pattern 33.

[0064] like Figure 1 As shown, the first connecting pattern 31, the second connecting pattern 32 and the third connecting pattern 33 can be stacked sequentially along the direction Z perpendicular to the substrate 10 and away from the substrate 10.

[0065] The light-emitting layer 40 includes a first light-emitting pattern 41 and a second light-emitting pattern 42. The first light-emitting pattern 41 is located around the second light-emitting pattern 42 and is separated from the second light-emitting pattern 42. The second light-emitting pattern 42 is located on the side of the third connecting pattern 33 away from the substrate 10.

[0066] In some examples, the light-emitting layer 40 can be formed using a vapor deposition process.

[0067] The cathode layer 50 is located on the side of the light-emitting layer 40 away from the substrate 10. The cathode layer 50 passes through the gap between the first light-emitting pattern 41 and the second light-emitting pattern 42 and is in electrical contact with at least one of the first connection pattern 31, the second connection pattern 32 and the third connection pattern 33.

[0068] like Figure 2 As shown, "the edge of the second connecting pattern 32 is inward relative to the edge of the third connecting pattern 33" can mean that the orthographic projection of the second connecting pattern 32 on the substrate 10 is located within the orthographic projection of the third connecting pattern 33 on the substrate 10, and there is a gap d1 between the boundary of the orthographic projection of the second connecting pattern 32 on the substrate 10 and the boundary of the orthographic projection of the third connecting pattern 33 on the substrate 10.

[0069] In some examples, the spacing d1 between the orthographic projection boundary of the second connection pattern 32 on the substrate 10 and the orthographic projection boundary of the third connection pattern 33 on the substrate 10 can be 0.25 μm to 1.75 μm. For example, the spacing d1 can be 0.25 μm, 0.5 μm, 0.75 μm, 1.0 μm, 1.25 μm, 1.5 μm, 1.75 μm, etc.

[0070] It is understandable that the spacing between the orthographic projection boundary of the second connection pattern 32 on the substrate 10 and the orthographic projection boundary of the third connection pattern 33 on the substrate 10 may be different at different locations of the orthographic projection boundary of the second connection pattern 32 on the substrate 10.

[0071] For example, the edge of the second connecting pattern 32 is recessed relative to the edge of the third connecting pattern 33, which may be the edge of the second connecting pattern 32 along... Figure 1 The direction indicated by the "thick arrow" is inward relative to the edge of the third connecting pattern 33.

[0072] This configuration allows for several advantages. First, after the connecting portion 30 is formed, when the light-emitting layer 40 is formed, it makes it easier for the light-emitting layer 40 to break at the boundary of the third connecting pattern 33, forming a second light-emitting pattern 42 located on the side of the third connecting pattern 33 away from the substrate 10 and a first light-emitting pattern 41 located around and separated from the second light-emitting pattern 42. Second, it avoids situations where the boundary of the third connecting pattern 33 extends too far beyond the boundary of the second connecting pattern 32, causing the edge of the third connecting pattern 33 to droop, making the light-emitting layer 40 less prone to breakage, and making it difficult for the cathode layer 50 to overlap with the first connecting pattern 31, the second connecting pattern 32, or the third connecting pattern 33.

[0073] For example, the first connecting pattern 31 and the third connecting pattern 33 can be made of the same material. In this case, the materials of the first connecting pattern 31 and the third connecting pattern 33 may include indium tin oxide (ITO).

[0074] The thicknesses of the first connecting pattern 31 and the third connecting pattern 33 can be the same or different. When the thicknesses of the first connecting pattern 31 and the third connecting pattern 33 are the same, the thickness range of the first connecting pattern 31 and the third connecting pattern 33 can be 600 angstroms to 800 angstroms. For example, the thicknesses of the first connecting pattern 31 and the third connecting pattern 33 can be 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, or 800 angstroms, etc.

[0075] The second connecting pattern 32 can be a single-layer structure or a multi-layer structure. When the second connecting pattern 32 is a single-layer structure, the material of the second connecting pattern 32 can include metal, such as aluminum.

[0076] In some examples, when the second connection pattern 32 is a multilayer structure, the second connection pattern 32 may include a molybdenum metal layer, an aluminum metal layer and a molybdenum metal layer stacked sequentially along the direction away from the substrate 10.

[0077] The thickness of the molybdenum metal layer can range from 400 angstroms to 800 angstroms, for example, the thickness of the molybdenum metal layer can be 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, etc. The thickness of the molybdenum metal layers on both sides of the aluminum metal layer can be the same or different. For example, the thickness of the molybdenum metal layer between the aluminum metal layer and the substrate 10 can be 500 angstroms, and the thickness of the molybdenum metal layer on the side of the aluminum metal layer away from the substrate 10 can be 700 angstroms. The thickness of the aluminum metal layer can range from 4500 angstroms to 5500 angstroms, for example, the thickness of the aluminum metal layer can be 4500 angstroms, 5000 angstroms, 5500 angstroms, etc.

[0078] In other examples, when the second connection pattern 32 is a multilayer structure, the second connection pattern 32 may include a molybdenum metal layer and an aluminum metal layer sequentially stacked along a direction away from the substrate 10. In this case, the thickness of the molybdenum metal layer can range from 400 angstroms to 800 angstroms, for example, the thickness of the molybdenum metal layer can be 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, etc. The thickness of the aluminum metal layer can range from 5000 angstroms to 6000 angstroms, for example, the thickness of the aluminum metal layer can be 5000 angstroms, 5500 angstroms, 6000 angstroms, etc.

[0079] The shapes of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 are not limited in this disclosure, as long as they can achieve electrical contact with the cathode layer 50. In some possible embodiments, the orthographic projections of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 on the substrate 10 can all be approximately rectangular (including rectangles and squares).

[0080] in, Figure 2 An example is given where the orthographic projections of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 on the substrate 10 are all squares. Figure 3A and Figure 3B Examples are given with the first connection pattern 31, the second connection pattern 32, and the third connection pattern 33 all projected onto the substrate 10 as rectangles.

[0081] It can be understood that "the orthographic projections of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 on the substrate 10 can be roughly rectangular" means that the orthographic projections of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 on the substrate 10 are generally rectangular, but not limited to standard rectangles. That is, the "rectangle" here includes not only the shape of a basic rectangle, but also shapes similar to rectangles, considering process conditions.

[0082] When the orthographic projections of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 on the substrate 10 are all rectangular, such as Figure 3A and Figure 3B As shown, the extension direction of the long side of the rectangle can be either a first direction X parallel to the substrate 10 or a second direction Y parallel to the substrate 10.

[0083] In the above embodiments of this disclosure, the size of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 is not limited. They can be designed according to actual needs, as long as the cathode layer 50 can make electrical contact with one of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33.

[0084] The cathode layer 50 is in electrical contact with at least one of the first connection pattern 31, the second connection pattern 32, and the third connection pattern 33. For example, the cathode layer 50 is in electrical contact with the first connection pattern 31.

[0085] Alternatively, the cathode layer 50 may be in electrical contact with at least one of the first connection pattern 31, the second connection pattern 32, and the third connection pattern 33; or it may be in electrical contact with two of the first connection pattern 31, the second connection pattern 32, and the third connection pattern 33. In this case, the cathode layer 50 may be in contact with the first connection pattern 31 and the second connection pattern 32 simultaneously, or it may be in electrical contact with the first connection pattern 31 and the third connection pattern 33 simultaneously, or it may be in electrical contact with the first connection pattern 31, the second connection pattern 32, and the third connection pattern 33 simultaneously.

[0086] Or, as Figure 1 As shown, the cathode layer 50 is in electrical contact with at least one of the first connection pattern 31, the second connection pattern 32, and the third connection pattern 33. Alternatively, the cathode layer 50 may be in electrical contact with the first connection pattern 31, the second connection pattern 32, and the third connection pattern 33 simultaneously.

[0087] For example, the material of the cathode layer 50 may include indium zinc oxide (IZO) or a magnesium-silver alloy.

[0088] In some examples, the cathode layer 50 can be formed using a sputtering process.

[0089] In the display panel 100 provided in this embodiment, the connecting portion 30 includes a first connecting pattern 31, a second connecting pattern 32, and a third connecting pattern 33. The edge of the second connecting pattern 32 is recessed relative to the edge of the third connecting pattern 33. So that after the connecting portion 30 is formed, when the light-emitting layer 40 is formed, the light-emitting layer 40 is broken at the edge of the third connecting pattern 33 of the connecting portion 30, forming a second light-emitting pattern 42 located on the side of the third connecting pattern 33 away from the substrate 10, and a first light-emitting pattern 41 located around the second light-emitting pattern 42.

[0090] In this way, the subsequently formed cathode layer 50 can pass through the gap between the first light-emitting pattern 41 and the second light-emitting pattern 42 and make electrical contact with at least one of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33. That is, the cathode layer 50 can be electrically connected to the connecting portion 30, realizing parallel connection with the connecting portion 30. At the same time, the first connecting pattern 31 of the connecting portion 30 is electrically connected to the auxiliary electrode 20, so that the cathode layer 50 can be electrically connected to the auxiliary electrode 20. The cathode layer 50 and the auxiliary electrode 20 form a parallel structure, thereby reducing the resistance of the cathode layer 50, reducing the voltage drop on the cathode layer 50, improving the display effect of the display panel 100, and improving the brightness uniformity of the display panel 100.

[0091] In some embodiments, such as Figure 2 and Figure 3AAs shown, the orthographic projection of the third connection pattern 33 on the substrate 10 is located inside the orthographic projection of the first connection pattern 31 on the substrate 10, and there is a gap d2 between the boundary of the orthographic projection of the third connection pattern 33 on the substrate 10 and the boundary of the orthographic projection of the first connection pattern 31 on the substrate 10.

[0092] This embodiment of the disclosure does not limit the existence of a distance d2 between the boundary of the orthographic projection of the third connecting pattern 33 on the substrate 10 and the boundary of the orthographic projection of the first connecting pattern 31 on the substrate 10. It can be understood that the distance d2 between the boundary of the orthographic projection of the third connecting pattern 33 on the substrate 10 and the boundary of the orthographic projection of the first connecting pattern 31 on the substrate 10 can be the same or different at different locations.

[0093] In this way, the area of ​​the orthographic projection of the first connection pattern 31 on the substrate 10 is larger than the area of ​​the orthographic projection of the third connection pattern 33 on the substrate 10, and the area of ​​the orthographic projection of the second connection pattern 32 on the substrate 10 is smaller than the area of ​​the orthographic projection of the first connection pattern 31 on the substrate 10. When the light-emitting layer 40 breaks at the boundary of the third connection pattern 33, not only can the sides of the second connection pattern 32 and the third connection pattern 33 be exposed, but also the part of the surface of the first connection pattern 31 away from the substrate 10 can be exposed. This allows the cathode layer 50 to contact the surface of the first connection pattern 31 away from the substrate 10, making the contact area between the cathode layer 50 and the first connection pattern 31 larger, the contact between the cathode layer 50 and the first connection pattern 31 more stable, and the contact resistance between the cathode layer 50 and the first connection pattern 31 smaller.

[0094] The contact resistance between the cathode layer 50 and the first connection pattern 31 is smaller, resulting in a smaller resistance after the cathode layer 50 is connected in parallel with the connection part 30 and the auxiliary electrode 20. The voltage drop on the cathode layer 50 is also smaller, which is more conducive to improving the display effect of the display panel 100 and improving the brightness uniformity of the display panel 100.

[0095] In some embodiments, such as Figure 4 As shown, the cathode layer 50 may include a first contact portion 51 and a second contact portion 52. The first contact portion 51 is located on the side of the first light-emitting pattern 41 away from the substrate 10, and the second contact portion 52 is located on the side of the second light-emitting pattern 42 away from the substrate 10.

[0096] In some examples, the first contact portion 51 and the second contact portion 52 can be connected to each other. In other examples, such as... Figure 4 As shown, the first contact portion 51 and the second contact portion 52 can be separated from each other.

[0097] In some examples, such as Figure 4As shown, there is a gap d3 between the second connecting pattern 32 and the first light-emitting pattern 41, exposing a portion of the surface of the first connecting pattern 31. The first contact portion 51 covers the side of the first light-emitting pattern 41 near the second connecting pattern 32 and is in electrical contact with the exposed surface of the first connecting pattern 31.

[0098] In this embodiment, the gap d3 between the second connecting pattern 32 and the first emitting pattern 41 is not limited. Similarly, the gap d3 between the second connecting pattern 32 and the first emitting pattern 41 can be the same or different at different positions.

[0099] In this way, through the electrical contact between the first contact portion 51 of the cathode layer 50 and the exposed surface of the first connecting pattern 31, the cathode layer 50 is electrically connected to the connecting portion 30, and thus the cathode layer 50 is electrically connected to the auxiliary electrode 20. The cathode layer 50 and the auxiliary electrode 20 form a parallel structure, which can reduce the resistance of the cathode layer 50 and reduce the voltage drop on the cathode layer 50, thereby improving the display effect of the display panel 100 and enhancing the brightness uniformity of the display panel 100.

[0100] It is understood that the thickness of the first contact portion 51 may be the same or different at different locations. For example, the thickness of the portion of the first contact portion 51 that is in electrical contact with the exposed surface of the first connecting pattern 31 may be different from the thickness of the portion of the first contact portion 51 that is in contact with the first light-emitting pattern 41. The thickness of the portion of the first contact portion 51 that is in contact with the exposed surface of the first connecting pattern 31 may be less than the thickness of the portion of the first contact portion 51 that is in contact with the first light-emitting pattern 41.

[0101] In other examples, such as Figure 5 As shown, the first contact portion 51 makes electrical contact with the side of the second connecting pattern 32.

[0102] In this way, through the electrical contact between the first contact portion 51 of the cathode layer 50 and the side of the second connecting pattern 32, the cathode layer 50 and the connecting portion 30 can be electrically connected, thereby achieving an electrical connection between the cathode layer 50 and the auxiliary electrode 20, forming a parallel structure between the cathode layer 50 and the auxiliary electrode 20. This parallel structure reduces the resistance of the cathode layer 50, which helps to lower the voltage drop across the cathode layer 50, improves the display effect of the display panel 100, and enhances the brightness uniformity of the display panel 100.

[0103] For example, the thickness of the portion of the first contact portion 51 that contacts the side of the second connecting pattern 32 may be less than the thickness of the portion of the first contact portion 51 that contacts the first light-emitting pattern 41.

[0104] In some other examples, such as Figure 5As shown, the first contact portion 51 can make electrical contact with the exposed surface of the first connection pattern 31, and at the same time make electrical contact with the side of the second connection pattern 32.

[0105] In this way, the cathode layer 50 can be electrically connected to the connecting portion 30 through the first contact portion 51 and the first connecting pattern 31 and the second connecting pattern 32 of the connecting portion 30, thereby achieving electrical connection between the cathode layer 50 and the auxiliary electrode 20. The cathode layer 50 and the auxiliary electrode 20 can form a parallel structure, reducing the resistance of the cathode layer 50 and decreasing the voltage drop on the cathode layer 50, which is beneficial to improving the display effect of the display panel 100 and improving the brightness uniformity of the display panel.

[0106] Meanwhile, the first contact portion 51 is electrically connected to both the first connecting pattern 31 and the second connecting pattern 32, resulting in a larger contact area between the cathode layer 50 and the connecting portion 30 and a smaller contact resistance between the cathode layer 50 and the connecting portion 30. This helps to further reduce the voltage drop on the cathode layer 50, improve the display effect of the display panel 100, and enhance the uniformity of the screen brightness of the display panel 100.

[0107] In some examples, such as Figure 6 As shown, the second contact portion 52 covers the side of the second light-emitting pattern 42 near the first light-emitting pattern 41 and is in electrical contact with the side of the third connecting pattern 33.

[0108] In this way, through the side electrical contact between the second contact portion 52 of the cathode layer 50 and the third connecting pattern 33, the cathode layer 50 and the connecting portion 30 can be electrically connected as a whole, thereby enabling the cathode layer 50 to be electrically connected to the auxiliary electrode 20, forming a parallel structure between the cathode layer 50 and the auxiliary electrode 20. This parallel structure reduces the resistance of the cathode layer 50 and the voltage drop across it, thus improving the display effect of the display panel 100 and enhancing the uniformity of the image display.

[0109] For example, the thickness of the second contact portion 52 may be different at different locations. For instance, the thickness of the portion of the second contact portion 52 that contacts the side of the third connecting pattern 33 may be different from the thickness of the portion of the second contact portion 52 that contacts the surface of the second light-emitting pattern 42 away from the substrate 10.

[0110] In some other examples, such as Figure 6 As shown, the first contact portion 51 can make electrical contact with the exposed surface of the first connecting pattern 31, and at the same time make electrical contact with the side of the second connecting pattern 32, and the second contact portion 52 makes electrical contact with the side of the third connecting pattern 33.

[0111] In this way, through the electrical contact between the first contact portion 51 and the first connecting pattern 31 and the second connecting pattern 32, and the electrical contact between the second contact portion 52 and the third connecting pattern 33, the cathode layer 50 and the connecting portion 30 are electrically connected, thereby achieving electrical connection between the cathode layer 50 and the auxiliary electrode 20. The cathode layer 50 and the auxiliary electrode 20 form a parallel structure, which reduces the resistance of the cathode layer 50 and the voltage drop on the cathode layer 50, thereby improving the display effect of the display panel 100 and enhancing the brightness uniformity of the display panel 100.

[0112] Meanwhile, the first contact portion 51 is electrically connected to both the first connecting pattern 31 and the second connecting pattern 32, and the second contact portion 52 is electrically connected to the third connecting pattern 33. This results in a larger contact area between the cathode layer 50 and the connecting portion 30, and a smaller contact resistance between the cathode layer 50 and the connecting portion 30. This helps to further reduce the voltage drop on the cathode layer 50, improve the display effect of the display panel 100, and enhance the uniformity of the display brightness of the display panel 100.

[0113] In some embodiments, such as Figure 7A As shown, the display panel 100 also includes a circuit structure layer 60, which is located between the connection portion 30 and the substrate 10. The circuit structure layer 60 includes a semiconductor layer 61, a gate layer 62, and a source / drain electrode layer 63. The auxiliary electrode 20 is located in at least one of the semiconductor layer 61, the gate layer 62, and the source / drain electrode layer 63.

[0114] "The auxiliary electrode 20 is located in at least one of the semiconductor layer 61, the gate layer 62, and the source / drain electrode layer 63" can mean that the auxiliary electrode 20 is located in one of the semiconductor layer 61, the gate layer 62, and the source / drain electrode layer 63, for example, in the source / drain electrode layer 63 (e.g., Figure 7A (As shown).

[0115] Alternatively, "the auxiliary electrode 20 is located in at least one of the semiconductor layer 61, the gate layer 62, and the source / drain electrode layer 63," or the auxiliary electrode 20 can be provided in two of the semiconductor layer 61, the gate layer 62, and the source / drain electrode layer 63. For example, the auxiliary electrode 20 can be provided in both the gate layer 62 and the source / drain electrode layer 63.

[0116] Alternatively, "the auxiliary electrode 20 is located in at least one of the semiconductor layer 61, the gate layer 62 and the source / drain electrode layer 63", or the auxiliary electrode 20 can be provided in all three of the semiconductor layer 61, the gate layer 62 and the source / drain electrode layer 63.

[0117] See Figure 7A The circuit structure layer 60 also includes a gate insulating layer 64 located between the semiconductor layer 61 and the gate layer 62, and an interlayer dielectric layer 65 located between the gate layer 62 and the source / drain electrode layer 63.

[0118] The gate insulating layer 64 and the interlayer dielectric layer 65 can both be made of insulating materials. For example, the material of the gate insulating layer 64 may include silicon dioxide or silicon nitride, and the material of the interlayer dielectric layer 65 may also include silicon dioxide or silicon nitride.

[0119] In some embodiments, such as Figure 7A and Figure 8 As shown, the circuit structure layer 60 includes a pixel circuit 601, which includes a plurality of thin-film transistors 602 and at least one storage capacitor 603.

[0120] Each thin-film transistor 602 may include a semiconductor pattern 611, a gate 621, a source 631, and a drain 632. The semiconductor pattern 611 is located in the semiconductor layer 61, the gate 621 is located in the gate layer 62, and the source 631 and drain 632 are both located in the source-drain electrode layer 63. The source 631 and drain 632 are electrically contacted with the semiconductor pattern 611 through the interlayer dielectric layer 65.

[0121] For example, the material of semiconductor pattern 611 may include polysilicon. The materials of source 631, drain 632, and gate 621 may include metals, such as copper, aluminum, molybdenum, etc.

[0122] It is understood that when the auxiliary electrode 20 is located in the gate layer 62, the auxiliary electrode 20 can be fabricated simultaneously with the gate 621, using the same photolithography process and the same mask, thus eliminating the need to deposit additional film layers, reducing costs, and simplifying the fabrication process of the display panel 100.

[0123] Similarly, when the auxiliary electrode 20 is located in the source and drain electrode layer 63, the auxiliary electrode 20 can be fabricated simultaneously with the source electrode 631 and the drain electrode 632, using the same photolithography process and the same mask, thus eliminating the need to deposit additional film layers, which helps to reduce costs and simplify the fabrication process of the display panel 100.

[0124] When the auxiliary electrode 20 is located in the semiconductor layer 61, the auxiliary electrode 20 can be formed by semiconductor pattern doping and metallization.

[0125] In some examples, such as Figure 7A As shown, the thin film transistor 602 can be a top-gate thin film transistor. In this case, the gate 621 is located on the side of the semiconductor pattern 611 away from the substrate 10, that is, the gate layer 62 is located on the side of the semiconductor layer 61 away from the substrate 10.

[0126] In other examples, the thin-film transistor 602 can be a bottom-gate thin-film transistor, in which case the gate 621 is located between the semiconductor pattern 611 and the substrate 10, that is, the gate layer 62 is located between the semiconductor layer 61 and the substrate 10.

[0127] In some examples, all of the multiple thin-film transistors 602 in the pixel circuit 601 may be N-type transistors. In other embodiments, all of the multiple thin-film transistors 602 in the pixel circuit 601 may be P-type transistors. In still other embodiments, some of the multiple thin-film transistors 602 in the pixel circuit 601 may be N-type transistors and others may be P-type transistors.

[0128] This disclosure does not limit the circuit structure of the pixel circuit 601, as long as it can drive the light-emitting device to emit light. For example, the pixel circuit 601 can be a 2T1C circuit structure, a 3T1C circuit structure, or a 7T2C circuit structure, etc.

[0129] Figure 8 and Figure 9 The pixel circuit 601 is illustrated as a 3T1C circuit structure. This pixel circuit 601 includes three thin-film transistors 602, namely transistor T1, transistor T2, and transistor T3. The source and drain of transistor T1 are connected to the high-level signal line VDD and the light-emitting device L, respectively, and the gate of transistor T1 is connected to the drain of transistor T2. The gate of transistor T2 is connected to the gate line GL, and the source of transistor T2 is connected to the data line DATA. The source of transistor T3 is connected to the drain of transistor T1, and the drain of transistor T3 is connected to the sensing signal line SENSE.

[0130] The gate line GL is used to control the opening and closing of transistor T2 during the display phase of the display panel 100. The data line DATA is used to provide data voltage to transistor T2. The high-level signal line VDD is used to provide a high-level voltage to transistor T1. The sensing signal line SENSE is used to receive the electrical signal from the drain of transistor T2 or the electrical signal from the light-emitting device L and transmit it to the external circuit. The external circuit detects the characteristic changes and uniformity of transistor T1, or detects the uniformity and aging degree of light-emitting device L, based on the electrical signal from the drain of transistor T2 or the electrical signal from the light-emitting device L.

[0131] The gate line GL extends along a first direction X parallel to the substrate 10, and the high-level signal line VDD, data line DATA, and sensing signal line SENSE extend along a second direction Y parallel to the substrate 10. The portion of the gate line GL whose orthogonal projection on the substrate 10 overlaps with the orthogonal projection of the semiconductor pattern 611 on the substrate 10 serves as the gate of the thin-film transistor 602.

[0132] In some embodiments, such as Figure 9As shown, the gate line GL can be composed of two parallel traces. This way, if one of the two parallel traces fails, the display panel 100 can still use the other trace to transmit control signals. Simultaneously, having two parallel traces for the gate line GL also reduces its resistance and decreases the voltage drop across it.

[0133] In some embodiments, such as Figure 9 As shown, along a first direction X parallel to the substrate, one pixel circuit 601 can be connected to one data line DATA. One sensing signal line SENSE can be electrically connected to four pixel circuits 601 simultaneously.

[0134] In some embodiments, such as Figure 7A As shown, the display panel 100 may further include a shielding layer 66 located between the substrate 10 and the semiconductor layer 61, and a buffer layer 67 located between the shielding layer 66 and the semiconductor layer 61.

[0135] For example, the shielding layer 66 includes a plurality of shielding patterns 661, and the orthographic projection of the semiconductor pattern 611 on the substrate 10 at least partially overlaps with the orthographic projection of the shielding pattern 661 on the substrate 10. The shielding pattern 661 can be used to block external light or light reflected or refracted from the side of the substrate 10 and incident on the semiconductor pattern 611, thereby ensuring the performance of the thin film transistor 602.

[0136] For example, the plates of the storage capacitor 603 may also be disposed in the shielding layer 66.

[0137] For example, the material of the shielding layer 66 may include metals, such as copper, aluminum, etc.

[0138] For example, the material of the buffer layer 67 can be an insulating material, such as silicon oxide or silicon nitride.

[0139] In some embodiments, such as Figure 7A As shown, the display panel 100 also includes a planarization layer 70. The planarization layer 70 is located between the connection portion 30 and the auxiliary electrode 20. The planarization layer 70 includes a first through-hole 71 that exposes the auxiliary electrode 20. A first connection pattern 31 contacts the auxiliary electrode 20 through the first through-hole 71.

[0140] The planarization layer 70 can be made of an insulating material. For example, the planarization layer 70 can be made of an organic insulating material, such as resin.

[0141] In some embodiments, such as Figure 7AAs shown, the first via 71 includes a first port 711 and a second port 712. The first port 711 is farther away from the substrate 10 than the second port 712, and the size of the first port 711 is larger than the size of the second port 712.

[0142] The wall 713 of the first through hole 71 is inclined relative to the plane of the substrate 10, and the edge of the second connecting pattern 32 extends to the wall 713 of the first through hole 71.

[0143] It is understood that the first port 711 and the second port 712 of the same first through hole 71 have the same shape but different sizes. This disclosure does not limit the shape of the first port 711 and the second port 712; for example, as shown... Figure 10 As shown, the orthographic projection of the first port 711 on the substrate 10 and the orthographic projection of the second port 712 on the substrate 10 can be approximately rectangular (e.g., square or rectangle).

[0144] The phrase "the orthographic projection of the first port 711 on the substrate 10 and the orthographic projection of the second port 712 on the substrate 10 can be approximately rectangular" means that the orthographic projections of the first port 711 and the second port 712 on the substrate 10 are generally rectangular, but not limited to a standard rectangle. That is, the "rectangle" here includes not only the shape of a basic rectangle, but also shapes similar to rectangles, taking into account process conditions.

[0145] In some examples, such as Figure 10 The orthographic projection of the first port 711 onto the substrate 10 and the orthographic projection of the second port 712 onto the substrate 10 can be approximately square.

[0146] In other examples, such as Figure 11 As shown, the orthographic projection of the first port 711 on the substrate 10 and the orthographic projection of the second port 712 on the substrate 10 can be roughly rectangular.

[0147] In some embodiments, such as Figure 7A As shown, there is an angle α between the hole wall 713 of the first through hole 71 and the plane where the substrate 10 is located, and the angle α is an acute angle.

[0148] In some examples, the angle α between the hole wall 713 of the first through hole 71 and the plane containing the substrate 10 can be in the range of 25° to 50°. For example, the angle α can be 25°, 30°, 35°, 40°, 45° or 50°, etc.

[0149] This design ensures that, on the one hand, the angle α between the hole wall 713 of the first through-hole 71 and the plane of the substrate 10 is not too small, allowing the cathode layer 50 to easily pass through the gap between the first light-emitting pattern 41 and the second light-emitting pattern 42 and make electrical contact with the second connecting pattern 32 of the connecting portion 30 during the formation of the cathode layer 50. On the other hand, it also ensures that the angle α between the hole wall 713 of the first through-hole 71 and the plane of the substrate 10 is not too large, thus helping to avoid situations where the light-emitting layer cannot break at the edge of the third connecting pattern 33, or where, after the light-emitting layer breaks, the surface of the first connecting pattern 31 away from the substrate 10 and the side of the second connecting pattern 32 are covered by the first light-emitting pattern 41, and the side of the third connecting pattern 33 is covered by the second light-emitting pattern 42. This further helps to prevent the cathode layer 50 from failing to make electrical contact with the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33.

[0150] Wherein, the edge of the second connecting pattern 32 extends to the hole wall 713 of the first through hole 71, and can be, for example, Figure 10 As shown, the edge of the orthographic projection of the second connection pattern 32 on the substrate 10 is located between the edge of the orthographic projection of the first port 711 on the substrate 10 and the edge of the orthographic projection of the second port 712 on the substrate 10.

[0151] In this embodiment, the edge of the second connecting pattern 32 extends to the hole wall 713 of the first through hole 71, thereby making it easier for the cathode layer 50 to make electrical contact with at least one of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33 of the connecting portion 30 through the gap between the first light-emitting pattern 41 and the second light-emitting pattern 42 when the cathode layer 50 is formed. For example, the cathode layer 50 can more easily make electrical contact with the second connecting pattern 32 through the gap between the first light-emitting pattern 41 and the second light-emitting pattern 42.

[0152] It is understandable that when the edge of the second connecting pattern 32 extends to the hole wall 713 of the first through hole 71, the edge of the third connecting pattern 33 can also extend to the hole wall 713 of the first through hole 71.

[0153] In some embodiments, see Figure 7A The light-emitting layer 40 can be broken on the hole wall 713 of the first through hole 71, thereby forming a second light-emitting pattern 42 located on the side of the third connecting pattern 33 away from the substrate 10, and a first light-emitting pattern 41 located around the second light-emitting pattern 42. The first light-emitting pattern 41 extends to the hole wall of the first through hole 71 near the edge of the second light-emitting pattern 42, and the second light-emitting pattern 42 also extends to the hole wall 713 of the first through hole 71 near the edge of the first light-emitting pattern 41.

[0154] In some embodiments, see Figure 7AThe cathode layer 50 can break on the wall 713 of the first through hole 71, forming a first contact portion 51 and a second contact portion 52 that are separated from each other. At this time, the edges of the first contact portion 51 and the second contact portion 52 that are close to each other are located on the wall 713 of the first through hole 71. That is, the edge of the first contact portion 51 near the second contact portion 52 is located on the wall 713 of the first through hole 71, and the edge of the second contact portion 52 near the first contact portion 51 is also located on the wall 713 of the first through hole 71.

[0155] In this way, the first contact portion 51 and the second contact portion 52 of the cathode layer 50 are separated on the hole wall 713 of the first through hole 71. The first contact portion 51 is more likely to make contact with the side wall of the second connecting pattern 32 and the surface of the first connecting pattern 31 away from the substrate 10. The second contact portion 52 is more likely to make electrical contact with the side wall of the third connecting pattern 33. As a result, the contact area between the cathode layer 50 and the connecting portion 30 can be larger, the contact resistance between the cathode layer 50 and the connecting portion 30 can be smaller, and the total resistance value after the cathode layer and the auxiliary electrode 20 are connected is smaller. The voltage drop on the cathode layer 50 is smaller, which improves the brightness uniformity of the display panel and improves the display effect of the display panel.

[0156] In other embodiments, such as Figure 7B As shown, the edge of the second connection pattern 32 can also extend into a first through hole 71, which is located on the surface of the planarization layer 70 away from the substrate 10.

[0157] At this time, the orthographic projection of the first port 711 on the substrate 10 is located inside the orthographic projection of the second connection pattern 32 on the substrate 10, and there is a gap between the edge of the orthographic projection of the first port 711 on the substrate 10 and the orthographic projection of the second connection pattern 32 on the substrate 10.

[0158] It is understood that when the first through-hole 71 extends from the edge of the second connection pattern 32, the first through-hole 71 also extends from the edge of the third connection pattern 33, thus being located on the surface of the planarization layer 70 away from the substrate 10.

[0159] For example, "the edge of the second connecting pattern 32 is recessed relative to the edge of the third connecting pattern 33" can be the edge of the second connecting pattern 32 along... Figure 7B The direction indicated by the "thick arrow" is inward relative to the edge of the third connecting pattern 33.

[0160] In some embodiments, such as Figure 7A and Figure 7BAs shown, the display panel 100 may further include a passivation layer 80, which is located between the planarization layer 70 and the auxiliary electrode 20. The passivation layer 80 includes a second via 81 that exposes at least a portion of the surface of the auxiliary electrode 20. The second via 81 communicates with a first via 71. A first connection pattern 31 contacts the auxiliary electrode 20 through the first via 71 and the second via 81.

[0161] The passivation layer 80 can be made of an insulating material. For example, the passivation layer 80 can be made of an inorganic insulating layer, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0162] "The second through hole 81 exposes at least a portion of the surface of the auxiliary electrode 20" can mean that the second through hole 81 exposes the entire surface of the auxiliary electrode 20, or it can mean, for example... Figure 7A and Figure 7B As shown, the second through hole 81 exposes part of the surface of the auxiliary electrode 20.

[0163] When the second through-hole 81 exposes a portion of the surface of the auxiliary electrode 20, such as Figure 10 and Figure 11 As shown, the orthogonal projection of the second through hole 81 on the substrate 10 lies within the orthogonal projection of the auxiliary electrode 20 on the substrate 10.

[0164] In some embodiments, such as Figure 10 and Figure 11 As shown, the orthographic projection of the second through hole 81 on the substrate 10 is located inside the orthographic projection of the second port 712 of the first through hole 71 on the substrate 10, and there is a gap d4 between the boundary of the orthographic projection of the second through hole 81 on the substrate 10 and the boundary of the orthographic projection of the second port 712 on the substrate 10.

[0165] In this embodiment, the size of the distance d4 between the boundary of the orthographic projection of the second via 81 on the substrate 10 and the boundary of the orthographic projection of the second port 712 on the substrate 10 is not limited. It can be understood that the distance d4 between the boundary of the orthographic projection of the second via 81 on the substrate 10 and the boundary of the orthographic projection of the second port 712 on the substrate 10 can be different at different locations.

[0166] In this way, the size of the second through hole 81 is smaller than the size of the second port 712, the orthographic projection of the first through hole 71 on the substrate 10 and the orthographic projection of the second through hole 81 on the substrate 10 overlap, the total area of ​​the orthographic projection of the first through hole 71 on the substrate 10 and the orthographic projection of the second through hole 81 on the substrate 10 is smaller, and the area occupied by the non-light-emitting area where the first through hole 71 and the second through hole 81 are located is smaller, which is beneficial to improving the aperture ratio of the display panel 100.

[0167] In some embodiments, such as Figure 10 and Figure 11 As shown, the orthographic projection of the second via 81 onto the substrate 10 is approximately rectangular (including squares and rectangles). It can be understood that "the orthographic projection of the second via 81 onto the substrate 10 is approximately rectangular" means that the overall orthographic projection of the second via 81 onto the substrate 10 is rectangular, but not limited to a standard rectangle. That is, the term "rectangle" here includes not only the basic rectangular shape, but also shapes resembling rectangles, considering process conditions. Figure 10 and Figure 11 An example is given where the orthographic projection of the second via 81 onto the substrate 10 is approximately square.

[0168] In some embodiments, such as Figure 7A and Figure 12 As shown, the display panel 100 also includes a pixel defining layer 90, which is located on the side of the connection portion 30 away from the substrate 10. The pixel defining layer 90 includes a third through-hole 91, which exposes a portion of the surface of the first connection pattern 31 away from the substrate 10, as well as the side surfaces of the second connection pattern 32 and the third connection pattern 33. The light-emitting layer 40 contacts the first connection pattern and the third connection pattern 33 through the third through-hole 91.

[0169] In some embodiments, such as Figure 7A and Figure 12 As shown, the display panel 100 also includes an anode layer 11, which is located between the light-emitting layer 40 and the auxiliary electrode 20. A connecting portion 30 is located on the anode layer 11. The anode layer 11 also includes an anode 12, and the pixel defining layer 90 also includes a pixel opening 92, which exposes a portion of the surface of the anode 12. The pixel opening 92 is offset from the third through-hole 91.

[0170] The connecting part 30 and the anode 12 are both located in the anode layer 11. The anode 12 and the connecting part 30 can be formed simultaneously. That is, the same mask is used when preparing the anode 12 and the connecting part 30, which can reduce the manufacturing cost of the display panel 100 and simplify the manufacturing process of the display panel 100.

[0171] The anode 12 may include a first anode layer 121, a second anode layer 122, and a third anode layer 123 sequentially stacked along a direction away from the substrate 10. The first anode layer 121 may be formed simultaneously with the first connection pattern 31, the second anode layer 122 may be formed simultaneously with the second connection pattern 32, and the third anode layer 123 may be formed simultaneously with the third connection pattern 33.

[0172] For example, such as Figure 7A As shown, the anode 12 can be electrically connected to the source 631 or drain 632 of the thin-film transistor 602 through the planarization layer 70 and the passivation layer 80.

[0173] For example, such as Figure 7A As shown, the anode 12 can form the aforementioned light-emitting device L with the light-emitting layer 40 and the cathode layer 50.

[0174] In some embodiments, such as Figure 10 and Figure 11 As shown, in the case where the display panel 100 further includes a planarization layer 70, and the planarization layer 70 includes a first through hole 71, the orthographic projection of the first port 711 of the first through hole 71 on the substrate 10 is located inside the orthographic projection of the third through hole 91 on the substrate 10, and there is a gap d5 between the boundary of the orthographic projection of the first port 711 on the substrate 10 and the boundary of the orthographic projection of the third through hole 91 on the substrate 10.

[0175] This disclosure does not limit the value of the distance d5 between the boundary of the orthographic projection of the first port 711 on the substrate 10 and the boundary of the orthographic projection of the third via 91 on the substrate 10. It is understood that the distance d5 between the boundary of the orthographic projection of the first port 711 on the substrate 10 and the boundary of the orthographic projection of the third via 91 on the substrate 10 may be different at different locations.

[0176] In this way, the orthographic projection of the first through hole 71 on the substrate 10 overlaps with the orthographic projection of the third through hole 91 on the substrate 10. The total area occupied by the orthographic projections of the first through hole 71 and the third through hole 91 on the substrate 10 is small, and the area occupied by the non-light-emitting areas where the first through hole 71 and the third through hole 91 are located is small, which is beneficial to improving the duty cycle of the display panel 100.

[0177] In some embodiments, such as Figure 12 As shown, the display panel includes multiple sub-pixels P, which are arranged in multiple rows along a first direction X and in multiple columns along a second direction Y. The first direction X and the second direction Y intersect.

[0178] For example, multiple sub-pixels P can each display multiple colors. Based on this, the display panel 100 can include at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, wherein the first color, the second color, and the third color can be three primary colors (e.g., red, green, and blue).

[0179] In some examples, the display panel 100 may include a first color subpixel, a second color subpixel, a third color subpixel, and a fourth color subpixel, wherein the first, second, and third colors are three primary colors (e.g., red, green, and blue), and the fourth color may be white.

[0180] For example, sub-pixel P may include the pixel circuit 601 and the light-emitting device L described above.

[0181] The display panel 100 may include a plurality of auxiliary electrodes 20. The number of auxiliary electrodes 20 is not limited in this embodiment. The number of auxiliary electrodes 20 can be designed according to actual needs.

[0182] In some examples, at least one auxiliary electrode 20 extends along a first direction X and is located between two adjacent rows of sub-pixels P.

[0183] It is understandable that "at least one auxiliary electrode 20 extends along the first direction X" can mean that one auxiliary electrode 20 extends along the first direction X. Alternatively, "at least one auxiliary electrode 20 extends along the first direction X" can mean that multiple auxiliary electrodes 20 extend along the first direction X. When multiple auxiliary electrodes 20 extend along the first direction X, all auxiliary electrodes 20 can extend along the first direction X.

[0184] In other examples, such as Figure 9 and Figure 12 As shown, at least one auxiliary electrode 20 extends along the second direction Y and is located between two adjacent rows of sub-pixels P.

[0185] It is understandable that "at least one auxiliary electrode 20 extends along the second direction Y" can mean that one auxiliary electrode 20 extends along the second direction Y. Alternatively, "at least one auxiliary electrode 20 extends along the second direction Y" can mean that multiple auxiliary electrodes 20 extend along the second direction Y. When multiple auxiliary electrodes 20 extend along the second direction Y, all auxiliary electrodes 20 can extend along the second direction Y.

[0186] In some other examples, at least one auxiliary electrode 20 extends along a first direction X, and at the same time, at least one auxiliary electrode 20 extends along a second direction Y. In this way, the auxiliary electrodes 20 can be distributed in a grid pattern on the display panel, which is more conducive to achieving electrical connection with the cathode layer 50, reducing the resistance on the cathode layer 50, reducing the voltage drop on the cathode layer 50, and thus more conducive to improving the problem of uneven brightness of the display panel 100.

[0187] In some embodiments, such as Figure 12 and Figure 13 As shown, the display panel 100 may include a plurality of pixels 101, and each pixel 101 includes a plurality of subpixels P.

[0188] In some examples, pixel 101 may include three sub-pixels P. In other examples, such as... Figure 12 As shown, pixel 101 may include four sub-pixels P. For example, pixel 101 may include a blue sub-pixel, a green sub-pixel, a red sub-pixel, and a white sub-pixel.

[0189] In some embodiments, such as Figure 13As shown, the auxiliary electrode 20 can be located between two adjacent rows of pixels 101. In other embodiments, the auxiliary electrode 20 can be located between two adjacent columns of pixels 101. In still other embodiments, some of the auxiliary electrodes 20 can be located between two adjacent rows of pixels 101, and other auxiliary electrodes 20 can be located between two adjacent columns of pixels 101.

[0190] In some embodiments, such as Figure 13 As shown, two columns of pixels 101 can be spaced between two adjacent auxiliary electrodes 20. In other embodiments, two rows of pixels 101 can be spaced between two adjacent auxiliary electrodes 20.

[0191] In some embodiments, such as Figure 13 As shown, an auxiliary electrode 20 is connected to a first connection pattern 31 of multiple connection portions 30. In this way, the auxiliary electrode 20 has multiple contact points with the cathode layer 50, and different portions of the auxiliary electrode 20 are connected in parallel with the cathode layer 50, thereby further reducing the resistance on the cathode layer 50 and reducing the voltage drop on the cathode layer 50, which is more conducive to improving the problem of uneven brightness of the display panel 100.

[0192] like Figure 14 As shown, some embodiments of this disclosure also provide a method for manufacturing a display panel 100, the method comprising:

[0193] S100, An auxiliary electrode 20 is formed on the substrate 10.

[0194] For example, a conductive layer can be deposited on the substrate 10, and the conductive layer can be patterned to form an auxiliary electrode 20.

[0195] S200, A connection portion 30 is formed on the side of the auxiliary electrode 20 away from the substrate 10. The connection portion 30 includes a first connection pattern 31, a second connection pattern 32 and a third connection pattern 33 stacked sequentially in a direction away from the substrate 10. The first connection pattern 31 is electrically connected to the auxiliary electrode 20, and the edge of the second connection pattern 32 is recessed relative to the edge of the third connection pattern 33.

[0196] S300, a light-emitting layer 40 is formed on the side of the connecting portion 30 away from the substrate 10. The light-emitting layer 40 breaks at the boundary of the third sub-layer to form a second light-emitting pattern 42 located on the third connecting pattern 33 and a first light-emitting pattern 41 located around the second light-emitting pattern 42 and separated from the second light-emitting pattern 42.

[0197] S400, A cathode layer 50 is formed on the side of the light-emitting layer 40 away from the substrate 10.

[0198] In the method for manufacturing the display panel 100 provided in the above embodiments of this disclosure, the formed connecting portion 30 includes a first connecting pattern 31, a second connecting pattern 32, and a third connecting pattern 33. The edge of the second connecting pattern 32 is recessed relative to the edge of the third connecting pattern 33. Thus, when the light-emitting layer 40 is formed, the light-emitting layer 40 can be broken at the edge of the third connecting pattern 33 of the connecting portion 30 to form a second light-emitting pattern 42 located on the third connecting pattern 33 and a first light-emitting pattern 41 located around the second light-emitting pattern 42. In this way, during the subsequent formation of the cathode layer 50, the cathode layer 50 can pass through the gap between the first light-emitting pattern 41 and the second light-emitting pattern 42 and make electrical contact with at least one of the first connecting pattern 31, the second connecting pattern 32, and the third connecting pattern 33.

[0199] By setting it up in this way, the cathode layer 50 is electrically connected to the connecting part 30, thereby allowing the cathode layer 50 to be electrically connected to the auxiliary electrode 20. The cathode layer 50 and the auxiliary electrode 20 can form a parallel structure, reducing the resistance of the cathode layer 50, reducing the voltage drop on the cathode layer 50, improving the display effect of the display panel 100, and increasing the brightness uniformity of the display panel 100.

[0200] In some embodiments, S200, forming a connection portion 30 on the side of the auxiliary electrode 20 away from the substrate 10, may include:

[0201] A first conductive layer is formed on the side of the auxiliary electrode 20 away from the substrate 10, and the first conductive layer is patterned to form a first connection pattern 31. It can be understood that when the connection portion 30 is located in the anode layer 11, the first anode layer 121 of the anode 12 can also be formed at the same time as the first conductive layer is patterned to form the first connection pattern 31.

[0202] A second conductive layer and a third conductive layer are sequentially formed on the side of the first conductive layer away from the substrate. The third conductive layer is patterned to form a third connection pattern 33. The second conductive layer is patterned to form a second connection pattern 32.

[0203] For example, a wet etching process can be used to pattern the second and third conductive layers. It is understood that different etching solutions are used to pattern the second and third conductive layers. Over-etching of the second conductive layer can be achieved by controlling the wet etching process conditions (e.g., etching time), causing the edge of the second connection pattern 32 to be recessed relative to the edge of the third connection pattern 33.

[0204] In some embodiments, after forming the auxiliary electrode 20 on the substrate 10 in step S100, the method for fabricating the display panel may include: forming a passivation layer 80 on the side of the auxiliary electrode 20 away from the substrate 10; forming a planarization layer 70 on the side of the passivation layer 80 away from the substrate 10; etching the planarization layer 70 to form a first via 71, the first via 71 exposing a portion of the surface of the passivation layer 80 away from the substrate 10; etching the exposed surface of the passivation layer 80 to form a second via 81, the second via 81 exposing at least a portion of the surface of the auxiliary electrode 20 away from the substrate 10.

[0205] like Figure 15 As shown, some embodiments of this disclosure provide a display device 1000, which includes the display panel 100 described in any of the above embodiments.

[0206] The aforementioned display device 1000 can be any component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator.

[0207] The beneficial effects that the display device 1000 provided in this disclosure can achieve are the same as the beneficial effects that the display panel 100 described in any of the above embodiments can achieve.

[0208] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: Substrate; An auxiliary electrode is located on the substrate; A connecting portion is located on the side of the auxiliary electrode away from the substrate; the connecting portion includes a first connecting pattern, a second connecting pattern and a third connecting pattern stacked sequentially in a direction away from the substrate, the first connecting pattern being electrically connected to the auxiliary electrode, and the edge of the second connecting pattern being recessed relative to the edge of the third connecting pattern; The light-emitting layer includes a first light-emitting pattern and a second light-emitting pattern, wherein the first light-emitting pattern is located around and separate from the second light-emitting pattern, and the second light-emitting pattern is located on the side of the third connecting pattern away from the substrate; A cathode layer is located on the side of the light-emitting layer away from the substrate. The cathode layer passes through the gap between the first light-emitting pattern and the second light-emitting pattern and is in electrical contact with at least one of the first connection pattern, the second connection pattern and the third connection pattern.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the third connection pattern on the substrate is located inside the orthographic projection of the first connection pattern on the substrate, and there is a gap between the boundary of the orthographic projection of the third connection pattern on the substrate and the boundary of the orthographic projection of the first connection pattern on the substrate.

3. The display panel according to claim 1, characterized in that, Also includes: A circuit structure layer is located between the connection portion and the substrate, and the circuit structure layer includes a semiconductor layer, a gate layer, and a source / drain electrode layer; The auxiliary electrode is located in at least one of the semiconductor layer, the gate layer, and the source / drain electrode layer.

4. The display panel according to claim 1, characterized in that, The cathode layer includes: The first contact portion is located on the side of the first light-emitting pattern away from the substrate; The second contact portion is located on the side of the second luminescent pattern away from the substrate.

5. The display panel according to claim 4, characterized in that, There is a gap between the second connecting pattern and the first luminescent pattern, exposing a portion of the surface of the first connecting pattern; the first contact portion covers the side of the first luminescent pattern near the second connecting pattern and is in electrical contact with the exposed surface of the first connecting pattern; And / or, The first contact portion makes electrical contact with the side of the second connection pattern.

6. The display panel according to claim 4, characterized in that, The second contact portion covers the side of the second luminescent pattern near the first luminescent pattern and is in electrical contact with the side of the third connecting pattern.

7. The display panel according to claim 4, characterized in that, The first contact portion and the second contact portion are separated from each other.

8. The display panel according to claim 1, characterized in that, Also includes: A planarization layer is located between the connection portion and the auxiliary electrode; the planarization layer includes a first through-hole that exposes the auxiliary electrode; The first connection pattern contacts the auxiliary electrode through the first through hole.

9. The display panel according to claim 8, characterized in that, The first via includes a first port and a second port, wherein the first port is farther away from the substrate than the second port, and the size of the first port is larger than the size of the second port; The wall of the first through hole is inclined relative to the plane of the substrate, and the edge of the second connecting pattern extends to the wall of the first through hole.

10. The display panel according to claim 9, characterized in that, The cathode layer includes a first contact portion and a second contact portion that are separated from each other, and the edges of the first contact portion and the second contact portion that are close to each other are located on the wall of the first through hole.

11. The display panel according to claim 8, characterized in that, Also includes: A passivation layer is located between the planarization layer and the auxiliary electrode; the passivation layer includes a second via that exposes at least a portion of the surface of the auxiliary electrode. The second through hole is connected to the first through hole; The first connection pattern contacts the auxiliary electrode through the first through hole and the second through hole.

12. The display panel according to claim 11, characterized in that, The orthogonal projection of the second through-hole onto the substrate lies within the orthogonal projection of the auxiliary electrode onto the substrate.

13. The display panel according to claim 11, characterized in that, The orthographic projection of the second through hole on the substrate is located inside the orthographic projection of the second port of the first through hole on the substrate, and there is a gap between the boundary of the orthographic projection of the second through hole on the substrate and the boundary of the orthographic projection of the second port on the substrate.

14. The display panel according to claim 11, characterized in that, The second through-hole has a rectangular orthographic projection on the substrate, and the second port of the first through-hole has a rectangular orthographic projection on the substrate.

15. The display panel according to claim 1, characterized in that, Also includes: A pixel defining layer is located on the side of the connection portion away from the substrate; the pixel defining layer includes a third via that exposes a portion of the surface of the first connection pattern away from the substrate, as well as the sides of the second connection pattern and the third connection pattern; The light-emitting layer is in contact with the first connection pattern and the third connection pattern through the third through-hole.

16. The display panel according to claim 15, characterized in that, Also includes: An anode layer is located between the light-emitting layer and the auxiliary electrode; the connecting portion is located in the anode layer; the anode layer further includes an anode, and the pixel defining layer further includes a pixel opening, the pixel opening exposing a portion of the surface of the anode; the pixel opening is offset from the third through hole.

17. The display panel according to claim 15, characterized in that, In the case where the display panel further includes a planarization layer, and the planarization layer includes a first through-hole, The orthographic projection of the first port of the first through hole on the substrate is located inside the orthographic projection of the third through hole on the substrate, and there is a gap between the boundary of the orthographic projection of the first port on the substrate and the boundary of the orthographic projection of the third through hole on the substrate.

18. The display panel according to any one of claims 1 to 17, characterized in that, The display panel includes a plurality of sub-pixels, which are arranged in multiple rows along a first direction and in multiple columns along a second direction; the first direction and the second direction intersect. The display panel includes multiple auxiliary electrodes; At least one auxiliary electrode extends along the first direction and is located between two adjacent rows of sub-pixels; and / or, At least one auxiliary electrode extends along the second direction and is located between two adjacent columns of sub-pixels.

19. The display panel according to claim 18, characterized in that, A first connection pattern in which one of the auxiliary electrodes connects to multiple of the connection portions.

20. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 19.

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