CMOS anti-latch effect structure

Abstract

The invention discloses a CMOS anti-latch effect structure, wherein NMOS and PMOS are formed in a high-voltage P well and a high-voltage N well, respectively. An N well isolation ring is formed on the peripheral side of the high-voltage P well, and the N well isolation ring is used to isolate the NMOS from a P-type semiconductor substrate. A P well is spaced between the N well isolation ring and the high-voltage N well. A parasitic SCR is formed between the P+ source region of the PMOS, the high-voltage N well, the P well and the N well isolation ring. A Schottky diode is formed on the top surface of the N well isolation ring. The metal electrode of the Schottky diode is grounded. When the parasitic SCR is turned on, a latch effect is generated, and when the parasitic SCR is turned on, the Schottky diode is reversely broken down, and the holding voltage when the parasitic SCR is turned on is superimposed on the reverse breakdown voltage of the Schottky diode, thereby increasing the holding voltage when the parasitic SCR is turned on and thereby improving the anti-latch effect capability of the CMOS circuit.

Description

Technical Field

[0001] The invention relates to a semiconductor integrated circuit, in particular to a CMOS anti-latch effect structure. Background Art

[0002] According to the reliability requirements, the chip-level ESD protection circuit needs to be set inside the CMOS integrated circuit to prevent failure. Under high voltage conditions, the positive and negative pins of the high voltage ESD protection circuit are designed. Some studies have proposed a stacked NMOS (STNMOS) structure. Generally, the device is isolated by using N well (Nwell, NW) and P well (Pwell) to achieve the purpose of anti-latch effect, and Nwell is grounded (GND = 0V). In order to provide a current excitation mode of a negative voltage source (-Vcc), the Nwell isolation ring is used to isolate the NMOS device from the P-type substrate (Psub) in the negative voltage circuit. However, some unconventional latchup paths often lead to circuit damage, such as the parasitic silicon controlled rectifier (SCR) generated between the input and output (I / O) PMOS and the grounded NW protection ring under negative voltage. Since the parasitic SCR has a lower holding voltage, the high-voltage CMOS has a higher latch-up risk. For example, a 32V CMOS in a 28HV process has a higher latch-up risk. 28HV refers to a high-voltage device in a 28nm process node.

[0003] like Figure 1 , which is a schematic diagram of the structure of an existing CMOS circuit with latch-up risk; both the NMOS and PMOS of the existing CMOS circuit with latch-up risk are formed on a P-type semiconductor substrate 101 . Figure 1 The P-type semiconductor substrate 101 is also denoted by P-sub.

[0004] Typically, the P-type semiconductor substrate 101 is a P-type silicon substrate.

[0005] The NMOS is formed in a high-voltage P-well 102 , and the PMOS is formed in a high-voltage N-well 103 . Figure 1 The high voltage P well 102 is also represented by HVPW, and the high voltage N well 103 is also represented by HVNW.

[0006] The high-voltage P-well 102 and the high-voltage N-well 103 are both formed on the P-type semiconductor substrate 101 .

[0007] An N-well isolation ring 104 is formed around the high-voltage P-well 102 . The N-well isolation ring 104 is used to isolate the NMOS from the P-type semiconductor substrate 101 . Figure 1The N-well isolation ring 104 is also represented by NW.

[0008] A P-well 105 is disposed between the N-well isolation ring 104 and the high-voltage N-well 103 . Figure 1 The middle P well 105 is also denoted by PW.

[0009] The NMOS includes: a first gate structure, an N+ source region 1091 , an N+ drain region 1092 and a P+ body lead-out region 1101 .

[0010] The first gate structure includes a first gate dielectric layer 111 a and a first gate conductive material layer 112 a stacked in sequence.

[0011] The N+ source region 1091 is formed in the first N-type diffusion region 1071 , the N+ drain region 1092 is formed in the second N-type diffusion region 1072 , and the P+ body lead-out region 1101 is formed in the first P-type diffusion region 1081 .

[0012] The first N-type diffusion region 1071 , the second N-type diffusion region 1072 and the first P-type diffusion region 1081 are all formed in the high-voltage P-well 102 ; a second P+ region 1102 and a second P-type diffusion region 1082 are also formed in the high-voltage P-well 102 , and the second P+ region 1102 is formed in the second P-type diffusion region 1082 .

[0013] The first side of the first gate structure is farther from the N-well isolation ring 104 than the second side of the first gate structure.

[0014] The second side of the first N-type diffusion region 1071 is aligned with or partially overlaps the first side of the first gate structure.

[0015] The first side of the second N-type diffusion region 1072 is aligned with or partially overlaps the second side of the second gate structure.

[0016] The second side of the first P-type diffusion region 1081 and the first side of the first N-type diffusion region 1071 are adjacent to each other and have a distance therebetween.

[0017] The first side of the second P-type diffusion region 1082 and the second side of the second N-type diffusion region 1072 are adjacent to each other and have a distance therebetween.

[0018] Shallow trench field oxygen 106 is provided on the first side of the first P-type diffusion region 1081, between the first P-type diffusion region 1081 and the first N-type diffusion region 1071, on the second side of the first N-type diffusion region 1071, on the first side of the second N-type diffusion region 1072, between the second N-type diffusion region 1072 and the second P-type diffusion region 1082, and on the second side of the second P-type diffusion region 1082, and the junction depths of the first N-type diffusion region 1071, the second N-type diffusion region 1072, the first P-type diffusion region 1081, and the second P-type diffusion region 1082 are all greater than the depth of the shallow trench field oxygen 106.

[0019] A shallow trench field oxide 106 is formed on the top of the P-well 105 .

[0020] The PMOS includes: a second gate structure, a P+ source region 1103 , a P+ drain region 1104 and an N+ body lead-out region 1093 .

[0021] The second gate structure includes a second gate dielectric layer 111 b and a second gate conductive material layer 112 b stacked in sequence.

[0022] The P+ source region 1103 is formed in the third P-type diffusion region 1083 , the P+ drain region 1104 is formed in the fourth P-type diffusion region 1084 , and the N+ body lead-out region 1093 is formed in the third N-type diffusion region 1073 .

[0023] The third P-type diffusion region 1083 , the fourth P-type diffusion region 1084 and the third N-type diffusion region 1073 are all formed in the high-voltage N-well 103 ; a second N+ region 1094 and a fourth N-type diffusion region 1074 are also formed in the high-voltage N-well 103 , and the second N+ region 1094 is formed in the fourth N-type diffusion region 1074 .

[0024] The first side of the second gate structure is farther from the P-well 105 than the second side of the second gate structure.

[0025] The second side of the third P-type diffusion region 1083 is aligned with or partially overlaps with the first side of the second gate structure.

[0026] The first side of the fourth P-type diffusion region 1084 is aligned with or partially overlaps the second side of the second gate structure.

[0027] The second side of the third N-type diffusion region 1073 and the first side of the third P-type diffusion region 1083 are adjacent to each other and have a distance therebetween.

[0028] The first side of the fourth N-type diffusion region 1074 and the second side of the fourth P-type diffusion region 1084 are adjacent to each other and have a distance therebetween.

[0029] Shallow trench field oxygen 106 is provided on the first side of the third N-type diffusion region 1073, between the third N-type diffusion region 1073 and the third P-type diffusion region 1083, on the second side of the third P-type diffusion region 1083, on the first side of the fourth P-type diffusion region 1084, between the fourth P-type diffusion region 1084 and the fourth N-type diffusion region 1074, and on the second side of the fourth N-type diffusion region 1074, and the junction depths of the third P-type diffusion region 1083, the fourth P-type diffusion region 1084, the third N-type diffusion region 1073 and the fourth N-type diffusion region 1074 are all greater than the depth of the shallow trench field oxygen 106.

[0030] The N+ source region 1091 and the P+ body lead region 1101 of the NMOS are both connected to a negative power supply electrode VSS;

[0031] The P+ source region 1103 and the N+ body lead region 1093 of the PMOS are both connected to a positive power supply electrode Vdd.

[0032] Figure 1 In the figure, the N-type diffusion regions 1071 to 1074 are also represented by NDF; the P-type diffusion regions 1081 to 1084 are also represented by PDF; the N+ source region 1091, the N+ drain region 1092, the N+ body lead-out region 1093, the second N+ region 1094 and the N+ region 1095 are also represented by N+; the P+ body lead-out region 1101, the second P+ region 1102, the P+ source region 1103 and the P+ drain region 1104 are also represented by P+.

[0033] An N+ region 1095 is formed on the top surface of the N-well isolation ring 104 and is grounded GND through the N+ region 1095 .

[0034] A parasitic SCR is formed between the P+ source region 1103 of the PMOS, the high-voltage N-well 103, the P-well 105 and the N-well isolation ring 104. The conduction path of the parasitic SCR is shown by the dotted line 113, and the conduction path of the parasitic SCR is also represented by a latchup path, that is, the conduction path when the latch effect occurs. In the existing structure, the holding voltage of the parasitic SCR is reduced, which makes the latch phenomenon easy to occur. Summary of the invention

[0035] The technical problem to be solved by the present invention is to provide a CMOS anti-latch effect structure, which can increase the holding voltage when the parasitic SCR is turned on and thereby improve the anti-latch effect capability of the CMOS circuit.

[0036] In order to solve the above technical problem, in the CMOS anti-latch effect structure provided by the present invention, both the NMOS and PMOS of the CMOS circuit are formed on a P-type semiconductor substrate.

[0037] The NMOS is formed in a high-voltage P-well, and the PMOS is formed in a high-voltage N-well.

[0038] The high-voltage P-well and the high-voltage N-well are both formed on the P-type semiconductor substrate.

[0039] An N-well isolation ring is formed around the high-voltage P-well, and the N-well isolation ring is used to isolate the NMOS from the P-type semiconductor substrate.

[0040] A P well is arranged between the N well isolation ring and the high voltage N well.

[0041] A parasitic SCR is formed between the P+ source region of the PMOS, the high voltage N-well, the P-well and the N-well isolation ring.

[0042] A Schottky diode is formed on the top surface of the N-well isolation ring.

[0043] A metal electrode of the Schottky diode is grounded.

[0044] When the parasitic SCR is turned on, a latching effect is generated, and when the parasitic SCR is turned on, the Schottky diode will be reversely broken down. The holding voltage when the parasitic SCR is turned on will be superimposed on the reverse breakdown voltage of the Schottky diode. The reverse breakdown voltage of the Schottky diode is used to increase the holding voltage when the parasitic SCR is turned on, thereby improving the anti-latch effect capability of the CMOS circuit.

[0045] A further improvement is that the P-type semiconductor substrate is a P-type silicon substrate.

[0046] A further improvement is that the NMOS includes: a first gate structure, an N+ source region, an N+ drain region and a P+ body lead region.

[0047] A further improvement is that the first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked in sequence.

[0048] A further improvement is that the first gate dielectric layer is a gate oxide layer or a high dielectric constant layer;

[0049] The first gate conductive material layer is a polysilicon gate or a metal gate.

[0050] A further improvement is that the N+ source region is formed in the first N-type diffusion region, the N+ drain region is formed in the second N-type diffusion region, and the P+ body lead region is formed in the first P-type diffusion region;

[0051] The first N-type diffusion region, the second N-type diffusion region and the first P-type diffusion region are all formed in the high-voltage P-well; a second P+ region and a second P-type diffusion region are also formed in the high-voltage P-well, and the second P+ region is formed in the second P-type diffusion region;

[0052] The first side of the first gate structure is farther from the N-well isolation ring than the second side of the first gate structure;

[0053] The second side of the first N-type diffusion region is aligned with or partially overlaps the first side of the first gate structure;

[0054] The first side of the second N-type diffusion region is aligned with or partially overlaps the second side of the second gate structure;

[0055] The second side of the first P-type diffusion region is adjacent to the first side of the first N-type diffusion region and has a distance therebetween;

[0056] The first side of the second P-type diffusion region and the second side of the second N-type diffusion region are adjacent to each other and have a distance therebetween.

[0057] A further improvement is that shallow trench field oxygen is provided on the first side of the first P-type diffusion region, between the first P-type diffusion region and the first N-type diffusion region, on the second side of the first N-type diffusion region, on the first side of the second N-type diffusion region, between the second N-type diffusion region and the second P-type diffusion region, and on the second side of the second P-type diffusion region, and the junction depths of the first N-type diffusion region, the second N-type diffusion region, the first P-type diffusion region and the second P-type diffusion region are all greater than the depth of the shallow trench field oxygen.

[0058] A further improvement is that a shallow trench field oxide is formed on the top of the P well.

[0059] A further improvement is that the area covered by the Schottky diode is less than or equal to the coverage area of ​​the top surface of the N-type isolation ring, and a third P+ region is formed on the top surface of the N-type isolation ring outside the coverage area of ​​the Schottky diode.

[0060] A further improvement is that the PMOS includes: a second gate structure, a P+ source region, a P+ drain region and an N+ body lead region.

[0061] A further improvement is that the second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked in sequence.

[0062] A further improvement is that the second gate dielectric layer is a gate oxide layer or a high dielectric constant layer;

[0063] The second gate conductive material layer is a polysilicon gate or a metal gate.

[0064] A further improvement is that the P+ source region is formed in the third P-type diffusion region, the P+ drain region is formed in the fourth P-type diffusion region, and the N+ body lead region is formed in the third N-type diffusion region;

[0065] The third P-type diffusion region, the fourth P-type diffusion region and the third N-type diffusion region are all formed in the high-voltage N-well; a second N+ region and a fourth N-type diffusion region are also formed in the high-voltage N-well, and the second N+ region is formed in the fourth N-type diffusion region;

[0066] The first side of the second gate structure is farther from the P-well than the second side of the second gate structure;

[0067] The second side of the third P-type diffusion region is aligned with or partially overlaps the first side of the second gate structure;

[0068] The first side of the fourth P-type diffusion region is aligned with or partially overlaps the second side of the second gate structure;

[0069] The second side of the third N-type diffusion region is adjacent to the first side of the third P-type diffusion region and has a distance therebetween;

[0070] The first side of the fourth N-type diffusion region and the second side of the fourth P-type diffusion region are adjacent to each other and have a distance therebetween.

[0071] A further improvement is that shallow trench field oxygen is provided on the first side of the third N-type diffusion region, between the third N-type diffusion region and the third P-type diffusion region, on the second side of the third P-type diffusion region, on the first side of the fourth P-type diffusion region, between the fourth P-type diffusion region and the fourth N-type diffusion region, and on the second side of the fourth N-type diffusion region, and the junction depths of the third P-type diffusion region, the fourth P-type diffusion region, the third N-type diffusion region and the fourth N-type diffusion region are all greater than the depth of the shallow trench field oxygen.

[0072] A further improvement is that the N+ source region and the P+ body lead region of the NMOS are both connected to a negative power supply electrode;

[0073] The P+ source region and the N+ body lead region of the PMOS are both connected to a positive power supply electrode.

[0074] In the present invention, in a CMOS in which an N-well isolation ring is arranged on the peripheral side of an NMOS, a Schottky diode is formed on the surface of the N-well isolation ring and is grounded through a metal electrode of the Schottky diode. In a parasitic SCR of the CMOS, the metal electrode of the Schottky diode is used as a cathode. In this way, when the parasitic SCR is turned on, the Schottky diode needs to be reversely broken down first. Finally, the reverse breakdown voltage of the Schottky diode will be superimposed on the total holding voltage of the parasitic SCR. Therefore, the present invention can increase the holding voltage of the parasitic SCR, thereby reducing the risk of a latch-up effect, thereby improving the anti-latch-up effect capability of the CMOS circuit.

[0075] The present invention is particularly suitable for improving the anti-latch capability of the 32V CMOS in the 28HV platform and reducing the latch risk of the 32V CMOS in the 28HV platform in a negative current excitation mode.

[0076] The Schottky diode of the present invention is arranged on the top surface of the N-type isolation ring, so the layout area will not be increased.

[0077] The Schottky diode of the present invention can be realized by using conventional processes in a semiconductor manufacturing plant (fab), so the present invention is compatible with existing processes and will not increase additional manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0079] Figure 1 It is a schematic diagram of the structure of an existing CMOS with latch-up risk;

[0080] Figure 2 It is a schematic structural diagram of a CMOS anti-latch effect structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0081] like Figure 2 2 is a schematic diagram of a CMOS anti-latch effect structure according to an embodiment of the present invention. In the CMOS anti-latch effect structure according to an embodiment of the present invention, both NMOS and PMOS of the CMOS circuit are formed on a P-type semiconductor substrate 201 . Figure 2 The P-type semiconductor substrate 201 is also denoted by P-sub.

[0082] In the embodiment of the present invention, the P-type semiconductor substrate 201 is a P-type silicon substrate.

[0083] The NMOS is formed in the high-voltage P-well 202 , and the PMOS is formed in the high-voltage N-well 203 . Figure 2 The high voltage P well 202 is also represented by HVPW, and the high voltage N well 203 is also represented by HVNW.

[0084] The high-voltage P-well 202 and the high-voltage N-well 203 are both formed on the P-type semiconductor substrate 201 .

[0085] An N-well isolation ring 204 is formed around the high-voltage P-well 202 . The N-well isolation ring 204 is used to isolate the NMOS from the P-type semiconductor substrate 201 . Figure 2 The N-well isolation ring 204 is also represented by NW.

[0086] A P-well 205 is disposed between the N-well isolation ring 204 and the high-voltage N-well 203 . Figure 2 The middle P well 205 is also denoted by PW.

[0087] A parasitic SCR is formed between the P+ source region 2103 of the PMOS, the high voltage N well 203, the P well 205 and the N well isolation ring 204. The conduction path of the parasitic SCR is shown by a dotted line 214, and the conduction path of the parasitic SCR is also represented by a latchup path, that is, a conduction path when a latch effect occurs.

[0088] A Schottky diode 213 is formed on the top surface of the N-well isolation ring 204 .

[0089] A metal electrode of the Schottky diode 213 is connected to the ground GND.

[0090] When the parasitic SCR is turned on, a latching effect is generated, and when the parasitic SCR is turned on, the Schottky diode 213 will be reversely broken down. The maintenance voltage when the parasitic SCR is turned on will be superimposed on the reverse breakdown voltage of the Schottky diode 213. The reverse breakdown voltage of the Schottky diode 213 is used to increase the maintenance voltage when the parasitic SCR is turned on, thereby improving the anti-latch effect capability of the CMOS circuit.

[0091] In the embodiment of the present invention, the NMOS includes: a first gate structure, an N+ source region 2091 , an N+ drain region 2092 and a P+ body lead-out region 2101 .

[0092] The first gate structure includes a first gate dielectric layer 211 a and a first gate conductive material layer 212 a stacked in sequence.

[0093] The first gate dielectric layer 211 a is a gate oxide layer or a high dielectric constant layer.

[0094] The first gate conductive material layer 212a is a polysilicon gate or a metal gate.

[0095] The N+ source region 2091 is formed in the first N-type diffusion region 2071 , the N+ drain region 2092 is formed in the second N-type diffusion region 2072 , and the P+ body lead-out region 2101 is formed in the first P-type diffusion region 2081 .

[0096] The first N-type diffusion region 2071 , the second N-type diffusion region 2072 and the first P-type diffusion region 2081 are all formed in the high-voltage P-well 202 ; a second P+ region 2102 and a second P-type diffusion region 2082 are also formed in the high-voltage P-well 202 , and the second P+ region 2102 is formed in the second P-type diffusion region 2082 .

[0097] The first side of the first gate structure is farther from the N-well isolation ring 204 than the second side of the first gate structure.

[0098] The second side of the first N-type diffusion region 2071 is aligned with or partially overlaps the first side of the first gate structure.

[0099] The first side of the second N-type diffusion region 2072 is aligned with or partially overlaps the second side of the second gate structure.

[0100] The second side of the first P-type diffusion region 2081 and the first side of the first N-type diffusion region 2071 are adjacent to each other and have a distance therebetween.

[0101] The first side of the second P-type diffusion region 2082 and the second side of the second N-type diffusion region 2072 are adjacent to each other and have a distance therebetween.

[0102] Shallow trench field oxygen 206 is provided on the first side of the first P-type diffusion region 2081, between the first P-type diffusion region 2081 and the first N-type diffusion region 2071, on the second side of the first N-type diffusion region 2071, on the first side of the second N-type diffusion region 2072, between the second N-type diffusion region 2072 and the second P-type diffusion region 2082, and on the second side of the second P-type diffusion region 2082, and the junction depths of the first N-type diffusion region 2071, the second N-type diffusion region 2072, the first P-type diffusion region 2081 and the second P-type diffusion region 2082 are all greater than the depth of the shallow trench field oxygen 206.

[0103] A shallow trench field oxide 206 is formed on the top of the P-well 205 .

[0104] The area covered by the Schottky diode 213 is smaller than or equal to the coverage area of ​​the top surface of the N-type isolation ring, and a third P+ region 2105 is formed on the top surface of the N-type isolation ring outside the coverage area of ​​the Schottky diode 213 .

[0105] The PMOS includes: a second gate structure, a P+ source region 2103 , a P+ drain region 2104 and an N+ body lead-out region 2093 .

[0106] The second gate structure includes a second gate dielectric layer 211 b and a second gate conductive material layer 212 b stacked in sequence.

[0107] The second gate dielectric layer 211 b is a gate oxide layer or a high dielectric constant layer.

[0108] The second gate conductive material layer 212 b is a polysilicon gate or a metal gate.

[0109] The P+ source region 2103 is formed in the third P-type diffusion region 2083 , the P+ drain region 2104 is formed in the fourth P-type diffusion region 2084 , and the N+ body lead-out region 2093 is formed in the third N-type diffusion region 2073 .

[0110] The third P-type diffusion region 2083 , the fourth P-type diffusion region 2084 and the third N-type diffusion region 2073 are all formed in the high-voltage N-well 203 ; a second N+ region 2094 and a fourth N-type diffusion region 2074 are also formed in the high-voltage N-well 203 , and the second N+ region 2094 is formed in the fourth N-type diffusion region 2074 .

[0111] The first side of the second gate structure is farther from the P-well 205 than the second side of the second gate structure.

[0112] The second side of the third P-type diffusion region 2083 is aligned with or partially overlaps with the first side of the second gate structure.

[0113] The first side of the fourth P-type diffusion region 2084 is aligned with or partially overlaps the second side of the second gate structure.

[0114] The second side of the third N-type diffusion region 2073 and the first side of the third P-type diffusion region 2083 are adjacent to each other and have a distance therebetween.

[0115] The first side of the fourth N-type diffusion region 2074 and the second side of the fourth P-type diffusion region 2084 are adjacent to each other and have a gap therebetween.

[0116] Shallow trench field oxygen 206 is provided on the first side of the third N-type diffusion region 2073, between the third N-type diffusion region 2073 and the third P-type diffusion region 2083, on the second side of the third P-type diffusion region 2083, on the first side of the fourth P-type diffusion region 2084, between the fourth P-type diffusion region 2084 and the fourth N-type diffusion region 2074, and on the second side of the fourth N-type diffusion region 2074, and the junction depths of the third P-type diffusion region 2083, the fourth P-type diffusion region 2084, the third N-type diffusion region 2073 and the fourth N-type diffusion region 2074 are all greater than the depth of the shallow trench field oxygen 206.

[0117] The N+ source region 2091 and the P+ body lead region 2101 of the NMOS are both connected to a negative power supply electrode VSS;

[0118] The P+ source region 2103 and the N+ body lead region 2093 of the PMOS are both connected to a positive power supply electrode Vdd.

[0119] Figure 2 In the figure, the N-type diffusion regions 2071 to 2074 are also represented by NDF; the P-type diffusion regions 2081 to 2084 are also represented by PDF; the N+ source region 2091, the N+ drain region 2092, the N+ body lead-out region 2093 and the second N+ region 2094 are also represented by N+; the P+ body lead-out region 2101, the second P+ region 2102, the P+ source region 2103, the P+ drain region 2104 and the third P+ region 2105 are also represented by P+.

[0120] In the embodiment of the present invention, in a CMOS in which an N-well isolation ring 204 is provided on the peripheral side of an NMOS, a Schottky diode 213 is formed on the surface of the N-well isolation ring 204 and is grounded GND through the metal electrode of the Schottky diode 213. In the parasitic SCR of the CMOS, the metal electrode of the Schottky diode 213 is used as the cathode. In this way, when the parasitic SCR is turned on, the Schottky diode 213 needs to be reversely broken down first. Finally, the reverse breakdown voltage of the Schottky diode 213 will be superimposed on the total holding voltage of the parasitic SCR. Therefore, the embodiment of the present invention can increase the holding voltage of the parasitic SCR, thereby reducing the risk of the latch-up effect, thereby improving the anti-latch-up effect capability of the CMOS circuit.

[0121] The embodiments of the present invention are particularly suitable for improving the anti-latch capability of the 32V CMOS in the 28HV platform and reducing the latch risk of the 32V CMOS in the 28HV platform in the negative current excitation mode.

[0122] The Schottky diode 213 of the embodiment of the present invention is disposed on the top surface of the N-type isolation ring, so the layout area will not be increased.

[0123] The Schottky diode 213 of the embodiment of the present invention can be realized by using conventional processes in a semiconductor manufacturing plant (fab), so the embodiment of the present invention is compatible with the existing processes and does not increase additional manufacturing costs.

[0124] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A CMOS anti-latch effect structure, characterized in that: Both NMOS and PMOS of CMOS circuits are formed on P-type semiconductor substrates; The NMOS is formed in a high-voltage P-well, and the PMOS is formed in a high-voltage N-well; The high-voltage P-well and the high-voltage N-well are both formed on the P-type semiconductor substrate; An N-well isolation ring is formed on the peripheral side of the high-voltage P-well, and the N-well isolation ring is used to isolate the NMOS from the P-type semiconductor substrate; A P well is provided between the N well isolation ring and the high voltage N well; A parasitic SCR is formed between the P+ source region of the PMOS, the high voltage N-well, the P-well and the N-well isolation ring; A Schottky diode is formed on the top surface of the N-well isolation ring; The metal electrode of the Schottky diode is grounded; When the parasitic SCR is turned on, a latching effect is generated, and when the parasitic SCR is turned on, the Schottky diode will be reversely broken down. The holding voltage when the parasitic SCR is turned on will be superimposed on the reverse breakdown voltage of the Schottky diode. The reverse breakdown voltage of the Schottky diode is used to increase the holding voltage when the parasitic SCR is turned on, thereby improving the anti-latch effect capability of the CMOS circuit.

2. The CMOS anti-latch effect structure according to claim 1, characterized in that: The P-type semiconductor substrate is a P-type silicon substrate.

3. The CMOS anti-latch-up structure according to claim 1, wherein: The NMOS includes: a first gate structure, an N+ source region, an N+ drain region and a P+ body lead region.

4. The CMOS anti-latch-up structure according to claim 3, wherein: The first gate structure includes a first gate dielectric layer and a first gate conductive material layer stacked in sequence.

5. The CMOS anti-latch-up structure according to claim 4, wherein: The first gate dielectric layer is a gate oxide layer or a high dielectric constant layer; The first gate conductive material layer is a polysilicon gate or a metal gate.

6. The CMOS anti-latch-up structure according to claim 3, wherein: The N+ source region is formed in the first N-type diffusion region, the N+ drain region is formed in the second N-type diffusion region, and the P+ body lead region is formed in the first P-type diffusion region; The first N-type diffusion region, the second N-type diffusion region and the first P-type diffusion region are all formed in the high-voltage P-well; a second P+ region and a second P-type diffusion region are also formed in the high-voltage P-well, and the second P+ region is formed in the second P-type diffusion region; The first side of the first gate structure is farther from the N-well isolation ring than the second side of the first gate structure; The second side of the first N-type diffusion region is aligned with or partially overlaps the first side of the first gate structure; The first side of the second N-type diffusion region is aligned with or partially overlaps the second side of the second gate structure; The second side of the first P-type diffusion region is adjacent to the first side of the first N-type diffusion region and has a distance therebetween; The first side of the second P-type diffusion region and the second side of the second N-type diffusion region are adjacent to each other and have a distance therebetween.

7. The CMOS anti-latch-up structure according to claim 6, wherein: Shallow trench field oxygen is provided on the first side of the first P-type diffusion region, between the first P-type diffusion region and the first N-type diffusion region, on the second side of the first N-type diffusion region, on the first side of the second N-type diffusion region, between the second N-type diffusion region and the second P-type diffusion region, and on the second side of the second P-type diffusion region, and the junction depths of the first N-type diffusion region, the second N-type diffusion region, the first P-type diffusion region, and the second P-type diffusion region are all greater than the depth of the shallow trench field oxygen.

8. The CMOS anti-latch-up structure according to claim 1, wherein: A shallow trench field oxide is formed on the top of the P-well.

9. The CMOS anti-latch-up structure according to claim 1, wherein: The area covered by the Schottky diode is smaller than or equal to the coverage area of ​​the top surface of the N-type isolation ring, and a third P+ region is formed on the top surface of the N-type isolation ring outside the coverage area of ​​the Schottky diode.

10. The CMOS anti-latch-up structure according to claim 3, wherein: The PMOS includes: a second gate structure, a P+ source region, a P+ drain region and an N+ body lead region.

11. The CMOS anti-latch-up structure according to claim 10, wherein: The second gate structure includes a second gate dielectric layer and a second gate conductive material layer stacked in sequence.

12. The CMOS anti-latch-up structure according to claim 11, wherein: The second gate dielectric layer is a gate oxide layer or a high dielectric constant layer; The second gate conductive material layer is a polysilicon gate or a metal gate.

13. The CMOS anti-latch-up structure according to claim 11, wherein: The P+ source region is formed in the third P-type diffusion region, the P+ drain region is formed in the fourth P-type diffusion region, and the N+ body lead region is formed in the third N-type diffusion region; The third P-type diffusion region, the fourth P-type diffusion region and the third N-type diffusion region are all formed in the high-voltage N-well; a second N+ region and a fourth N-type diffusion region are also formed in the high-voltage N-well, and the second N+ region is formed in the fourth N-type diffusion region; The first side of the second gate structure is farther from the P-well than the second side of the second gate structure; The second side of the third P-type diffusion region is aligned with or partially overlaps the first side of the second gate structure; The first side of the fourth P-type diffusion region is aligned with or partially overlaps the second side of the second gate structure; The second side of the third N-type diffusion region is adjacent to the first side of the third P-type diffusion region and has a distance therebetween; The first side of the fourth N-type diffusion region and the second side of the fourth P-type diffusion region are adjacent to each other and have a distance therebetween.

14. The CMOS anti-latch-up structure according to claim 13, wherein: Shallow trench field oxygen is provided on the first side of the third N-type diffusion region, between the third N-type diffusion region and the third P-type diffusion region, on the second side of the third P-type diffusion region, on the first side of the fourth P-type diffusion region, between the fourth P-type diffusion region and the fourth N-type diffusion region, and on the second side of the fourth N-type diffusion region, and the junction depths of the third P-type diffusion region, the fourth P-type diffusion region, the third N-type diffusion region, and the fourth N-type diffusion region are all greater than the depth of the shallow trench field oxygen.

15. The CMOS anti-latch-up structure according to claim 10, wherein: The N+ source region and the P+ body lead region of the NMOS are both connected to a negative power supply electrode; The P+ source region and the N+ body lead region of the PMOS are both connected to a positive power supply electrode.

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