Image signal transmission device and its signal output circuit with bandwidth enhancement mechanism

Abstract

A signal output circuit with a bandwidth enhancement mechanism, applied in an image signal transmission device, includes a pre-stage driver circuit and a post-stage driver circuit. The pre-stage driver circuit includes a continuous-time linear equalizer and is configured to receive a digital input signal and perform high-frequency enhancement to increase the bandwidth of the digital input signal, thereby generating a pre-stage output signal. The zeros and two poles of the frequency response of the pre-stage driver circuit are determined by multiple circuit parameter values ​​of the pre-stage driver circuit. The post-stage driver circuit is configured to receive the pre-stage output signal and amplify it to generate a post-stage output signal for the image signal receiving device.

Description

Technical Field

[0001] This application relates to signal output technology, and more particularly to an image signal transmission device and its signal output circuit with a bandwidth enhancement mechanism. Background Technology

[0002] High Definition Multimedia Interface (HDMI) is a fully digital image and audio transmission interface that can transmit uncompressed audio and video signals. Because it allows the simultaneous transmission of audio and video signals using the same cable, HDMI technology greatly simplifies system wiring installation.

[0003] Systems employing this transmission technology include a source end for transmitting audio and video signals and a receiver end for receiving these signals. The source end relies on the configuration of its signal output circuitry to properly adjust the audio and video signals so that the receiver can receive high-quality signals. However, signal output circuitry often struggles to balance signal quality with power consumption. Summary of the Invention

[0004] In view of the problems of the prior art, one object of this application is to provide an image signal transmission device and a signal output circuit with a bandwidth enhancement mechanism to improve the prior art.

[0005] This application includes a signal output circuit with a bandwidth enhancement mechanism, applied in an image signal transmission device (TX), comprising a pre-stage driver circuit and a post-stage driver circuit. The pre-stage driver circuit includes a continuous time linear equalizer (CTLE) and is configured to receive a digital input signal and perform high-frequency enhancement to increase the bandwidth of the digital input signal, thereby generating a pre-stage output signal. The zeros and two poles of the frequency response of the pre-stage driver circuit are determined by multiple circuit parameter values ​​of the pre-stage driver circuit. The post-stage driver circuit is configured to receive the pre-stage output signal and amplify it to generate a post-stage output signal for the image signal receiving device (RX).

[0006] This application also includes an image signal transmission device applied in an image signal transmission system, comprising: a digital signal processing circuit and a signal output circuit. The digital signal processing circuit is configured to generate a digital input signal. The signal output circuit includes: a pre-stage driver circuit and a post-stage driver circuit. The pre-stage driver circuit includes a continuous-time linear equalizer and is configured to receive the digital input signal and perform high-frequency enhancement to increase the bandwidth of the digital input signal, thereby generating a pre-stage output signal. The zero point and two poles of the frequency response of the pre-stage driver circuit are determined by multiple circuit parameter values ​​of the pre-stage driver circuit. The post-stage driver circuit is configured to receive the pre-stage output signal and amplify it to generate a post-stage output signal for transmission to the image signal receiving device of the image signal transmission system.

[0007] The features, practical operation, and effects of this application are described in detail below with reference to the accompanying drawings and preferred embodiments. Attached Figure Description

[0008] To make the above and other objects, features, advantages and embodiments of this application more apparent and understandable, the accompanying drawings are described below:

[0009] Figure 1 This is a block diagram of an image signal transmission system according to some embodiments of this application;

[0010] Figure 2 A circuit diagram of a pre-amplifier drive circuit drawn according to some embodiments of this application;

[0011] Figure 3 A schematic diagram of the frequency response of a pre-amplifier driver circuit according to some embodiments of this application; and

[0012] Figure 4 This is a schematic diagram illustrating the frequency response of a pre-amplifier drive circuit according to some embodiments of this application, under different resistance values ​​of the variable resistor and the variable capacitance value. Detailed Implementation

[0013] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to the cooperation or interaction of two or more components.

[0014] One objective of this application is to provide an image signal transmission device and a signal output circuit with a bandwidth enhancement mechanism, which achieves high bandwidth and low power consumption through the configuration of the pre-stage drive circuit.

[0015] Please refer to Figure 1 . Figure 1This diagram shows a block diagram of an image signal transmission system 100 according to an embodiment of this application. The image signal transmission system 100 includes an image signal transmitting device (TX) 110 and an image signal receiving device (RX) 120.

[0016] In one embodiment, the image signal transmission system 100 is a system for transmitting images and sound via a high-definition multimedia interface. The image signal transmission device 110 is a source, such as, but not limited to, a set-top box, DVD player, or computer. The image signal receiving device 120 is a sink, such as, but not limited to, a television, projector, or other display device. The image signal transmission device 110 is configured to process the audio and video signals and then transmit them to the image signal receiving device 120 for playback.

[0017] The image signal transmission device 110 includes a digital signal processing circuit 130 and a signal output circuit 140.

[0018] Digital signal processing circuit 130 is configured to generate differential digital input signals Vip and Vin. Signal output circuit 140 has a bandwidth enhancement mechanism to amplify the output of digital input signals Vip and Vin. Signal output circuit 140 includes a pre-stage driver circuit 150 and a post-stage driver circuit 160.

[0019] The preamplifier driver circuit 150 is configured to receive digital input signals Vip and Vin and perform high-frequency enhancement to increase the bandwidth of the digital input signals Vip and Vin, thereby generating preamplifier output signals Vop1 and Von1. The preamplifier output signals Vop1 and Von1 are also differential signals.

[0020] Please refer to Figure 2 . Figure 2 This invention discloses a circuit diagram of a pre-amplifier driver circuit 150 according to one embodiment of the present application. In one embodiment, the pre-amplifier driver circuit 150 includes a continuous-time linear equalizer, which includes two input transistors MN1 and MN2, two load resistors R1 and R2, two load capacitors C1 and C2, a variable resistor R3, a variable capacitor C3, and two current sources I1 and I2.

[0021] Each input transistor MN1 and MN2 includes a gate, a drain, and a source. The gate of input transistor MN1 is configured to receive a digital input signal Vip. The gate of input transistor MN2 is configured to receive a digital input signal Vin. The drain of input transistor MN1 is electrically coupled to the output terminal O1, and the drain of input transistor MN2 is electrically coupled to the output terminal O2. The drain of input transistor MN1 is configured to generate a pre-amplifier output signal Vop1 to the output terminal O1, and the drain of input transistor MN2 is configured to generate a pre-amplifier output signal Von1 to the output terminal O2.

[0022] Load resistor R1 is electrically coupled between the drain of input transistor MN1 and the operating voltage source VDD. Load resistor R2 is electrically coupled between the drain of input transistor MN2 and the operating voltage source VDD. Load capacitor C1 is electrically coupled between the drain of input transistor MN1 and ground GND. Load capacitor C2 is electrically coupled between the drain of input transistor MN2 and ground GND. Variable resistor R3 and variable capacitor C3 are electrically connected in parallel between the sources of input transistors MN1 and MN2. Current source I1 is electrically coupled between the source of input transistor MN1 and ground GND. Current source I2 is electrically coupled between the source of input transistor MN2 and ground GND.

[0023] In one embodiment, the zero point and two poles of the frequency response of the pre-stage driver circuit 150 are determined by multiple circuit parameter values ​​of the pre-stage driver circuit 150.

[0024] Please refer to the following at the same time Figure 3 . Figure 3 This diagram shows the frequency response of a pre-stage drive circuit 150 according to an embodiment of this application. The horizontal axis represents frequency, and the vertical axis represents gain.

[0025] In one embodiment, the circuit parameters of the front-end drive circuit 150 include the transconductance of the transistors, the resistance values ​​of each resistor, and the capacitance values ​​of each capacitor. For example, the transconductance of the input transistors MN1 and MN2 is gm, the resistance value of each load resistor R1 and R2 is Rd, the capacitance value of each load capacitor C1 and C2 is Cd, the resistance value of the variable resistor is Rs, and the capacitance value of the variable capacitor is Cs.

[0026] Therefore, regarding the frequency response of the pre-stage drive circuit 150, its conversion function H(s) can be expressed as follows:

[0027] H(s)=(gmRd)(1+sRsCs) / ((1+sRcCs+(gmRs / 2)) / (1+sRdCd)')

[0028] Furthermore, the DC gain of the pre-drive circuit 150 can be expressed by the following formula:

[0029] (gmRd) / (1+(gmRs / 2))

[0030] Zero point ω on the frequency response Z It can be expressed as follows:

[0031] ω Z =1 / (RsCs)

[0032] One of the poles ω P1 It can be expressed as follows:

[0033] ω P1 =(1+gmRs / 2) / (RsCs)

[0034] Another pole ω P2 This can be expressed as: 1 / (RdCd)

[0035] ω P2 =1 / (RdCd)

[0036] Therefore, by adjusting the circuit parameters mentioned above, the zero point and two poles of the frequency response of the pre-stage drive circuit 150 can be changed accordingly, thereby improving the DC gain and high-frequency components to different degrees.

[0037] Please refer to the following at the same time Figure 4 . Figure 4 This diagram illustrates the frequency response of the pre-stage drive circuit 150 in one embodiment of this application under different resistance values ​​Rs of the variable resistor and capacitance values ​​Cs of the variable capacitor. The horizontal axis represents frequency, and the vertical axis represents gain.

[0038] exist Figure 4 In the diagram, the arrow labeled Rs indicates the trend of frequency response as the resistance value Rs increases. For example... Figure 4 As shown, the larger the resistance value Rs, the smaller the DC gain. On the other hand, the arrow labeled Cs indicates the trend of frequency response as the capacitance value Cs increases. Figure 4 As shown, the larger the capacitance value Cs, the lower the positions of the zero and poles will be.

[0039] Therefore, with appropriate selection of resistor value Rs and capacitor value Cs, the pre-stage driver circuit 150 can improve the high-frequency response of digital input signals Vip and Vin, thereby increasing the bandwidth of digital input signals Vip and Vin.

[0040] The post-stage drive circuit 160 is configured to receive and amplify the pre-stage output signals Vip and Vin to generate post-stage output signals Vop2 and Von2, which are then sent to the image signal receiving device 120. In one embodiment, the post-stage drive circuit includes current-mode logic (CML) circuitry. Furthermore, the post-stage output signals Vop2 and Von2 are also differential signals.

[0041] In some technologies, the signal output circuit uses amplification achieved by connecting two stages of current-mode logic circuits in series. However, this approach fails to achieve power saving because the current-mode logic circuits consume a significant amount of current.

[0042] In contrast, the signal output circuit of this application can improve the bandwidth of the output signal with low current consumption by setting the pre-stage drive circuit implemented with a continuous-time linear equalizer, thereby achieving both high bandwidth and low power consumption.

[0043] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make changes without departing from the technical spirit of this application.

[0044] In summary, the image signal transmission device and its signal output circuit with bandwidth enhancement mechanism in this application can achieve high bandwidth and low power consumption through the configuration of the pre-stage drive circuit.

[0045] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes fall within the scope of patent protection of this application. In other words, the scope of patent protection of this application must be based on the content disclosed in this specification.

[0046] Although this application has disclosed the embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the scope defined in the claims.

[0047] Explanation of reference numerals in the attached figures:

[0048] 100: Image signal transmission system

[0049] 110: Image signal transmission device

[0050] 120: Image signal receiving device

[0051] 130: Digital Signal Processing Circuit

[0052] 140: Signal output circuit

[0053] 150: Pre-amplifier driver circuit

[0054] 160: Post-stage drive circuit

[0055] C1, C2: Load capacitors

[0056] C3: Variable capacitor

[0057] Cs: Capacitance value of the variable capacitor

[0058] GND: Ground terminal

[0059] I1, I2: Current sources

[0060] MN1, MN2: Input transistors

[0061] O1, O2: Output terminals

[0062] Vip, Vin: Digital input signals

[0063] Vop1, Von1: Preamp output signals

[0064] Vop2, Von2: Output signals of the later stage

[0065] R1, R2: Load resistors

[0066] R3: Variable resistor

[0067] Rs: Resistance value of the variable resistor

[0068] ω P1 ω P2 :pole

[0069] ω Z : Midnight

Claims

1. A signal output circuit with bandwidth boosting mechanism, applied in an image signal transmitting device, comprising: a pre-stage driving circuit, comprising a continuous-time linear equalizer, and configured to receive a digital input signal for high frequency boosting to boost bandwidth of the digital input signal, and to generate a pre-stage output signal, wherein a zero point and two poles of a frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values of the pre-stage driving circuit; and a post-stage driving circuit, configured to receive the pre-stage output signal for amplification to generate a post-stage output signal to an image signal receiving device, wherein the continuous-time linear equalizer comprises: two input transistors, each comprising: a gate, configured to receive the digital input signal; a drain, electrically coupled to an output terminal, configured to generate the pre-stage output signal to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and a ground terminal; a variable resistor and a variable capacitor, electrically connected in parallel between the sources of the two input transistors; and two current sources, each electrically coupled between the source of one of the two input transistors and the ground terminal, wherein the plurality of circuit parameter values comprise resistance values of the two load resistors, capacitance values of the two load capacitors, a resistance value of the variable resistor, and a capacitance value of the variable capacitor, the resistance values of the two load resistors are Rd, the capacitance values of the two load capacitors are Cd, the resistance value of the variable resistor is Rs, the capacitance value of the variable capacitor is Cs, and a transconductance of the two input transistors is gm, the zero point is 1 / (RsCs), and the two poles are (1+gmRs / 2) / (RsCs) and 1 / (RdCd) respectively.

2. The signal output circuit according to claim 1, characterized by The digital input signal, the pre-stage output signal, and the post-stage output signal are differential signals.

3. The signal output circuit according to claim 1, wherein The pre-stage driving circuit receives the digital input signal from a digital signal processing circuit included in the image signal transmitting device.

4. The signal output circuit according to claim 1, wherein A transfer function between the digital input signal and the pre-stage output signal is: (gmRd)(1+sRsCs) / ((1+sRcCs+(gmRs / 2)) / (1+sRdCd)').

5. The signal output circuit according to claim 1, wherein A direct current gain of the continuous-time linear equalizer is: (gmRd) / (1+(gmRs / 2)).

6. The signal output circuit according to claim 1, wherein The post-stage driving circuit comprises a current-mode logic circuit.

7. An image signal transmitting device, applied in an image signal transmission system, comprising: a digital signal processing circuit, configured to generate a digital input signal; and a signal output circuit, comprising: ​ a pre-stage driving circuit, comprising a continuous-time linear equalizer, and configured to receive the digital input signal for high frequency boosting to increase bandwidth of the digital input signal, thereby generating a pre-stage output signal, wherein a zero point and two poles of a frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values of the pre-stage driving circuit; and a post-stage driving circuit, configured to receive the pre-stage output signal for amplification, thereby generating a post-stage output signal to an image signal receiving device of the image signal transmission system, wherein the continuous-time linear equalizer comprises: two input transistors, each comprising: a gate, configured to receive the digital input signal; a drain, electrically coupled to an output terminal, configured to generate the pre-stage output signal to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and a ground terminal; a variable resistor and a variable capacitor, electrically connected in parallel between the sources of the two input transistors; and two current sources, each electrically coupled between the source of one of the two input transistors and the ground terminal, wherein the plurality of circuit parameter values comprises a resistance value of each of the two load resistors, a capacitance value of each of the two load capacitors, a resistance value of the variable resistor, and a capacitance value of the variable capacitor, the resistance value of each of the two load resistors is Rd, the capacitance value of each of the two load capacitors is Cd, the resistance value of the variable resistor is Rs, the capacitance value of the variable capacitor is Cs, and a transconductance of the two input transistors is gm, the zero point is 1 / (RsCs), and the two poles are (1+gmRs / 2) / (RsCs) and 1 / (RdCd), respectively.

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