Monitor

Abstract

An apparatus configuration designed to mitigate display defects caused by voltage drops in current supply lines provides a display with better display quality. The display includes: a plurality of VOLETs arranged in an array along a first direction and a second direction; data lines supplying voltages for controlling gate electrodes of the plurality of VOLETs; TFTs each connected between a gate electrode of each of the VOLETs and the data lines and controlling voltage supply to the gate electrodes of the VOLETs; gate lines connected to the gate electrodes of the TFTs and transmitting signals for controlling the TFTs; a plurality of current supply lines extending along the first direction and supplying current to each of a group of VOLETs aligned along the first direction; and auxiliary lines extending along the second direction and connecting at least two of the plurality of current supply lines.

Description

Technical Field

[0001] The present invention relates to a display. Background Art

[0002] In recent years, as organic semiconductor devices have been increasingly used as light source devices in practice, displays using organic semiconductor devices as light source devices have become commercially available. Nowadays, research on developing displays using organic semiconductor devices as light source devices is continuously ongoing to find ways to achieve higher brightness, higher precision, lower power consumption, and longer lifespan to further improve performance.

[0003] Pixels of existing displays using organic semiconductor devices as light-emitting devices are made of an organic light emitting diode (OLED) (also referred to as an “OLED”) and a transistor that controls the current flowing through the organic light emitting diode. The organic light emitting diode is a device that emits light according to the current input from a thin-film transistor (TFT) (also referred to as a “TFT”), and the thin-film transistor is formed on a substrate in an organic electroluminescence (EL) layer sandwiched between an anode electrode and a cathode electrode.

[0004] In contrast, Patent Document 1 listed below describes a vertical organic light emitting transistor (VOLET) (also referred to as a “VOLET”), which is used as a device that can reduce the number of control devices and increase the light-emitting area to achieve higher brightness. The vertical organic light emitting transistor emits light according to the amount of current flowing through the transistor itself, and the transistor adjusts the current flow by controlling the voltage applied to the gate electrode. Patent Document 2 listed below describes a display using a vertical organic light emitting transistor, and thus the display is expected to have a significantly increased brightness.

[0005] Patent Literature (PTL)

[0006] PTL 1: Patent Document 1: WO 2009 / 036071

[0007] PTL 2: Patent Document 2: JP-A-2014-505324 Summary of the Invention

[0008] In recent years, displays have been widely used not only as household television (TV) or personal computer (PC) monitors, but also, for example, as advertisements in station buildings, backgrounds in event venues, etc. Therefore, with the above-mentioned performance improvements, how to increase the size has become an important issue in the current development of displays.

[0009] In a display using an organic semiconductor, an organic light-emitting diode and a thin-film transistor that make up a pixel are provided in a display portion, and a driver for driving these devices is provided in an outer periphery of the display portion. This is still a common configuration adopted by many displays today.

[0010] Increasing the size of a display using this configuration results in an increase in the transmission distance of signals output from various drivers provided in the outer periphery for controlling or driving various devices over the entire display portion. The longer the wiring line connecting the driver and the device, the greater the resistance of the wiring between the driver and the device. An increase in the resistance of the wiring may cause a voltage drop (also referred to as an "IR drop") due to the passing current, or may cause signal delay or degradation.

[0011] A current supply line for supplying current to a light-emitting device is particularly susceptible to an increase in resistance. That is, even when the same voltage is applied to cause current to flow from a current supply portion into each light-emitting device, the voltage decreases according to the resistance of the wiring and the passing current as the distance from the current supply portion increases. This results in an actual amount of supplied current being less than the current value required for displaying image data. Such a difference may accumulate to a certain extent such that display defects become apparent enough for an observer to visually perceive a gradual decrease in brightness. In addition, since in many cases the current supply line is shared by a group of light-emitting devices aligned in a row, a change in the resistance of the wiring of the current supply line causes a brightness difference between the lines, which results in a display defect of the lines.

[0012] As a measure to solve the above problems, the method described in Patent Document 3 listed above can be applied, in which the emission brightness of each pixel is detected, and a voltage taking into account the voltage drop is supplied to a data line and a current supply line. However, additional complex circuits will occupy a substantial portion of the light-emitting area and suppress the ability to increase brightness. In addition, since more devices are used, the display may become more prone to malfunction and failure.

[0013] It is also possible to use the outer peripheral portion in which a driver is provided, or an external device can be added. However, the expansion of the outer peripheral portion or the addition of an external device will impose restrictions on the usage mode and installation position of the display, which is contrary to the expectation of changing the application purpose.

[0014] In addition, in feedback control where a voltage is applied taking into account fluctuations, depending on the calculation method, errors may occur, so there may also be a situation where voltage correction is insufficient to prevent the brightness change from being recognized as a display defect. Therefore, measures to prevent display defects should preferably be provided as a device structure rather than by correcting the brightness change.

[0015] When the applicant of the present invention investigated a display using vertical organic light-emitting transistors, the following problems regarding vertical organic light-emitting transistors were further found. Similar to field-effect transistors, vertical organic light-emitting transistors include a source electrode, a gate electrode, and a drain electrode.

[0016] Unlike field-effect transistors such as thin-film transistors, for example, vertical organic light-emitting transistors are provided with an EL device and an organic semiconductor layer between the source electrode and the drain electrode. The material properties of these layers cause vertical organic light-emitting transistors to have the following characteristic features: compared with field-effect transistors such as thin-film transistors, for example, the current flowing between the source electrode (anode electrode) and the drain electrode (cathode electrode) is more easily affected by the voltage applied across these electrodes. That is, compared with the existing configuration having an organic light-emitting diode and a thin-film transistor, the current supply line is more affected by voltage drop, so the above display defect may be more likely to occur.

[0017] In view of the above problems, an object of the present invention is to provide a device configuration that is designed to mitigate display defects caused by voltage drop in the current supply line to provide a display with better display quality.

[0018] A display according to the present invention includes:

[0019] A plurality of vertical organic light-emitting transistors arranged in an array along a first direction and a second direction orthogonal to the first direction;

[0020] Data lines for supplying a voltage for controlling the gate electrodes of the plurality of vertical organic light-emitting transistors;

[0021] Thin-film transistors each connected between the gate electrode of each of the vertical organic light-emitting transistors and the data line and controlling the voltage supply to the gate electrode of the vertical organic light-emitting transistor;

[0022] Gate lines connected to the gate electrodes of the thin-film transistors and transmitting signals for controlling the thin-film transistors;

[0023] A plurality of current supply lines extending in a first direction and supplying current to each of a group of vertical organic light-emitting transistors aligned in the first direction; and

[0024] At least one auxiliary line extending in a second direction and connecting at least two of the plurality of current supply lines.

[0025] The current supply lines for supplying current to the vertical organic light-emitting transistors extend in a first direction and are shared by a group of organic light-emitting transistors arranged in the first direction. The plurality of current supply lines are arranged in a second direction. At least two of the current supply lines are connected by an auxiliary line extending in the second direction.

[0026] As long as two or more current supply lines are connected, any number of auxiliary lines may exist. Although it is preferred that the current supply lines connected by the auxiliary line are positioned close to each other, the adjacent current supply lines do not have to be connected to each other.

[0027] The above configuration reduces the local voltage drop. Even in a situation where a large local voltage drop inevitably exists in one of the current supply lines, since the voltage is supplied by other current supply lines connected thereto through the auxiliary line, the voltage is made uniform among the current supply lines. This makes it difficult to distinguish a pixel region or column having a brightness much lower than that of the surrounding pixels, thereby significantly improving the display quality.

[0028] In addition, since, according to the above configuration, the auxiliary line connects the current supply lines in the second direction, the voltage drop occurs not only in each current supply line but also over the entire screen, resulting in a gradual decrease in brightness. Therefore, if the voltage is supplied taking into account the voltage drop in the above configuration, the voltage is corrected in a gradual manner, and the voltage is adjusted two-dimensionally and jointly in response to the brightness trend of the entire screen, rather than correcting the voltage for each of the current supply lines. Therefore, complex calculations for the brightness correction of each current supply line are not required. In addition, even if there are errors caused by the calculation method, since the voltage is corrected over the entire screen, local display defects hardly occur, making it unlikely that the display defects can be distinguished.

[0029] In the above display,

[0030] The auxiliary line may be formed closer to the substrate than the source electrode of the vertical organic light-emitting transistor.

[0031] The pixel configuration of a display using an organic light-emitting diode includes at least two thin-film transistors in a lower layer and an organic light-emitting diode in an upper layer, where the upper layer is the layer farther from the substrate. On the other hand, the pixel configuration of a display using a vertical organic light-emitting transistor includes at least one thin-film transistor in a lower layer and a vertical organic light-emitting transistor in an upper layer. Thus, the area for another unnecessary thin-film transistor in the lower layer becomes available. Compared with the existing pixel configuration, using this area as a wiring area enables maintaining or enhancing brightness and forming auxiliary lines.

[0032] In the above display,

[0033] The auxiliary line may include wiring made of the material constituting the gate line and formed in the layer where the gate line is provided.

[0034] The gate electrode of the thin-film transistor is formed in the layer below the source electrode and the drain electrode of the thin-film transistor. Thus, in many cases, the gate line connected to the gate electrode of the thin-film transistor is provided in the lowermost layer closest to the substrate, and the data line and the power line connected to light-emitting devices such as an organic light-emitting diode and a vertical organic light-emitting transistor are provided in the layer above the gate line so that they can be easily connected to the light-emitting devices. That is, compared with other layers, the layer where the gate line is provided is more easily used for wiring.

[0035] In addition, compared with a display using an organic light-emitting diode, a display using a vertical organic light-emitting transistor has one less thin-film transistor, so that the area for the unnecessary thin-film transistor can be utilized, which enables forming auxiliary lines while minimizing the reduction in the size of the light-emitting area and avoiding a significant decrease in brightness.

[0036] The gate line is wiring for transmitting a signal for high-speed control of the thin-film transistor and is therefore made of a material having a lower resistance than the materials of other layers. Thus, making the auxiliary line of the same material as the gate line enables achieving a configuration in which the influence of the resistance of the auxiliary line on the current supply line connected by the auxiliary line is reduced, so that the voltage becomes uniform between the current supply lines.

[0037] In the above display,

[0038] The auxiliary line may include wiring made of the material constituting the gate electrode of the vertical organic light-emitting transistor and disposed in the layer where the gate electrode of the vertical organic light-emitting transistor is provided.

[0039] For example, even when a complex control circuit needs to be configured and it is difficult to ensure an area for wiring, the above configuration enables an auxiliary line to be formed in a layer below the vertical organic light-emitting transistor. The auxiliary line can also be configured to extend in parallel in a layer above the auxiliary line formed in the same layer as the above gate line, which further enables the voltage to be made uniform between the current supply lines.

[0040] A display according to the present invention includes:

[0041] A plurality of vertical organic light-emitting transistors arranged in an array along a first direction and a second direction orthogonal to the first direction;

[0042] Data lines for supplying a voltage for controlling gate electrodes of the plurality of vertical organic light-emitting transistors;

[0043] Thin film transistors each connected between a gate electrode of each of the vertical organic light-emitting transistors and the data lines and controlling the voltage supply to the gate electrodes of the vertical organic light-emitting transistors; and

[0044] Gate lines connected to the gate electrodes of the thin film transistors and transmitting signals for controlling the thin film transistors,

[0045] At least two adjacent ones of the plurality of vertical organic light-emitting transistors have source electrode layers continuously formed therebetween.

[0046] In the above configuration, the source electrode layer of one vertical organic light-emitting transistor is directly connected to the source electrode layer of an adjacent vertical organic light-emitting transistor so that the voltage applied to the corresponding source electrode layers of the vertical organic light-emitting transistors does not have a large difference.

[0047] The above configuration also enables the source electrode layers of the vertical organic light-emitting transistors to be formed over a large area so that high-precision patterning is not required. Therefore, the source electrode layers of the vertical organic light-emitting transistors can be formed by a simpler patterning such as, for example, inkjet screen printing (which is a printing method). This helps to suppress an increase in the number of production steps and processing costs that may be caused by the formation and patterning of the source electrode layers of the vertical organic light-emitting transistors.

[0048] The source electrodes of the coupled vertical organic light-emitting transistors enable current to be distributed among the surrounding connected pixels, which makes the formation of some contact holes unnecessary. Simplification of the contact hole formation method can suppress an increase in processing costs and a decrease in the panel production yield that may be caused by contact failure.

[0049] The above display may further include

[0050] Multiple current supply lines extending in a first direction and supplying current to each of a group of vertical organic light-emitting transistors aligned in the first direction.

[0051] In the above display, since the source electrode layer is continuous between adjacent vertical organic light-emitting transistors among the multiple vertical organic light-emitting transistors, current is supplied to the vertical organic light-emitting transistors via the source electrodes. Through the additional current supply lines, the resistance between the source electrodes of the vertical organic light-emitting transistors is reduced, so that the voltage at the source electrodes of each vertical organic light-emitting transistor becomes more uniform.

[0052] The above display may further include

[0053] At least one auxiliary line extending in a second direction and connecting at least two of the multiple current supply lines.

[0054] In the above display,

[0055] The auxiliary line may be formed closer to the substrate than the source electrodes of the vertical organic light-emitting transistors.

[0056] In the above display,

[0057] The auxiliary line may include wiring made of the material constituting the gate line and formed in the layer where the gate line is provided.

[0058] In the above display,

[0059] The auxiliary line may include wiring made of the material constituting the gate electrodes of the vertical organic light-emitting transistors and disposed in the layer where the gate electrodes of the vertical organic light-emitting transistors are provided.

[0060] Each of the above configurations makes the resistance between the source electrodes of the vertical organic light-emitting transistors smaller, which enables the voltage at the source electrodes of the vertical organic light-emitting transistors to be more uniform.

[0061] According to the present invention, a display with better display quality is achieved through a device configuration designed to mitigate display defects caused by voltage drops in the current supply lines. Brief Description of the Drawings

[0062] Figure 1 Is a schematic configuration diagram of a part of a display in an embodiment.

[0063] Figure 2 Is Figure 1 A circuit diagram of the light-emitting part in area A1 of the shown display.

[0064] Figure 3A plan view of a schematic device configuration of a light-emitting portion and its vicinity in an embodiment.

[0065] Figure 4 is a cross-sectional view taken along Figure 3 A-A' shown in the figure.

[0066] Figure 5 is a cross-sectional view taken along Figure 3 B-B' shown in the figure.

[0067] Figure 6 A plan view of a schematic device configuration of a light-emitting portion and its vicinity in an embodiment.

[0068] Figure 7 is a cross-sectional view taken along Figure 6 A-A' shown in the figure.

[0069] Figure 8 is a cross-sectional view taken along Figure 6 B-B' shown in the figure.

[0070] Figure 9 A plan view of a schematic device configuration of a light-emitting portion and its vicinity in an embodiment.

[0071] Figure 10 is a cross-sectional view taken along Figure 9 A-A' shown in the figure. Detailed implementation mode

[0072] Hereinafter, the configuration of the display of the present invention will be described with reference to the accompanying drawings. Each of the accompanying drawings hereinafter provided is a schematic illustration. The dimensional ratios and numbers of the elements in the drawings are not necessarily the same as the actual dimensional ratios and numbers of the elements.

[0073] First embodiment

[0074] Figure 1 is a schematic configuration diagram of a part of the display 1 in an embodiment. As Figure 1 shown in the figure, the display 1 of this embodiment includes an array composed of light-emitting portions 10, and each light-emitting portion 10 includes a vertical organic light-emitting transistor, a data line 11 for supplying a voltage to the gate electrode of the vertical organic light-emitting transistor, a current supply line 12 for supplying a current to the source electrode of the vertical organic light-emitting transistor, a gate line 13 for transmitting a signal for controlling the thin-film transistor, and an auxiliary line 14 for connecting the current supply line 12.

[0075] The display 1 also includes, in its outer peripheral portion: a source driver 15a that supplies a voltage to the data lines 11 to apply a voltage to the gate electrode of the vertical organic light-emitting transistor according to image data to be displayed; a current supply portion 15b that supplies a current to the current supply line 12 so that a current is supplied to the source electrode of the vertical organic light-emitting transistor; and a gate driver 15c that outputs a control signal for the thin-film transistor to the gate line 13.

[0076] Figure 2 is Figure 1 A detailed circuit diagram of the light-emitting portion 10 in the region A1 of the display 1 shown. As Figure 2 shown, the light-emitting portion 10 includes a vertical organic light-emitting transistor 20, a thin-film transistor 21 that controls the voltage supply to the gate electrode of the vertical organic light-emitting transistor 20, and a capacitor 23 connected between the source electrode and the gate electrode of the vertical organic light-emitting transistor 20. In reference Figure 1 and Figure 2 the description of, the direction in which the current supply line 12 extends will be referred to as the X direction (first direction), and the direction in which the auxiliary line 14 extends will be referred to as the Y direction (second direction).

[0077] The data line 11 is a wiring line that applies the voltage output from the source driver 15a to the gate electrode of the vertical organic light-emitting transistor 20 via the thin-film transistor 21 so as to adjust the emission brightness of the vertical organic light-emitting transistor 20 according to the displayed image. Although the data line 11 is formed in the X direction in this embodiment, the data line may be formed in the Y direction.

[0078] The current supply line 12 is formed in the X direction to connect to each of the group of vertical organic light-emitting transistors 20 aligned in the X direction. Each current supply line 12 supplies the current output from the current supply portion 15b to the source electrode of each vertical organic light-emitting transistor included in the group of vertical organic light-emitting transistors 20.

[0079] The gate line 13 is connected to the gate electrode of the thin-film transistor 21 so that the control signal output from the gate driver 15c is transmitted to the gate electrode of the thin-film transistor 21. Accordingly, the power application and control signal transmission between the gate electrode of the vertical organic light-emitting transistor 20 and the data line 11 are controlled by turning on and off the thin-film transistor 21. Although the gate line 13 is formed in the Y direction in this embodiment, the gate line may be formed in the X direction.

[0080] The auxiliary line 14 extends in the Y direction between the light-emitting portions 10 aligned in the X direction. The auxiliary line 14 does not have to be formed between adjacent light-emitting portions 10 among all the light-emitting portions 10 aligned in the X direction. Although the current supply line 12 is formed in the X direction and the auxiliary line 14 is formed in the Y direction in this embodiment, the current supply line 12 may be formed in the Y direction and the auxiliary line 14 may be formed in the X direction.

[0081] The capacitor 23 is a voltage holding device between the gate electrode and the source electrode of the vertical organic light-emitting transistor 20, and is configured to maintain the displayed image for a predetermined time during the off state of the thin-film transistor 21.

[0082] Next, the structure of each device formed on the substrate will be described. Figure 3 is a top plan view of a schematic device configuration of the light-emitting portion 10 and its vicinity in an embodiment. Figure 4 is along Figure 3 the cross-sectional view taken along A-A' shown. As Figure 3 and Figure 4 shown in, the vertical organic light-emitting transistor 20 and the thin-film transistor 21 are disposed in a region outlined by the data line 11, the current supply line 12, and the gate line 13.

[0083] Figure 5 is along Figure 3 the cross-sectional view taken along B-B' shown. As Figure 3 and Figure 5 shown in, the auxiliary line 14 is formed in the same layer as the gate line 13 connected to the gate electrode layer 21g of the thin-film transistor 21 and is made of the same material as the gate line 13. Hereinafter, the auxiliary line 14 made of the same material as the gate line 13 and located in the same layer as the gate line 13 will be referred to as the wiring layer auxiliary line 14a.

[0084] The substrate 30 is light-transmissive and outputs the light emitted from the vertical organic light-emitting transistor 20 to the outside. Specific materials will be described later.

[0085] In the following description, the direction in which the data line 11 and the current supply line 12 extend will be referred to as the X direction, the direction in which the gate line 13 extends will be referred to as the Y direction, the direction orthogonal to these directions will be referred to as the Z direction, and the direction away from the substrate 30 (in the Z direction) will be referred to as the upper layer.

[0086] The vertical organic light-emitting transistor 20 is configured to include, from the upper layer, a drain electrode layer 20d corresponding to a cathode electrode, an organic EL layer 20c, an organic semiconductor layer 20a, and a source electrode layer 20s, and in the underlying layer, a gate electrode layer 20g via a gate insulating layer 20h made of a dielectric material. The source electrode layer 20s is formed by coating the surface of the surface layer 31 with a conductive material containing carbon (carbon nanotubes in this embodiment). Applying a voltage to the gate electrode layer 20g changes the Schottky barrier between the organic semiconductor layer 20a and the source electrode layer 20s, and when a predetermined threshold is exceeded, current flows from the source electrode layer 20s to the organic semiconductor layer 20a and the organic EL layer 20c, enabling the vertical organic light-emitting transistor 20 to emit light.

[0087] In the display 1 of this embodiment, the substrate 30 is made of a material that transmits visible light. Both the gate electrode layer 20g and the source electrode layer 20s transmit visible light and are configured such that there are gaps allowing visible light to pass through, enabling the light output from the organic EL layer 20c to pass through the substrate 30 and exit to the outside, thereby displaying an image. Such a configuration in which light passes through the substrate 30 and is emitted is called a "bottom emission type", and has the advantage of being easy to manufacture due to the simple interconnection between the electrodes.

[0088] The source electrode layer 21s and the drain electrode layer 21d of the thin-film transistor 21 are connected via an oxide semiconductor layer 21a, and the gate electrode layer 21g is formed via an insulating layer or a dielectric layer below the oxide semiconductor layer 21a. The voltage applied to the gate electrode layer 21g creates a corresponding conductive channel in the oxide semiconductor layer 21a, supplying power to the source electrode layer 21s and the drain electrode layer 21d.

[0089] The source electrode layer 21s and the drain electrode layer 21d of the thin-film transistor 21 are respectively connected to the data line 11 and the gate electrode layer 20g of the vertical organic light-emitting transistor 20.

[0090] As Figure 3 shown, the vertical organic light-emitting transistor 20 is formed to substantially cover the entire area outlined by the data line 11, the current supply line 12, and the gate line 13 to achieve high brightness of the display 1, while the thin-film transistor 21 is formed to occupy as little space as possible in the corners of the area outlined here, minimizing the impact on the light-emitting area of the vertical organic light-emitting transistor 20.

[0091] The capacitor 23 is not shown in Figures 3 to 5 . The vertical organic light-emitting transistor 20 of this embodiment includes a capacitor 23 as a parasitic device, as shown in Figure 4 or Figure 5As shown, the source electrode layer 20s and the gate electrode layer 20g are arranged opposite to each other via the gate insulating layer 20h. This capacitor 23 can also function as a voltage holding device. If the capacitance provided by this capacitor 23 configured as a parasitic device is insufficient, another capacitor can be added.

[0092] Examples of materials that can be used for the corresponding layers are listed below.

[0093] For the gate line 13 and the wiring layer auxiliary line 14a, metal alloys of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), niobium (Nb), magnesium (Mg), silver (Ag), copper (Cu), and combinations thereof can be used.

[0094] For the substrate 30, a glass material or a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyimide can be used.

[0095] For the drain electrode layer 20d of the vertical organic light-emitting transistor 20, single-layer or multi-layer graphene, carbon nanotubes, aluminum (Al), silver (Ag), lithium fluoride (LiF), molybdenum oxide (Mo X O Y )), indium tin oxide (ITO), and zinc oxide (ZnO) can be used.

[0096] For the gate electrode layer 20g of the vertical organic light-emitting transistor 20, metal-doped or undoped transparent conductive oxides that can be doped with metals such as zinc oxide (ZnO), indium oxide (In2O3), tin dioxide (SnO2), and cadmium oxide (CdO), as well as p-doped or n-doped silicon (Si) or gallium arsenide (GaAs) can be used. The metals are, for example, aluminum (Al), tin (Sn), yttrium (Y), scandium (Sc), and gallium (Ga) and materials containing combinations thereof, or aluminum (Al), gold (Au), silver (Ag), platinum (Pt), cadmium (Cd), nickel (Ni), and tantalum (Ta) and combinations thereof.

[0097] For the gate insulating layer 20h between the surface layer 31 and the gate electrode layer 20g of the vertical organic light-emitting transistor 20, silicon oxide (SiO X ), aluminum oxide (Al2O3), silicon nitride (Si3N4), yttrium oxide (Y2O3), lead titanate (PbTiO X ), aluminum titanate (AlTiO X ), glass, and organic compounds such as parylene polymers, polystyrene, polyimide, polyvinyl phenol, polymethyl methacrylate, and fluoropolymers can be used.

[0098] For the organic semiconductor layer 20a of the vertical organic light-emitting transistor 20, the materials that can be used include: linear cyclic polycyclic aromatic compounds (or acene compounds), such as naphthalene, anthracene, rubrene, tetracene, pentacene, hexacene and their derivatives; pigments, such as (for example) copper phthalocyanine (CuPc) compounds, azo compounds, perylene compounds and their derivatives; low molecular weight compounds, such as (for example) hydrazone compounds, triphenylmethane compounds, diphenylmethane compounds, stilbene compounds, allyl vinyl compounds, pyrazoline compounds, triphenylamine derivatives (TPD), arylamine compounds, low molecular weight amine derivatives (α-NPD), 2,2',7,7'-tetrakis(diphenylamino)-9,9'-spirobifluorene (Spiro-TAD), N,N'-di(1-naphthyl)-N,N'-diphenyl-4,4'-diaminobiphenyl (Spiro-NPB), 4,4',4"-tris[N-3-methylphenyl-N-phenylamino]-triphenylamine (mMTDATA), 2,2',7,7'-tetrakis(2,2-diphenylvinyl)-9,9-spirobifluorene (Spiro-DPVBi), 4,4'-bis(2,2-diphenylvinyl)biphenyl (DPVBi), (8-quinolinolate)aluminum (Alq), tris(8-quinolinolato)aluminum (Alq3), tris(4-methyl-8quinolinolato)aluminum (Almq3) and their derivatives;Polymer compounds, such as (for example) polythiophene, poly(p-phenylenevinylene) (PPV), biphenyl-containing polymers, dialkoxy-containing polymers, alkoxyphenyl PPV, phenyl PPV, phenyl / dialkoxy PPV copolymers, poly(2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV), poly(ethylenedioxythiophene) (PEDOT), poly(styrenesulfonic acid) (PSS), poly(aniline) (PAM), poly(N-vinylcarbazole), poly(vinylpyrene), poly(vinylanthracene), pyrene formaldehyde resin, halogenated ethylcarbazole formaldehyde resin and their modified products; n-type transporting organic low molecules, oligomers or polymers, such as (for example) 5,5_-bis(perfluorohexylcarbonyl)-2,2_:5_,2_:5_,2_-tetrathiophene (DFHCO-4T), α,ω-bis(perfluorohexyl)tetrathiophene (DFH-4T), bis(perfluorophenylcarbonyl)-2,2'5',2”5”,2-tetrathiophene (DFCO-4T), poly{[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl]-5,5'-(2,2'-bithiophene)} (P(NDI2OD-T2)), N,N'-bis(n-octyl)-dicyanoanthradithiophene-3,4,9,10-bis(dicarboximide) (PDI8-CN2), N,N'-1H,1H-perfluorobutyldicyanoperylene diimide (PDIF-CN2), and copper fluoride phthalocyanine (F16CuPc), fullerenes, naphthalene, and perylene and oligothiophene derivatives; and aromatic compounds having a thiophene ring, such as thiophene[3,2-b]thiophene, dinaphthyl[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT), 2-decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene (BTBT), etc.;

[0099] The appropriate selection of an organic semiconductor having a matching energy level enables the advantageous use of a hole injection layer, a hole transport layer, an organic EL layer, an electron transport layer, an electron injection layer, etc. for a standard OLED display for the vertical organic light emitting transistor 20. The material of the organic EL layer 20c is selected from the above group so that the light emitted to the outside is adjusted to have colors such as red, green, and blue. As another option, the vertical organic light emitting transistor 20 can be configured to emit white light, that is, the same vertical organic light emitting transistor 20 can be configured to selectively emit light of a desired color using a color filter.

[0100] The surface layer 31 is a layer formed on the gate insulating layer 20h for the purpose of fixing the source electrode layer 20s (specifically, the CNT layer). The surface layer 31 can be formed by applying a composition containing a binder resin made of a silane coupling material, an acrylic resin, etc.

[0101] For the oxide semiconductor layer 21a included in the thin film transistor 21, an In-Ga-Zn-O semiconductor, a Zn-O semiconductor (ZnO), an In-Zn-O semiconductor (IZO (registered trademark)), a Zn-Ti-O semiconductor (ZTO), a Cd-Ge-O semiconductor, a Cd-Pb-O semiconductor, cadmium oxide (CdO), a Mg-Zn-O semiconductor, an In-Sn-Zn-O semiconductor (for example, In2O3-SnO2-ZnO), an In-Ga-Sn-O semiconductor, etc. can be used.

[0102] Although the thin film transistor 21 in this embodiment is an oxide semiconductor, the thin film transistor can be made of amorphous silicon. The semiconductor can be p-type or n-type. Any of the configurations including specifically a staggered type, an inverted staggered type, a coplanar type, an inverted coplanar type, etc. can be adopted.

[0103] A bank layer 24 is formed between the organic semiconductor layer 20a and the surface layer 31 for insulation. At the point where the source electrode layer 20s is connected to the data line 11, the bank layer 24 is formed to fill, for example, the gaps provided in the surface layer 31 and the gate insulating layer 20h to allow electrical connection.

[0104] For the vertical organic light emitting transistor 20, the vertical organic light emitting transistor 20 described in the above patent documents 1 and 2 can be used. In addition, the configuration described in patent document 3 can also be adopted.

[0105] The above configuration in which the current supply line 12 is connected by the wiring layer auxiliary line 14a enables the connection point between the current supply line 12 and the wiring layer auxiliary line 14a to have the same voltage value as the connection points of other connected current supply lines 12. That is, in the case of an extreme local voltage drop due to the resistance change of the current supply line 12, the voltage is raised by other current supply lines 12 connected to the wiring layer auxiliary line 14a. As in this embodiment, the more connection points between the current supply line 12 and the wiring layer auxiliary line 14a, the more uniformly the voltage of the current supply line 12 becomes over the display 1.

[0106] In this way, the voltage of the current supply line 12 connected by the wiring layer auxiliary line 14a becomes uniform. Therefore, a display 1 with better display quality is achieved, in which local voltage drops rarely occur in each current supply line 12, making it less likely for display defects to be distinguishable.

[0107] Second Embodiment

[0108] The configuration of the second embodiment of the display 1 of the present invention will be mainly described centering on points different from the first embodiment.

[0109] Figure 6 is a top plan view of a schematic device configuration of the light-emitting portion 10 and its vicinity in an embodiment. Figure 7 is along Figure 6 a cross-sectional view taken along A - A' as shown. As a cross-sectional view taken along A - A' as shown in Figure 6 shows the same configuration as in the first embodiment in Figure 7 shown. Figure 4 is a cross-sectional view taken along B - B as shown. As shown in Figure 8 and Figure 6 in the second embodiment, in addition to the wiring layer auxiliary line 14a, an electrode layer auxiliary line 14b made of the same material as the gate electrode layer 20g of the vertical organic light-emitting transistor 20 is formed in the same layer as the gate electrode layer 20g of the vertical organic light-emitting transistor 20 in parallel with the wiring layer auxiliary line 14a. Figure 6 and Figure 8 Since, as described above, the electrode layer auxiliary line 14b is disposed in the same layer as the gate electrode layer 20g of the vertical organic light-emitting transistor 20, this auxiliary line may not be provided in the region where the vertical organic light-emitting transistor 20 is formed. That is, the electrode layer auxiliary line is formed in a region different from the region where the vertical organic light-emitting transistor 20 exists. However, since the wiring layer auxiliary line 14a and the electrode layer auxiliary line 14b are formed in different layers as shown in

[0110] and Figure 6 in Figure 8 shown, the wiring layer auxiliary line 14a and the electrode layer auxiliary line 14b can overlap in the Z direction.

[0111] That is, such a configuration enables the reduction of the respective resistance values of the two auxiliary lines 14 (14a and 14b) while minimizing the reduction in the size of the light-emitting region. The smaller the resistance of the auxiliary lines 14 (14a and 14b), the smaller the voltage drop caused by the current flowing through the auxiliary lines 14 (14a and 14b), which enables the voltage difference in each current supply line 12 to be reduced more. This further ensures that local voltage drops rarely occur in each current supply line 12 and enables the realization of a display 1 with better display quality.

[0112] Third Embodiment

[0113] The configuration of the third embodiment of the display 1 of the present invention will be mainly described centering on points different from the first embodiment and the second embodiment.

[0114] Although the above description outlines the configuration of providing only the wiring layer auxiliary line 14a and the configuration of providing both the wiring layer auxiliary line 14a and the electrode layer auxiliary line 14b, it is also possible to provide only the electrode layer auxiliary line 14b.

[0115] Fourth Embodiment

[0116] The configuration of the fourth embodiment of the display 1 of the present invention will be mainly described centering on points different from the first embodiment, the second embodiment, and the third embodiment.

[0117] Figure 9 is a top plan view of a schematic device configuration of the light-emitting part 10 and its vicinity in an embodiment. Figure 10 is along Figure 9 the cross-sectional view taken along A-A' shown. As Figure 9 and Figure 10 shown, in the fourth embodiment, the source electrode layer 20s of the vertical organic light-emitting transistor 20 continuously extends between at least two or more pixels so that it substantially serves as the current supply line 12. Additionally, during the manufacturing process of the display 1, after the source electrode layer 20s is formed, additional processing and / or machining (such as chemical doping) can be performed on the source electrode layer 20s so that the conductivity of the source electrode layer 20s can be significantly increased. After the stack layer 24 is formed, another processing and / or machining (such as chemical treatment, heat treatment, and / or ultra-violet (UV) radiation) can be performed on the exposed region of the source electrode layer 20s to reverse the effect of the previous treatment so that the source electrode layer 20s can recover its initial inherent resistivity and electronic characteristics, while the stack layer 24 acts as a mask to maintain the increased conductivity of the source electrode layer 20s covered by it.

[0118] As in the fourth embodiment, the more pixels having the source electrode layer 20s coupled together, the more uniform the voltage in the source electrode layer 20s of the corresponding vertical organic light-emitting transistors 20 becomes over the entire display 1, such that a display 1 is achieved that exhibits almost no visible display defects and exhibits better display quality.

[0119] Although the source electrode layer 20s is described as being continuous between the corresponding vertical organic light-emitting transistors 20 such that no current supply line 12 is provided in the fourth embodiment, the current supply line 12 may also be formed in combination with the configuration of the fourth embodiment.

[0120] Fifth Embodiment

[0121] The configuration of the fifth embodiment of the display 1 of the present invention will be mainly described centering on points different from the first to fourth embodiments.

[0122] The fourth embodiment in which the current supply line 12 is provided may be combined with any one of the configurations of the first to third embodiments, and by such combined use of the measures, the voltage difference in each current supply line 12 can be more reduced compared to the voltage difference in the fourth embodiment. This ensures that local voltage drops rarely occur in each current supply line 12, and enables a display 1 with better display quality to be achieved.

[0123] Other Embodiments

[0124] Other embodiments will be described below.

[0125] <1>The display 1 may be configured to display an image by emitting light output from the organic EL layer 20c to the side opposite to the substrate 30. Such a configuration is referred to as a "top emission type", and has the advantage that it also enables the device and wiring to be configured between the vertical organic light-emitting transistors 20 and the substrate 30.

[0126] <2>The above-described configuration and control method of the display 1 are merely examples, and the present invention is not limited to the various shown configurations.

Claims

1. A display device, comprising: a plurality of vertical organic light-emitting transistors arranged in an array along a first direction and a second direction orthogonal to the first direction; data lines for applying a voltage for controlling gate electrodes of the plurality of vertical organic light-emitting transistors; thin film transistors each connected between the gate electrode of each of the vertical organic light-emitting transistors and the data lines and controlling supply of the voltage to the gate electrodes of the vertical organic light-emitting transistors; gate lines connected to the gate electrodes of the thin film transistors and transmitting signals for controlling the thin film transistors; a plurality of current supply lines extending along the first direction and supplying current to each of a set of vertical organic light-emitting transistors aligned along the first direction; and at least one auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines, the auxiliary line including a wiring formed of a material constituting the gate lines and formed in a layer in which the gate lines are provided.

2. The display device according to claim 1, wherein the auxiliary line is formed closer to the substrate than a source electrode of the vertical organic light-emitting transistor.

3. The display device according to claim 1, wherein the auxiliary line includes a wiring formed of a material constituting the gate electrode of the vertical organic light-emitting transistor and disposed in a layer in which the gate electrode of the vertical organic light-emitting transistor is provided.

4. The display device according to claim 2, wherein the auxiliary line includes a wiring formed of a material constituting the gate electrode of the vertical organic light-emitting transistor and disposed in a layer in which the gate electrode of the vertical organic light-emitting transistor is provided.

5. A display device, comprising: a plurality of vertical organic light-emitting transistors arranged in an array along a first direction and a second direction orthogonal to the first direction; data lines for applying a voltage for controlling gate electrodes of the plurality of vertical organic light-emitting transistors; thin film transistors each connected between the gate electrode of each of the vertical organic light-emitting transistors and the data lines and controlling supply of the voltage to the gate electrodes of the vertical organic light-emitting transistors; and gate lines connected to the gate electrodes of the thin film transistors and transmitting signals for controlling the thin film transistors, wherein at least two of the plurality of vertical organic light-emitting transistors adjacent to each other have a source electrode layer continuously formed therebetween.

6. The display device according to claim 5, further comprising a plurality of current supply lines extending along the first direction and supplying current to each of a set of vertical organic light-emitting transistors aligned along the first direction.

7. The display device according to claim 6, further comprising at least one auxiliary line extending along the second direction and connecting at least two of the plurality of current supply lines.

8. The display device according to claim 7, wherein the auxiliary line is formed closer to the substrate than a source electrode of the vertical organic light-emitting transistor.

9. The display according to claim 7, wherein the auxiliary line includes a wiring line made of a material constituting the gate line and formed in a layer in which the gate line is provided.

10. The display according to claim 7, wherein the auxiliary line includes a wiring line made of a material constituting the gate electrode of the vertical organic light-emitting transistor and disposed in a layer in which the gate electrode of the vertical organic light-emitting transistor is provided.

11. The display according to claim 8, wherein the auxiliary line includes a wiring line made of a material constituting the gate line and formed in a layer in which the gate line is provided.

12. The display according to claim 8, wherein the auxiliary line includes a wiring line made of a material constituting the gate electrode of the vertical organic light-emitting transistor and disposed in a layer in which the gate electrode of the vertical organic light-emitting transistor is provided.

13. The display according to claim 11, wherein the auxiliary line includes a wiring line made of a material constituting the gate electrode of the vertical organic light-emitting transistor and disposed in a layer in which the gate electrode of the vertical organic light-emitting transistor is provided.

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