Reconfigurable system chip compiler and automatic compiling method for information security

Abstract

The application discloses a reconfigurable system chip compiler and an automatic compiling method for information security application, and the method comprises the following steps: firstly, inputting a source program of a cryptographic algorithm; then, performing software compiling function syntax checking on the source program; when the checking result is passed, compiling and mapping are performed by using a compiler; then, a simulator is used to run simulation to execute the cryptographic algorithm, configuration code is generated by using a simulator array, and finally, a binary configuration code file generated by the simulator is used to guide hardware behavior operation. The reconfigurable system chip compiler comprises a source program input module, a software compiling function verification module, a compiling and mapping module, a simulation execution module, a configuration code generation module and a hardware debugging module. By implementing the application, the problems that the existing mapping technology is not mature enough, the algorithm mapping personnel is required to be high, the algorithm mapping time period is long, simulation debugging is difficult and the hardware change is poor in inclusiveness are solved.

Description

Technical Field

[0001] This invention relates to a reconfigurable system-on-a-chip compiler and automatic compilation method for information security applications, belonging to the field of reconfigurable system-on-a-chip compilation technology. Background Technology

[0002] With the development and innovation of information technology, the demand for data processing capabilities in the information explosion era is constantly increasing. Traditional computing methods mainly fall into two categories: ASIC (Application Specific Integrated Circuit), and GPP (General Purpose Processor). Due to its specialized nature and production characteristics, ASIC hardware cannot be changed once it enters production. As the complexity of silicon manufacturing processes continues to increase, the initial investment becomes extremely expensive. Therefore, when ASIC production volume does not reach a certain scale, fully custom ASIC acceleration units can only be adopted by a few computing logic applications with a large number of uses. GPP executes specific computing tasks through instruction sets, modifying the instruction sequence to complete different functional computing tasks without requiring hardware circuit modifications. Therefore, GPP offers excellent flexibility. However, to complete a computing task, GPP needs to read instructions and data from memory, decode and execute them. Each instruction execution incurs significant performance overhead, so GPP performance is generally far inferior to ASIC.

[0003] Coarse-grained Reconfigurable Architecture (CGRA) can essentially be seen as a compromise between the high flexibility of general-purpose processors (GPPs) and the high performance of ASICs, combining time-based and space-based computation. Compared to both GPPs and ASICs, reconfigurable computing systems achieve a trade-off between flexibility, performance, area, and power consumption; however, their complexity also increases application development costs. The goal of reconfigurable compiler systems is to automatically compile applications into reconfigurable computing systems. These systems utilize highly parallel hardware logic units to execute computationally intensive parts of the application, improving application performance and providing hardware support for high-performance computing tasks. They work in conjunction with highly flexible general-purpose processors (GPPs) to complete computational tasks. Furthermore, with the development of information technology, the computational complexity of reconfigurable architecture applications is increasing exponentially, especially in computationally intensive cryptographic algorithms. Manually deploying applications to reconfigurable computing platforms has become impractical. Therefore, researching how to improve the automated mapping of reconfigurable compilers for information security is crucial and has become a research hotspot in the field of reconfigurable computing in recent years.

[0004] A reconfigurable processor compiler system is a software system that translates application behavior described by users in a high-level language into functionally equivalent binary machine code that can be recognized by the target hardware. The most important metric for a compiler is correctness, ensuring that the source program can be executed correctly on the hardware. In addition, a good CGRA compiler system should also possess the following characteristics:

[0005] 1) Easy to program: This means providing users with a good upper-level programming interface without exposing too many underlying hardware features. Programmers can implement application functions without understanding the hardware, which can improve programmers' productivity and shorten the algorithm development cycle.

[0006] 2) Develop more parallelism: CGRA provides a wealth of computing units that can perform parallel computing in the time and space domains. The compiler needs to effectively tap the hardware potential and the parallel space of the source program to accelerate the execution of the source program and improve the utilization of hardware resources.

[0007] 3) Short compilation time: Obviously, the lower the compilation time overhead, the better. In some applications that require dynamic hardware reconfiguration, the compilation time requirements are even more stringent. In short, the compiler should provide users with a more convenient, faster, and more efficient way to use the hardware resources in the chip.

[0008] Against this backdrop, the design of compilers for reconfigurable cryptographic chips for information security has become a hot research topic. While existing compiler tools for reconfigurable chips based on cryptographic algorithms have been optimized to some extent, differences in algorithm mapping time and performance exist in practical applications due to varying levels of understanding of hardware structure and algorithm protocols among algorithm developers. Summary of the Invention

[0009] The technical problem to be solved by this invention is: to propose a simplified automated mapping process for reconfigurable system chip compilers oriented towards information security, in view of the above-mentioned prior art, to solve the problems of high requirements for algorithm mapping personnel, long algorithm mapping time cycle, difficulty in simulation debugging, and poor tolerance to hardware changes when the existing mapping technology is not mature enough.

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0011] This invention first proposes an automatic compilation method for a reconfigurable system-on-a-chip compiler oriented towards information security, comprising:

[0012] S1. Input cryptographic algorithm source code: The source code file is described by a high-level language with special markings designed based on the characteristics of the cryptographic algorithm;

[0013] S2. Execute the software compilation function syntax check of the source program: Perform functional verification on the input algorithm description language, simulate the execution behavior of the hardware, and verify whether the function is correct. If it is, proceed to the next step; otherwise, return to the previous step.

[0014] S3. Perform compiler compilation mapping: Compile the source files that have been functionally verified to obtain a data flow graph with data dependencies through the compiler;

[0015] S4. Simulate and execute cryptographic algorithms using a simulator: Execute the data flow graph with data dependencies generated by the compiler to obtain simulation results;

[0016] S5. Generate configuration code from simulator array: Map the array with correct execution results to generate a binary language file that the hardware can recognize and execute.

[0017] S6. Perform hardware debugging: Use the binary configuration code file generated by the emulator to guide hardware behavior.

[0018] Furthermore, in the automatic compilation method of the reconfigurable system chip compiler proposed in this invention, step S1 uses a high-level C language with tags to describe the cryptographic algorithm, which supports up to two nested For loops and does not support irregular loops including while loops. The special basic function unit BFU, the search unit SBOX, and the bit permutation unit BENES operator functions are used for programming.

[0019] Furthermore, in the automatic compilation method of the reconfigurable system chip compiler proposed in this invention, step S2, simulating the execution behavior of hardware includes the execution rules and execution scheme of hardware circuit logic, including the function writing of the basic functional unit BFU operator programming function, the lookup unit SBOX operator programming function, and the bit permutation unit BENES operator programming function, which are consistent with the hardware circuit description.

[0020] Furthermore, the automatic compilation method of the reconfigurable system-on-a-chip compiler proposed in this invention, with its BFU operator programming function, can perform a variety of operations, which conforms to the characteristics of computationally intensive cryptographic algorithms.

[0021] Furthermore, the automatic compilation method of the reconfigurable system-on-a-chip compiler proposed in this invention enables the BFU operator programming function to implement addition (AU), logic operation (LU), shift operation (SU), and multiplication operation (MU). Each BFU unit has three 32-bit inputs and two 32-bit outputs. The three inputs of the BFU are named A, B, and T, and the outputs are named X and Y, where X is the result output and Y is the bypass output.

[0022] Furthermore, the automatic compilation method of the reconfigurable system chip compiler proposed in this invention has four SBOXes in a reconfigurable configuration line, each SBOX has four lookup tables, and each lookup table is divided into upper and lower sub-lookup tables. Different sub-lookup tables are selected to search according to different configurations. At the same time, SBOXes have different search modes to implement different search functions.

[0023] Furthermore, the automatic compilation method of the reconfigurable system chip compiler proposed in this invention takes four 32-bit operands as input to the BENES operator programming function and outputs four 32-bit data, realizing arbitrary bit permutation of 128-bit data. Each reconfigurable configuration line contains one 128-bit BENES for nonlinear bit permutation.

[0024] Furthermore, in the automatic compilation method of the reconfigurable system chip compiler proposed in this invention, in step S4, the simulator translates the mapping graph with data dependencies generated by the verified source program into a graphical interface and generates binary machine code that can be recognized by the target hardware for use by the hardware.

[0025] To address the technical problems, this invention also proposes a reconfigurable system-on-a-chip compiler for information security, comprising:

[0026] The source code input module is configured to: describe the source code file using a high-level language with special tags designed based on the characteristics of cryptographic algorithms;

[0027] The software compilation function verification module is configured to: perform function verification on the input algorithm description language, simulate the execution behavior of the hardware, and verify whether the function is correct.

[0028] The compilation mapping module is configured to: compile source files that have been functionally verified to obtain a data flow graph with data dependencies through the compiler;

[0029] The simulation execution module is configured to: execute the data flow graph with data dependencies generated by the compiler to obtain simulation results;

[0030] The configuration code generation module is configured to: generate binary language files that can be recognized and executed by the hardware from array mappings with correct execution results;

[0031] The hardware debugging module is configured to use binary configuration code files generated by the emulator to guide hardware behavior.

[0032] Furthermore, the reconfigurable system-on-a-chip compiler for information security proposed in this invention includes a software compilation function verification module comprising an input / output FIFO module, a shift-enabled SREG memory unit module, an IMD immediate value memory unit, a MEM data cache module, a BFU operator calculation module, an SBOX nonlinear lookup table unit, and execution functions for a BENES bit permutation unit module; wherein...

[0033] The input and output FIFO modules are as follows: the input FIFO module receives 128-bit wide data, stores it in internal memory, and updates the data after the operator reads the data from the interface; the output FIFO module receives the output data from the computation operator.

[0034] IMD (Immediate Data Unit) is used to store configuration data.

[0035] The SREG storage unit module with shift capability is used for caching and shift calculations in intermediate processes;

[0036] The MEM data cache module is used to store initialization data and cached data during intermediate processes.

[0037] The BFU operator computation module is configured to implement addition (AU), logic operation (LU), shift operation (SU), and multiplication operation (MU). Each BFU unit has three 32-bit inputs and two 32-bit outputs. The three inputs of the BFU are named A, B, and T, and the outputs are named X and Y, where X is the result output and Y is the bypass output.

[0038] The SBOX nonlinear lookup table unit is configured to select different sub-lookup tables according to different configurations and to implement different lookup functions according to different lookup modes;

[0039] The execution function of the BENES bit permutation unit module is configured to take four 32-bit operands as input and output four 32-bit data, realizing arbitrary bit permutation of 128-bit data. Each reconfigurable configuration line contains one 128-bit BENES for non-linear bit permutation.

[0040] Compared with the prior art, the present invention, by adopting the above technical solution, has the following beneficial effects:

[0041] 1. This invention solves the problem of high requirements for algorithm mapping personnel. Compared with the traditional automated mapping process of reconfigurable compilers, this invention has lower requirements for algorithm mapping personnel. At the same time, software compilation and debugging is more flexible than hardware simulation and operation.

[0042] 2. Compared with the traditional automated mapping process of reconfigurable compilers, this invention solves the problem of time wasted in the process of writing cryptographic algorithm source code, which is caused by users' lack of understanding of the algorithm and lack of experience in writing software code, resulting in syntax and functional errors, and thus requiring repeated mapping simulation and debugging.

[0043] 3. Compared with the traditional automated mapping process of reconfigurable compilers, this invention can display the intermediate data of the algorithm implementation process on the operator port during the software pre-compilation process. This effect provides standard data for subsequent hardware simulation debugging and data flow updates.

[0044] 4. Compared to the traditional automated mapping process of reconfigurable compilers, the software debugging process is relatively simple. At the same time, during the debugging of source code, the results of each cycle can be viewed, that is, the data of each cycle on the hardware interface or data buffer.

[0045] 5. Compared to the traditional automated mapping process of reconfigurable compilers, the software's debugging process does not require attention to mapping schemes, operator mapping layouts, and interconnections, which greatly reduces the requirements for algorithm developers and further shortens the development cycle. Attached Figure Description

[0046] Figure 1 A flowchart for compiling automated mappings for traditional reconfigurable architectures.

[0047] Figure 2 This is a flowchart illustrating the automated mapping process for the reconfigurable architecture compilation of this invention.

[0048] Figure 3 This is a schematic diagram of the structure of the BFU calculation module of the present invention.

[0049] Figure 4 This is a representation of the SBOX lookup in this invention.

[0050] Figure 5 This is a schematic diagram of the BENES128bit of the present invention.

[0051] Figure 6 This is a schematic diagram of the built-in function modules included in the software compilation environment of this invention. Detailed Implementation

[0052] The specific embodiments of the present invention will be further explained below with reference to the accompanying drawings. The following examples are only used to more clearly illustrate the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0053] This invention discloses a simplified process design for a reconfigurable system-on-a-chip (SoC) compilation framework for information security. Its flexibility lies in the user's ability to configure the hardware's computing functions, and its high performance stems from the use of hardware parallel computing. Furthermore, the configuration scheme often becomes crucial in influencing computing performance when implementing a specific computing function. To address the drawbacks of long manual configuration times, unstable results, and poor hardware compatibility, reconfigurable processors typically shorten the development cycle of reconfigurable systems by using customized high-level languages ​​as input. This reduces the need for users to have a high level of hardware expertise and allows for a more optimized mapping of various computing function units onto the reconfigurable processor, making it an indispensable part of reconfigurable systems.

[0054] Traditional compiler mapping and debugging schemes involve compiling high-level languages ​​into simulators for debugging. This process cannot guarantee the correctness of the syntax and functionality of the source code. Furthermore, the simulator debugging process is very time-consuming and labor-intensive, and without intermediate results, it is difficult to correct errors. To address this issue, this invention proposes a software compilation and execution scheme to further accelerate the reconfigurable automated mapping process and further reduce the requirements for hardware proficiency.

[0055] like Figure 1 As shown in the flowchart of the traditional reconfigurable architecture compilation automation mapping process, the user first writes hardware-related high-level language representations through algorithm protocols, then compiles the written source program with a compiler, then simulates the compiled data flow graph with certain data dependencies using a simulator, and finally generates configuration code from the mapping graph with correct simulation results for use by the hardware. In this process, if there are any minor modifications to the written source program, the above steps need to be repeated, which is a time-consuming and labor-intensive process.

[0056] Therefore, to further save time and reduce the requirements for algorithm mapping personnel, this invention proposes a pre-compilation checking module for reconfigurable automated compilation mapping based on cryptographic algorithms; such as Figure 2 As shown, the correctness of the written cryptographic algorithm is ensured by adding a pre-compilation process for the source code. Software compilation is highly flexible and can save a lot of debugging time for compiler simulators. First, the user writes hardware-related high-level language according to the algorithm protocol. In this process, the user may not have a sufficient understanding of the protocol and hardware structure, resulting in many problems and errors during the writing process. By adding this process, it can be ensured that the cryptographic algorithm source program is correctly executed before the compiler compiles it. The correctly compiled mapping can be directly simulated by the simulator to generate configuration code for use by the hardware.

[0057] The software compilation function verification module environment setup includes a hardware execution logic scheme, comprising execution functions for the input / output FIFO module, the SREG memory unit module with shift function, the IMD immediate value memory unit, the MEM data cache module, the BFU operator calculation module, the SBOX nonlinear lookup table unit, and the BENES bit permutation unit module. After a cryptographic algorithm is written, these functions are called for software execution to simulate the calculation results in advance. The software debugging has a certain degree of versatility and flexibility; input / output results and intermediate process results can be printed out to view the data generation on the hardware interface, further shortening the algorithm development cycle while ensuring correct algorithm mapping.

[0058] like Figure 3 The diagram shows a basic function unit (BFU) module. It has three 32-bit inputs and two 32-bit outputs, represented by A, B, T, X, and Y respectively. It can perform addition (AU), logical operations (LU), shift operations (SU), and multiplication (MU). A reconfigurable row computation unit contains eight BFUs. The logical operations it can perform include AND, OR, XOR, and any combination of three inputs; the shift operations it can perform include logical left shift, logical right shift, circular left shift, and circular right shift; and the addition operations it can perform include selectable parallel 4-way modulo-2 operations. 8 Addition, Parallel 2-way Modulo 2 16 Addition, modulo 2 32 Addition, modulo 2 32 It supports addition with carry, performing the operation X=A+B+T, where the 0th bit of T is valid in 32-bit addition mode; the multiplication operations that can be implemented include 16-bit multiplication, X[31:0] = A[15:0]* B[15:0], and 8-bit multiplication, X[31:0] = {8'b0, A[7:0]} *{8'b0, B[7:0]}; the logic functions that implement these functions are represented in the pre-compiled verification environment, and the correctness of the functions will be further verified by software compilation of the source program, which can shorten the time significantly compared to hardware debugging and software debugging.

[0059] like Figure 4As shown, the SBOX, as a non-linear lookup unit, has four SBOXes within a reconfigurable configuration row. Each SBOX contains four lookup tables. To maximize the use of lookup table resources, each lookup table is divided into upper and lower sub-lookup tables. Different sub-lookup tables are selected for lookup based on different configurations. Furthermore, the SBOX has different modes to implement different lookup functions. Within the software compilation framework, built-in functions for the SBOX are written, and the lookup table resource files used by each cryptographic algorithm are added. The lookup operations can then be performed according to certain rules through function calls.

[0060] like Figure 5 The BENES operator shown is used to implement nonlinear bit permutation functionality. One BENES is contained within a reconfigurable configurable row computation unit. The BENES takes four 32-bit operands as input and outputs four 32-bit data, enabling arbitrary bit permutations of 128-bit data. Within the software compilation framework, built-in functions for BENES are written, and resource files for the permutation units used by various cryptographic algorithms are added. Bit permutation operations can be performed according to certain rules through function calls.

[0061] Embodiments of the present invention also provide a reconfigurable system-on-a-chip compiler for information security, comprising:

[0062] The source code input module is configured to: describe the source code file using a high-level language with special tags designed based on the characteristics of cryptographic algorithms;

[0063] The software compilation function verification module is configured to: perform function verification on the input algorithm description language, simulate the execution behavior of the hardware, and verify whether the function is correct.

[0064] The compilation mapping module is configured to: compile source files that have been functionally verified to obtain a data flow graph with data dependencies through the compiler;

[0065] The simulation execution module is configured to: execute the data flow graph with data dependencies generated by the compiler to obtain simulation results;

[0066] The configuration code generation module is configured to: generate binary language files that can be recognized and executed by the hardware from array mappings with correct execution results;

[0067] The hardware debugging module is configured to use binary configuration code files generated by the emulator to guide hardware behavior.

[0068] like Figure 6The software compilation environment shown includes built-in function modules, including the basic computation unit module BFU, which can perform addition, arithmetic logic operations, shift operations, and multiplication; the lookup table unit SBOX, which implements more complex nonlinear operations; the BENES unit, which performs single-bit permutation; the storage unit module MEM, which stores initialization data and cached data for intermediate processes; the cache unit SREG, which has shift functionality, for caching and shifting calculations during intermediate processes; the input storage unit IFIFO; the output storage unit OFIFFO; and the LFSR module, which allows for fine-grained shifting. These functional modules are implemented according to hardware logic in the software compilation environment. The source code written by the algorithm developers is simulated and executed to verify the correctness of its functionality. Simultaneously, the results of intermediate processes can be viewed, further shortening the algorithm development cycle.

[0069] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An automatic compilation method for a reconfigurable system-on-a-chip compiler oriented towards information security, characterized in that, include: S1. Input cryptographic algorithm source code: The source code file is described by a high-level language with special markings designed based on the characteristics of the cryptographic algorithm; S2. Software compilation syntax check of the source program: Perform functional verification on the input algorithm description language, simulate hardware execution behavior, and verify whether the function is correct. If correct, proceed to the next step; otherwise, return to the previous step. The simulated hardware execution behavior includes the execution rules and execution scheme of the hardware circuit logic, including the programming functions of the basic functional unit BFU operator, the lookup unit SBOX operator, and the bit substitution unit BENES operator, which are consistent with the hardware circuit description. There are four SBOXes in a reconfigurable configuration row. Each SBOX has four lookup tables. Each lookup table is divided into upper and lower sub-lookup tables. Different sub-lookup tables are selected to search according to different configurations. At the same time, SBOXes have different search modes to implement different search functions. S3. Perform compiler compilation mapping: Compile the source files that have been functionally verified to obtain a data flow graph with data dependencies through the compiler; S4. Simulate and execute cryptographic algorithms using a simulator: Execute the data flow graph with data dependencies generated by the compiler to obtain simulation results; S5. Generate configuration code from simulator array: Map the array with correct execution results to generate a binary language file that the hardware can recognize and execute. S6. Perform hardware debugging: Use the binary configuration code file generated by the emulator to guide hardware behavior.

2. The automatic compilation method for a reconfigurable system-on-a-chip compiler according to claim 1, characterized in that, In step S1, the cryptographic algorithm is described using a high-level C language with labels. It supports up to two nested For loops and does not support irregular loops including while loops. The special basic function unit BFU, the search unit SBOX, and the bit permutation unit BENES operator functions are used for programming.

3. The automatic compilation method for a reconfigurable system-on-a-chip compiler according to claim 1, characterized in that, BFU operator programming functions can perform a variety of operations, which is consistent with the characteristics of computationally intensive cryptographic algorithms.

4. The automatic compilation method for a reconfigurable system-on-a-chip compiler according to claim 3, characterized in that, The BFU operator programming function can implement addition (AU), logical operation (LU), shift operation (SU), and multiplication operation (MU). Each BFU unit has three 32-bit inputs and two 32-bit outputs. The three inputs of the BFU are named A, B, and T, and the outputs are named X and Y, where X is the result output and Y is the bypass output.

5. The automatic compilation method for a reconfigurable system-on-a-chip compiler according to claim 1, characterized in that, The BENES operator programming function takes four 32-bit operands as input and outputs four 32-bit data, enabling arbitrary bit permutations of 128-bit data. Each reconfigurable configuration line contains one 128-bit BENES for non-linear bit permutations.

6. The automatic compilation method for a reconfigurable system-on-a-chip compiler according to claim 1, characterized in that, In step S4, the simulator translates the mapping graph with data dependencies generated by the verified source program into a graphical interface and generates binary machine code that can be recognized by the target hardware for use by the hardware.

7. A reconfigurable system-on-a-chip compiler for information security, characterized in that, include: The source code input module is configured to: describe the source code file using a high-level language with special tags designed based on the characteristics of cryptographic algorithms; The software compilation function verification module is configured to: perform function verification on the input algorithm description language, simulate the execution behavior of the hardware, and verify whether the function is correct. The compilation mapping module is configured to: compile source files that have been functionally verified to obtain a data flow graph with data dependencies through the compiler; The simulation execution module is configured to: execute the data flow graph with data dependencies generated by the compiler to obtain simulation results; The configuration code generation module is configured to: generate binary language files that can be recognized and executed by the hardware from array mappings with correct execution results; The hardware debugging module is configured to: use binary configuration code files generated by the emulator to guide hardware behavior. The software compilation function verification module includes execution functions for an input / output FIFO module, an IMD immediate value storage unit, an SREG storage unit module with shift function, a MEM data cache module, a BFU operator calculation module, an SBOX nonlinear lookup table unit, and a BENES bit permutation unit module. The input and output FIFO modules are as follows: the input FIFO module receives 128-bit wide data, stores it in internal memory, and updates the data after the operator reads data from the interface; the output FIFO module receives output data from the computation operator. IMD (Immediate Data Unit) is used to store configuration data; The SREG storage unit module with shift capability is used for caching and shift calculations in intermediate processes; The MEM data cache module is used to store initialization data and cached data during intermediate processes. The BFU operator computation module is configured to implement addition (AU), logic operation (LU), shift operation (SU), and multiplication operation (MU). Each BFU unit has three 32-bit inputs and two 32-bit outputs. The three inputs of the BFU are named A, B, and T, and the outputs are named X and Y, where X is the result output and Y is the bypass output. The SBOX nonlinear lookup table unit is configured to select different sub-lookup tables according to different configurations and to implement different lookup functions according to different lookup modes; The execution function of the BENES bit permutation unit module is configured to take four 32-bit operands as input and output four 32-bit data, realizing arbitrary bit permutation of 128-bit data. Each reconfigurable configuration line contains one 128-bit BENES for non-linear bit permutation.

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