Method and system for implementing audio out switching for power supplies

Abstract

A power converter (100) comprises a watchdog circuit (104) having an input adapted to be coupled to a pause signal of a switching power supply. The watchdog circuit (104) is configured to provide an enable signal at its output based on the pause signal indicating that the power converter (100) has stopped switching for a threshold duration that is less than an audible range. A pulse generator circuit (110) has an input coupled to the output of the watchdog circuit and is configured to generate at least one pulse based on the enable signal. A switching circuit (114) has an input terminal adapted to be coupled to an input voltage and at least one other terminal adapted to be coupled to an inductor (116). The switching circuit (114) is configured to provide a negative current from an output (120) of the power converter through the at least one other terminal based on the at least one pulse.

Description

Technical Field

[0001] This disclosure generally relates to implementing external audio switching for power supply. Background Technology

[0002] Examples of power supply circuits include any of synchronous rectifier power converters, asynchronous rectifier power converters, resonant power converters, and a variety of other types of switching power converters. Power converters and power supply devices typically operate in power-saving modes, such as when little or no load is applied to the output. In these cases, the switching device may operate in bursts of switching activity, separated by periods when the device is not switching. If the repetition rate of such bursts exceeds a certain duration (e.g., audio duration), the switching bursts may become audible, which is undesirable in many applications. Summary of the Invention

[0003] One example includes a power converter comprising a watchdog circuit having an input suitable for coupling to a pause signal of a switching power supply. The watchdog circuit is configured to provide a start signal at its output based on the pause signal, the pause signal indicating that the power converter has stopped switching for a duration less than an audible threshold. A pulse generator circuit has an input coupled to the output of the watchdog circuit and is configured to generate at least one pulse based on the start signal. A switching circuit has an input suitable for coupling to an input voltage and at least one other terminal suitable for coupling to an inductor. The switching circuit is configured to provide a negative current from the output of the power converter through at least one other terminal based on at least one pulse.

[0004] Another example provides a system including a switching circuit having an input terminal and an output terminal. The input terminal is coupled to an input voltage of the system, and the output terminal is coupled to an output voltage of the system. A main control loop circuit is configured to control the switching circuit in pulse width modulation (PWM) mode to regulate the output voltage relative to a target voltage. An auxiliary control loop circuit is configured to control the switching circuit to provide a negative current in response to skip mode operation when switching is paused for a threshold duration less than the duration of operation of the switching circuit within the audible range. The negative current flows from the output terminal through an inductor to discharge the output voltage. The main control loop circuit is configured to transition from skip mode to PWM mode based on the output voltage and the target voltage to maintain the operation of the switching circuit outside the audible range.

[0005] As another example, a method includes receiving a pause signal having a state indicating operation in a skip mode, in which the switching circuitry of a power converter has stopped switching in pulse width modulation (PWM) mode. The method includes providing a start signal based on the pause signal in response to detecting that the switching circuitry has stopped switching for a threshold duration. The method includes generating at least one pulse during the skip mode based on the start signal. The method includes providing a negative current from the output of the power converter through an inductor based on the at least one pulse. The method includes discharging an output voltage at the output of the power converter based on the burst of the negative current. The method includes transitioning from the skip mode to the PWM mode based on the output voltage and a target voltage to maintain the operation of the switching circuitry outside the audible range. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example control loop for this audio switching.

[0007] Figure 2 The diagram illustrates methods for reducing external audio switching. Figure 1 The signal diagram for the operation of the control loop.

[0008] Figure 3 This is another example of a control loop used to implement external audio switching.

[0009] Figure 4 It is used for Figure 3 Signal diagram of the control loop.

[0010] Figure 5A An example of a buck-boost converter is depicted.

[0011] Figure 5B This demonstrates the switching during audio external switching. Figure 5A The graph shows the negative inductor current applied by the converter.

[0012] Figure 6 A signal diagram illustrating an example of the control signals used to operate a buck-boost converter is shown.

[0013] Figure 7A An example of a buck converter is depicted.

[0014] Figure 7B This demonstrates the switching during audio external switching. Figure 7A The graph shows the negative inductor current applied by the converter.

[0015] Figure 8 The diagram illustrates the switching between audio and video. Figure 7A The signal diagram of the control signals associated with the circuit.

[0016] Figure 9The diagram illustrates the switching between audio and video. Figure 7A Another signal diagram showing the control signals associated with the buck converter.

[0017] Figure 10 This is a signal diagram illustrating an example of the signals associated with the operation of a boost converter used to perform external audio switching.

[0018] Figure 11 An example of a watchdog circuit is depicted.

[0019] Figure 12 An example of a pulse generator is depicted.

[0020] Figure 13 It can be used for implementation Figure 12 Example circuits for turning on or off time generators.

[0021] Figure 14 Examples of gate driver circuitry and switches for converters such as buck-boost converters are depicted.

[0022] Figure 15 An example of an integrated circuit for a power converter that can implement external audio control is depicted.

[0023] Figure 16 This is a flowchart illustrating an example method of operating a power converter in the audio range. Detailed Implementation

[0024] This disclosure relates to an audio external control scheme for a power converter, such as a switching power supply. The audio external control is configured to enable switching in bursts that occur intermittently at time intervals beyond the audible range. For example, the audio external switching control loop is configured to provide a negative current burst (e.g., one or more negative current pulses) through an inductor during a skip mode where the device is not switching. The negative current flows through the inductor from the output of the power converter to discharge the output voltage based on the negative current. This induced discharge of the output voltage allows the skip mode where the device is not switching to exit naturally without prematurely forcing a pulse width modulation (PWM) operating mode to maintain audio external operation. That is, the negative inductor current discharges the output voltage to cause a natural transition from the skip mode to the active switching mode by the main control loop, thereby regulating the output voltage based on the output voltage dropping below a target voltage. Because the output voltage discharges in this way, the control also prevents net positive energy from accumulating on the output capacitor at the output of the converter, which avoids runaway that may occur in other methods of implementing audio external operation in a forced PWM mode.

[0025] As an example, a power converter (e.g., a buck converter, boost converter, or buck-boost converter) includes a main control loop configured to regulate the output voltage to a target voltage. The power converter also includes an external audio control loop configured to provide a burst of negative current to discharge the output voltage through an inductor at a frequency outside the audible range. For example, the external audio control loop includes a watchdog circuit having an input adapted to receive a pause signal from the power converter. For example, the pause signal is set high when the converter switching circuit has stopped switching and is operating in skip mode and is set low during PWM operation mode switching. The watchdog circuit monitors the skip duration (e.g., starting when the pause signal is asserted) to ensure that the burst switching frequency remains outside the audible range, such as a frequency of at least about 20 kHz (corresponding to a time period of 50 microseconds or less). In response to the watchdog circuit detecting that the pause signal is high for a threshold duration (e.g., about 40 microseconds or less), the watchdog circuit provides a start signal. A pulse generator circuit is configured to generate one or more pulses based on the start signal. One or more pulses are used to generate a burst of negative current to discharge the output voltage. For example, a pulse generator provides one or more pulses to a driver circuit configured to control a converter switching circuit to provide negative current through an inductor.

[0026] In the example where the switching circuit is implemented by a field-effect transistor (FET), when the switch opens after a negative burst through the inductor, the negative current automatically returns to the input voltage through the back-gate diode of the corresponding FET. When the output voltage is lower than the target voltage, the main control loop of the power converter enters PWM mode to control the switching circuit (via PWM switching) to regulate the output voltage relative to the target voltage. The main control loop terminates the switching of the switching circuit based on the output voltage being regulated, and the power converter re-enters skip mode, where the pause signal becomes high. This control process, implemented by the main control loop and the auxiliary control loop during low-load or no-load conditions, can be implemented to keep periodic switching bursts outside the audible range.

[0027] Advantageously, because the external audio control circuit applies a negative current burst to discharge the output voltage before providing a positive pulse, the external audio control circuit ensures that the output voltage does not run away from control, such as by repeatedly charging the output capacitor. Furthermore, because energy is first inductively discharged from the output voltage and returned to the input voltage, the method disclosed herein can operate with increased power efficiency compared to many existing methods. For example, one existing method is to maintain the nominal load on the output during power-saving modes (e.g., when a low or no external load is applied). However, this method results in continuous energy dissipation. Another existing method is to force switching at a fixed rate, which may exceed the audible range. However, this other existing method can lead to runaway, as forced switching can cause the output voltage to increase significantly above the target voltage.

[0028] As used herein, the term "circuit" can include a collection of active and / or passive components that perform circuit functions, such as analog and / or digital circuits. Additionally or alternatively, for example, the term "circuit" can include an integrated circuit (IC) in which all or some of the circuit elements are fabricated on a common substrate (e.g., a semiconductor substrate, such as a die or chip) or within a common package as described herein. For example, the circuitry of a power converter (e.g., control loops, switching circuits, drivers, etc.) can be implemented in an IC chip.

[0029] Furthermore, the term "couple" is used throughout the specification. This term can encompass connection, communication, or signaling paths that achieve a functional relationship consistent with the description of this disclosure. For example, in a first example, if device A generates a signal to control device B to perform an action, then device A is coupled to device B via intervention component C; or in a second example, if intervention component C substantially does not alter the functional relationship between device A and device B such that device B is controlled by device A via a control signal generated by device A, then device A is coupled to device B via intervention component C.

[0030] Figure 1 This is a block diagram of a power converter 100 including an auxiliary control loop 102 configured to implement audio external control for the power converter. The auxiliary control loop 102 can be implemented using analog circuitry, digital circuitry, or a combination of analog and digital circuitry. The power converter 100 also includes a main control loop 103 configured to adjust the output voltage VOUT of the power converter according to a target voltage. While the auxiliary control loop 102 is... Figure 1 In this example, the auxiliary control loop 102 is shown to be separate from the main control loop 103, but in another example, the auxiliary control loop 102 may be part of the main control loop 103 (e.g., integrated into the main control loop 103).

[0031] exist Figure 1In the example, auxiliary control loop 102 includes a watchdog circuit 104 having an input 106 adapted to receive a pause signal from power converter 100. For example, the pause signal is a binary signal generated by the main control loop 103 of power converter 100, indicating that the associated switching circuit 114 has stopped switching and converter 100 is operating in a skip mode (e.g., in a non-switching, skipped state). The skip mode corresponds to a duration during which the power switch of switching circuit 114 is deactivated. When the switch is deactivated during skip mode, such as during light load or no load conditions, the magnitude of the output voltage VOUT is set based on the output capacitor coupled to output terminal 120. In one example, the pause signal is high during skip mode and low during switching (PWM) mode. The PWM mode corresponds to the sequential on-time and off-time of the power switch of switching circuit 114, such as supplying current to output terminal 120 during normal load operation of power converter 100. If left unattended, the charge held by the output capacitor may discharge due to light load or through leakage. Watchdog circuit 104 is configured to provide a start signal at 108 in response to detecting that a pause signal has been high for a threshold duration (e.g., corresponding to operation in skip mode). As an example, the threshold duration (which may be fixed or programmable) for triggering a negative current burst is set sufficiently to enable auxiliary control loop 102 to control power converter 100 at frequencies outside the audible range for a period of time (e.g., 40 microseconds or longer).

[0032] exist Figure 1 In the example, watchdog circuit 104 is configured to provide a start signal at output 108 to instruct pulse generator circuit 110 to initiate a burst. Therefore, the start signal at 108 is utilized to force the switching of switch circuit 114 to be disabled in an alternative manner during skip mode. Pulse generator circuit 110 is configured to generate one or more pulses in response to the start signal from watchdog circuit 104. In one example, pulse generator 110 is configured to provide a fixed number of one or more pulses based on the start signal. In another example, pulse generator is configured to provide a variable number of pulses based on the start signal. The number of pulses can be varied according to the level of the output voltage at the time the start signal occurs. Alternatively, the number of pulses can be programmed in response to user input (e.g., by storing the value in a register). As another example, pulse generator is configured to control the number and / or width of pulses based on the output voltage VOUT of the power supply relative to the target output voltage. For example, the difference between the output voltage and the target voltage (e.g., corresponding to an error signal) can be utilized to control the pulses provided for each time period of skip mode.

[0033] As in Figure 1As shown in the example, a pulse generator provides one or more pulses to driver circuit 112. Driver circuit 112 has an output coupled to the control input of each corresponding switching device of switching circuit 114. Switching circuit 114 may include any number of N switching devices (e.g., field-effect transistors or bipolar transistors) depending on the type of power converter being implemented. The switching circuit 114 of power converter 100 includes components electrically coupled to the input voltage V. IN The input terminal 118 and the output terminal 120 are coupled to the output voltage VOUT. Inductor 116 is also coupled to the switching circuit 114, as through one or more inductor terminals 122. Switching circuit 114 is connected to VOUT. IN The specific arrangement and connection between VOUT and inductor 116 can vary depending on the type of power converter being implemented.

[0034] Switching circuit 114 is configured to provide a burst of negative current from output 120 through terminal 122 and inductor 116 based on one or more pulses provided by pulse generator at 111. The negative current burst inductively discharges the output voltage VOUT until the output drops below a threshold, and main control loop 103 resumes operation of power converter 100. For example, main control loop 103 may provide a control signal to driver circuit 112 to operate switching circuit 114 to provide positive current from input 118 to output 120 through inductor 116 to increase the output voltage according to a target voltage. The control method can be a forced PWM mode or a ramp PWM mode, which can be changed according to the applied requirements.

[0035] By triggering the pulse generator 110 to cause the switching circuit 114 to provide a negative burst at a frequency outside the audible range of the power converter, the power converter can operate in an audio manner that is unlikely to distract the user in any other way. The provided negative current further improves energy efficiency compared to existing methods such as those disclosed herein, and eliminates the need for periodically forced PWM to achieve audio-outside operation.

[0036] Figure 2 It is a display Figure 1 Example signal diagram 200 of the signal in the power converter 100. Signal diagram 200 includes signals transmitted through... Figure 1 The current in inductor 116 and terminal 122 corresponds to the inductor current 202. Figure 2 A start signal 204 corresponding to the signal at output 108 of the watchdog circuit 104 is also shown. Signal diagram 200 also depicts a pause signal 206. (As shown...) Figure 2As shown in the example, in response to the start signal 204 going high (e.g., at t1 and t4), a negative burst of inductor current 208 (e.g., through inductor 116) is provided in response to a series of pulses (e.g., pulse 111 provided by pulse generator 110). The negative burst of inductor current 208 has a duration shown at tneg. As disclosed herein, the negative burst of inductor current 208 causes a decrease in output voltage. In response to reducing the output voltage below a target voltage, pause signal 206 goes low as shown at 210 (at time t2). At this time t2, since the output voltage has decreased below the target voltage, the main control loop takes over the power converter, such as by entering PWM mode and providing a positive burst of inductor current shown at 212, until the output voltage is regulated (at time t3) and switching stops. When switching stops (at time t3), the pause signal continues, shown at 216.

[0037] By way of example, the transition between the negative burst 208 and the subsequent burst of the positive inductor current 212 (e.g., at time t2) can be controlled by a main control loop that regulates the output voltage in PWM mode. Therefore, the positive inductor current 212 increases the output voltage by accumulating charge in the output capacitor (e.g., coupled to output terminal 120) based on a control loop that regulates the output voltage VOUT to the target voltage. When the output voltage VOUT has been regulated to the desired target, the start signal 204 goes low, as indicated at 214, and the pause signal 206 goes high at 216. For example, in response to the pause signal going high at 216, the watchdog circuit 104 activates a timer to ensure that switching does not stop for a period exceeding an audible time period (e.g., approximately 50 microseconds or longer). In this way, the auxiliary control loop 102 operates to ensure that the time period between switching bursts 218 is less than a threshold duration, which, if exceeded, could lead to audible switching of the power converter. As disclosed herein, the negative burst at the beginning of each burst cycle ensures that the output voltage VOUT does not run away to accumulate charge on the output capacitor. Because the negative burst discharges the output voltage, the method disclosed in this paper also allows the main control loop to exit the skip mode naturally without forcing the converter into a forced PWM mode.

[0038] Figure 3 It describes what can be used for implementation Figure 1 An example of an auxiliary control loop 300 of the control loop 102. The auxiliary control loop 300 includes a watchdog circuit 301 with an input adapted to receive a pause signal (such as...). Figure 1The pause signal 106 shown is from the main control loop 103. As disclosed herein, the pause signal can indicate whether the switching circuitry of the power converter is switching. For example, the control logic of the main control loop provides the pause signal based on the output voltage relative to a target voltage (e.g., the error amplifier of the main control loop compares the output voltage with the target voltage). When the pause signal is high, it indicates that the power converter is in a skip mode in which the switching circuitry is temporarily not switching. For example, during zero or light load conditions, when the output voltage VOUT is at or above the target, the main control loop can enter a skip mode and disconnect the switching for the period of time when it is in the skip mode. The pause signal is provided to an input at NAND gate 302 and a watchdog timer 304. The watchdog timer 304 can be implemented as an analog timer circuit or a digital timer circuit.

[0039] Watchdog timer 304 is configured to provide a force switch signal to another input of NAND gate 302. For example, watchdog timer 304 is configured to ensure that skip mode does not continue for a threshold duration that would allow the power converter to enter audible range. Therefore, watchdog timer 304 provides a force switch signal to indicate that the threshold duration has elapsed since the assertion of the pause signal (e.g., a duration of approximately 40 microseconds after the pause signal becomes high), and that switching is enabled by a switching circuit as disclosed herein while the pause signal remains high. The time interval implemented by watchdog timer 304 can be predetermined or programmable. For example, the time interval is set according to the configuration of components in the analog circuitry used to implement the watchdog timer, and different components can result in different time intervals. In another example, the time interval can be set to a value (e.g., a counter or timer value) provided to the digital circuitry used to implement watchdog timer 304. NAND gate 302 then performs a logic NAND operation and provides the resulting start signal at 306 to the input of inverter 308. Therefore, the inverter provides an inverter version of the start signal at 310, which corresponds to the input of the pulse generator 312.

[0040] For example, pulse generator 312 corresponds to Figure 1A pulse generator 110. A pulse generator 312 is configured to provide a series of one or more pulses. For example, the pulses may be a fixed number of pulses or a variable number of pulses with a fixed or variable duty cycle. For example, the number of pulses and / or duty cycles may be set based on the operating parameters of the power converter. The pulse generator provides one or more pulses (e.g., a burst of one or more pulses) at an output terminal 314 provided to the output logic. For example, a burst of one or more pulses at 314 is directed to the input of a NOR gate 320. A start signal at 306 is applied to another input of the NOR gate 320, and the combined result (e.g., via a logic NOR operation) provides a pulse output signal, which is applied to the input of a gate driver (e.g., driver 112) for controlling a power switching device of a switching circuit (e.g., switching circuit 114).

[0041] Figure 4 It is a diagram and auxiliary control loop (e.g., Figure 1 circuit 102 or Figure 3 The signal diagram 400 combines the operation-related signals of the circuit 300 with certain signals of the power converter employing an auxiliary control circuit. Signal diagram 400 includes a forced switching signal 402, which corresponds to the output of a watchdog timer 304 operable to enable switching while the pause signal is still logic high. Signal diagram 400 also illustrates the pause signal 404, pulse signals (e.g.,...). Figure 1 The pulse signal 402 (111) and the inductor current (IL) signal at 406 and the output voltage (VOUT) at 408 are used. A combination of the forced switching signal 402 and the pause signal 404, when high, causes the pulse generator to provide a pulse signal 405, which may include one or more pulses. The pulse signal 405 is used to drive the switching circuit to provide a negative burst of the inductor current 406, as shown at 410. By way of example, the forced switching signal 402 goes high as soon as the watchdog timer expires and remains high for a predetermined duration, shown as pulse width 403. The forced switching signal 402 may be generated on the watchdog itself or at the boundary between the main control loop and the watchdog. When the forced switch is high and the pause signal is high, the pulse generator is activated to generate the pulse signal 405 with one or more pulses. Figure 4In one example, when both the forced switching signal and the pause signal are logic high, the pulse generator provides four pulses for pulse signal 405. In another example, a different number of pulses can be used to provide pulse signal 405, as disclosed herein. Pulse signal 405 controls the converter to first switch with one or more negative pulses 410 of the inductor current, and then switch to a natural switch as shown at 414. During the negative burst of inductor current 410, output voltage 408 decreases accordingly, as shown at 415. In response to the output voltage decreasing by a sufficient amount, the main control loop takes over to exit skip mode and resume switching to regulate output voltage VOUT to the target voltage. Therefore, when switching is resumed, the pause signal is deasserted low, as shown at 412. In response, the main control loop controls the switching device of the converter to apply a burst of positive inductor current as shown at 414. As shown, the output voltage increases and is regulated to the target voltage accordingly, at which point forced switching 402 is reset to logic low, as shown at 416. When the forced switching signal goes low, at 416, the main circuit is configured to naturally enter a skip state, and the pause signal goes high as the output voltage VOUT increases beyond the target voltage being regulated. When the switching is terminated to trigger the watchdog timer 304 to repeat the audio external control, the pause signal 404 is asserted as high.

[0042] Figure 5A An example of a buck-boost converter 500 is illustrated. Figure 5B This is a graph of the inductor current at 502, occurring during a negative burst of the inductor current used in converter 500. In this example, the buck-boost converter 500 includes a first switching device S1 coupled between the input voltage VIN and inductor terminal node L1. A second switching device S2 is coupled between inductor terminal L1 and ground. A third switching device is coupled between the output voltage VOUT and the second inductor node L2. A fourth switching device S4 is coupled between inductor node L2 and ground. In this example, the output capacitor COUT is coupled between the output voltage VOUT and ground.

[0043] As disclosed herein, an auxiliary control circuit, which can be implemented as control circuit 102 or 300, is configured to control switching devices S1, S2, S3, and S4 to achieve external audio control. For example, the auxiliary control circuit controls switching devices S1, S2, S3, and S4 to provide one or more negative bursts of inductor current, such that net positive charge does not accumulate on the output capacitor COUT.

[0044] like Figure 5BAs shown in graph 502, during the ON period (TON) that occurs, such as when pulse signals 111 or 405 are logic high, current switching devices S2 and S3 are turned on and current flows through the inductor between L2 and L1 and through switch S2 from the output terminal of S3 along current path 508. During the TON interval, S1 and S4 are turned off. During the second phase of a negative burst, such as when pulse signals 111 or 405 are logic low, which is represented as TOFF, S1, S2, S3, and S4 are all turned off. Therefore, during TOFF, inductor current continues to flow, but flows from ground through the back-gate diode of S4, through the inductor (from L2 to L1), and through the back-gate diode of S1 to return energy to VIN. In one example, to ensure that the negative current used for converter 500 does not accumulate cycle by cycle, TON can be set as follows:

[0045]

[0046] Where Vd represents the back-gate diode voltage (e.g., Vd≈0.7V), and T represents the pulse duration (T=TON+TOFF). The formula above for setting TON can be changed based on the type of converter used.

[0047] Therefore, by tri-states both the buck and boost power phases of converter 500, the stored energy is transferred from COUT to the inductor (during TON), and then returned to the input voltage through the corresponding back-gate diode as shown in current path 510 (during TOFF). In some examples, the TON and TOFF phases of each pulse can be repeated on multiple pulses depending on the number of one or more pulses generated (e.g., by pulse generator 110 or 312). Thus, during each TON phase, the output voltage VOUT discharges through path 508 to provide a negative current through inductor L. OFF During the TON phase, switches S1, S2, S3 and S4 are disconnected, and based on the energy stored in the inductor during the TON phase, the negative current continues to flow from ground to the input voltage VIN through inductor L.

[0048] Figure 6 It is a signal diagram, which includes signals from... Figure 5A The signal diagram 600 includes the signals of the buck-boost converter 500 and corresponding signals associated with the operation of auxiliary control loops (e.g., control loops 102 or 300) as disclosed herein. The signal diagram 600 therefore includes an output voltage (VOUT) 602, an inductor current (IL) 604, a pause signal 606, a forced switching signal 608, and a PWM mode signal 610. For example, the output voltage signal 602 corresponds to... Figure 5AVOUT in, and the inductor current 604 corresponds to the current between L1 and L2 during the TON and TOFF phases during the negative current burst, as shown at 510 and 508.

[0049] like Figure 6 As shown, the pause signal is an inverted version of the PWM mode signal 610. Therefore, when the PWM mode signal is high, the main control loop implements PWM switching for the power converter 500. Figure 6 As shown, a negative current burst is applied to the inductor at the start of each switching burst phase, based on the AND operation of the forced switching signal 608 and the AND operation of the pause signal 606, respectively. This results in a negative pulse of the inductor current 604, as shown at 612. As disclosed herein, the negative inductor current causes a corresponding decrease in the output voltage 602 (by discharging the output capacitor COUT) until the main control loop detects that the output voltage is less than the target voltage. Based on a comparison of the output voltage and the target voltage, the main control loop cancels the assertion of the pause signal and asserts the PWM mode signal, resulting in entry into a PWM mode for continuous switching to provide a positive current pulse through the inductor used to regulate the output voltage to the desired target voltage. When the output voltage is regulated, the main control loop asserts the pause signal (to logic high) and cancels the assertion of the PWM mode signal (to logic low). As described herein, the time interval between the forced switching signals that become high, as shown at 620, is controlled by a watchdog circuit to be less than the audible duration for the converter 500. In this way, audible switching noise can be prevented during the operation of the power converter, including when operating in power-saving mode. Furthermore, by reducing the output voltage through induced discharge, the power converter can naturally exit the skip mode.

[0050] Figure 7A An example of a buck converter 700 that can implement external audio control schemes is depicted. Figure 7B This is a graph of the inductor current at 502, showing the current during a negative burst in the inductor current used in the buck converter 700. The buck converter 700 includes a switch S1 coupled between the input voltage VIN and the inductor terminal L1. Another switching device S2 is coupled between the inductor terminal L1 and ground. An inductor is coupled between the inductor terminal L1 and the output terminal of the converter 700 corresponding to the output voltage VOUT. The output capacitor COUT is coupled between the converter's output terminal and ground.

[0051] As an example, an auxiliary control loop, which may be implemented by control loop 102 or 300, is configured to operate the power converter 700 to prevent audible switching noise. As disclosed herein, external audio control is achieved by applying a burst of negative current to inductor L1, used to discharge the output voltage VOUT, at a rate repeated at a frequency outside the audible range of the converter 700. Reference Figure 7B During the turn-on phase (TON) of a negative burst, such as when pulse signal 111 or 405 is logic high, switching device S1 is turned off and switch S2 is closed, causing current to flow along current path 704 from output VOUT through inductor L, inductor terminal L1, and through switch S2 to ground. This negative current through inductor L stores energy in the inductor. Therefore, during the next phase (TOFF) of a pulse, such as when pulse signal 111 or 405 is logic low, current flows through the back-gate diode of S1 along path 706 when switches S1 and S2 are turned off. That is, current flows through inductor L1 and through the back-gate diode of switching device S1 from output VOUT along path 706 to return energy to output voltage VIN. As disclosed herein, a negative discharge burst generated by an auxiliary control loop may include a single pulse or multiple pulses. Each pulse includes a TON phase and a TOFF phase as disclosed herein.

[0052] Figure 8 It demonstrates and implements the association between audio external switching. Figure 7A The signal diagram 800 shows the signals in the buck converter 700. Signal diagram 800 includes inductor current (IL) 802, output voltage (VOUT) 804, and signals related to... Figure 7A The voltage at node L1 corresponds to the switching voltage (VSW) 806. As disclosed herein, a negative current pulse 808 ensures that switching is applied at frequencies outside the audio range. Figure 8 In the example, a first single negative current pulse 808 is applied at the start of the burst, and a second negative pulse 810 is applied during the duration of the first pulse to ensure that the switching remains outside the audio range. After the second negative pulse 810, the output voltage VOUT at 804 travels to the comparator threshold (e.g., approximately 1.5 V), causing the power converter to exit skip mode and enter PWM switching mode. The main control loop controls the operation of switches S1 and S2 during PWM switching mode to apply a positive current to the output voltage used to charge capacitor COUT. Figure 8 An example is provided in which a single pulse signal is provided, such as by pulse generator 110 or 312, using only a single negative pulse.

[0053] Figure 9 It demonstrates the implementation of external audio control. Figure 7AAnother example of the operation of the buck converter 700 is shown in signal diagram 900. Figure 9 In the example, multiple negative pulses are applied to drive a switch with a duty cycle, and each pulse includes about Figure 7B The publicly disclosed TON and TOFF phases. Figure 9 In the diagram 900, signal diagram 900 includes a forced switching signal 902, a pause signal 904, an inductor current signal (IL) 906, and an output voltage (VOUT) 908. As disclosed herein, a watchdog circuit (e.g., circuit 104 or 301) initiates the negative current burst 910 based on a high forced switching signal and a pause signal. In this example, the negative current burst 910 of the inductor current 906 includes multiple (e.g., four) pulses at the start of each negative burst, generated as a series of corresponding pulses based on a pulse signal generated by pulse generator 110 or 312. An external audio control loop ensures that the negative pulses are applied in each burst to discharge the output voltage VOUT before charging it according to a target (e.g., by controlling switches S1 and S2 as described with respect to FIG7). Therefore, the external audio control loop maintains the time period of each pause signal shown at 914 to remain within the external audio duration (e.g., less than 50 microseconds). The negative inductor current IL applied during the negative burst 910 thus reduces the output voltage VOUT shown at 908, which is commensurate with the negative inductor current 910. In response to the output voltage dropping below the target voltage, the main control loop is configured to regulate the output voltage by applying a positive inductor current during the remaining duration of the assertion forced switching signal 902 using PWM switching.

[0054] As mentioned above, external audio controls can be applied to any DC-DC converter (e.g., buck converter, boost converter, or buck-boost converter). Figure 10 An example signal diagram 1000 for an example boost converter (not shown) is depicted. As an example, by referring to the buck-boost converter 500 of Figure 5, the boost converter can be implemented by permanently shorting S1 and making S2 an open circuit. Signal diagram 1000 includes a forced PWM signal 1002, a forced switching signal 1004, a pause signal 1006, an inductor current signal (IL) 1008, and an output voltage signal (VOUT) 1010. Figure 10In the example, a negative current burst 1012 is applied to an inductor, such as that implemented by the external audio control loop 102 or 300, based on the forced switching signal and the pause signal being high to cause a corresponding decrease in the output voltage 1010. In this example, the pause signal naturally goes low in response to the main control loop (such as control loop 103) detecting a decrease in the output voltage 1010 relative to the target voltage. In response, the main control loop of the boost converter asserts the forced PWM signal 1002 high and, in turn, implements PWM switching until this forced PWM assertion is canceled. Once the switching of the power converter stops, the converter enters a skip mode, as indicated by the pause signal 1006 asserted as logic high. The duration between the pause signals going low in successive cycles is shown at 1014.

[0055] Figure 11 An example of a watchdog timer circuit 1100, which may be implemented as a watchdog timer 304 or in watchdog circuit 104, is illustrated. The watchdog timer circuit 1100 has an input 1102 to receive a start signal, such as the pause signal disclosed herein. The pause signal can therefore be applied at 1102 to start the watchdog timer circuit 1100. Input 1102 is connected to the input of a Schmitt trigger 1104 via a series resistor 1106. A capacitor 1108 is connected between the input of the Schmitt trigger 1104 and electrical ground. Resistor 1106 and capacitor 1108 thus form an RC circuit to set the time constant associated with the watchdog timer 1100. Therefore, the resistance and capacitance values ​​are configurable to set the threshold duration of the timer circuit 1100 to operate the converter in an outside-audio range (e.g., less than 50 microseconds between consecutive switching intervals). Switch 1110 is coupled between the input of the Schmitt trigger and electrical ground. A reset signal can be applied to switch 1110 to periodically discharge the capacitor, as at the beginning of each cycle. Therefore, timer circuit 1100 can provide a watchdog expiration (WATCHDOG_EXPIRE) signal indicating that the duration of the start signal from 1102 (e.g., corresponding to the pause signal) has reached a set threshold duration provided by its RC circuitry. For example, the watchdog expiration signal corresponds to an assertion-forced toggle signal that asserts to logic high, as disclosed herein. Although Figure 11 The example illustration shows a simulated implementation of the watchdog timer, but a corresponding digital implementation can also be used, in which a digital counter is timed according to a clock frequency to set a threshold duration between bursts to operate in the audio out-of-range as disclosed herein.

[0056] Figure 12 Examples of pulse generators 1200, such as those used to implement the pulse generators 110 or 312 disclosed herein, are depicted. Figure 12 In the example, pulse generator 1200 includes input 1202 to receive (such as a start signal provided by watchdog circuit 104 or) Figure 3 The signal at position 310 corresponds to the start pulse signal. The start signal is provided to the input of AND gate 1204. AND gate 1204 also receives feedback input of the off-time (TOFF) of the pulse generated from pulse generator 1200. For example, the output of the pulse generator is applied to the input of the AND gate via inverter 1206. The output of the AND gate is connected to the input of turn-on time generator 1208. The turn-on time generator provides a TON output signal to the input of inverter 1210. The turn-on signal of the inverter is applied to the input of AND gate 1212. Another input of AND gate 1212 is the start signal set at input 1202. The output of AND gate 1212 is provided to the input of turn-off time generator 1214, which is configured to provide a TOFF signal to the aforementioned inverter 1206. Another AND gate 1216 has an input coupled to the output of the turn-on time generator to receive the TON signal. Another input of AND gate 1216 is coupled to a start signal located at 1212. AND gate 1216 thus provides corresponding output pulses with on-time and off-time based on the timing configuration of each of the on-time generator 1208 and the off-time generator 1214. The output pulses thus correspond to the outputs of pulse generators 110 or 312 disclosed herein.

[0057] As yet another example, each of the time generators, whether turned on or off, can be based on... Figure 13 Example timing circuit 1300 is implemented. Circuit 1300 is configured to set the timing for the on and off times of each output pulse generated by pulse generator 1200. For example, circuit 1300 includes a resistor 1302 coupled to the input of Schmitt trigger 1304. Capacitor 1306 is coupled to the node between resistor 1302 and Schmitt trigger 1304. The values ​​of resistor 1302 and capacitor 1306 can be set to define an RC time constant for timing circuit 1300. The output of the Schmitt trigger is provided to the input of AND gate 1308 to provide a logic output signal based on the output of Schmitt trigger 1304 and the input of circuit 1300, which is also applied to the other input of AND gate 1308. In this way, the timing and delay between the input and output of the circuit can be set to achieve Figure 12 The required on and off times of the pulse generator circuit 1200 in the circuit.

[0058] Figure 14An example of a gate driver circuit 1400, such as driver 112, in a buck-boost converter (e.g., corresponding to converter 500 of FIG. 5) is depicted. Thus, in this example, circuit 1400 includes switches S1 and S2 connected between the input voltage VIN and electrical ground. Another set of switches S3 and S4 are connected between VOUT and electrical ground. The node between S1 and S2 corresponds to the terminals of a first inductor, and the node between S3 and S4 corresponds to the terminals of a second inductor. An inductor L is connected between the inductor terminals. In this example, each of the switching devices S1, S2, S3, and S4 corresponds to a field-effect transistor; it is thought that other types of transistor devices may be used in other examples. Corresponding drivers 1402, 1404, 1406, and 1408 are coupled to the gates G1, G2, G3, and G4 of each of the respective switching devices. For example, each of drivers 1402, 1404, 1406, and 1408 can be implemented as a high-intensity digital driver to provide corresponding pulses to control the gate of each switching device during switching operations for negative burst and positive switching modes. An on signal for switching device S1 is applied to the input of inverter 1410. The inverter's on signal S1 is applied to non-overlapping circuit 1412 to provide corresponding control signals to each of gate drivers 1402 and 1404, respectively. The non-overlapping circuit is configured to ensure that each of switching devices S1 and S2 operates in an exclusive manner, such that neither is turned on simultaneously. Similarly, an on signal S3 is applied to inverter 1414, and the inverter's signal is applied to another non-overlapping circuit 1416. Non-overlapping circuit 1416 is coupled to each of the corresponding drivers 1406 and 1408 and is configured to ensure that the operation of switching devices S3 and S4 is not simultaneously turned on. As an example, non-overlapping circuits 1412 and 1416 can be implemented as cross-coupled logic, which includes an arrangement of NAND or NOR gates configured to provide corresponding non-overlapping on and off signals. Other types of circuitry, such as anti-cross-conduction circuitry, can be used to implement non-overlapping circuits 1412 and 1416 to ensure mutually exclusive operation of switches S1 and S2, as well as S3 and S4.

[0059] Figure 15 An example of a power converter 1500 capable of external audio control is depicted. Figure 15In the example, power converter 1500 includes an integrated circuit (IC) chip 1502 configured as a buck-boost power converter. The converter can be similarly used to implement other types of power converters disclosed herein (e.g., buck or boost converters). Power converter 1500 includes an external inductor 1504 coupled between inductor terminals LX1 and LX2 of IC chip 1502. IC chip 1502 also includes an input terminal 1506 adapted to be coupled to an input voltage VIN and an output terminal 1508 adapted to be coupled to an output voltage VOUT. For example, an output capacitor is coupled to terminal 1508 as part of power converter 1500.

[0060] IC chip 1502 includes a switching circuit 1510 coupled to input terminal 1506 and output terminal 1508. An inductor 1504 is therefore located between the switching circuit and the output terminal. Figure 15 In the example, the switching circuit 1510 includes switching devices S1, S2, S3, and S4. For example, switching devices S1, S2, S3, and S4 are shown as field-effect transistors, each having a back-gate diode between its source and drain. In other examples, different types of transistor devices may be used. S1 is coupled between terminal 1506 and LX1. Switching device S2 is coupled between LX1 and ground terminal 1512. Switching device S2 is coupled between ground terminal 1512 and LX2. Switching device S4 is coupled between LX2 and output terminal 1508. Gate driver circuit 1514 is coupled to the gates of S1 and S2, and other gate driver circuit 1516 is coupled to the gates of S3 and S4. The IC includes a controller 1520 configured to implement control logic.

[0061] Controller 1520 includes a main control loop circuit 1522 and an auxiliary control loop circuit 1524. The main control loop circuit 1522 is configured to control the switching circuit 1510 in pulse width modulation (PWM) mode to regulate the output voltage VOUT relative to a target voltage (VTARGET). The auxiliary control loop circuit 1524 is configured to control the switching circuit 1510 to provide a burst of negative current in response to operation in a skip mode for a threshold duration. As disclosed herein, the threshold duration of the skip mode controlled by the auxiliary control loop circuit 1524 is less than the audio range. The auxiliary control loop circuit 1524 may be implemented as circuit 102 or 300 disclosed herein. During the skip mode, for example, the auxiliary control loop circuit 1524 is configured to provide one or more pulses to the gate driver to provide a burst of negative current that flows through inductor 1504 from output terminal 1508 to discharge the output voltage VOUT. The main control loop circuit 1522 is configured to transition from skip mode to PWM mode based on the output voltage VOUT and the target voltage VTARGET, so that the operation of the switching circuit 1510 is kept outside the audio range.

[0062] IC chip 1502 may also include feedback circuitry 1526, configured to provide feedback to controller 1520 based on the output voltage and target voltage, enabling the main control loop and auxiliary control loop to operate as disclosed herein. For example, feedback circuitry 1526 includes an error amplifier 1528 having an input coupled to receive an input corresponding to the output voltage VOUT. In one example, the voltage divider includes resistors 1530 and 1532 coupled between terminal 1508 and ground. The inverter input is coupled to node 1534 between resistors 1530 and 1532. The target voltage VTARGET is coupled to the non-inverter input. Error amplifier 1528 is configured to compare the divided voltage (representing the output voltage VOUT) at 1534 with the target voltage VTARGET. Error amplifier 1528 is configured to provide an error signal at output 1536 based on the output voltage VOUT and the target voltage VTARGET. Output 1536 is coupled to the inputs of current comparator 1538 and clamping circuit 1540. A sensed input current ISNS (e.g., from a current sensing circuit) is provided to the other input of comparator 1538. Comparator 1538 provides a feedback signal to controller 1520, which is used by the main control loop to regulate the output voltage VOUT at 1508. Clamping circuit 1540 is configured to clamp an error signal at 1536 to generate a pause signal at its output 1542, which is then provided to the controller. For example, the pause signal is provided to main control loop 1522 and auxiliary control loop 1524 and is used to specify when the converter operates in skip mode, as disclosed herein. Therefore, the main control loop is configured to control switching circuit 1510 into pulse width modulation operating mode and provide a positive current based on the pause signal with a logic low value. For example, clamping circuit 1540 provides a pause signal with a logic low value based on an error signal at 1536 indicating that the output voltage is less than the target voltage, so that the main control loop can control switching circuit 1510 to provide current to output terminal 1508 for charging the output capacitor as disclosed herein.

[0063] Figure 16 This is a flowchart illustrating an example method 1600 for operating a power converter in the audio range. This method can be implemented using the control loops and other circuitry disclosed herein (see, for example...). Figure 1 , Figure 3 Figures 5 and 7 Figure 15In one example, method 1600 can be used during power-saving modes, such as under light or no-load conditions. At 1602, a pause signal is received (e.g., at the input of the watchdog circuits 104, 301 of the auxiliary control loops 102, 300, 1524). The pause signal has a state indicating operation in skip mode, in which the switching circuits of the power converter (e.g., switching circuits 114, S1, S2, S3, S4, 1500) have stopped switching in pulse width modulation (PWM) mode. The configuration of the switching circuits can vary depending on the type of power converter being implemented. For example, the pause signal can be asserted by the main control loop or other circuitry to indicate that the power converter is operating in skip mode.

[0064] At 1604, in response to the detection that the switching circuit has stopped switching for a threshold duration (e.g., about 40 microseconds or less), a start signal, such as that provided by watchdog circuits 104 and 301, is provided based on a pause signal. For example, the duration may be tracked by a watchdog timer of the watchdog circuit (e.g., timer 304 or 1100) and used to provide the start signal. As an example, the start signal is triggered to ensure that the duration between adjacent switching cycles does not exceed the threshold duration for which the switching circuit will operate within an audible range. As disclosed herein, the start signal may be provided based on a forced switching signal and a pause signal (e.g., by ANDing the forced switching signal and the pause signal via NAND gate 302).

[0065] At 1606, at least one pulse is generated during skip mode based on a start signal, such as by pulse generators 110, 312, and 1200. As disclosed herein, the number and / or width of the pulses can be varied according to application requirements. For example, during skip mode, the pulse generator is configured to generate one or more pulses at 1606 as a predetermined number of pulses generated based on the start signal, a variable number of pulses generated based on the start signal, or one or more pulses based on output voltage control relative to a target voltage (e.g., based on an error signal control at 1536).

[0066] At 1608, a negative current (e.g., a negative current burst) is provided from the output of the power converter through the inductor based on at least one pulse. For example, an auxiliary control loop, such as that implemented by control loops 102, 300, 1524, is configured to control a switching circuit (e.g., circuits 114, S1, S2, S3, S4, 1500) based on one or more pulses to provide one or more pulses of negative inductor current. At 1610, the output voltage is discharged based on the negative current. For example, a negative current is drawn from the output to ground through the inductor during a first phase of a given pulse, and then the current is returned to the input voltage during a second phase of the given pulse, as disclosed herein (e.g., by controlling one or more switching devices). At 1612, the method transitions the power converter from a skip mode to a PWM operating mode based on the output voltage and a target voltage. For example, negative current operation is used to discharge the output voltage (e.g., stored in the output capacitor COUT) to a level below the target voltage, and the main control loop, as implemented by loop 103 or 1522, is configured to enter PWM mode and control switching to provide positive inductor current (e.g., through operation of the switching circuit in PWM mode) to regulate the output voltage relative to the target voltage. In this way, the method keeps the operation of the switching circuit outside the audible range.

[0067] The above description is an example of the invention. Of course, for the purposes of describing the invention, it is impossible to describe every possible combination of components or methods, but those skilled in the art will recognize that many further combinations and arrangements of the invention are possible. Therefore, the invention is intended to include all such changes, modifications, and variations falling within the spirit and scope of the appended claims. Furthermore, where the disclosure or claims recite the element “a,” “an,” “first,” or “another,” or its equivalents, it should be interpreted as including one or more such elements, neither requiring nor excluding two or more such elements. As used herein, the term “includes” means including but not limited to, and the term “including” means including but not limited to. The term “based on” means at least partially based on.

Claims

1. A power converter, the power converter comprising: A watchdog circuit having an input suitable for coupling to a pause signal of a switching power supply, the watchdog circuit being configured to provide a start signal at its output based on the pause signal indicating that the power converter has stopped switching for a duration less than a threshold of the audible switching range of the power converter; A pulse generator circuit having an input coupled to the output of the watchdog circuit and configured to generate at least one pulse based on the start signal; and A switching circuit having an input terminal adapted to be coupled to an input voltage and at least one other terminal adapted to be coupled to an inductor, the switching circuit being configured to provide a negative current from the output of the power converter through the at least one other terminal based on the at least one pulse.

2. The power converter according to claim 1, further comprising a driver circuit coupled between the pulse generator circuit and the switching circuit, and an output terminal of the driver circuit coupled to a control input terminal of a corresponding switch of the switching circuit.

3. The power converter of claim 1, wherein the pulse generator circuit is configured to provide a predetermined number of pulses based on the start signal.

4. The power converter of claim 1, wherein the pulse generator circuit is configured to provide a variable number of pulses based on the activation signal.

5. The power converter of claim 1, wherein the pulse generator circuit is configured to control the at least one pulse based on an output voltage at the output terminal of the power converter relative to a target output voltage.

6. The power converter of claim 1, wherein the pulse generator circuit is configured to generate the at least one pulse as a plurality of pulses having a predetermined duty cycle.

7. The power converter according to claim 1, wherein the watchdog circuit comprises: A timer configured to generate a forced switching signal based on operating in skip mode for a duration of the threshold; and A logic circuit configured to provide the start signal based on the forced switching signal and the pause signal.

8. The power converter of claim 7, wherein the threshold duration of the skip mode is less than 40 microseconds.

9. The power converter of claim 7, wherein the watchdog circuit and the pulse generator define at least a portion of an auxiliary control loop, the power converter further comprising a main control loop configured to control the switching circuit in a pulse width modulation operating mode based on the output voltage of the power converter relative to a target voltage, the main control loop being further configured to control the switching circuit to provide a positive current to the output during the pulse width modulation operating mode.

10. The power converter according to claim 9, further comprising: A feedback circuit configured to provide an error signal based on the output voltage of the power converter relative to the target voltage, wherein a pause signal is generated based on the error signal; and The control logic is configured to control the switching circuit to enter the pulse width modulation operation mode and provide the positive current based on the pause signal having a state indicating that the output voltage is less than the target voltage.

11. The power converter of claim 9, further comprising a clamping circuit configured to set the state of the pause signal based on the output voltage relative to the target voltage.

12. The power converter of claim 1, wherein the power converter is configured as one of a buck converter, a boost converter, or a buck-boost converter.

13. A system for external audio switching, the system comprising: A switching circuit having an input terminal and an output terminal, the input terminal being coupled to an input voltage and the output terminal being coupled to the output voltage of the system; The main control loop circuit is configured to control the switching circuit in pulse width modulation (PWM) mode to adjust the output voltage relative to the target voltage. and An auxiliary control loop circuit is configured to control the switching circuit to provide a negative current in response to pausing switching in a skip mode for a threshold duration less than the duration of operation of the switching circuit within the audible range. The negative current flows through an inductor from the output terminal to discharge the output voltage. The main control loop circuit is configured to transition from the skip mode to the PWM mode based on the output voltage and the target voltage to maintain the operation of the switching circuit outside the audible range.

14. The system of claim 13, wherein the auxiliary control loop circuit comprises: A watchdog circuit configured to provide a start signal based on a pause signal, the pause signal indicating that the switching circuit has stopped switching in the PWM mode and has been operating in the skip mode for the threshold duration; and A pulse generator circuit is configured to generate at least one pulse based on the activation signal, and the negative current is provided based on the at least one pulse.

15. The system of claim 14, wherein the watchdog circuit comprises: A timer configured to generate a forced switching signal based on operation in the skip mode for a threshold duration sufficient to sustain switching outside the audible range by the switching circuitry; and The logic is configured to provide the start signal based on the forced switching signal and the pause signal.

16. The system of claim 15, wherein the threshold duration of the skip mode sufficient to maintain the switching outside the audible range by the switching circuit is less than 40 microseconds.

17. The system of claim 14, wherein the pulse generator circuit is configured to operate in one of the following ways: providing a predetermined number of pulses based on the start signal, providing a variable number of pulses based on the start signal, or controlling the pulses based on the output voltage relative to the target voltage.

18. The system of claim 13, wherein the main control loop circuit, the auxiliary control loop circuit, and the switching circuit are implemented in an integrated circuit chip.

19. The system of claim 13, further comprising the inductor coupled to at least one inductor terminal between the switching circuit and the output terminal.

20. A method for switching audio signals, the method comprising: Receive a pause signal indicating a state of operation in skip mode, in which the switching circuit of the power converter has stopped switching in pulse width modulation mode, i.e., PWM mode. In response to detecting that the switching circuit has stopped switching within a threshold duration, a start signal is provided based on the pause signal; At least one pulse is generated during the skip mode based on the activation signal; as well as Based on the at least one pulse, a negative current is provided from the output of the power converter through an inductor; The negative current discharges the output voltage at the output terminal of the power converter. as well as The switching circuit transitions from the skip mode to the PWM mode based on the output voltage and the target voltage, so as to maintain the operation of the switching circuit outside the audible range of the switching circuit.

21. The method of claim 20, wherein providing the start signal comprises: A forced switching signal is generated based on the operation in the skip mode during the threshold duration; as well as The start signal is provided based on the forced switching signal and the pause signal.

22. The method of claim 20, wherein the at least one pulse during the skip mode comprises one of: a predetermined number of pulses generated based on the start signal, a variable number of pulses generated based on the start signal, or a plurality of pulses based on one or more pulses controlled by the output voltage relative to the target voltage.

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