Multiple-input multiple-output detection mechanism and related operation methods

Abstract

Circuitry and methods for operating a detector in a wireless communication system are disclosed. The detector dynamically adjusts one or more internal configurations to achieve variable complexity detection. Based on this adjustment, the processing complexity of each received symbol vector and channel input pair can vary between communication time intervals.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 966,966, filed January 28, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to the field of communications, and more specifically, to wireless communication methods and apparatus. Background Technology

[0004] The rapid development of computing technology has created a greater demand for data communication. This ever-increasing demand, in turn, drives further development of communication technologies. One such technological advancement corresponds to Multiple-Input Multiple-Output (MIMO) devices, systems, algorithms, etc. MIMO-related technologies utilize multiple transmit antennas and multiple receive antennas to leverage multipath propagation, allowing for a significant increase in wireless link capacity. In other words, communication devices can use MIMO technology to simultaneously exchange multiple data signals. However, simultaneous communication also introduces new challenges that need to be addressed. For example, the use of simultaneous data signals / channels increases the processing demands on both transmitting and receiving devices. Furthermore, the additional data signals / channels increase cross-channel interference. Summary of the Invention

[0005] Implementations of this disclosure provide a wireless communication method and apparatus for performing variable complexity detection. One or more implementations provide a method for operating a communication device. The method may include: receiving a wireless signal at the communication device, wherein the wireless signal represents a symbol transmitted by an external device via a wireless channel; determining real-time communication parameters associated with the received wireless signal; deriving a control indicator based on the real-time communication parameters; and generating a detection result from the wireless signal using a detector, according to the control indicator and a corresponding configuration, wherein the detection result estimates the symbol transmitted by the external device. The control indicator may variably control the configuration of the detector to variably control the complexity measurement associated with generating the detection result.

[0006] Additionally, generating the detection result may include implementing a fixed processing segment based on an implementation count N indicated by a control indicator. The fixed processing segment may correspond to a fixed complexity, and the implementation count (N) may correspond to the number of iterations implemented in parallel or serially. For each iteration, the fixed processing segment may be configured to generate a decoding result based on unique variable permutation data corresponding to the implemented iteration.

[0007] Furthermore, the fixed processing section may include circuitry configured by hardware to generate the decoding result. Implementing the fixed processing section may include: (1) iteratively inputting the modulation symbol vector and channel input pair into the fixed processing section N times; and / or (2) processing the channel input and modulation symbol vector according to unique variable permutation data corresponding to the implemented iteration. Additionally, the detector may include at least a first circuit and a second circuit, having matched hardware configurations, wherein the first circuit includes the fixed processing section. Implementing the fixed processing section may include: (1) implementing the first circuit and the second circuit in parallel at least; (2) simultaneously inputting the modulation symbol vector and channel input pair into the first circuit and the second circuit; and / or (3) at each of the first circuit and the second circuit, processing the channel input and modulation symbol vector according to the corresponding unique variable permutation data.

[0008] Alternatively or concurrently, the fixed processing section may include a set of functions configured by hardware circuitry and / or software to generate the decoding result. Implementing the fixed processing section may include: (1) implementing the software function set N times iteratively using the modulation symbol vector and the channel input pair as inputs to the fixed processing section; and / or (2) processing the channel input and the modulation symbol vector according to unique variable permutation data corresponding to the implemented iteration.

[0009] Alternatively, each implementation of the fixed processing segment may include applying a unique portion of the permutation dataset to the channel input. Furthermore, generating the detection result through N iterations may include processing a portion of the permutation dataset instead of the entire permutation dataset.

[0010] The method for operating the communication device may further include: calculating a channel input that estimates the effects of one or more wireless channels and symbols. Implementing the fixed processing segment may include: generating finite permutation results for each iteration based on the channel input and unique variable permutation data corresponding to the implemented iteration. Further, implementing the fixed processing segment may include: for each iteration: (1) generating QR decomposition results based on the analysis of the finite permutation results; and / or (2) generating a symbol decoding result set according to a fixed complexity decoding mechanism. The fixed complexity decoding mechanism may be a spherical decoding mechanism, and the symbol decoding result set includes one or more survival paths and / or one or more distances. Generating detection results may include: (1) generating N symbol decoding result sets by iteratively implementing the fixed processing segment; and / or calculating a log likelihood ratio (LLR) value set based on the N symbol decoding result sets, wherein the LLR value set includes the detection results.

[0011] The method for operating the communication device may further include: (1) calculating channel inputs that estimate one or more effects of the wireless channel and symbols; and / or (2) dividing a set of channel input and symbol pairs (e.g., corresponding to multiple time instances within a time interval and / or multiple frequency points within a frequency bandwidth) into L sets. The parameter L may represent resource allocation, and a resource-based count (N) may be derived for each of the L sets. l Where l = 1, 2, ..., L-1, L). The derived control indicator may include: dynamically calculating N associated with the first channel input set to the l-th channel input set. l Generating detection results may include: based on N as indicated by the control indicator. l This implements fixed processing segments. Fixed processing segments can correspond to allocations associated with resource allocation, and / or N. l This can correspond to the number of iterations implemented in parallel or serial mode. For each iteration, a fixed processing segment can be configured to generate a decoding result based on unique variable permutation data corresponding to the implemented iteration. Furthermore, N is dynamically calculated. l This may include: (1) determining the realization count (N); and / or (2) reducing N based on a comparison with the total constraint. Alternatively, the method for operating the communication device may further include: determining the signal quality based on the channel input. Dynamically calculating N l This may include: (1) determining the implementation count (N); and / or reducing N based on signal quality. Alternatively, the method for operating the communication device may further include: determining a low-power operating mode for the communication device or a portion thereof. Dynamically calculating N. l This may include: (1) determining the implementation count (N); and / or reducing N based on determining a low-power operating mode.

[0012] One or more implementations provide a communication device comprising: at least one circuit configured to derive symbol decoding results from a received multiple-input multiple-output (MIMO) signal for detecting a symbol set; and a controller circuit coupled to the at least one circuit. The at least one circuit may include a layer permutation circuit module configured to process a channel input associated with the received MIMO signal based on variable permutation data. The controller circuit is configured to: (1) dynamically derive an implementation count based on the channel input for adjusting the complexity associated with the detected symbol set; and / or (2) input a modulation symbol vector and a channel input pair for multiple iterations matching the implementation count, wherein a unique instance of the variable permutation data is used for each iteration to derive the symbol decoding result.

[0013] Alternatively or additionally, at least one circuit may include: a decomposition circuit module coupled to a layer permutation circuit module; and a vector decoder coupled to the decomposition circuit module. The decomposition circuit module may be configured to decompose the processing result from the layer permutation circuit module into R-components and Q-components. The vector decoder may be configured to derive symbol decoding results based on the modulation symbol vector, R-components, and Q-components. Additionally, the communication device may further include an output calculator coupled to at least one circuit. The output calculator is configured to generate a detection result set based on the symbol decoding results. In one or more implementations, the vector decoder may correspond to a fixed complexity, and / or the controller circuitry may be configured to dynamically derive implementation counts to dynamically change the overall complexity associated with processing the modulation symbol vector and channel input pair. In some implementations, the vector decoder may be a spherical decoder. Alternatively or additionally, the output calculator is a log-likelihood ratio (LLR) calculator configured according to a log-maximum a posteriori (log-map) mechanism or a max-log-maximum a posteriori (max-log-map) mechanism.

[0014] One or more implementations provide a tangible, non-transitory computer-readable medium storing processor instructions that, when executed by one or more processors, cause the one or more processors to perform a method. The method may include: receiving a wireless signal at a communication device, wherein the wireless signal represents symbols transmitted by an external device via a wireless channel; determining real-time communication parameters associated with the received wireless signal; deriving an implementation count (N) based on the real-time communication parameters; and / or generating a detection result from the wireless signal according to an implementation of a fixed processing function iteratively according to N. Generating the detection result may include: iteratively inputting a modulation symbol vector and a channel input pair into the fixed processing function N times. The fixed processing function may be configured to generate a decoding result for each iteration based on unique variable permutation data corresponding to the implemented iteration. In some implementations, the method may include one or more features described herein. Attached Figure Description

[0015] To more clearly describe the technical solutions in the implementation of this disclosure, the accompanying drawings are briefly described below. The drawings only illustrate some aspects or implementations of this disclosure; those skilled in the art can derive other drawings from these drawings without any inventive effort.

[0016] Figure 1 This is a schematic diagram of a wireless communication system according to one or more implementations of this disclosure.

[0017] Figure 2 This is a schematic block diagram of a transceiver according to one or more implementations of this disclosure.

[0018] Figure 3 This is a schematic block diagram of a first example detector according to one or more implementations of this disclosure.

[0019] Figure 4 This is a schematic block diagram of a second example detector according to one or more implementations of this disclosure.

[0020] Figure 5 This is a schematic block diagram of a third example detector according to one or more implementations of this disclosure.

[0021] Figure 6 It is a schematic flowchart of an example method according to one or more implementations of this disclosure.

[0022] Figure 7 It is a schematic block diagram of a terminal device according to one or more implementations of this disclosure.

[0023] Figure 8 It is a schematic block diagram of a system chip according to one or more implementations of this disclosure.

[0024] Figure 9 It is a schematic block diagram of a communication device according to one or more implementations of this disclosure. Detailed Implementation

[0025] The technical solutions in one or more implementations of this disclosure are described below. A communication system includes a transceiver configured to detect information (e.g., symbols) for a MIMO communication scheme. The transceiver may include a detector (via, for example, hardware circuitry, software, and / or firmware) configured to implement a variable complexity MIMO detection mechanism. Therefore, the detector can determine in real time the complexity associated with each modulation symbol vector (e.g., a representation of a specific symbol value) and process the received radio signals accordingly. The detector can implement a variable complexity MIMO detection mechanism without significantly increasing the detector's complexity, slightly increasing or not increasing the detector buffer, and / or significantly affecting hardware throughput.

[0026] One or more implementations of this disclosure can utilize fixed-complexity processing branches (e.g., hardware circuitry or software routines) to implement a variable-complexity MIMO detection mechanism. For example, a variable-complexity detector may include a set of fixed-complexity detection circuit branches connected in parallel. Alternatively, the variable-complexity detector may iteratively implement the detection process using the set of fixed-complexity detection circuit branches. The variable-complexity detector may include a complexity controller that controls the set of fixed-complexity detection circuit branches, for example, by controlling the number of active branches, the number of iterations, and / or the corresponding processing allocation. The complexity controller can effectively change the configuration of the variable-complexity detector between time intervals based on the data throughput within each time interval, thereby changing the complexity of each received symbol vector and channel matrix pair.

[0027] In the following description, numerous specific details are set forth to provide a thorough understanding of the technology described herein. In other implementations, the technology described herein may be practiced without these specific details. In other instances, well-known features such as specific functions or routines have not been described in detail to avoid unnecessarily obscuring this disclosure. References to “implementation,” “an implementation,” etc., in this specification refer to specific features, structures, materials, or characteristics included in at least one implementation of the described technology. Therefore, such phrases appearing in this specification do not necessarily all refer to the same implementation. On the other hand, these references are not necessarily mutually exclusive. Furthermore, in one or more implementations, specific features, structures, materials, or characteristics can be combined in any suitable manner. It should be understood that the various implementations shown in the figures are merely illustrative representations and are not necessarily drawn to scale.

[0028] For clarity, certain details describing the structure or processes of some important aspects of the disclosed technology that are well-known and generally associated with communication systems and subsystems, but may unnecessarily obscure, are omitted in the following description. Furthermore, while the following disclosure illustrates several implementations of different aspects of this disclosure, several other implementations may have different configurations or components than those described herein. Therefore, the disclosed technology can be implemented in other ways by having additional elements or by omitting some of the elements described below.

[0029] Many implementations or aspects of the techniques described below may take the form of computer or processor executable instructions, including routines executed by a programmable computer or processor. Those skilled in the art will understand that the described techniques can be practiced on computer or processor systems other than those shown and described below. The techniques described herein can be implemented in a dedicated computer or data processor specifically programmed, configured, or constructed to execute one or more of the computer executable instructions described below. Therefore, the terms "computer" and "processor" as commonly used herein refer to any data processor. Information processed by these computers and processors can be presented on any suitable display medium, including liquid crystal displays (LCDs). Instructions for performing computer or processor executable tasks can be stored in or on any suitable computer-readable medium, including hardware, firmware, or a combination of hardware and firmware. Instructions can be contained in any suitable storage device, including, for example, flash drives and / or other suitable media.

[0030] The terms “coupled” and “connected”, and their derivatives, are used herein to describe structural relationships between components. It should be understood that these terms are not intended to be synonyms. Rather, in a particular implementation, “connected” can be used to indicate that two or more elements are in direct contact with each other. Unless explicitly stated otherwise in the context, the term “coupled” can be used to indicate that two or more elements are in direct or indirect contact with each other (through other inserted elements between them), or that two or more elements cooperate or interact with each other (e.g., in a causal relationship, such as for signal transmission / reception or for function calls), or both. The term “and / or” in this specification describes only one type of association between related objects, indicating that three relationships may exist; for example, A and / or B can indicate three cases: A exists alone, both A and B exist, and B exists alone. Additionally, the character “ / ” in this specification generally indicates an “or” relationship between related objects.

[0031] Applicable Environment

[0032] Figure 1 This is a schematic diagram of a wireless communication system 100 according to one or more implementations of this disclosure. For example... Figure 1As shown, the wireless communication system 100 may include network device 110. Network device 110 may include circuitry configured to provide communication coverage to a specific geographic area. Some examples of network device 110 may include: a Base Transceiver Station (BTS), a Node B (NB), an evolved Node B (eNB or eNodeB), a next-generation Node B (gNB or gNode B), and a Wi-Fi access point (AP). Other examples of network device 110 may include a relay station, an access point, a vehicle-mounted device, a wearable device, etc. Network device 110 may include other wireless connectivity devices for communication networks, such as: Global System for Mobile Communications (GSM) networks, Code Division Multiple Access (CDMA) networks, Wideband CDMA (WCDMA) networks, Long-Term Evolution (LTE) networks, cloud radio access networks (CRAN), networks based on Institute of Electrical and Electronics Engineers (IEEE) 802.11 (e.g., WiFi networks), Internet of Things (IoT) networks, device-to-device (D2D) networks, next-generation networks (e.g., fifth-generation (5G) networks), and Public Land Mobile Network (PLMN). Optionally, a 5G system or network may also be referred to as a New Radio (NR) system or network.

[0033] Alternatively or concurrently, the wireless communication system 100 may include terminal device 120. Terminal device 120 may be an end-user device configured to facilitate wireless communication. Terminal device 120 may be configured to wirelessly connect to network device 110 (via, for example, wireless channel 115) according to one or more appropriate communication protocols / standards. Terminal device 120 may be a mobile or fixed terminal device. Terminal device 120 may be an access terminal, user equipment (UE), user unit, user station, mobile site, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user device. Some examples of terminal device 120 may include: cellular phones, smartphones, cordless phones, Session Initiation Protocol (SIP) phones, Wireless Local Loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, wearable devices, IoT devices, terminal devices in future 5G networks, terminal devices in future evolved PLMNs, and so on.

[0034] For illustrative purposes, Figure 1 The wireless communication system 100 is illustrated with network device 110 and terminal device 120. However, it should be understood that the wireless communication system 100 may include additional / other devices, such as additional instances of network device 110 and / or terminal device 120, network controllers, mobility management entities, etc.

[0035] Wireless communication architecture

[0036] Figure 2 This is a schematic block diagram of an example transceiver 200 according to one or more implementations of this disclosure. Transceiver 200 may include devices (e.g., circuitry, software, and / or firmware) configured to transmit and / or receive wireless communication signals. Transceiver 200 may include a transmission path 210 and / or a receiver path 250.

[0037] Transmission path 210 may include circuitry and / or functionality configured to transmit content data 212 (e.g., content intended for transmission, such as voice signals, system / device data, and / or one or more images) to another device. During the transmission of content data 212, transmission path 210 may generate a wireless output signal based on the processing / conversion of the content data 212. Transmission path 210 may include a transmission format module 214, an encoder 216, a transmission condition module 218, and / or a modulator 220.

[0038] The transmission format module 214 may include circuitry and / or functionality configured to rearrange and / or update the transmission content data 212 for transmission. In some implementations, the transmission format module 214 may interleave portions of the transmission content data 212 according to a predetermined format / sequence. Furthermore, the transmission format module 214 may divide the transmission content data 212 into multiple segments (e.g., serial-to-parallel conversion), each segment corresponding to a single data stream for each MIMO communication scheme.

[0039] Encoder 216 may include circuitry and / or functionality configured to change the format of the values ​​of the transmitted content data 212. For example, encoder 216 may encode the formatted data according to one or more encoding mechanisms (e.g., turbo codes, low-density parity-check (LDPC) codes, etc.) to increase robustness and / or recoverability.

[0040] The transmission conditions module 218 may include circuitry and / or functions configured to adjust the transmitted content data 212 or its processing results for wireless transmission. For example, the transmission conditions module 218 may format coded data for beamforming and / or transmission diversity. The transmission conditions module 218 may calculate and apply antenna parameters (e.g., assignment and / or weighting) to achieve diversity and / or directionality using simultaneously transmitted signals.

[0041] Modulator 220 may include circuitry and / or functionality configured to convert the processed result into a wireless signal. Modulator 220 may generate symbols representing the input processed result (e.g., wireless signal amplitude, power, and / or phase). For example, modulator 220 may generate symbols based on an amplitude modulation scheme (e.g., quadrature amplitude modulation (QAM)) or phase-shift keying (PSK) (e.g., QPSK, 16-PSK, etc.). Modulator 220 may further map or assign the signal to a transmission frequency (e.g., a carrier or subcarrier).

[0042] Transmission path 210 and / or receiver path 250 may be coupled to or connected to antenna group 230, which includes a set of transmit antennas and / or receiver antennas. Antenna group 230 may be configured to enable MIMO communication that simultaneously transmits and / or receives wireless signals using multiple antennas. For example, modulator 220 and / or individual drivers may apply voltage, current, and / or power to the antennas according to the modulation output and cause the voltage, current, and / or power to oscillate. Each antenna may be used to transmit a unique data stream. When receiving such a signal, the antenna may receive or detect voltage, current, and / or power oscillations corresponding to the transmitted wireless signal. The measured signal values ​​may be processed by receiver path 250 to recover the transmitted content data 212.

[0043] Receiver path 250 may include circuitry and / or functions configured to receive wireless signals and generate received content data 262. The received content data 262 may be the result of recovering transmitted content data based on wireless signals received via receiver path 250. In practice, receiver path 250 may include circuitry and / or functions configured to reverse the processing of transmission path 210 to recover transmitted content data 212. Furthermore, receiver path 250 may include configurations to cancel or resume... Figure 1 The losses or changes (e.g., inter-symbol interference, inter-carrier interference, inter-device interference, Doppler effect, multipath interference, fading, internal device noise, etc.) caused or introduced by the wireless channel 115. For example, the received wireless signal can be represented as:

[0044] Equation (1): Y = HX + N

[0045] The received wireless signal can be represented as 'Y', while the original transmitted wireless signal can be represented as 'X'. Noise introduced into the received wireless signal can be represented as 'N'. Wireless channel 115 or its effect on the transmitted signal can be represented as 'H'. Receiver path 250 can be configured to remove H from Y and recover X. Receiver path 250 can also be configured to further process X and recover its original format content data.

[0046] Receiver path 250 may include demodulator-detector 254 (“detector 254”), receiver condition module 256, decoder 258, and / or receiver format module 260. Demodulator-detector 254 may be configured to implement functions and / or processes complementary to modulator 220. For example, detector 254 may include circuitry and / or functions configured to isolate or recover baseband signals from the transmission frequency. Detector 254 may be further configured to detect symbols within the output signal (e.g., the received signal) from antenna group 230. The detector may demodulate the detected symbols to generate output data.

[0047] Receiver condition module 256 may be configured to implement functions and / or processes complementary to transmission condition module 218. Receiver condition module 256 may include circuitry and / or functions configured to reverse or remove antenna / transmission data formatting (e.g., beamforming and / or transmission diversity parameters) from detector output.

[0048] Decoder 258 may be configured to implement functions and / or processes complementary to encoder 216. Decoder 258 may include circuitry and / or functions configured to remove additional formatting / data introduced to increase robustness and / or recoverability. In some implementations, decoder 258 may correct errors introduced during wireless communication and / or internal signal processing (e.g., by implementing error-correcting decoding mechanisms).

[0049] Receiver format module 260 can be configured to implement functions and / or processes complementary to transmission format module 214. Receiver format module 260 can interleave the decoder output according to a predetermined format / sequence. For example, receiver format module 260 can combine separate streams or data packets into a single stream / packet, for example, through parallel-to-serial conversion. Therefore, receiver path 250 can generate received content data 262 corresponding to the original content data transmitted by another device.

[0050] Signal detector architecture

[0051] Figure 3 This is a first example detector 300 according to one or more implementations of this disclosure (e.g., Figure 2 A schematic block diagram of an instance of detector 254. The first example detector 300 (“first detector 300”) can initially be configured according to a fixed-complexity detection mechanism, but is used to implement a variable-complexity detection mechanism. Therefore, the first example detector 300, or one or more portions thereof, can serve as the basis for implementing a variable-complexity detection mechanism.

[0052] The first detector 300 may include hardware circuitry, software, and / or firmware that detects transmitted information (e.g., symbols) with a fixed complexity for each modulation symbol vector. For example, an instance of a symbol vector that includes only real components (e.g., no phase-correlated components) may have lower complexity than a vector that includes both real and imaginary parts. Therefore, the first detector 300 may include sufficient resources (e.g., a fixed amount of available memory / buffer size, minimum processing speed, etc.) for processing the most complex scenarios involving modulation symbol vectors.

[0053] The first detector 300 may include a layer permutation module 302, a decomposition module 304, a vector decoder module 306, a buffer 308, and an output calculator 310. In some implementations, the layer permutation module 302, the decomposition module 304, the vector decoder module 306, the buffer 308, and / or the output calculator 310 may be implemented in hardware, such as by an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc. Alternatively, one or more portions of the first detector 300 may be implemented in software or firmware. In some implementations, the layer permutation module 302, the decomposition module 304, the vector decoder module 306, the buffer 308, and / or the output calculator 310 may be configured to implement a K-optimal mechanism utilizing tree search through a breadth-first search strategy.

[0054] The layer permutation module 302 is configured to improve MIMO detection accuracy by processing channel information according to a specific permutation. The layer permutation module 302 can generate a permutation output 314 based on this processing. This processing can be represented as:

[0055]

[0056] For equation (2), the permutation output 314 is obtained from... The channel input 312 is represented by 'H', and the permutation matrix is ​​represented by 'Π'.

[0057] The decomposition module 304 is configured to identify the distinct value components associated with the permutation processing result (e.g., permutation output 314). For example, the decomposition module 304 can implement QR decomposition, which identifies the values ​​corresponding to the upper triangular matrix (R) and the orthogonal matrix (Q). The resulting components may correspond to the amplitude and / or phase parameters of the wireless signal representing different sign values. The decomposition can be expressed as:

[0058]

[0059] In some implementations, the Q component can be an orthogonal matrix, and the R component can be an upper triangular matrix.

[0060] Vector decoder module 306 is configured to compare a portion of the received signal with a set of values ​​in a modulation constellation. In other words, vector decoder module 306 can compare a portion of the received radio signal with values ​​corresponding to a desired symbol set. For comparison, vector decoder module 306 can use symbol vector 320 representing the desired symbol and its QR component. In some implementations, vector decoder module 306 can be configured with a tree-search-based algorithm of fixed complexity (e.g., a radius-based spherical decoder, a K-optimal decoder, and / or other breadth-first decoders) that searches for symbol vectors within a sphere of a predetermined radius surrounding the received signal values. Vector decoder module 306 can analyze symbol vector 320 based on decomposition result 318 to generate symbol comparison result 322. In some implementations, symbol comparison result 322 can represent one or more survival paths, one or more distances (e.g., Euclidean distance or Manhattan distance), and / or other values ​​describing the relationship between survival paths and corresponding symbol values ​​of the received signal according to the decoding mechanism.

[0061] Buffer 308 is configured to temporarily store symbol comparison results 322. Buffer 308 may temporarily store symbol comparison results 322 based on internal processing timing / sequence and / or communication throughput. Based on such timing-related conditions, output calculator 310 can access and process symbol comparison results 322 to generate detection results 324. Output calculator 310 is configured to generate an estimate or determination that the analyzed portion of the radio signal represents an estimated symbol value or was initially transmitted as an estimated symbol value. In some implementations, output calculator 310 may generate detection results 324 as soft detection results (e.g., log-likelihood ratio (LLR)), which represent one or more probabilities or confidence levels associated with the set of symbol values, rather than generating hard detection results that ultimately indicate a symbol value / vector. Soft detection results can be processed by subsequent circuitry / functions to conclude that a portion of the received radio signal corresponds to a determined symbol value / vector.

[0062] Figure 4 This is a schematic block diagram of a second example detector 400 (“second detector 400”) according to one or more implementations of this disclosure. The second detector 400 (e.g., Figure 2 An instance of detector 254 can be a variable complexity detector, configured to utilize the variable complexity of each modulation symbol vector.

[0063] The second detector 400 includes a fixed processing section 401 configured to provide basic detection functionality for implementing a variable complexity detection mechanism. The fixed processing section 401 may include a fixed set of hardware and / or processor functions (e.g., software / firmware routines) configured to analyze the received signal according to predetermined constraints. For example, the second detector 400 may include a set of circuits (i.e., a circuit path) configured to process a unique layer permutation matrix in each iteration. The second detector 400 may iteratively use this single set of circuits to analyze all applicable permutation matrices within a communication time interval. The second detector 400 may be configured to activate (e.g., via bit settings and / or physical switches) a subset of the circuit paths to control variable complexity and process the iteration number and permutation matrix in each iteration. Alternatively or additionally, the second detector 400 may dynamically assign permutation matrices to the active circuit path for the corresponding iteration. Furthermore, the second detector 400 may iteratively utilize multiple circuit paths or subsets thereof to process the received signal. Therefore, the second detector 400 can adjust or control the complexity of each received symbol vector and channel matrix pair based on a control configuration (e.g., by controlling the active processing path (e.g., by bit settings and / or switches), and / or by dynamically controlling the iterative detection process control configuration).

[0064] The fixed processing section 401 can be coupled to a complexity controller 450, which is configured to dynamically control the complexity of the entire detection process, such as the complexity of each received symbol vector and channel matrix pair. The complexity controller 450 can generate / derive a control indicator 452 for adjusting the configuration of the second detector 400 (e.g., path activation, permutation matrix, and / or iteration parameters) and the corresponding complexity.

[0065] Complexity controller 450 can derive control indicator 452 based on real-time parameters or requirements of wireless communication (e.g., data throughput, time interval settings, etc.) and / or the available resources / capacity of second detector 400. In this context, the throughput of the wireless link can vary over time. The time interval used for the wireless link can be fixed, such as a time slot in a fifth-generation (5G) communication protocol, a subframe in a fourth-generation (4G) communication protocol, a transmission time interval (TTI) in a wideband code division multiple access (WCDMA) protocol, a frame in a Wi-Fi protocol, etc. Conversely, the length of time for which a given link configuration supports maximum throughput can be fixed. In 4G and 5G, the allocated total bandwidth can limit the maximum throughput. In 4G and 5G, the aforementioned time interval can be the time during which the transmitter can use a fixed bandwidth. Therefore, complexity controller 450 can dynamically adjust the configuration of second detector 400 to match the throughput of the wireless link and handle the corresponding load within a fixed interval.

[0066] As an illustrative example, when the required total data throughput is slower and / or the time interval is set longer compared to a threshold condition, the complexity controller 450 may derive a control indicator 452 for iteratively detecting symbols using a smaller number of active hardware circuitry paths. The threshold condition may correspond to the processing power of a fixed processing segment 401 or a multiple / fraction thereof. Alternatively, when the required data throughput is faster and / or the time interval is set shorter compared to a threshold condition, the complexity controller 450 may derive a control indicator 452 to reduce or eliminate iterative processing and activate more hardware circuitry paths.

[0067] In some implementations, the complexity controller 450 may derive a control indicator 452 to include an implementation count (N). The implementation count controls the number of permutation-QR decomposition decoder sets, where these sets are allocated to process modulation symbol vector and channel input 312 pairs. The implementation count may be dynamically calculated by the complexity controller 450 and included in the control indicator 452. The complexity controller 450 may derive the implementation count as a maximum integer not greater than the ratio of the maximum throughput (e.g., its capacity) supported by the second detector 400 to the actual network throughput during the current time interval (e.g., at the time of calculation and for the corresponding received signal).

[0068] Fixed processing section 401 may be implemented or used according to control instruction 452. In some implementations, fixed processing section 401 includes layer permutation module 402, decomposition module 404, and vector decoder 406. Complexity controller 450 may control the configuration of layer permutation module 402, decomposition module 404, and / or vector decoder 406, thereby controlling the complexity associated with processing the modulation symbol vector and channel input 312 pairs.

[0069] As an illustrative example, layer permutation module 402 can be configured to process channel information based on specific permutations. Each implementation of fixed processing segment 401 (e.g., each circuit path, each iteration, or a combination thereof) can process a different permutation matrix. In other words, layer permutation modules 4021 to 402 N The implementation can be the hardware, software, and / or firmware as described above. Layer replacement modules 4021 to 402 N Each implementation can generate (e.g., as an intermediate result) variable permutation data 416 (e.g., represented as Π1 to Π). N The variable permutation data 416 is a corresponding variable permutation data in the matrix. In some implementations, the variable permutation data 416 may be pre-calculated and stored in the layer permutation module 402 and / or the complexity controller 450. Alternatively, the variable permutation data 416 may be dynamically calculated based on instantaneous measurements of the channel input 312 (via, for example, layer permutation modules 4021 to 402). NComplexity controller 450 and / or another upstream circuit / function). Therefore, layer substitution module 402 (e.g., layer substitution modules 4021 to 402) N Each implementation of ) can generate a unique instance of finite permutation result 414 based on the corresponding variable permutation data 416 (e.g., finite permutation results 4141 to 414). N (The corresponding one in the middle). Finite permutation results 4141 to 414 N It can be represented as HΠ1 to HΠ N .

[0070] Decomposition module 404 can be configured to identify the different value components associated with the finite permutation result 414. For example, decomposition modules 4041 to 404 N Each implementation can be decomposed into finite permutation results 4141 to 414 N The Q and R components of a corresponding finite permutation result are given. Therefore, the decomposition module 404 can generate a variable decomposition result 418 (represented as Q1R1 to Q). N R N Each variable decomposition result corresponds to a specific implementation.

[0071] Vector decoder 406 can be configured to compare a portion of the received signal with a set of values ​​in the modulation constellation. For example, vector modules 4061 to 406... N Each implementation can yield variable decomposition results from 4181 to 418. N The corresponding variable decomposition result is compared with the symbol vector 320 (via, for example, the spherical decoding mechanism described above). Therefore, the vector decoder 406 can generate N sets of symbol decoding results 422. In some implementations, the vector decoder 406 can operate with a fixed complexity. However, based on the complexity controller 450 and multiple iterations and / or circuit paths, the vector decoder 406 can be used as a component within a variable complexity detector (i.e., the second detector 400).

[0072] Similar to Figure 3Buffers 308 and 408 can temporarily store symbol decoding results 422. In some implementations, the capacity of buffer 408 is larger than that of buffer 308. Since the symbol decoding results 422 can be derived iteratively as described above, buffer 408 can be configured to store a larger amount of data compared to buffer 308, which is configured to store results under maximum throughput conditions. Buffer 408 can transfer the symbol decoding results 422 to the output calculator 410 that generates the detection results 424. In some implementations, the output calculator 410 and the detection results 424 can be the same as the output calculator 310 and the detection results 324, respectively. Alternatively, the capacity of the output calculator 410 (e.g., internal cache, processing speed, corresponding circuit footprint, etc.) can be smaller than that of the output calculator 310 based on the iterative architecture. Therefore, each iterative instance of the detection results 424 can correspond to a portion of the detection results 324. In some implementations, the output calculator 410 can calculate the detection result 424 into an LLR value set based on the log-map or max-log-map mechanism.

[0073] In one or more implementations, one or more derived results can be fed back to the complexity controller 450 and used to derive the control indicator 452. For example, the complexity controller 450 may use the past channel matrix or its eigenvalues, the variable decomposition result 418 or its diagonal elements, the detection result 424, or a combination thereof, to supplement or replace the current channel input 312.

[0074] Traditional fixed-complexity detectors include components / functions with sufficient capacity to support peak throughput requirements. However, the throughput of a wireless link varies over time, for example, due to time-varying fading channels, noise power, and dynamic resource allocation. Therefore, for communications corresponding to lower throughput, some parts of the fixed-complexity detector remain unused or idle. In other words, fixed-complexity detectors typically require additional resources (e.g., internal memory, processing speed, corresponding circuit footprint, etc.) that are not always utilized, leading to inefficiency. Even when fixed-complexity detectors are implemented in software (e.g., via digital signal processors (DSPs), central processing units (CPUs), graphics processing units (GPUs), etc.), a maximum capacity (e.g., million instructions per second (MIPS)) is required to support maximum throughput. As the throughput of the wireless link varies over time, the actual resource consumption (e.g., MIPS) in the processing device also changes.

[0075] In contrast, the second detector 400 can improve efficiency by dynamically controlling the utilization of the fixed processing section 401 through the complexity controller 450. As an illustrative example, in some implementations, the fixed processing section 401 can be implemented as a circuit. To implement the variable complexity mechanism, the complexity controller 450 can iteratively input uniquely paired modulation symbol vectors and channel matrices into the fixed processing section 401 N times. For each iteration, the complexity controller 450 and / or the layer permutation module 402 can use different / corresponding instances of the variable permutation data 416. Alternatively, the fixed processing section 401 can be implemented as a software function set. The complexity controller 450 can call the function set N times using the same modulation symbol vector 320 and channel input 312, but for each function call, a unique / corresponding instance of the variable permutation data 416 is used.

[0076] Figure 5 This is a schematic block diagram of a third example detector 500 (“third detector 500”) according to one or more implementations of this disclosure. The third detector 500 (e.g., Figure 2 An instance of detector 254 can be a variable complexity detector, configured to utilize the variable complexity of each modulation symbol vector. The third detector 500 can be... Figure 4 The second example detector 400 is an alternative implementation.

[0077] The third detector 500 includes a fixed processing section 501 configured to provide basic detection functionality for implementing a variable complexity detection mechanism. The fixed processing section 501 may include a fixed set of hardware and / or processor functions (e.g., software / firmware routines). The fixed processing section 501 can be coupled with… Figure 4 The fixed processing segment 401 is configured similarly. For example, the third detector 500 may include one or more circuit paths, each configured to process a unique layer permutation matrix in each iteration. The third detector 500 may be configured to iteratively implement and / or activate one or more circuit paths to analyze all applicable layer permutations. The fixed processing segment 501 may differ from the fixed processing segment 401, for example, in terms of complexity, size, capacity, etc., corresponding to different implementation details.

[0078] The fixed processing section 501 can be coupled to a complexity controller 550, which is configured to dynamically control the complexity of the entire detection process, such as the complexity of each received symbol vector and channel matrix pair. The complexity controller 550 can generate / derive a control indicator 552, which is used to adjust the configuration of the third detector 500 (e.g., path activation, layer assignment, and / or iteration parameters) and the corresponding complexity.

[0079] The complexity controller 550 can derive control indicators 552 based on real-time parameters or requirements of wireless communication (e.g., data throughput, time interval settings, etc.) and / or the available resources / capacity of the third detector 500. For example, the complexity controller 550 can derive control indicators 552 to divide all pairs of modulation symbol vectors and correlated channel matrices into L groups within a given time interval. Therefore, N of the fixed processing segment 501 can be allocated... l (Where l∈1,...,L) implementations are used to process the l-th pair of modulation symbol vectors and the associated channel matrix. The fixed processing segment 501 may have a complexity, size, capacity, etc., configured according to the total complexity of all pairs of modulation symbol vectors and channel matrices. In other words, the hardware or processor capability can be configured to handle the total complexity of all pairs of modulation symbol vectors and channel matrices. In some implementations, such as for 4G, 5G, or other similar networks, this set may be implemented as component carriers or a fixed bandwidth. The corresponding N can be predetermined or dynamically calculated based on the channel input 312. l A permutation matrix (represented as Π1 to Π) Nl Therefore, N can be... l The group symbol decoding result 522 (e.g., spherical decoding result) is fed to the output calculator 410 (e.g., LLR calculator).

[0080] As an illustrative example, complexity controller 550 can dynamically partition all pairs of symbol vector 320 and channel inputs into multiple sets corresponding to resource allocation parameters (L) for a given time interval. Segment numbers can be included in control indicator 552 and provided to layer permutation module 502. Layer permutation modules 5021 to 502 N Each implementation can generate (e.g., as an intermediate result) variable permutation data 516 (e.g., represented as Π1 to Π). Nl The corresponding variable permutation data in the matrix can be predetermined and stored in the layer permutation module 502 and / or complexity controller 550, or dynamically calculated based on the instantaneous measurement of the channel input 312 (via, for example, the layer permutation module 502, complexity controller 550, and / or another upstream circuit / function). Therefore, each implementation of the layer permutation module 502 (e.g., layer permutation modules 5021 to 502) Nl A unique instance of finite permutation result 514 can be generated based on the corresponding variable permutation data 516 (e.g., finite permutation results 5141 to 514). Nl (A corresponding finite permutation result). Decomposition module 504 can process / decompose variable permutation data 516 to generate variable decomposition result 418. For example, decomposition modules 5041 to 504 Nl Each implementation can be decomposed into finite permutation results 5141 to 514 NlThe real and imaginary parts of a corresponding finite permutation result are used to generate the corresponding variable decomposition result 518Q1R1 to Q. Nl R Nl The variable decomposition result 518 can be obtained by vector decoder 506 (represented as implementation 5061 to 506). Nl Iterative processing is performed to generate symbol decoding result 522.

[0081] Similar to Figure 3 Buffer 308 and / or Figure 4 Buffers 408 and 508 can temporarily store the symbol decoding result 522. In some implementations, the capacity of buffer 508 is smaller than that of buffers 308 and / or 408. Since the symbol decoding result 522 can be derived iteratively as described above, buffer 408 can be configured to store a smaller amount of data compared to buffer 308, which is configured to store the result under the maximum throughput condition. Buffer 508 can transmit the symbol decoding result 522 to the output calculator 410 that generates the detection result 424 as described above.

[0082] In one or more implementations, one or more derived results can be fed back to the complexity controller 550 and used to derive the control indicator 552. For example, the complexity controller 550 can use the past channel matrix or its eigenvalues, the variable decomposition result 518, the detection result 424, or a combination thereof to supplement or replace the current channel input 312.

[0083] In some implementations, the fixed processing segment 501 can be implemented as a circuit. The complexity controller 550 and / or another circuit can then process the set N. l The modulation symbol vector 320 and channel input 312 are input to the fixed processing section 501 N. l Next. For each implementation, a unique instance of the variable permutation data 516 can be used for derivation. Alternatively, the fixed processing segment 501 can be implemented as a set of software functions. Utilizing set N l With the same modulation symbol vector and channel input, this function set can be called / implemented N l Each function call / implementation can derive the symbol decoding result 522 from a unique instance of the variable permutation data 516. The iterative process can be repeated L times to cover all L sets of symbol vectors and associated channel inputs.

[0084] In some implementations, the third detector 500 can be configured to dynamically determine the resource-based count (N). lFor example, complexity controller 550 can be configured in hardware and / or software to dynamically determine resource-based counts based on conditions and constraints associated with MIMO communication. Complexity controller 550 can be configured to determine whether the maximum throughput of the third detector 500 is greater than the maximum throughput of the current radio link and / or whether there are no limitations on receiver power consumption. Therefore, complexity controller 550 can determine that N can be partitioned among newly input pairs of received symbol vectors and channel matrices (e.g., such that N1 + N2 + ... + N). L Less than or equal to the total constraint), and reduce N (by, for example, deriving and using N). l Alternatively, the complexity controller 550 may select the resource-based count N based on certain metrics such as the estimated signal-to-noise ratio (SNR) of the symbol vector and channel matrix pairs. l A smaller instance. The complexity controller 550 can reduce resource-based counts to achieve a higher SNR. In some implementations, the complexity controller 550 can be configured to detect operating modes or conditions that are of greater concern to power consumption, such as when the third detector 500 and / or the corresponding device are operating in a low-power mode. The complexity controller 550 can be configured to reduce the resource-based count N in response to such detection. l This allows the third detector 500 to shut down one or more of the resources. Furthermore, the complexity controller 550 can detect optimal signal conditions (e.g., represented by channel input 312 and / or SNR) based on one or more predetermined thresholds. Therefore, the complexity controller 550 can reduce resource-based counting because a lower error rate can be achieved in detecting optimal signal conditions even with reduced resources.

[0085] Control Flow

[0086] Figure 6 This is a schematic flowchart of example method 600 according to one or more implementations of this disclosure. Method 600 can be used to implement a variable complexity MIMO detection mechanism. Method 600 can be used to operate... Figure 1 Terminal equipment 120 Figure 1 Network equipment 110 Figure 2 transceiver 200 Figure 4 The second detector 400, the third detector 500 and / or other circuits / functions therein.

[0087] At box 602, a receiving device (e.g., transceiver 200 and / or a corresponding wireless device, such as terminal device 120 and / or network device 110) can receive wireless signals. This can be achieved through the methods described above. Figure 2The antenna group 230 receives wireless signals. The received wireless signals may correspond to MIMO signals transmitted by a remote device. Due to... Figure 1 Interference or degradation (e.g., fading) caused by the wireless channel 115 may result in a received wireless signal that differs from the transmitted signal. The transmitted signal may correspond to one or more symbols representing the intended content / payload. The received wireless signal may be processed as described below to detect one or more symbols in order to recover the intended content / payload at the receiving device. Thus, the receiving device can effectively reverse the transmitter processing and / or any effects from the wireless channel 115.

[0088] At box 604, the receiving device may determine one or more real-time communication parameters associated with the received wireless signal. For example, the receiving device may determine... Figure 4 and 5 The channel input 312, and / or the signal quality associated with the received wireless signal (e.g., signal-to-noise ratio (SNR), communication throughput, etc.).

[0089] The channel input 312 and / or signal quality can be determined based on a portion of the received wireless signal, an indicator, a predetermined protocol, or a combination thereof. For example, the received signal may include a reference portion or pilot signal predetermined according to the communication system and / or the corresponding communication protocol / standard. The receiving device can compare the reference portion or pilot signal with predetermined information to determine the channel input 312 and / or signal quality. Furthermore, the received signal may include a feedback indicator (e.g., a channel quality indicator (CQI)) describing the wireless channel 115 according to the transmitting device. The receiving device can use the feedback indicator to determine the channel input 312 and / or signal quality.

[0090] At box 606, the receiving device can dynamically determine the configuration or complexity used to process the received wireless signal. For example, detectors 400 / 500 (e.g., Figure 4 Complexity controller 450 and / or Figure 5 The complexity controller 550 can be exported. Figure 4 Control indicator 452 Figure 5 Control indicator 552, Implementation count (N), Resource allocation (L), Resource-based count (N) l ( ), time intervals, and / or other parameters mentioned above. The receiving device may derive one or more indicators / parameters based on the device's real-time parameters and / or available resources / capacity.

[0091] As an illustrative example, complexity controllers 450 / 550 may dynamically derive control indicators 452 / 552 based on comparing real-time parameters with one or more corresponding thresholds. In some implementations, complexity controllers 450 / 550 may compare wireless communication throughput with one or more thresholds to determine an implementation count N. Alternatively or additionally, complexity controllers 450 / 550 may include a predetermined value for resource allocation L. Complexity controllers 450 / 550 may derive a resource-based count N based on the implementation count N and resource allocation L, for example, according to a predetermined equation or procedure. l .

[0092] In one or more implementations, the complexity controller 550 can determine whether the maximum throughput of the third detector 500 is greater than the maximum throughput of the current wireless link and / or whether there is no limitation on receiver power consumption. The complexity controller 550 can determine that N can be partitioned between the newly input received symbol vector and channel matrix pairs and reduce the implementation count N, for example, by deriving and using a resource-based count N. l Instead of deriving and using the implemented count N, the detector can dynamically select and implement the second detector 400 or the third detector 500 based on real-time communication parameters.

[0093] Alternatively, the complexity controller may select a resource-based count N based on certain metrics such as the SNR of the symbol vector and channel matrix input 312 pairs. l A smaller instance. The complexity controller can derive a resource-based count N. l A smaller value is obtained to achieve a higher SNR. Furthermore, the complexity controller can detect optimal signal conditions (e.g., represented by channel input 312 and / or SNR) based on one or more predetermined thresholds. Therefore, the complexity controller 550 can reduce the resource-based count N. l In some implementations, the complexity controller can be configured to detect operating modes or conditions that are of greater concern to power consumption, such as when the detector and / or the corresponding device are operating in a low-power mode. The complexity controller can be configured to reduce the resource-based count N in response to such detection. l This allows the detector to shut down one or more of the resources.

[0094] At box 608, the receiving device can detect symbols based on dynamically determined configuration / complexity. For example, the second detector 400 and / or the third detector 500 can implement corresponding fixed processing segments 401 / 501 according to control instructions 452 / 552. Therefore, the detectors can generate... Figure 4 and Figure 5 The detection result 424 corresponds to the estimation of the original transmitted symbols from the remote device.

[0095] At box 620, the variable complexity detector can be configured dynamically. In some implementations, the complexity controller 450 / 550 can be configured based on an implementation count N or a resource-based count N. l To implement fixed processing sections 401 / 501 (e.g., one or more hardware circuits and / or software functions). At block 622, a detector (e.g., at complexity controllers 450 / 550 and / or layer permutation modules 402 / 502) identifies variable permutation data 416 / 516 for processing the received signal. The detector identifies a unique instance of the variable permutation data 416 / 516, each variable permutation data corresponding to an implementation / iteration. At block 624, the detector (e.g., at layer permutation modules 402 / 502) computes a permutation result (e.g., finite permutation result 414 / 514) based on the identified variable permutation data. The detector can compute the permutation result through multiple implementations. For each iteration, layer permutation modules 402 / 502 computes an instance or result set based on the unique instance of the variable permutation data 416 / 516, channel input 312, and / or one or more of the above processing results. At block 626, the detector (e.g., at decomposition modules 404 / 504) decomposes the permutation result. For example, decomposition modules 404 / 504 can generate variable decomposition results 418 / 518, each corresponding to the Q and R components of the input permutation result 414 / 514. At block 628, a detector (e.g., at vector decoder 406 / 506) can process the symbol vector based on the decomposition results. For example, vector decoder 406 / 506 (e.g., a spherical decoder) can generate symbol decoding results 422 / 522 based on the variable decomposition results 418 / 518 as described above. One or more processing results can be used to dynamically determine the configuration / complexity of the latter part of the current time interval and / or one or more subsequent time intervals.

[0096] At block 610, the detector can detect symbols. For example, the detector can use the buffers 408 / 508 and output calculator 410 as described above to process the symbol decoding results 422 / 522 and generate a detection result 424. In some implementations, the detection result 424 may include a soft result. Therefore, the detector may include hard decision circuitry to detect or determine symbols based on the soft result.

[0097] At box 612, the receiving device can recover / process the originally transmitted content based on the detected symbols. For example, the receiving device can use... Figure 2 The receiver path 250 is used to recover / process content data 262.

[0098] Exemplary devices and systems

[0099] Figures 7 to 9 This illustrates the inclusion of or contain of variable complexity detectors (e.g., Figure 4 The second detector 400 and / or Figure 5 Example devices and systems of the third detector (500).

[0100] Figure 7 Terminal device 700 according to one or more implementations of this disclosure (e.g., Figure 1 A schematic block diagram of an example of terminal device 120. Figure 7 As shown, the terminal device 700 includes a processing unit 710 (e.g., used as...). Figure 2 The transceiver 200 (or a portion thereof, such as a DSP, CPU, GPU, etc.) and memory 720. The processing unit 710 can be configured to implement a transceiver 200 or a portion thereof, such as a DSP, CPU, GPU, etc., and memory 720. Figure 6 Method 600 and / or other instructions of the above implementation.

[0101] Figure 8 The system-on-a-chip 800 is based on one or more implementations of this disclosure (e.g., Figure 1 Terminal equipment 120 and / or Figure 1 A schematic block diagram of the components within the network device 110. Figure 8 The system-on-a-chip 800 includes an input interface 801, an output interface 802, a processor 803, and a memory 804 (e.g., a non-transitory computer-readable medium) that can be connected via internal communication lines, wherein the processor 803 is configured to execute code in the memory 804. The memory 804 may include code corresponding to... Figure 6 The processor 803 can implement method 600 and / or other aspects of the above implementation.

[0102] Figure 9 A communication device 900 according to one or more implementations of this disclosure (e.g., Figure 1 Terminal equipment 120 and / or Figure 1 A schematic block diagram of a network device 110 (an example). The communication device 900 may include a processor 910 and a memory 920. The memory 920 may store program code, and the processor 910 may execute the program code stored in the memory 920. The memory 920 may include components corresponding to… Figure 6 The processor 910 can implement method 600 and / or other aspects of the above implementation.

[0103] Optionally, the communication device 900 may include a transceiver 930 (e.g., Figure 2(An example of transceiver 200). Transceiver 930 may be configured (through, for example, hardware circuitry, software code from memory 920, and / or firmware) to implement method 600 and / or other aspects of the above implementations.

[0104] It should be understood that the processor in the implementation of this technology can be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above method can be implemented through integrated logic circuits in the processor's hardware or through software instructions. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the implementation of this technology. The general-purpose processor can be a microprocessor, or alternatively, it can be any conventional processor. The steps of the methods disclosed in the implementation of this technology can be directly embodied in the execution of a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0105] It is understood that the memory in this implementation can be volatile memory or non-volatile memory, or may include both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate Synchronous DRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0106] Complexity controllers 450 / 550, control indicators 452 / 552, fixed processing segments 401 / 501, variable permutation data 416 / 516, or combinations thereof, enable the practical implementation of variable complexity MIMO detection. Through adjustable configuration, the second detector 400 and the third detector 500 can fully utilize hardware or processor capabilities. The second detector 400 and the third detector 500 can utilize hardware of fixed complexity to achieve and provide fixed throughput within a time interval, without the hardware capacity traditionally required for variable complexity MIMO detection due to the number of symbols per time interval (i.e., tens or hundreds of symbols per time interval).

[0107] in conclusion

[0108] The specific embodiments of the disclosed technology described above are not intended to be exhaustive or to limit the disclosed technology to the precise forms disclosed above. While specific examples of the disclosed technology have been described above for illustrative purposes, various equivalent modifications can be made within the scope of the described technology, as will be appreciated by those skilled in the art. For example, although processes or blocks are presented in a given order, alternative implementations may execute routines with steps, or employ systems with blocks in different orders, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternatives or sub-combinations. Each of these processes or blocks can be implemented in various different ways. Furthermore, although processes or blocks are sometimes shown as being executed serially, alternatively, these processes or blocks may be executed or implemented in parallel, or may be executed at different times. Moreover, any specific numbers mentioned herein are merely examples; alternative implementations may employ different values ​​or ranges.

[0109] Based on the above specific embodiments, these and other changes can be made to the disclosed technology. While this specific embodiment describes certain examples of the disclosed technology and the contemplated best mode, the disclosed technology can be implemented in a variety of ways, no matter how detailed the above description appears in the text. The details of the system may vary considerably in its specific implementation, but are still covered by the technology disclosed herein. As stated above, specific terms used in describing certain features or aspects of the disclosed technology should not be construed as implying a redefinition of those terms herein, but rather as limiting them to any particular characteristic, feature, or aspect of the disclosed technology associated with those terms. Therefore, the invention is not limited except by the appended claims. Generally, the terms used in the following claims should not be construed as limiting the disclosed technology to the specific examples disclosed in the specification, unless these terms are expressly defined in the above specific embodiments section.

[0110] Those skilled in the art will recognize that the examples, units, and algorithm steps described in conjunction with the implementations disclosed in this specification can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the function is executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0111] While certain aspects of the invention are presented below in the form of certain claims, the applicant considers all aspects of the invention in any number of claims. Therefore, the applicant reserves the right to add appended claims after the filing of this application, in the form of such appended claims in this application or a subsequent application.

Claims

1. A method for operating a communication device, the method comprising: The communication device receives wireless signals, wherein the wireless signals represent symbols transmitted by an external device via a wireless channel; Determine the real-time communication parameters associated with the received wireless signals; Derive control indicators based on the real-time communication parameters; and Using a detector, a detection result is generated from the wireless signal according to the control indicator and the corresponding configuration, wherein the detection result estimates the symbol sent by the external device; The control indicator variably controls the configuration of the detector to variably control the complexity measurement associated with generating the detection result; The generation of the detection result includes: implementing a fixed processing segment according to the implementation count N indicated by the control indicator; The detector includes at least a first circuit and a second circuit, the first circuit and the second circuit having matching hardware configurations, wherein the first circuit includes the fixed processing section; Implementing the fixed processing segment includes: The first circuit and the second circuit shall be implemented in parallel at least; The modulation symbol vector and channel input pair are simultaneously input into the first circuit and the second circuit; and At each of the first and second circuits, the channel input and the modulation symbol vector are processed according to the corresponding unique variable permutation data.

2. The method according to claim 1, wherein, The fixed processing segment corresponds to a fixed complexity; The implementation count N corresponds to the number of iterations in the parallel or serial implementation; and For each iteration, the fixed processing segment is configured to generate a decoding result based on unique variable permutation data corresponding to the implemented iteration.

3. The method according to claim 2, wherein: The fixed processing section includes circuitry configured by hardware to generate the decoding result; Implementing the fixed processing segment includes: The modulation symbol vector and channel input pair are input into the fixed processing segment N times in iterations; as well as The channel input and the modulation symbol vector are processed based on the unique variable permutation data corresponding to the implemented iteration.

4. The method according to claim 2, wherein: The fixed processing section includes a set of software functions configured to generate the decoding result; Implementing the fixed processing segment includes: The software function set is implemented N times iteratively using the modulation symbol vector and channel input pair as input to the fixed processing segment; as well as The channel input and the modulation symbol vector are processed based on the unique variable permutation data corresponding to the implemented iteration.

5. The method according to claim 2, wherein, Each implementation of the fixed processing segment includes applying a unique portion of the permutation dataset to the channel input.

6. The method according to claim 5, wherein, Generating the detection results through N iterations includes iteratively processing the entire permutation dataset.

7. The method according to claim 2, further comprising: Calculate the channel input to estimate one or more effects of the wireless channel and the symbol; as well as The fixed processing segment includes generating finite permutation results for each iteration based on the channel input and the unique variable permutation data corresponding to the implemented iteration.

8. The method according to claim 7, wherein, Implementing the fixed processing segment includes: for each iteration, Based on the analysis of the finite permutation results, QR decomposition results are generated; and Generate a symbol decoding result set based on a fixed-complexity decoding mechanism.

9. The method according to claim 8, wherein: The symbol decoding result set includes one or more survival paths and / or one or more distances; as well as Generating the detection results includes: By iteratively implementing the fixed processing segment, N symbol decoding result sets are generated; and Based on the N symbol decoding result set, calculate the log-likelihood ratio (LLR) value set, wherein the LLR value set includes the detection results.

10. The method according to claim 1, further comprising: Calculate the channel input to estimate one or more effects of the wireless channel and the symbol; A set of channel input and symbol pairs is divided into L groups, where L corresponds to the resource-based count N. l Resource allocation; in: Derivation of the control indicator includes: dynamically calculating N associated with the first channel input set to the l-th channel input set. l ; Generating the detection result includes: based on N indicated by the control indicator. l To implement a fixed processing segment, wherein: The fixed processing segment corresponds to the capacity associated with the resource allocation; N l The number of iterations corresponding to parallel or serial implementations; and For each iteration, the fixed processing segment is configured to generate a decoding result based on unique variable permutation data corresponding to the implemented iteration.

11. The method according to claim 10, wherein, Dynamic calculation of N l include: Determine the implementation count N; and Based on the comparison with the total constraints, reduce N.

12. The method of claim 10, further comprising: The signal quality is determined based on the channel input; Among them, N is calculated dynamically. l include: Determine the implementation count N; and Based on the signal quality, reduce N.

13. The method of claim 10, further comprising: Determine the low-power operating mode of the communication device or a portion thereof; Among them, N is calculated dynamically. l include: Determine the implementation count N; and Based on the determination of the low-power operating mode, N is reduced.

14. A communication device, comprising: At least one circuit is configured to derive symbol decoding results from a received multiple-input multiple-output (MIMO) signal for symbol set detection, wherein the at least one circuit includes a layer permutation circuit module configured to process a channel input associated with the received MIMO signal based on variable permutation data; and A controller circuit, coupled to the at least one circuit, is configured to: Implementation counts are dynamically derived based on the channel input to adjust the complexity associated with detecting the symbol set; these implementation counts are used to implement fixed processing segments; and Input modulation symbol vectors and channel input pairs for multiple iterations matching the implementation count, wherein unique variable permutation data is used in each iteration to derive the symbol decoding result; Wherein, the at least one circuit includes at least a first circuit and a second circuit, the first circuit and the second circuit having matching hardware configurations, the first circuit including the fixed processing section; wherein, the first circuit and the second circuit are configured to: The first circuit and the second circuit shall be implemented in parallel at least; Receive the simultaneously input modulation symbol vector and channel input pair, and At each of the first and second circuits, the channel input and the modulation symbol vector are processed according to the corresponding unique variable permutation data.

15. The communication device according to claim 14, wherein, The at least one circuit includes: A decomposition circuit module, coupled to the layer permutation circuit module, the decomposition circuit module being configured to decompose the processing result from the layer permutation circuit module into R components and Q components; and A vector decoder, coupled to the decomposition circuit module, is configured to derive the symbol decoding result based on the modulation symbol vector, the R component, and the Q component; and The communication device also includes: An output calculator, coupled to the at least one circuit, is configured to generate a set of detection results based on the symbol decoding results.

16. The communication device according to claim 15, wherein: The vector decoder corresponds to a fixed complexity. as well as The controller circuitry is configured to dynamically derive the implementation count to dynamically change the overall complexity associated with processing the modulation symbol vector and channel input pair.

17. The communication device according to claim 16, wherein, The vector decoder is a MIMO decoder.

18. The communication device according to claim 15, wherein, The output calculator is a log-likelihood ratio (LLR) calculator, which is configured based on either the log-maximum a posteriori (log-map) mechanism or the maximum log-maximum a posteriori (max-log-map) mechanism.

19. A tangible, non-transitory computer-readable medium storing processor instructions thereon, wherein, when executed by one or more processors, the processor instructions cause the one or more processors to perform a method, the method comprising: Receive wireless signals at a communication device, wherein the wireless signals represent symbols transmitted by an external device through a wireless channel; Determine the real-time communication parameters associated with the received wireless signals; The count N is derived based on the real-time communication parameters; and A detection result is generated from the wireless signal by iteratively implementing a fixed processing function according to N. in: Generating the detection result includes: iteratively inputting the modulation symbol vector and channel input pair into the fixed processing function N times; and The fixed processing function is configured to generate a decoding result for each iteration based on unique variable permutation data corresponding to the implemented iteration; The fixed processing function is implemented by at least a first circuit and a second circuit, the first circuit and the second circuit having matching hardware configurations; Implementing the fixed processing function includes: The first circuit and the second circuit can be used in parallel at least. The modulation symbol vector and channel input pair are simultaneously input into the first circuit and the second circuit, and At each of the first and second circuits, the channel input and the modulation symbol vector are processed according to the corresponding unique variable permutation data.

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