Display substrate and manufacturing method thereof, and display device

Abstract

The embodiments of the present application provide a display substrate, a method for manufacturing the same, and a display device, belonging to the field of display devices. The display substrate includes a display area and a wiring area. The display substrate comprises: a substrate; a first gate layer disposed on one side of the substrate; and a source-drain metal layer disposed on a side of the first gate layer facing away from the substrate. The source-drain metal layer comprises a stacked first metal layer, a second metal layer, and a third metal layer; wherein the orthographic projections of the first metal layer and / or the third metal layer on the substrate do not overlap with the wiring area. The display substrate, a method for manufacturing the same, and a display device provided by the embodiments of the present application can reduce the height of the wiring area and reduce the occurrence of metal cracks and corrosion.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of display devices, and more specifically, to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Currently, OLED products are developing towards narrow bezels, high frequencies, and large sizes. To address these issues, new metal traces need to be added to achieve narrow bezel output and reduce transmission signal delay time and voltage drop.

[0003] However, when a new metal layer is added for routing, the wiring area of ​​the display substrate also faces the risk of increasing in height. When the height of the wiring area increases, cracks may easily appear on the edge of the wiring area. Summary of the Invention

[0004] The embodiments of the present application provide a display substrate and a method for preparing the same, as well as a display device, in order to reduce the height of the wiring area and the occurrence of metal cracks and corrosion.

[0005] A first aspect of an embodiment of the present application provides a display substrate, the display substrate comprising a display area and a wiring area, the display substrate comprising:

[0006] substrate;

[0007] a first gate layer, disposed on one side of the substrate;

[0008] a source-drain metal layer, arranged on a side of the first gate layer facing away from the substrate, the source-drain metal layer comprising a first metal layer, a second metal layer, and a third metal layer stacked;

[0009] The orthographic projections of the first metal layer and / or the third metal layer on the substrate do not overlap with the wiring area.

[0010] Optionally, the first metal layer serves as a source / drain of the display substrate and is connected to the active layer of the display substrate;

[0011] The third metal layer serves as a first transfer electrode of the display substrate, and is used to connect the first metal layer and the second metal layer;

[0012] The second metal layer serves as a second switching electrode of the display substrate, and is used to connect the third metal layer and the pixel electrode of the display substrate.

[0013] Optionally, the orthographic projection of the first metal layer on the substrate overlaps with the wiring area, and the display substrate further includes:

[0014] A passivation layer is provided between the first metal layer and the second metal layer, wherein an orthographic projection of the passivation layer on the substrate at least partially overlaps with an orthographic projection of the first metal layer on the substrate.

[0015] Optionally, the display substrate further includes:

[0016] A touch metal layer is provided on a side of the source and drain metal layer away from the first gate layer, and an orthographic projection of the touch metal layer on the substrate overlaps with the wiring area.

[0017] Optionally, the display substrate further includes:

[0018] An insulating layer is provided between the first gate layer and the source / drain metal layer, wherein an orthographic projection of the insulating layer on the substrate overlaps with the wiring region.

[0019] Optionally, the display substrate further includes:

[0020] A planar layer is provided on a side of the source / drain metal layer away from the first gate layer, and the planar layer is located between the touch metal layer and the source / drain metal layer, and an orthographic projection of the planar layer on the substrate overlaps with the wiring area.

[0021] Optionally, the display substrate further includes:

[0022] A touch insulating layer is provided between the touch metal layer and the planar layer, and an orthographic projection of the touch insulating layer on the substrate overlaps with the wiring area.

[0023] Optionally, in the wiring region, an orthographic projection of the planar layer on the substrate at least partially overlaps with an orthographic projection of the second metal layer on the substrate.

[0024] Optionally, in the wiring area, an orthographic projection of the touch insulating layer on the substrate at least partially overlaps with an orthographic projection of the second metal layer on the substrate.

[0025] Optionally, in the wiring area, the touch metal layer is in direct contact with at least a portion of the source and drain metal layer.

[0026] Optionally, in the wiring region, the source and drain metal layer is in direct contact with at least a portion of the first gate layer.

[0027] Optionally, in the wiring region, an orthographic projection of the source and drain metal layer on the substrate covers an orthographic projection of the first gate layer on the substrate.

[0028] Optionally, in the wiring region, the second metal layer is in direct contact with at least a portion of the first gate layer;

[0029] Alternatively, the second metal layer is in direct contact with at least a portion of the first metal layer;

[0030] Alternatively, the second metal layer is in direct contact with at least a portion of the third metal layer.

[0031] A second aspect of the embodiments of the present application provides a display device, comprising the display substrate provided in the first aspect of the embodiments of the present application.

[0032] A third aspect of an embodiment of the present application provides a method for preparing a display substrate, wherein the display substrate includes a display area and a wiring area. The method includes:

[0033] providing a substrate;

[0034] forming a first gate layer on the substrate;

[0035] forming a source-drain metal layer on a side of the first gate layer facing away from the substrate, the source-drain metal layer comprising a first metal layer, a third metal layer, and a second metal layer that are stacked;

[0036] The orthographic projections of the first metal layer and / or the third metal layer on the substrate do not overlap with the wiring area.

[0037] Beneficial effects:

[0038] The present application provides a display substrate and a preparation method thereof, and a display device, wherein a display substrate including a substrate, a first gate layer and a source-drain metal layer is provided, wherein the source-drain metal layer includes a first metal layer, a third metal layer and a second metal layer arranged in a stacked manner, and the orthographic projection of the first metal layer and / or the third metal layer on the substrate does not overlap with the wiring area of ​​the display substrate. That is, by reducing the number of source-drain metal layers located in the wiring area, the height of the wiring area of ​​the display substrate can be reduced, thereby reducing the occurrence of metal cracks and corrosion in the wiring area. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 This is a schematic diagram of a planar structure of a display substrate proposed in one embodiment of the present application;

[0041] Figure 2 This is a schematic side structural diagram of a display substrate proposed in one embodiment of the present application;

[0042] Figure 3 This is a schematic structural diagram of a display substrate including two layers of metal wiring in a wiring area, proposed in one embodiment of the present application;

[0043] Figure 4 This is a schematic structural diagram of another display substrate including two layers of metal wiring in a wiring area proposed in one embodiment of the present application;

[0044] Figure 5 This is a schematic structural diagram of a display substrate including a layer of metal wiring in a wiring area, proposed in one embodiment of the present application;

[0045] Figure 6 This is a flowchart of a method for preparing a display substrate according to an embodiment of the present application;

[0046] Figure 7 This is a structural schematic diagram of a method for preparing a display substrate according to an embodiment of the present application;

[0047] Figure 8 This is a structural diagram of a method for preparing a display substrate according to an embodiment of the present application, in which the first gate layer is produced;

[0048] Figure 9 This is a structural schematic diagram of completing the production of an insulating layer in a method for preparing a display substrate proposed in one embodiment of the present application;

[0049] Figure 10 This is a structural schematic diagram of a method for preparing a display substrate according to an embodiment of the present application, in which the first metal layer is produced;

[0050] Figure 11 This is a structural schematic diagram of completing insulating layer etching in a method for preparing a display substrate proposed in one embodiment of the present application;

[0051] Figure 12 This is a structural schematic diagram of a method for preparing a display substrate according to an embodiment of the present application, in which the third metal layer is produced;

[0052] Figure 13 This is a structural schematic diagram of a method for preparing a display substrate according to an embodiment of the present application, in which the second metal layer is produced;

[0053] Figure 14 This is a structural diagram of a method for preparing a display substrate according to an embodiment of the present application, in which a flat layer and a touch insulating layer are produced;

[0054] Figure 15 This is a structural diagram of completing the fabrication of a touch metal layer in a method for preparing a display substrate proposed in one embodiment of the present application;

[0055] Figure 16 This is a schematic structural diagram of a method for preparing a display substrate according to an embodiment of the present application, in which a passivation layer is produced;

[0056] Figure 17 This is a schematic structural diagram of a method for preparing a display substrate according to an embodiment of the present application, in which a passivation layer and a third metal layer are fabricated;

[0057] Figure 18 This is a structural schematic diagram of completing etching of a passivation layer and a first metal layer in a method for preparing a display substrate proposed in one embodiment of the present application;

[0058] Figure 19 This is a structural schematic diagram of completing the production of the third metal layer in a method for preparing a display substrate proposed in one embodiment of the present application.

[0059] Explanation of the accompanying drawings: 10. Substrate; 101. Polyimide layer; 102. Buffer layer; 11. First gate layer; 12. Insulation layer; 13. Source and drain metal layer; 131. First metal layer; 132. Second metal layer; 133. Third metal layer; 14. Passivation layer; 15. Flat layer; 16. Touch insulation layer; 17. Touch metal layer; 18. Active layer; 19. Second gate layer. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0061] In the related art, a display panel with three layers of metal wiring includes a first metal layer, a third metal layer and a second metal layer, wherein the first metal layer (SD1) is electrically connected to the active layer of the display panel and serves as the source and drain of the thin film transistor, while the third metal layer (SDM) and the second metal layer (SD2) serve as transfer electrodes, respectively, connecting the first metal layer to the pixel electrode of the light-emitting layer of the display substrate, thereby realizing control of the light emission of the pixel electrode.

[0062] The addition of additional metal trace layers results in a larger number of film layers stacked in the wiring area of ​​the display substrate, increasing the height of the wiring area. This also creates excessive protrusions within the wiring area, making these areas susceptible to cracks or corrosion during later processing. Furthermore, the high height of the wiring area can also lead to residual planarization film material between the wiring areas, making it easy for moisture to flow between them and increasing reliability risks.

[0063] In view of this, the embodiments of the present application provide a display substrate, a preparation method thereof, and a display device, by providing a display substrate including a substrate 10, a first gate layer 11, and a source-drain metal layer 13, wherein the source-drain metal layer 13 includes a first metal layer 131, a third metal layer 133, and a second metal layer 132 arranged in a stacked manner, and the orthographic projection of the first metal layer 131 and / or the third metal layer 133 on the substrate 10 does not overlap with the wiring area of ​​the display substrate, that is, by reducing the number of source-drain metal layers 13 located in the wiring area, the height of the wiring area of ​​the display substrate can be reduced, thereby reducing the occurrence of metal cracks and corrosion in the wiring area.

[0064] Reference Figure 1 As shown in FIG, a display substrate disclosed in an embodiment of the present application includes a display area, a bending area, and a wiring area. The display area refers to the area of ​​the display substrate used for emitting light and displaying content. The light provided by the light-emitting layer will be emitted from the display area. The wiring area is used to connect with the IC (Integrated Circuit Chip) and supply power to the entire display substrate. There are generally multiple wiring areas. At the same time, as Figure 2 As shown, after the display substrate is bent, the wiring area is located on the back side of the display substrate.

[0065] Reference Figure 3 , which is a schematic structural diagram of a display substrate in a wiring area disclosed in an embodiment of the present application, wherein the display substrate includes, from bottom to top, a substrate 10 , a first gate layer 11 and a source / drain metal layer 13 .

[0066] Specifically, substrate 10 can be a flexible substrate or a rigid substrate. A flexible substrate can make the display panel bendable or foldable; a rigid substrate can meet the rigidity requirements of the display panel. The specific performance of substrate 10 is determined based on the actual needs of the product.

[0067] In addition, the substrate 10 may include a single-layer structure or a multi-layer structure. Figure 7 As shown, the substrate 10 may include a polyimide layer 101 and a buffer layer 102 stacked in sequence. In other embodiments, the substrate 10 may also include multiple polyimide layers 101 and buffer layers 102 stacked in sequence. The buffer layer 102 may be made of materials such as silicon nitride or silicon oxide to effectively block water, oxygen, and alkaline ions. It should be noted that the structure of the substrate 10 is not limited to this and can be determined based on actual application needs.

[0068] Reference Figure 3As shown, a first gate layer 11 is provided on one side of a substrate 10. Prior to forming the first gate layer 11, an active layer and an insulating layer 12 are typically formed on the substrate 10. Furthermore, in a display substrate, the display substrate may further include a second gate layer and an insulating layer provided between the first gate layer 11 and the second gate layer. The relevant structures are all existing in the related art and will not be described in detail in the embodiments of this application. The orthographic projections of the active layer and the second gate layer on the substrate 10 do not overlap with the wiring region.

[0069] The source-drain metal layer 13 is disposed on the side of the first gate layer 11 facing away from the substrate 10. Specifically, in the embodiment of the present application, the source-drain metal layer 13 includes a first metal layer 131, a second metal layer 132, and a third metal layer 133, wherein the third metal layer 133 is disposed between the first metal layer 131 and the second metal layer 132. The first metal layer 131 serves as the source and drain of the thin film transistor and is connected to the active layer of the display substrate. The third metal layer 133 serves as the first transfer electrode of the display substrate and is connected to the first metal layer 131. The second metal layer 132 serves as the second transfer electrode of the display substrate and is connected to the third metal layer 133. It is also connected to the pixel electrode of the display substrate, thereby achieving light emission control of the pixel electrode.

[0070] Furthermore, in order to reduce the height of the wiring area, refer to Figure 3-Figure 5 As shown, the orthographic projection of the first metal layer 131 and / or the third metal layer 133 on the substrate 10 does not overlap with the wiring area. That is, the distribution of the source and drain metal layer 13 in the wiring area of ​​the display substrate includes three cases. The first case, referring to Figure 3 As shown, the orthographic projection of the first metal layer 131 on the substrate 10 does not overlap with the wiring area; in the second case, refer to Figure 4 As shown, the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the wiring area; in the third case, refer to Figure 5 As shown, the orthographic projections of the first metal layer 131 and the third metal layer 133 on the substrate 10 do not overlap with the wiring area.

[0071] By ensuring that the orthographic projections of the first metal layer 131 and / or the third metal layer 133 on the substrate 10 do not overlap with the wiring area of ​​the display substrate, that is, by reducing the number of source and drain metal layers 13 located in the wiring area, the height of the wiring area of ​​the display substrate can be lowered, thereby reducing the occurrence of metal cracks and corrosion in the wiring area.

[0072] Below, the embodiments of the present application will respectively explain the formation process of these three situations.

[0073] When the orthographic projection of the first metal layer 131 on the substrate 10 does not overlap with the wiring area, the orthographic projections of the third metal layer 133 and the second metal layer 132 on the substrate 10 overlap with the wiring area.

[0074] Specifically, when preparing the display substrate, after the first gate layer 11 is formed on the substrate 10, the first metal layer 131 is formed on the side of the first gate layer 11 facing away from the substrate 10, and then the first metal layer 131 located in the wiring area is completely etched, so that the first metal layer 131 within the wiring area is not retained, and then the third metal layer 133 and the second metal layer 132 are formed in sequence on the first metal layer 131, and the third metal layer 133 and the second metal layer 132 located in the wiring area are retained. In this way, the first metal layer 131 does not exist within the wiring area, thereby reducing the number of stacked film layers in the wiring area and reducing the overall height of the wiring area.

[0075] It should be noted that, referring to Figure 3 As shown, before forming the first metal layer 131, an insulating layer 12 is typically formed on the side of the first gate layer 11 facing away from the substrate 10. That is, in the overall structure, the insulating layer 12 is located between the first gate layer 11 and the source / drain metal layer 13. Furthermore, within the wiring region, the insulating layer 12 corresponding to the position of the first gate layer 11 needs to be etched so that the third metal layer 133 in the source / drain metal layer 13 is in direct contact with at least a portion of the first gate layer 11, forming an electrical connection. Simultaneously, the second metal layer 132 is also in direct contact with at least a portion of the third metal layer 133, forming an electrical connection.

[0076] When the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the wiring area, that is, the orthographic projections of the first metal layer 131 and the second metal layer 132 on the substrate 10 overlap with the wiring area.

[0077] Specifically, refer to Figure 4 As shown, when preparing the display substrate, after forming the first gate layer 11, a first metal layer 131 is formed on the side of the first gate layer 11 facing away from the substrate 10. Subsequently, a passivation layer 14 is formed on the side of the first metal layer 131 facing away from the first gate layer 11. The passivation layer 14 is retained in the wiring area. Then, a third metal layer 133 is formed on the side of the passivation layer 14 facing away from the first metal layer 131, and the third metal layer 133 within the wiring area is etched. Due to the protection of the passivation layer 14, the first metal layer 131 is not damaged by the etching gas of the third metal layer 133 during the etching process of the third metal layer 133. Finally, a second metal layer 132 is formed on the side of the third metal layer 133 facing away from the first metal layer 131. At the same time, the first metal layer 131 is in direct contact with at least a portion of the first gate layer 11 to form an electrical connection.

[0078] It should be noted that when etching the third metal layer 133 in the wiring area, the passivation layer 14 corresponding to the position of the first gate layer 11 also needs to be etched away so that the subsequently formed second metal layer 132 can directly contact the first metal layer 131 to achieve electrical connection.

[0079] When the orthographic projections of the first metal layer 131 and the third metal layer 133 on the substrate 10 do not overlap with the wiring area, only the orthographic projection of the second metal layer 132 on the substrate 10 overlaps with the wiring area.

[0080] Specifically, refer to Figure 5 As shown, after the first gate layer 11 is formed on the substrate 10, an insulating layer 12 is formed on the first gate layer 11, and then a first metal layer 131 is formed on the insulating layer 12, and the first metal layer 131 located in the wiring area is completely etched, and then a third metal layer 133 is formed on the first metal layer 131, and then the third metal layer 133 located in the wiring area is completely etched, and the insulating layer 12 at a position corresponding to the first gate layer 11 in the wiring area is etched to expose the first gate layer 11, and then a second metal layer 132 is formed, and the second metal layer 132 located in the wiring area is retained, so that the second metal layer 132 is in direct contact with the first gate layer 11 to achieve electrical connection.

[0081] The above embodiment reduces the number of stacked film layers in the wiring area, thereby reducing the height of the wiring area. This helps reduce metal cracks and corrosion in the wiring area during subsequent processes. Reducing the height of the wiring area also helps reduce residual material within the wiring area, reducing the risk of reliability failure. Furthermore, in the above embodiment, the number of masks remains unchanged throughout the entire manufacturing process, thereby maintaining no increase in manufacturing costs.

[0082] In an optional embodiment, the embodiment of the present application further provides a display substrate, in which the display substrate further includes a touch metal layer 17 and a touch insulating layer 16, and the orthographic projections of the touch metal layer 17 and the touch insulating layer 16 on the substrate 10 overlap with the wiring area.

[0083] Specifically, refer to Figure 3 As shown, before the touch insulating layer 16 is formed, a planar layer 15 is further provided on the side of the source and drain metal layer 13 facing away from the first gate layer 11. The orthographic projection of the planar layer 15 on the substrate 10 overlaps with the wiring area, and the orthographic projection of the planar layer 15 located in the wiring area on the substrate 10 at least partially overlaps with the orthographic projection of the second metal layer 132 on the substrate 10.

[0084] The touch insulation layer 16 is arranged on the side of the planar layer 15 away from the source and drain metal layer 13. The orthographic projection of the touch insulation layer 16 on the substrate 10 overlaps with the wiring area, and the orthographic projection of the touch insulation layer 16 located in the wiring area on the substrate 10 at least partially overlaps with the orthographic projection of the second metal layer 132 on the substrate 10.

[0085] The planarization layer 15 and the touch insulating layer 16 can isolate the water vapor in the wiring area, thereby preventing the water vapor from invading between the source and drain metal layers 13 in the wiring area.

[0086] The touch metal layer 17 is disposed on the side of the touch insulation layer 16 facing away from the planar layer 15, that is, on the side of the source / drain metal layer 13 facing away from the first gate layer 11. The orthographic projection of the touch metal layer 17 on the substrate 10 overlaps with the wiring area and covers the first gate layer 11. At the same time, the touch metal layer 17 is in direct contact with the second metal layer 132 in the source / drain metal layer 13, thereby connecting the touch metal layer 17 to the source / drain metal layer 13 and the first gate layer 11, thereby achieving electrical connection.

[0087] Based on the same inventive concept, an embodiment of the present application discloses a display device, including a display substrate provided by any of the above embodiments of the present application.

[0088] Specifically, the display device may include a computer monitor, a television, a billboard, a laser printer with display function, a telephone, a mobile phone, a personal digital assistant (PDA), a laptop computer, a digital camera, a camcorder, a viewfinder, a vehicle, a large-area wall, a theater screen or a stadium sign, etc.

[0089] Figure 6 A flow chart showing the steps of a method for preparing a display substrate is shown. Figure 6 As shown, an embodiment of the present application discloses a method for preparing a display substrate, wherein the display substrate includes a display area and a wiring area, and the preparation method includes:

[0090] Step 201: Provide a substrate 10.

[0091] Specifically, the steps of completing the manufacturing of the substrate 10 may include the steps of completing the polyimide layer 101 and the buffer layer 102, such as Figure 7 shown.

[0092] Step 202 : forming a first gate layer 11 on the substrate 10 .

[0093] Specifically, the steps before forming the first gate layer 11 may further include the step of forming an active layer 18, wherein the orthographic projection of the active layer 18 on the substrate 10 does not overlap with the wiring region, such as Figure 8shown.

[0094] Step 203: A source-drain metal layer 13 is formed on the side of the first gate layer 11 facing away from the substrate 10, wherein the source-drain metal layer 13 includes a first metal layer 131, a third metal layer 133 and a second metal layer 132 which are stacked, wherein the orthographic projection of the first metal layer 131 and / or the third metal layer 133 on the substrate 10 does not overlap with the wiring area.

[0095] Specifically, the steps before forming the source-drain metal layer 13 may further include the step of forming the insulating layer 12, such as Figure 9 At the same time, the steps after forming the source and drain metal layer 13 also include the steps of forming a planar layer 15, a touch insulating layer 16 and a touch metal layer 17, wherein the orthographic projections of the planar layer 15, the touch insulating layer 16 and the touch metal layer 17 on the substrate 10 overlap with the wiring area, as shown in FIG. Figure 15 and Figure 16 shown.

[0096] Furthermore, there are three situations in which the orthographic projection of the first metal layer 131 and / or the third metal layer 133 on the substrate 10 does not overlap with the wiring area. The first situation is that the orthographic projection of the first metal layer 131 on the substrate 10 does not overlap with the wiring area. The second situation is that the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the wiring area. The third situation is that the orthographic projections of both the first metal layer 131 and the third metal layer 133 on the substrate 10 do not overlap with the wiring area.

[0097] Specifically, when the orthographic projection of the first metal layer 131 on the substrate 10 does not overlap with the wiring area, the preparation method includes:

[0098] Step 2031 : After forming the first metal layer 131 on the side of the first gate layer 11 facing away from the substrate 10 , the first metal layer 131 in the wiring region is etched.

[0099] Specifically, before forming the first metal layer 131, an insulating layer 12 is formed on the side of the first gate layer 11 facing away from the substrate 10, and then the first metal layer 131 is formed on the insulating layer 12. Subsequently, the first metal layer 131 in the wiring area is etched, and the insulating layer 12 in the wiring area is etched at the same time, so that the orthographic projection of the insulating layer 12 on the substrate 10 partially overlaps with the orthographic projection of the first gate layer 11 on the substrate 10, as shown in FIG. Figure 10-12 shown.

[0100] Step 2032 : forming a third metal layer 133 and a second metal layer 132 in sequence on a side of the first metal layer 131 facing away from the substrate 10 , wherein the orthographic projections of the third metal layer 133 and the second metal layer 132 on the substrate 10 overlap with the wiring region.

[0101] Specifically, in the wiring area, the third metal layer 133 is directly connected to the first gate layer 11 to achieve electrical connection between the source and drain metal layer 13 and the first gate layer 11, as shown in FIG. Figure 13 shown.

[0102] In the case where the orthographic projection of the third metal layer 133 on the substrate 10 does not overlap with the wiring area, the preparation method includes:

[0103] Step 2033: forming a first metal layer 131 on a side of the first gate layer 11 facing away from the substrate 10;

[0104] Step 2034: forming a passivation layer 14 on a side of the first metal layer 131 away from the first gate layer 11;

[0105] Step 2035 : After forming the third metal layer 133 on the side of the passivation layer 14 facing away from the first metal layer 131 , the third metal layer 133 located in the wiring area is etched.

[0106] Specifically, due to the protection of the passivation layer 14, during the etching process of the third metal layer 133, the first metal layer 131 will not be damaged by the etching gas of the third metal layer 133. Figure 17 and Figure 18 shown.

[0107] Step 2036 : forming a second metal layer 132 on a side of the third metal layer 133 facing away from the first metal layer 131 , wherein the orthographic projections of the first metal layer 131 and the second metal layer 132 on the substrate 10 overlap with the wiring region.

[0108] In the case where the orthographic projections of the first metal layer 131 and the third metal layer 133 on the substrate 10 do not overlap with the wiring area, the preparation method includes:

[0109] Step 2037: After forming the first metal layer 131 on the side of the first gate layer 11 facing away from the substrate 10, the first metal layer 131 located in the wiring area is etched. Figure 10 shown.

[0110] Step 2038: After forming the third metal layer 133 on the side of the first metal layer 131 facing away from the substrate 10, the third metal layer 133 in the wiring area is etched. Figure 19 shown.

[0111] Step 2039 : Form a second metal layer 132 on the side of the third metal layer 133 facing away from the substrate 10 , wherein the orthographic projection of the second metal layer 132 on the substrate 10 overlaps with the wiring region.

[0112] Specifically, in the step of etching the first metal layer 131, the insulating layer 12 on the first gate layer 11 is not etched. Figure 10 and Figure 11 As shown, after forming the third metal layer 133, the third metal layer 133 and the insulating layer 12 are etched so that the orthographic projection of the insulating layer 12 on the substrate 10 partially overlaps with the orthographic projection of the first gate layer 11 on the substrate 10, as shown in FIG. Figure 19 and Figure 11 shown.

[0113] The display substrate fabricated using the above-described fabrication method reduces the number of stacked film layers in the wiring area, thereby lowering the height of the wiring area. This helps reduce metal cracks and corrosion in the wiring area during subsequent processing. Furthermore, reducing the height of the wiring area also helps reduce residual material within the wiring area, reducing the risk of reliability failure. Furthermore, in the above-described embodiment, the number of masks remains unchanged throughout the entire fabrication process, thereby minimizing manufacturing costs.

[0114] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0115] It should also be noted that, in this article, the orientation or position relationship indicated by the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance. Moreover, the terms "include", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device that includes a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, an element defined by the phrase "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or terminal device that includes the element.

[0116] The technical solutions provided by this application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand this application, and the contents of this specification should not be construed as limiting this application. At the same time, for those skilled in the art, according to this application, there may be various changes in the specific implementation methods and application scopes. It is not necessary and impossible to list all implementation methods here, and obvious changes or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A display substrate comprising a display area and a wiring area, characterized in that: The display substrate comprises: substrate; a first gate layer, disposed on one side of the substrate; a source / drain metal layer, disposed on a side of the first gate layer facing away from the substrate, the source / drain metal layer comprising a first metal layer, a third metal layer, and a second metal layer stacked together; the first metal layer serving as the source / drain of the display substrate and connected to the active layer of the display substrate; the third metal layer serving as a first transfer electrode of the display substrate and connecting the first metal layer and the second metal layer; and the second metal layer serving as a second transfer electrode of the display substrate and connecting the third metal layer and the pixel electrode of the display substrate; The orthographic projections of the first metal layer and / or the third metal layer on the substrate do not overlap with the wiring area; and the method includes: etching the first metal layer and / or the third metal layer within the wiring area.

2. The display substrate according to claim 1, wherein: The orthographic projection of the first metal layer on the substrate overlaps with the wiring area, and the display substrate further includes: A passivation layer is provided between the first metal layer and the second metal layer, wherein an orthographic projection of the passivation layer on the substrate at least partially overlaps with an orthographic projection of the first metal layer on the substrate.

3. The display substrate according to claim 1, wherein The display substrate further includes: A touch metal layer is provided on a side of the source and drain metal layer away from the first gate layer, and an orthographic projection of the touch metal layer on the substrate overlaps with the wiring area.

4. The display substrate according to claim 3, wherein: The display substrate further includes: An insulating layer is provided between the first gate layer and the source / drain metal layer, wherein an orthographic projection of the insulating layer on the substrate overlaps with the wiring region.

5. The display substrate according to claim 4, wherein: The display substrate further includes: A planar layer is provided on a side of the source / drain metal layer away from the first gate layer, and the planar layer is located between the touch metal layer and the source / drain metal layer, and an orthographic projection of the planar layer on the substrate overlaps with the wiring area.

6. The display substrate according to claim 5, wherein: The display substrate further includes: A touch insulating layer is provided between the touch metal layer and the planar layer, and an orthographic projection of the touch insulating layer on the substrate overlaps with the wiring area.

7. The display substrate according to claim 6, wherein: In the wiring region, an orthographic projection of the planar layer on the substrate at least partially overlaps with an orthographic projection of the second metal layer on the substrate.

8. The display substrate according to claim 6, wherein: In the wiring area, an orthographic projection of the touch insulating layer on the substrate at least partially overlaps with an orthographic projection of the second metal layer on the substrate.

9. The display substrate according to any one of claims 1 to 8, wherein: In the wiring area, the touch metal layer is in direct contact with at least a portion of the source and drain metal layer.

10. The display substrate according to claim 9, wherein: In the wiring region, the source-drain metal layer is in direct contact with at least a portion of the first gate layer.

11. The display substrate according to claim 10, wherein: In the wiring region, an orthographic projection of the source and drain metal layer on the substrate covers an orthographic projection of the first gate layer on the substrate.

12. The display substrate according to claim 10, wherein: In the wiring region, the second metal layer is in direct contact with at least a portion of the first gate layer; Alternatively, the second metal layer is in direct contact with at least a portion of the first metal layer; Alternatively, the second metal layer is in direct contact with at least a portion of the third metal layer.

13. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 12.

14. A method for preparing a display substrate, wherein the display substrate comprises a display area and a wiring area, wherein: The preparation method comprises: providing a substrate; forming a first gate layer on the substrate; A source-drain metal layer is formed on a side of the first gate layer facing away from the substrate, the source-drain metal layer comprising a first metal layer, a third metal layer, and a second metal layer stacked together; the first metal layer serves as the source / drain of the display substrate and is connected to the active layer of the display substrate; the third metal layer serves as a first transfer electrode of the display substrate and is used to connect the first metal layer and the second metal layer; the second metal layer serves as a second transfer electrode of the display substrate and is used to connect the third metal layer and the pixel electrode of the display substrate; The orthographic projections of the first metal layer and / or the third metal layer on the substrate do not overlap with the wiring area; and the method includes: etching the first metal layer and / or the third metal layer within the wiring area.

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