Semiconductor device and method of manufacturing the same, three-dimensional memory, and memory system

Abstract

The application provides a semiconductor device and a manufacturing method thereof, a three-dimensional memory and a storage system. The manufacturing method comprises the following steps: providing a substrate, the substrate is provided with a virtual gate layer, and the substrate comprises a first region and a second region; forming a plurality of first patterns on the virtual gate layer in the first region, and forming a second pattern on the virtual gate layer in the second region; removing the second pattern; and patterning the virtual gate layer through the plurality of first patterns to form a virtual gate. By avoiding the problem that the size of the first pattern fluctuates due to etching load effect, the reliability of the semiconductor device formed by the method is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a three-dimensional memory, and a storage system. Background Technology

[0002] Currently, with the rapid development of very large-scale integrated circuits, semiconductor devices are moving towards higher component density and higher integration in order to achieve faster computing speeds and larger data storage capacity.

[0003] In semiconductor devices, different regions typically correspond to different functional devices, resulting in different requirements for device pattern density. This can lead to severe etching load effects at the boundaries of different regions during semiconductor device formation, causing the forming dimensions of some device patterns to not conform to the critical dimensions in the corresponding regions. This affects the functional role of some critical patterns and thus impacts the reliability of semiconductor devices. Summary of the Invention

[0004] This application provides a semiconductor device and its fabrication method, a three-dimensional memory, and a storage system, aiming to solve the problem of low reliability of the semiconductor device caused by differences in pattern density in different regions.

[0005] To address the aforementioned problems, in a first aspect, this application provides a method for fabricating a semiconductor device, comprising: providing a substrate on which a dummy gate layer is formed, the substrate including a first region and a second region; forming a plurality of first patterns on the dummy gate layer located in the first region and forming a second pattern on the dummy gate layer located in the second region; removing the second pattern; and patterning the dummy gate layer using the plurality of first patterns to form a dummy gate.

[0006] The distance between the second pattern and an adjacent first pattern is equal to the distance between two adjacent first patterns.

[0007] The size of the first pattern is equal to the size of the second pattern.

[0008] A sacrificial layer is also formed on the substrate, and the virtual gate layer and the sacrificial layer are sequentially covered on the substrate; in the step of forming a plurality of first patterns on the virtual gate layer located in the first region and forming a second pattern on the virtual gate layer located in the second region, the second pattern and the plurality of first patterns are formed on the surface of the sacrificial layer.

[0009] The step of forming a plurality of first patterns on the virtual gate layer located in the first region and forming a second pattern on the virtual gate layer located in the second region includes: forming a pattern layer on the virtual gate layer; performing ion doping on the pattern layer located in the first region or the second region; and using the pattern layer to form a plurality of first patterns in the first region and a second pattern in the second region.

[0010] The step of removing the second pattern includes: forming an oxide layer covering the second pattern and a plurality of first patterns, wherein the thickness of the oxide layer covering the plurality of first pattern layers is greater than the thickness of the oxide layer covering the second pattern; and sequentially etching away the oxide layer covering the second pattern and the second pattern.

[0011] The step of sequentially etching away the oxide layer covering the second pattern and the second pattern includes: etching away the oxide layer covering the second pattern and a plurality of first patterns to remove the oxide layer covering the second pattern and thinning the oxide layer covering the plurality of first patterns; etching away the exposed second pattern and retaining the plurality of first patterns.

[0012] The step of sequentially etching away the oxide layer covering the second pattern and the second pattern further includes: removing the oxide layer covering the plurality of first patterns.

[0013] The step of etching the virtual gate layer through multiple first patterns to form a virtual gate includes: forming secondary patterns on both sides of each first pattern; removing multiple first patterns; and etching the virtual gate layer through the secondary patterns to form the virtual gate.

[0014] The step of forming secondary patterns on both sides of each first pattern includes: forming a secondary pattern layer covering a plurality of first patterns; and etching back the secondary pattern layer to form secondary patterns on both sides of each first pattern.

[0015] The step of etching the virtual gate layer through the plurality of first patterns to form a virtual gate further includes: replacing the virtual gate with a gate structure.

[0016] In a second aspect, this application also provides a semiconductor device, comprising: a substrate, the substrate including a first region and a second region; and a plurality of first gate structures located on the substrate in the first region, the plurality of first gate structures being arranged at equal intervals.

[0017] The semiconductor device further includes: a plurality of source / drain contacts on the substrate in the first region, each source / drain contact being located between two adjacent first gate structures, and each source / drain contact being equidistant from the two adjacent first gate structures.

[0018] Thirdly, this application also provides a three-dimensional memory, which includes a memory cell array and peripheral circuitry, wherein the peripheral circuitry includes the semiconductor devices described above.

[0019] Fourthly, this application also provides a storage system including a controller and a three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the three-dimensional memory to store data, the three-dimensional memory including the semiconductor devices as described above.

[0020] In the semiconductor device fabrication method provided in this application, by designing to form a second pattern in a second region when forming a plurality of first patterns in a first region, a plurality of first patterns are also formed in a first region to avoid forming a plurality of first patterns on a single first region, thereby reducing the etching load effect present when forming a plurality of first patterns and reducing the fluctuation of the first pattern size caused by the etching load effect. This makes it possible for the spacing of the virtual gate to be uniformly distributed after the virtual gate layer is patterned by a plurality of first patterns to form a virtual gate, which is beneficial to improving the reliability of the semiconductor device formed by this method. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of this application, the drawings used in the description of the various embodiments made according to this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0023] Figures 2A-2O These are cross-sectional schematic diagrams of the semiconductor device provided in the embodiments of this application at various stages of the manufacturing method;

[0024] Figure 3 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application;

[0025] Figure 4 This is a schematic block diagram of a three-dimensional memory structure provided in an embodiment of this application;

[0026] Figure 5 This is a schematic block diagram of a storage system provided in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0030] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0031] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0032] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in an embodiment of this application, such as... Figure 1 As shown, the manufacturing method may include the following steps:

[0033] Step S101: Provide a substrate on which a virtual gate layer is formed, the substrate including a first region and a second region.

[0034] The cross-sectional view of the semiconductor device after step S101 is shown below. Figure 2A As shown.

[0035] Specifically, the substrate 10 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). In this embodiment, for example... Figure 2A As shown, the substrate 10 can be divided into a first region A and a second region B according to the location of different functional devices. The first region A can be a region for forming short-channel devices, which is a patterned dense region, and the second region B can be a region for forming long-channel devices, which is a patterned sparse region. In this embodiment, the virtual gate layer 11 can be selected as polysilicon material, and the process for forming the virtual gate layer 11 can be one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and ALD (atomic layer deposition) processes. The first region A can be specifically used to form a fin field-effect transistor (FinFET), such as... Figure 2A As shown, a first fin structure 101 is formed in the first region A, and a long channel structure 102 is formed in the second region B. Since the first region A can be a short channel device region and the second region B can be a long channel device region, the channel lengths corresponding to the first fin structure 101 and the long channel structure 102 are different. Figure 2AAs not shown, the substrate 10 also includes a source and a drain.

[0036] In one embodiment, a sacrificial layer 13 is further formed on the substrate 10. The sacrificial layer 13 may be made of silicon nitride, and the process for forming the sacrificial layer 13 may be one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The dummy gate layer 11 and the sacrificial layer 13 are sequentially covered on the substrate 10.

[0037] It should be further explained that when the dummy gate layer 11 is selected as polysilicon and the sacrificial layer 13 is selected as silicon nitride, a first buffer layer 12 is also formed between the dummy gate layer 11 and the sacrificial layer 13. This buffer layer 12 is used to better bond the dummy gate layer 11 and the sacrificial layer 13. Preferably, the first buffer layer 12 is selected as silicon dioxide or other materials that can promote the bonding between the polysilicon and silicon nitride materials.

[0038] Step S102: A plurality of first patterns are formed on the virtual gate layer located in the first region, and a second pattern is formed on the virtual gate layer located in the second region.

[0039] In one embodiment, step S102 may specifically include the following steps:

[0040] Step S1021: As Figures 2B-2C As shown, a pattern layer 15 is formed on the virtual gate layer 11, and the pattern layer 15 located in the first region A or the second region B is ion-doped.

[0041] Step S1022: As Figures 2D-2E As shown, the pattern layer 15 is used to form a plurality of first patterns 151 in the first region A and a second pattern 152 in the second region B.

[0042] In one embodiment, since a sacrificial layer 13 is also formed on the substrate 10, correspondingly, in step S102, the second pattern 152 and a plurality of the first patterns 151 are formed on the surface of the sacrificial layer 13.

[0043] In this embodiment, the pattern layer 15 is selected as a polycrystalline silicon material and can be formed by any of the processes of CVD, PVD, and ALD. Multiple first patterns 151 can be formed on the sacrificial layer 13 using the pattern layer 15. The first patterns 151 can serve as the mandrel structure required in the first region A in subsequent processes, and the geometric effect of the mandrel structure's sidewalls is used to form a spacer. The spacer corresponds to the shape and size of the final virtual gate, thus defining the shape, size, and position of the virtual gate based on the mandrel structure. It should be noted that when the pattern layer 15 is selected as a polycrystalline silicon material and the sacrificial layer 13 is selected as a silicon nitride material, a second buffer layer 14 needs to be formed on the sacrificial layer 13 before forming the pattern layer 15 to enhance the bonding force between the sacrificial layer 13 and the pattern layer 15. Preferably, the second buffer layer 14 can be an oxide layer or other materials that can promote the bonding between polycrystalline silicon and silicon nitride. For example, in this embodiment, it can be a silicon dioxide layer formed by processes such as CVD, PVD and ALD, or a nitrogen-containing oxide layer formed by directly oxidizing the patterned layer 15 made of silicon nitride.

[0044] In step S1021, selective doping of the patterned layer 15 located in the first region A or the second region B is achieved firstly by forming a first mask layer 16 on the patterned layer 15, then defining openings on the first mask layer 16 to indicate the locations of the regions to be doped, and finally performing ion doping on the exposed patterned layer 15 through these openings. In one embodiment, as... Figure 2C As shown, an opening corresponding to the second region B can be defined on the first mask layer 16, and then the pattern layer 15 located in the second region can be doped. In this embodiment, since the ion doping process is carried out at room temperature, photoresist, silicon dioxide film, and metal film can all be used as materials for the mask layer.

[0045] In step S1022, the pattern layer 15 is etched using the same etching process to obtain multiple first patterns 151 located in the first region A and second patterns 152 located in the second region B. Step S1022 may specifically include the following steps: Figure 2D As shown, a patterned first photoresist layer 17 is formed on the patterned layer 15; as Figure 2E As shown, the patterned first photoresist layer 17 is used as a mask to etch the pattern layer 15 to form the plurality of first patterns in the first region A and the second pattern in the second region B.

[0046] In this embodiment, as Figure 2DAs shown, the patterned first photoresist layer 17 includes multiple first photoresist patterns 171 located in the first region A and second photoresist patterns 172 located in the second region B. The specific formation process of the multiple first photoresist patterns 171 and second photoresist patterns 172 can be as follows: first, a protective layer 18 is formed on the patterned layer 15; then, an unpatterned first photoresist layer 17 is formed on the protective layer 18; and finally, openings of a predetermined width are defined on the unpatterned first photoresist layer 17 using a photolithography process to form multiple first photoresist patterns located in the first region A. The photoresist pattern 171 and the second photoresist pattern 172 located in the second region B are provided. The material of the protective layer 18 is harder than that of the first photoresist layer 17. Therefore, during the patterning process, after the pattern on the first photoresist layer 17 is transferred to the protective layer 18, the pattern on the harder protective layer 18 is less prone to change. Thus, transferring the pattern on the protective layer 18 to the patterning layer 15 to form multiple first patterns 151 and second patterns 152 helps improve the dimensional stability of the first patterns 151 and second patterns 152. (See also...) Figure 2D The preset width of the opening refers to the distance d1 between two adjacent first photoresist patterns 171 and the distance d2 between the second photoresist pattern 172 and an adjacent first photoresist pattern 171.

[0047] Specifically, such as Figure 2D The patterned first photoresist layer 17 shown is a mask. The patterned layer 15 is etched using a dry etching process, such as plasma etching, to form a pattern. Figure 2E The diagram shows multiple first patterns 151 and second patterns 152. The formation of the first patterns 151 and second patterns 152 is actually the result of pattern transfer between the first photoresist pattern 171 and the second photoresist pattern 172. Therefore, the spacing between two adjacent first patterns 151 is d1, and the spacing between a second pattern 152 and an adjacent first pattern 151 is d2.

[0048] It should be further explained that if only the need to increase the spatial pattern density is considered, since the first region A is a pattern-dense region and the second region B is a pattern-sparse region, it is only necessary to form multiple first patterns 151 as multiple mandrel structures in the first region A, and it is not necessary to form a second pattern 152 in the second region B. Correspondingly, the second photoresist pattern 172 in the second region B is not needed. However, when multiple first patterns 151 are formed by etching the pattern layer 15 using multiple first photoresist patterns 171 in the first region A, if the second region B does not have a second photoresist pattern 172, the uneven distribution of pattern density in the first region A and the second region B during etching will result in different levels of etching gas consumption in the first region A and the second region B, leading to uneven etching rate distribution in the first region A and the second region B. This will result in a significant etching load effect at the boundary between the first region A and the second region B. Therefore, among the multiple first patterns 151 formed by etching, the size d (pitch) of a first pattern 151 adjacent to the second region B will differ from the size d of the other first patterns 151. Since the first pattern 151 is related to the shape, size, and position of the subsequently formed virtual gate, the fluctuation of the width of the first pattern 151 affects the stability of the semiconductor device structure and function.

[0049] In this embodiment, not only are multiple first patterns 151 formed in the first region A, but second patterns 152 are also formed in the second region B. Correspondingly, the pattern layer 15 is etched using the multiple first photoresist patterns 171 in the first region A and the second photoresist patterns 172 in the second region B. Due to the presence of the second photoresist patterns 172, the difference in pattern density between the first region A and the second region B during etching is reduced to at least a certain extent, reducing the etching load effect at the boundary between the first region A and the second region B, thereby improving the consistency of the width of the multiple first patterns 151 formed. Optionally, the number of second patterns 152 can be one or more, and correspondingly, the number of second photoresist patterns 172 can also be one or more.

[0050] In one embodiment, the spacing d1 between two adjacent first patterns 151 is equal to the spacing d2 between the second pattern 152 and an adjacent first pattern 151.

[0051] Specifically, by designing the spacing d1 between two adjacent first photoresist patterns 171 to be equal to the spacing d2 between the second photoresist pattern 172 and an adjacent first photoresist pattern 171, the spacing d1 between two adjacent first patterns 151 is ensured to be equal to the spacing d2 between the second pattern 152 and an adjacent first pattern 151. During the etching of the pattern layer 15, since the spacing d1 between two adjacent first photoresist patterns 171 is equal to the spacing d2 between the second photoresist pattern 172 and an adjacent first photoresist pattern 171, the uniformity of the pattern density distribution in the first region A and the second region B can be further improved, reducing the corresponding etching load effect and thus improving the dimensional consistency of the multiple formed first patterns 151.

[0052] In another embodiment, the percentage difference p between the spacing d1 between two adjacent first patterns 151 and the spacing d2 between the second pattern 152 and the adjacent first pattern 151 is less than a preset ratio, where p = (|d1-d2| / d1)*100%. For example, this preset ratio can be set between 10% and 20%, that is, when the spacing d1 between two adjacent first patterns 151 is approximately the same as the spacing d2 between the second pattern 152 and the adjacent first pattern 151, the corresponding etching load effect can be reduced to a certain extent, thereby improving the consistency of the size d of the multiple formed first patterns 151.

[0053] In one embodiment, the size d of the first pattern 151 is equal to the size of the second pattern 152.

[0054] Specifically, by designing the size of the first photoresist pattern 171 to be equal to the size of the second photoresist pattern 172, the size d of the first pattern 151 is ensured to be equal to the size of the second pattern 152. During the etching of the pattern layer 15, since the size of the first photoresist pattern 171 is equal to the size of the second photoresist pattern 172, the uniformity of the pattern density distribution in the first region A and the second region B can be further improved, thereby enhancing the consistency of the size of the multiple formed first patterns 151.

[0055] Step S103: Remove the second pattern.

[0056] Optionally, since the second region B is a graphic sparse area, it is not necessary to retain the second pattern 152 as a core structure to achieve the purpose of doubling the spatial graphic density, so it can be removed.

[0057] In one embodiment, step S103 may include steps S1031 to S1032, as follows:

[0058] Step S1031: Form an oxide layer covering the second pattern and the plurality of first patterns, wherein the thickness of the oxide layer covering the plurality of first pattern layers is greater than the thickness of the oxide layer covering the second pattern.

[0059] The cross-sectional schematic diagram of the semiconductor device after step S1031 is shown below. Figure 2F As shown.

[0060] Specifically, since either the first region A or the second region has been selectively subjected to ion doping in step S1021, therefore, as Figure 2E and Figure 2F As shown, after selective doping of the pattern layer 15 in the second region B, the composition of the second pattern 152 differs from that of the undoped first pattern 151. In one embodiment, as... Figure 2C As shown, nitrogen ions are used to dope the pattern layer 15 of the second region B, resulting in a difference in the thickness of the oxide layer covering the first pattern 151 and the second pattern 152 when multiple first patterns 151 and second patterns 152 are simultaneously oxidized by a thermal oxidation process to form an oxide layer. This difference manifests as the oxide layer thickness on the second pattern being less than the oxide layer thickness on the first pattern. In other embodiments, chloride or phosphorus ions can also be used to dope the pattern layer 15 of the first region A, similarly resulting in a difference in the oxide layer thickness of different regions after the same process steps.

[0061] Step S1032: Sequentially etch away the oxide layer covering the second pattern and the second pattern. Since the thickness of the oxide layer 19 covering the first pattern 151 and the second pattern 152 has differed, the second pattern 152 can be selectively removed by means of this difference, while retaining multiple first patterns 151.

[0062] In one embodiment, step S1032 may specifically include the following steps: Figure 2G As shown, the oxide layer 19 covering the second pattern 152 and the plurality of first patterns 151 is etched to remove the oxide layer 19B covering the second pattern 152 and to thin the oxide layer 19A covering the plurality of first patterns 151; as Figure 2H As shown, the second pattern 152 is etched away, while multiple first patterns 151 are retained.

[0063] Specifically, the etching process covering the oxide layer 19 of the sacrificial layer 13, the plurality of first patterns 151, and the second pattern 152 can be a wet etching process. For example, the amount of selective acidic solution (HF) can be controlled to control the etching thickness of the oxide layer 19, thereby removing the oxide layer 19B on the surface of the second pattern 152 and thinning the oxide layer 19A on the plurality of first patterns 151. Since a second buffer layer 14 is formed between the pattern layer 15 and the sacrificial layer 13 when the pattern layer 15 is made of polysilicon and the sacrificial layer 13 is made of silicon nitride, and the material of the second buffer layer 14 can be an oxide layer, when removing the oxide layer 19B covering the second pattern 152, the exposed portion of the second buffer layer 14 is also etched away, leaving only the remaining second buffer layer 14' located at the bottom of the first pattern 151 and the second pattern.

[0064] When the oxide layer 19B on the second pattern 152 is removed, the second pattern 152 is exposed. Optionally, when the material of the pattern layer 15 is polysilicon, the second pattern 152 can be selectively removed by a dry etching process. Figure 2H As shown, after the second pattern 152 is removed, the sacrificial layer 13 still has a remaining oxide layer 19A and a remaining second buffer layer 14'. The presence of the remaining oxide layer 19A will affect the critical dimensions of the gate in the subsequent first region A, so it needs to be removed. Therefore, after step S1032, the method further includes removing the oxide layer 19A covering the plurality of first patterns 151. After this step, the cross-sectional view of the semiconductor device is shown in the figure. Figure 2I As shown.

[0065] In one embodiment, since a second buffer layer 14 is also formed between the pattern layer 15 and the sacrificial layer 13, and after removing the oxide layer 19B covering the second pattern 152, there is still a remaining second buffer layer 14' at the bottom of the first pattern 151 and the second pattern 152, therefore... Figure 2I As shown, while removing the remaining oxide layer 19A by wet etching, the remaining oxide layer 14' located in the second region B can also be removed, and the width of the remaining second buffer layer 14' at the bottom of the first pattern 151 can be no greater than the size d of the first pattern 151.

[0066] Step S104: Pattern the virtual gate layer using multiple of the first patterns to form a virtual gate.

[0067] In one embodiment, the sacrificial layer 13 and the virtual gate layer 11 are directly etched sequentially by multiple first patterns 151 to pattern the virtual gate layer 11, thereby forming a virtual gate. The size of the corresponding virtual gate is also d. In another embodiment, since the first region A is a pattern-dense region and the area where the short-channel device is located, the size of the virtual gate to be formed needs to be smaller than d. Therefore, a self-aligned double patterning (SADP) process is used to form the corresponding virtual gate on the first region A, achieving a doubling of the number of virtual gates. In one embodiment, step S104 may specifically include steps S1041 to S1043, as follows:

[0068] Step 1041: Form secondary patterns located on both sides of each of the first patterns.

[0069] The cross-sectional view of the semiconductor device after step S1041 is shown below. Figure 2J As shown. Specifically, step S1041 may include the following steps: forming a secondary pattern layer covering a plurality of first patterns 151; etching back the secondary pattern layer to form secondary patterns 20 located on both sides of the first patterns 151.

[0070] Specifically, the secondary pattern layer can be formed by deposition on the surface of multiple first patterns 151 using an ALD process. Then, the secondary pattern layer is etched back using a process such as reactive ion etching to form secondary patterns 20 located on both sides of the first pattern 151. The secondary patterns 20 serve as sidewalls (spacers) in the SADP process. The secondary patterns 20 are left behind due to the geometric effects of the sidewalls of the first pattern 151 (mandrel).

[0071] Step S1042: Remove multiple instances of the first pattern.

[0072] The cross-sectional view of the semiconductor device after step S1042 is shown below. Figure 2K As shown.

[0073] Specifically, in this embodiment, when the pattern layer 15 is made of polycrystalline silicon and the secondary pattern 20 is made of silicon nitride, the first pattern 151 can be selectively removed using a tetramethylammonium hydroxide (TMAH) solution. Since this embodiment also selectively includes a second buffer layer 14, after removing the first pattern 151, the remaining second buffer layer 14' is also removed.

[0074] Step S1043: The virtual gate layer is etched by the secondary pattern to form the virtual gate.

[0075] Since the second region B is the region where the long-channel device is located, the size of the gate to be formed therein does not need to be less than d. Therefore, before step S1043, the method further includes: Figure 2L As shown, a second photoresist layer 21 is formed on the virtual gate layer 11 in the second region B. The second photoresist layer 21 serves to protect the virtual gate layer 11 in the second region B. In one embodiment, when a sacrificial layer 13 is pre-formed on the virtual gate layer 11, the second photoresist layer 21 is specifically formed on the surface of the sacrificial layer 13.

[0076] The sectional view after step S1043 is shown below. Figure 2M As shown, the virtual gate 11' formed on the first region A by SADP process, and adjacent virtual gates 11' in the first region A are arranged at an equal spacing d, thereby solving the problem of gate gap instability caused by etching load effect. Preferably, the size of the virtual gate 11' can be 0.5d. In one embodiment, when a sacrificial layer 13 and a first buffer layer 12 are pre-formed on the virtual gate layer 11, after the virtual gate 11' is formed, as... Figure 2N As shown, it also includes the step of removing the first buffer layer 12' and sacrificial layer 13' remaining after etching the virtual gate layer 11.

[0077] In one embodiment, after step S104, step S105 is further included: replacing the virtual gate with a gate structure.

[0078] The cross-sectional view of the semiconductor device after step S105 is shown below. Figure 2O As shown. Since adjacent virtual gates 11' in the first region are arranged at equal intervals d, the resulting gate structure 11" is also arranged at equal intervals. Therefore, as... Figure 3 As shown, after forming the source / drain contact on the first fin structure 101 in the first region A, the spacing between the source / drain contact and the gate structure 11” can be avoided to be too large or too small, thereby preventing leakage in the corresponding FinFET. Preferably, the material of the gate structure 11” is metal. Specifically, the gate structure 11” includes a plurality of first gate structures 11”A located in the first region A and a second gate structure 11”B located in the second region B.

[0079] Please see Figure 3 , Figure 3 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor device 200 can be formed using the semiconductor device fabrication method described above. Correspondingly, the formation process of the semiconductor device 200 can be referred to as follows: Figures 2A-2O .like Figure 3As shown, the semiconductor device 200 includes a substrate 10 and a plurality of first gate structures 11”A. The substrate 10 includes a first region A and a second region B, and the plurality of first gate structures 11”A are located on the substrate 10 in the first region A, and the plurality of first gate structures 11”A are arranged at equal intervals.

[0080] Specifically, the substrate 10 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). The substrate 10 can be divided into a first region A and a second region B according to the location of different functional devices. The first region A can be a region for forming short-channel devices, which is a patterned dense region, while the second region B can be a region for forming long-channel devices, which is a patterned sparse region. Further, a first fin structure 101 is formed in the first region A, and a long-channel structure 102 is formed in the second region B. Since the first region A can be a short-channel device region and the second region B can be a long-channel device region, the channel lengths corresponding to the first fin structure 101 and the long-channel structure 102 are different. Figure 3 As not shown, the substrate 10 also includes a source and a drain.

[0081] Specifically, the semiconductor device 200 further includes a plurality of source / drain contacts 22 located on the substrate 10 in the first region A. Each source / drain contact 22 is located between two adjacent first gate structures 11”A, and the distance from each source / drain contact 22 to the two adjacent first gate structures 11”A is equal. Specifically, each source / drain contact 22 is used to connect to a source or drain disposed in the substrate 10.

[0082] In some embodiments of this application, the semiconductor device 200 may be a three-dimensional memory. In other embodiments, the semiconductor device 200 may also be part of a three-dimensional memory; please refer to the following for details. Figure 4 , Figure 4 This is a schematic block diagram of the structure of a three-dimensional memory provided in an embodiment of this application. The three-dimensional memory 400 includes a memory cell array 402 and peripheral circuitry 401, wherein the peripheral circuitry 401 includes the aforementioned semiconductor device 200. Specifically, the three-dimensional memory 400 may be a NAND chip.

[0083] The memory cell array 402 and the peripheral circuit 401 can be arranged adjacently or face-to-face. When the memory cell array 402 and the peripheral circuit 401 are face-to-face bonded, the three-dimensional memory 400 also includes a first wafer and a second wafer. The memory cell array 402 is formed on the first wafer, and the peripheral circuit 401 for controlling the read and write operations of the memory cell array is formed on the second wafer. The peripheral circuit 401 includes a semiconductor device 200, and the first wafer and the second wafer are face-to-face bonded.

[0084] Please see Figure 5 , Figure 5 This is a schematic block diagram of the storage system provided in an embodiment of this application. The storage system 500 includes a controller 502 and a three-dimensional memory 501. The controller 502 is coupled to the three-dimensional memory 501 and is used to control the storage of data in the three-dimensional memory 501. The three-dimensional memory 501 includes the semiconductor device 200 described above. Specifically, the storage system 500 may be a solid-state drive (SSD).

[0085] In addition to the embodiments described above, this application may have other implementation methods. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by this application.

[0086] In summary, although the preferred embodiments have been disclosed above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which a virtual gate layer is formed. The substrate includes a first region and a second region; the first region is a device patterned dense region, and the second region is a device patterned sparse region. A patterned layer is formed on the virtual gate layer; a patterned first photoresist layer is formed on the patterned layer, the patterned first photoresist layer including a plurality of first photoresist patterns located in the first region and a second photoresist pattern located in the second region; Using the patterned first photoresist layer as a mask, the patterned layer is etched in the same etching process to form a plurality of first patterns in the first region and a second pattern in the second region; The size of the first photoresist pattern is equal to the size of the second photoresist pattern; Remove the second pattern; The virtual gate layer is patterned using multiple of the first patterns to form a virtual gate.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The distance between the second pattern and an adjacent first pattern is equal to the distance between two adjacent first patterns.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The size of the first pattern is equal to the size of the second pattern.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, A sacrificial layer is also formed on the substrate, and the sacrificial layer is disposed on the pattern layer; in the step of using the patterned first photoresist layer as a mask to etch the pattern layer in the same etching process to form a plurality of first patterns in the first region and a second pattern in the second region, the second pattern and the plurality of first patterns are formed on the surface of the sacrificial layer.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a pattern layer on the virtual gate layer includes: A patterned layer is formed on the virtual gate layer; The patterned layer located in the first region or the second region is ion-doped.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The step of removing the second pattern includes: An oxide layer is formed covering the second pattern and a plurality of first patterns, wherein the thickness of the oxide layer covering the plurality of first pattern layers is greater than the thickness of the oxide layer covering the second pattern; The oxide layer covering the second pattern and the second pattern are sequentially etched away.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The step of sequentially etching away the oxide layer covering the second pattern and the second pattern includes: The oxide layer covering the second pattern and the plurality of first patterns is etched to remove the oxide layer covering the second pattern and to thin the oxide layer covering the plurality of first patterns; The exposed second pattern is etched away, while multiple first patterns are retained.

8. The method for fabricating a semiconductor device according to claim 6, characterized in that, After the step of sequentially etching away the oxide layer covering the second pattern and the second pattern, the method further includes: Remove the oxide layer covering the plurality of first patterns.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of etching the virtual gate layer through multiple first patterns to form a virtual gate includes: Form secondary patterns on both sides of each of the first patterns; Remove multiple instances of the first pattern; The virtual gate is formed by etching the virtual gate layer using the secondary pattern.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The step of forming secondary patterns located on both sides of each of the first patterns includes: A secondary pattern layer is formed that covers multiple of the first patterns; The secondary pattern layer is etched back to form secondary patterns located on both sides of each of the first patterns.

11. The method for fabricating a semiconductor device according to claim 1, characterized in that, Following the step of etching the virtual gate layer through the plurality of first patterns to form a virtual gate, the method further includes: The virtual gate is replaced with a gate structure.

12. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method for manufacturing the semiconductor device according to any one of claims 1 to 11, and the semiconductor device comprises: The substrate includes a first region and a second region; the first region is a device patterned dense region, and the second region is a device patterned sparse region; A plurality of first gate structures are located on the substrate in the first region, and the plurality of first gate structures are arranged at equal intervals.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: A plurality of source / drain contacts are located on the substrate in the first region, each source / drain contact being located between two adjacent first gate structures, and each source / drain contact being equidistant from the two adjacent first gate structures.

14. A three-dimensional memory, characterized in that, The three-dimensional memory includes a memory cell array and peripheral circuitry, wherein the peripheral circuitry includes a semiconductor device as described in any one of claims 12-13.

15. A storage system, characterized in that, It includes a controller and a three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory, the three-dimensional memory including a semiconductor device as described in any one of claims 12-13.

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