Package frame for chips, processing method and related products

Abstract

The present disclosure relates to a packaging frame for a chip, a processing method and related products. In an artificial intelligence training scenario, an integrated circuit device can include a printed circuit board, a packaging substrate can be disposed on the printed circuit board, and a first system on chip and a first memory chip can be further disposed on the packaging substrate. The first system on chip can be communicatively connected with the first memory chip through the packaging substrate.

Description

Technical Field

[0001] This disclosure generally relates to the field of circuits, and more specifically, to the field of chip packaging and manufacturing. Background Technology

[0002] Functionally, cloud-based artificial intelligence (AI) chips primarily perform two tasks: training and inference.

[0003] Training refers to sending massive amounts of data to a server and repeatedly adjusting AI algorithms to enable them to master specific functions. This process requires extremely high computing performance, accuracy, and versatility. Therefore, cloud training typically employs state-of-the-art process nodes and utilizes technologies such as COWOS (Chip-on-Wafer-on-Substrate) wafer-level chip packaging to interconnect System-on-Chip (SOC) chips with multiple High Bandwidth Memory (HBM) chips.

[0004] Inference refers to the direct application of a trained model. The model's parameters are already fixed, and it does not require massive data computation. Therefore, the requirements for computational performance, accuracy, and versatility are not as stringent. As a result, cloud inference does not require the use of very expensive HBM chips. Instead, packaged SOC chips are typically interconnected with multiple Double Data Rate SDRAM (DDR) chips on a printed circuit board (PCB).

[0005] In summary, cloud training SoC chips and inference SoC chips require connections to different types of memory chips, therefore, cloud training and inference cannot share the same SoC chip. With the evolution of wafer manufacturing process nodes, the cost of SoC chip fabrication is increasing, meaning the economic benefits of sharing the same SoC chip are becoming increasingly significant. Therefore, how to achieve interconnection between the same SoC chip and different types of memory chips to reduce SoC chip fabrication costs and improve economic efficiency has become a pressing technical problem to be solved. Summary of the Invention

[0006] To address at least one of the aforementioned technical problems, this disclosure provides a packaging framework, processing method, and related products for chips, thereby enabling interconnection between the same system-on-a-chip and different types of memory chips.

[0007] In one aspect, this disclosure provides a packaging framework for a chip, comprising: a packaging substrate; a first system-on-a-chip (SoC) housing region disposed on the packaging substrate for housing the first SoC; and an input / output (IoO) chip disposed on the packaging substrate; wherein the IoO chip and the chip housing region are connected via the packaging substrate.

[0008] In another aspect, this disclosure provides a packaging device comprising: a packaging frame as described above; and a first system-on-a-chip disposed in the chip accommodating region for connection to the input / output chip via the packaging substrate.

[0009] In another aspect, this disclosure provides an integrated circuit device, comprising: a packaging device as described above; a printed circuit board; and a second memory chip disposed on the printed circuit board and connected to the packaging device via the printed circuit board, thereby enabling the connection between the second memory chip and the first system-on-a-chip.

[0010] In another aspect, this disclosure provides an electronic device and board, comprising: a packaging frame or a packaging device as described above, or an integrated circuit device as described above.

[0011] In another aspect, this disclosure provides a method for fabricating a packaging frame for a chip, comprising: providing a packaging substrate having a first accommodating region and a second accommodating region thereon, wherein the first accommodating region and the second accommodating region are connected via the packaging substrate, wherein the first accommodating region is used to accommodate a first system-on-a-chip (SoC); providing an input / output chip; and disposing the input / output chip in the second accommodating region such that the input / output chip is connected to the first accommodating region via the packaging substrate.

[0012] In another aspect, this disclosure provides a method for processing a packaged device, comprising: providing a package substrate having a first accommodating region and a second accommodating region thereon, wherein the first accommodating region and the second accommodating region are connected via the package substrate; providing a first system-on-a-chip (SoC); providing an input / output chip; disposing the first SoC in the first accommodating region and disposing the input / output chip in the second accommodating region such that the input / output chip is connected to the first SoC via the package substrate.

[0013] In another aspect, this disclosure provides a method for fabricating an integrated circuit device, comprising: fabricating a packaged device as described above; providing a printed circuit board having a fourth accommodating region and a fifth accommodating region thereon, wherein the fourth accommodating region and the fifth accommodating region are connected via the printed circuit board; providing a second memory chip; disposing the packaged device in the fourth accommodating region and disposing the second memory chip in the fifth accommodating region such that the second memory chip is connected to the packaged device via the printed circuit board.

[0014] By utilizing the I / O chip-incorporated packaging scheme disclosed herein, a first system-on-a-chip (SoC) for connecting a first memory chip (e.g., a high-bandwidth memory) can be connected to a second memory chip (e.g., a double-data-rate synchronous dynamic random access memory). This enables interconnection between the same SoC and different types of memory chips, thereby reducing the SoC's wafer fabrication cost and improving product economics. Furthermore, the I / O chip-incorporated packaging scheme also allows the first SoC to connect to more second memory chips, thereby expanding storage capacity and facilitating full utilization of transmission bandwidth. Attached Figure Description

[0015] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0016] Figure 1-1 and Figure 1-2 These are schematic diagrams illustrating multiple structures of an integrated circuit device in an artificial intelligence training scenario according to embodiments of this disclosure;

[0017] Figure 2 This is a schematic diagram illustrating the structure of an integrated circuit device in an artificial intelligence inference scenario according to embodiments of this disclosure;

[0018] Figure 3-1 and Figure 3-2 This is a schematic diagram illustrating a plurality of structures of a packaging frame for a chip according to embodiments of the present disclosure;

[0019] Figure 4 This is a schematic diagram illustrating the structure of a packaged device according to an embodiment of the present disclosure;

[0020] Figure 5-1 and Figure 5-2 This is a schematic diagram illustrating a plurality of structures of an integrated circuit device according to embodiments of the present disclosure;

[0021] Figure 6This is a flowchart illustrating a method for fabricating a packaging frame for a chip according to an embodiment of this disclosure;

[0022] Figure 7 This is a flowchart illustrating a method for fabricating a packaged device according to an embodiment of this disclosure; and

[0023] Figure 8 This is a flowchart illustrating a method for fabricating an integrated circuit device according to an embodiment of the present disclosure. Detailed Implementation

[0024] The technical solutions in the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure. Furthermore, only devices related to the inventive point are shown in the accompanying drawings; other devices unrelated to the inventive point are not shown.

[0025] It should be understood that the terms "first," "second," "third," and "fourth," etc., used in the claims, specification, and drawings of this disclosure are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "including" used in the specification and claims of this disclosure indicate the presence of the described feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. The terms "available," "can be used," or "for," etc., used in the specification and claims of this disclosure indicate the presence of the described function or effect, but do not limit the state in which the function or effect is being performed.

[0026] Furthermore, it should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0027] To facilitate understanding, some terms used in this invention will be explained as follows.

[0028] A system-on-a-chip (SOC) is a system or product formed by combining multiple integrated circuits with specific functions on a single chip.

[0029] Printed circuit boards (PCBs) are used to provide electrical connections for electronic components, which helps to significantly reduce wiring and assembly errors. PCB traces enable interconnection between electronic components.

[0030] High-bandwidth memory (HBM) offers higher speed and bandwidth, making it suitable for applications with high memory bandwidth requirements, such as cloud-based AI processing.

[0031] Several embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0032] Figure 1-1 A schematic diagram of an integrated circuit device 100 in an artificial intelligence training scenario according to an embodiment of this disclosure is shown.

[0033] like Figure 1-1 As shown, in an artificial intelligence training scenario, the integrated circuit device 100 may include a printed circuit board, on which a packaging substrate may be disposed, and on which a first system-on-a-chip 101 and a first memory chip may be disposed.

[0034] The first system-on-a-chip 101 is a system-on-a-chip that can be connected to the first memory chip. Figure 1-1 In this process, the first system-on-a-chip 101 can communicate with the first memory chip through the package substrate wiring.

[0035] The first memory chip can be used to provide high-speed storage for a system-on-a-chip (SoC), for example, it can be a high-bandwidth memory chip. Figure 1-1 In this context, the first memory chip can be used to provide high-speed storage for the first system-on-a-chip 101 to support the storage and computation of massive amounts of data during the artificial intelligence training process.

[0036] like Figure 1-1 As shown, PHY stands for On-Chip Interconnect, used for data transmission between the chip and other circuit structures. Figure 1-1 In this context, PHY can be the interface between the first system-on-a-chip 101 and the first memory chip.

[0037] A data bus represents the wiring connecting chips, used to transmit data. For example... Figure 1-1 As shown, the data bus can connect the first system-on-a-chip 101 to the first memory chip via the PHY interface.

[0038] The packaging substrate is the carrier for chip packaging, serving functions such as providing electrical connections, protection, support, and assembly for the chip. Figure 1-1 In this process, the packaging substrate can be used to connect the first system-on-a-chip 101 to the first memory chip, and to connect the first system-on-a-chip 101 and the first memory chip to the PCB under the packaging substrate.

[0039] Further as Figure 1-1 As shown, the first system-on-a-chip 101 can achieve a communicative connection with the first memory chip through the wiring of the package substrate, that is, the data bus laid in the package substrate.

[0040] It needs to be understood that, despite Figure 1-1 Four first memory chips are shown, but this is merely an exemplary representation, and those skilled in the art can select any desired number of first memory chips according to actual needs.

[0041] Figure 1-2 This diagram illustrates yet another structural schematic of an integrated circuit device 100 in an artificial intelligence training scenario according to an embodiment of this disclosure.

[0042] like Figure 1-2 As shown, the packaging substrate may include a packaging substrate and a packaging interlayer.

[0043] The package substrate (PKG) serves to carry and protect the chip and to connect the chip to the underlying circuitry. Figure 1-2 In this process, the packaging substrate can be used to carry the first system-on-a-chip 101 and the first memory chip, and to realize the connection between the first system-on-a-chip 101 and the first memory chip and the PCB on the lower layer of the packaging substrate.

[0044] An interposer can be disposed on or within the packaging substrate, used to interconnect multiple chips and act as a bridge connecting the chips and the packaging substrate. The interposer can be, for example, a silicon interposer (Si interposer) or a redistribution layer interposer (RDL interposer). Through the interposer, smaller linewidth and spacing interconnects can be formed, increasing wiring density and thus meeting the requirements of high-performance chips (such as first-generation memory chips). Figure 1-2 In this process, the first system-on-a-chip 101 can communicate with the first memory chip through the traces in the package interposer (i.e., the data bus set in the package interposer).

[0045] It needs to be understood that, despite Figure 1-2 The illustration exemplifies a packaging interposer disposed on the surface of the packaging substrate, covering the area mapped between the first system-on-a-chip 101 and the first memory chip on the surface of the packaging substrate. However, in other embodiments, the packaging interposer may only cover the data bus area connecting the first system-on-a-chip 101 and the first memory chip. Furthermore, the packaging interposer may also be embedded or buried within the packaging substrate. For example, a recess can be formed on the packaging substrate, the shape and size of which are adapted to the packaging interposer. The packaging interposer can then be disposed within the recess, and the first system-on-a-chip 101 and the first memory chip can be disposed on the packaging interposer. Alternatively, a partial area of ​​the first system-on-a-chip 101 and the first memory chip, such as the area where the chip interconnect interface is located, can be disposed on the packaging interposer to achieve a communicative connection between the packaging interposer and the first system-on-a-chip 101 and the first memory chip. Furthermore, by wiring or laying lines in the packaging interposer, a communicative connection between the first system-on-a-chip 101 and the first memory chip can be achieved.

[0046] Artificial intelligence training requires processing massive amounts of data, a process that demands extremely high computing power and precision. For example... Figure 1-1 and Figure 1-2 As shown, training typically requires the setup of a memory chip (i.e., the first memory chip) that provides high-speed storage, and requires the use of advanced process nodes. For example, the interconnection between the first system-on-a-chip 101 and the first memory chip can be achieved through COWOS (Chip-on-Wafer-on-Substrate) packaging technology.

[0047] Figure 2 This is a schematic diagram illustrating the structure of an integrated circuit device 200 in an artificial intelligence reasoning scenario according to an embodiment of this disclosure.

[0048] like Figure 2 As shown, in an artificial intelligence inference scenario, the integrated circuit device 200 may include a printed circuit board, on which a packaging substrate and a second memory chip may be disposed, and on which a second system-on-a-chip 201 may be disposed.

[0049] The second system-on-a-chip 201 can be a system-on-a-chip for connection to a second memory chip. Figure 2 In this chip, the second system-on-a-chip 201 can achieve a communicative connection with the second memory chip through PCB traces, without having to achieve a communicative connection through a high-cost packaging interposer.

[0050] The bandwidth of the second memory chip can typically be lower than that of the first memory chip. For example, it can be a Double Data Rate SDRAM (DDR) chip, a Low Power Double Data Rate SDRAM (LPDDR) chip, or a Graphics Double Data Rate SDRAM (GDDR) chip.

[0051] In addition, the pin size and spacing of the second memory chip are larger than those of the first memory chip, so the connection between the second system-on-a-chip 201 and the second memory chip can be made through PCB routing.

[0052] I&F stands for the interface between the packaged system-on-a-chip (SoC) and the memory chip. Figure 2 In this context, I&F refers to the interface between the first system-on-a-chip 201 packaged and the second memory chip.

[0053] In artificial intelligence inference, pre-trained models are used directly. Their parameters are fixed, and massive amounts of data computation are not required. Therefore, the requirements for computational performance, accuracy, and versatility are not as stringent. Consequently, in this scenario, there is no need to use extremely expensive memory chips used for high-speed storage (i.e., high-performance memory chips). Figure 1-1 and Figure 1-2 (The first memory chip shown). Figure 2 As shown, in the inference scenario, a second memory chip can be set up and connected to the packaged second system-on-a-chip 201 via PCB traces.

[0054] In summary, in different application scenarios, such as artificial intelligence training and inference, system-on-a-chip (SoC) needs to connect to different types of memory chips, thus making it impossible to share the same SoC. Furthermore, as wafer manufacturing process nodes evolve, the cost of SoC fabrication increases, meaning the economic benefits of sharing the same SoC become increasingly significant.

[0055] In view of this, this disclosure provides a better solution. Figure 3-1 This is a schematic diagram illustrating a package frame 300 for a chip according to an embodiment of this disclosure.

[0056] like Figure 3-1A packaging frame 300 for a chip is provided. The packaging frame 300 includes a packaging substrate; a first system-on-a-chip (SoC) housing area 301 disposed on the packaging substrate for housing the first SoC 101; and an input / output chip disposed on the packaging substrate; wherein the input / output chip and the first SoC housing area are connected through the packaging substrate.

[0057] An input / output chip (I / O chip) is a type of data transfer chip. In this disclosure, the I / O chip can be used to implement data communication or transmission between the first system-on-a-chip 101 and the second memory chip. For specific implementation details, please refer to the following description. Figure 5-1 and Figure 5-2 The description.

[0058] like Figure 3-1 As shown, the I / O chip is mounted on the package substrate. More specifically, the I / O chip can be connected to the pins of the package substrate by means of, for example, soldering.

[0059] Combination Figure 1-1 or Figure 1-2 As shown, the first system-on-a-chip 101 can be used to connect with the first memory chip. Therefore, by integrating the input / output chip package framework 100, the same system-on-a-chip (i.e., the first system-on-a-chip 101) can be connected with different types of memory chips (i.e., the first memory chip and the second memory chip), avoiding the increased wafer fabrication costs caused by designing different system-on-a-chips to adapt to different application scenarios (such as cloud inference and training).

[0060] It should be understood that descriptions such as "the first system-on-a-chip 101 is used or can be used to connect with the first memory chip" in this article only indicate that the first system-on-a-chip 101 is a system-on-a-chip that can be used to connect with the first memory chip, and do not limit the two to being physically connected.

[0061] In addition, there can be multiple I / O chips, and the multiple I / O chips are arranged around the first system-on-chip (SoC) storage area 301 to facilitate communication with multiple interfaces of the SoC.

[0062] like Figure 3-1 As shown, there can be four I / O chips, which can be symmetrically arranged on both sides of the first on-chip system chip storage area 301. The two I / O chips on the same side can be located at the two ends of the storage area 301, so as to maximize the spacing between the two I / O chips on the same side, facilitate wiring, and then be used to connect with more second memory chips.

[0063] However, in other embodiments, the number and arrangement of I / O chips are not limited to the methods described above, but can be specifically designed according to bandwidth, product space size, and shape. For example, the number of I / O chips can be only two, located on both sides of the first on-chip system chip storage area 301, or it can be set to six, with three on each side. In addition, the I / O chips are not limited to being located only on both sides of the first on-chip system chip storage area 301; they can be evenly distributed around the first on-chip system chip storage area 301.

[0064] Furthermore, such as Figure 3-1 As shown, the I / O chip can be quadrilateral. Each side can have a connection interface, arranged as follows: one side or one interface (the side or interface closest to the first system-on-a-chip (SoC) storage area 301) is used to connect to the SoC storage area 301, and the remaining three sides or three interfaces are used to connect to the second memory chips. This layout design allows one I / O chip to interconnect with multiple second memory chips, facilitating the connection of more second memory chips and fully utilizing the transmission bandwidth of the SoC.

[0065] More specifically, such as Figure 3-1 As shown, the I / O chip can be rectangular. In the figure, PHY x32 / PHY x64 represent the interfaces on the I / O chip used to connect to 32-bit / 64-bit second memory chips, respectively. One side of the I / O chip's long side has an interface for connecting to the first system-on-a-chip (SoC) storage area 301, and the opposite side has an interface for connecting to a 64-bit second memory chip. The two short sides have interfaces for connecting to 32-bit and 64-bit second memory chips, respectively. In one embodiment, an I / O chip can interconnect with the SoC storage area 301 through one side's chip interface, and then interconnect with multiple 32-bit or 64-bit second memory chips through the chip interfaces on the other sides, ultimately achieving interconnection between the SoC storage area 301 and multiple second memory chips.

[0066] Furthermore, without affecting the routing or data bus layout between the I / O chip and the first system-on-a-chip (SoC) storage area 301, such as without affecting the normal signal transmission, routing yield, or process feasibility between the two, the I / O chip can be placed adjacent to the storage area 301, which helps to reduce latency and reduce the area occupied by the routing area, thereby reducing costs.

[0067] The first system-on-a-chip (SoC) accommodating area 301 refers to an area used to accommodate the first SoC 101. This accommodating area 301 can be configured to connect with the first SoC 101 by adapting its pins. By configuring this accommodating area 301, it is possible to flexibly adapt to different application requirements; it also facilitates streamlined production, as the SoC can be packaged simply by placing it in this area and completing the pin connections, thus improving production efficiency.

[0068] like Figure 3-1 As shown, the accommodating area 301 can be set as a square. However, in other embodiments, the accommodating area can also be other shapes, such as rectangles, circles, etc. Preferably, the packaging frame 300 can be designed for different sizes or shapes of system-on-a-chip chips to ensure mass production while making the shape and size of the accommodating area 301 as close as possible to the shape and size of the SOC chip to be packaged (1:1), thereby reducing costs and improving packaging efficiency.

[0069] exist Figure 3-1 In this package, the packaging substrate can be used to carry I / O chips and chips to be placed in the first system-on-a-chip (SoC) accommodating area 301, and can also be used to realize the interconnection between the first SoC accommodating area 301 and the I / O chips, as well as to realize the connection between the first SoC accommodating area 301 and the I / O chips and other circuit structures (such as PCB) in the lower layer of the package frame.

[0070] Figure 3-2 This is yet another structural schematic diagram illustrating a packaging frame for a chip according to an embodiment of this disclosure.

[0071] like Figure 3-2 As shown, the packaging substrate may include a packaging substrate and a packaging interlayer. The interlayer may be disposed on the packaging substrate or disposed in the packaging substrate. The I / O chip and the first on-chip system chip storage area 301 can be connected through the packaging interlayer.

[0072] The encapsulation interposer can be a silicon interposer. And... Figure 3-2 In this design, the package interposer is relatively small, covering only the wiring or data bus area between the housing area 301 and the I / O chip, thus effectively reducing the cost of the package interposer. Furthermore, this package interposer can be embedded or embedded in the package substrate, such as... Figure 3-2As shown, by embedding a small piece of the encapsulation interposer into the encapsulation substrate, interconnection between the storage area 301 and the I / O chip can be achieved. Simultaneously, the contact surface between the encapsulation substrate and the chip to be encapsulated can be planar, thereby helping to reduce the complexity of the encapsulation and ensuring the structural stability of the entire encapsulation framework. Furthermore, each I / O chip can have its wiring area in the storage area 301 configured as shown in the diagram. Figure 3-2 The encapsulation intermediary layer shown ( Figure 3-2 (Only one location is shown in the diagram, the other three are not shown), to facilitate the interconnection of each I / O chip with the capacitive storage area 301.

[0073] In other embodiments, the package interposer may also be an RDL interposer. The package interposer may also be configured to cover the entire containment area 301 and the I / O chip. Alternatively, the package interposer may be disposed on the package substrate.

[0074] Figure 4 This is a schematic diagram illustrating the structure of a packaged device 400 according to an embodiment of the present disclosure.

[0075] like Figure 4 As shown, the packaging device 400 may include the packaging frame 300 for the chip as described above; and a first system-on-a-chip 101 disposed in the first system-on-a-chip containment area 301 to be connected to the I / O chip via the packaging substrate.

[0076] The first system-on-a-chip 101 is a system-on-a-chip that can be connected to the first memory chip. For example... Figure 4 As shown, the first system-on-a-chip 101 can be used to achieve a communicative connection with the I / O chip through the wiring of the package substrate. Then, through the I / O chip, it can further connect with other circuit structures (such as a second memory chip) outside the package device 400. In addition to enabling the connection between the first system-on-a-chip 101 and the I / O chip, the package substrate can also be used to carry the I / O chip and the first system-on-a-chip 101, and to enable the connection between the first system-on-a-chip 101 and the I / O chip and other circuit structures (such as a PCB) under the package device.

[0077] More specifically, such as Figure 4 The detailed description of the function, specific settings, quantity, shape, interface layout, etc. of the I / O chips shown is consistent with the previous text. Figure 3-1 and Figure 3-2 The descriptions of the corresponding I / O chips are the same or similar, and will not be repeated here. A detailed description of the connection between the first system-on-a-chip 101 and the I / O chips is provided in conjunction with the preceding text. Figure 3-1 and Figure 3-2The contents of the first on-chip system-on-a-chip (SoC) amplifier area 301 and the I / O chip connection described herein are the same or similar, and will not be repeated here.

[0078] Figure 5-1 This is a schematic diagram illustrating the structure of an integrated circuit device 500 according to an embodiment of the present disclosure.

[0079] like Figure 5-1 As shown, an integrated circuit device 500 is provided, including: a packaged device 400 as described above (i.e., Figure 5-1 The structure within the dashed box; a printed circuit board; and a second memory chip, which is disposed on the printed circuit board and connected to the package device 400 through the printed circuit board, thereby realizing the connection between the second memory chip and the first system-on-a-chip 101.

[0080] More specifically, the second memory chip can achieve a communicative connection with the packaged device 400 through printed circuit board traces, i.e., data buses laid in the printed circuit board.

[0081] As mentioned above, the bandwidth of the second memory chip is lower than that of the first memory chip, and it can be a DDR, LPDDR or GDDR chip, etc.

[0082] The pin size and pitch of the second memory chip are both larger than those of the first memory chip. More specifically, the pin size and pitch of the second memory chip are usually much larger than those of the first memory chip. For example, the first memory chip can be HBM2E, with a pin pitch of 55um in the X direction and 96um in the Y direction, and a pin size of 25um x 25um; the second memory chip can be LPDDR5, with a pin pitch of 0.4mm and a pin size of 0.26mm.

[0083] The first system-on-a-chip (SoC) 101 disclosed herein can be used to connect to a first memory chip; therefore, the pin pitch and size of its interface must first be adapted to the pin pitch and size of the first memory chip. To reduce wafer fabrication costs, this type of SoC 101 must also be able to connect to a second memory chip. Due to the differences in pin pitch and size between the two, very fine manufacturing processes are required. For example, the SoC 101 can connect to the second memory chip using a packaging interposer process. However, since the interface (pins) of the second memory chip (not shown in the figure) essentially occupies the entire area of ​​the second memory chip, it is usually necessary to place the entire second memory chip on the packaging interposer. This approach significantly increases the size of the packaging interposer, leading to increased packaging costs and consequently, a very high cost for the entire chip product.

[0084] Therefore, as Figure 5-1 As shown, this invention introduces an I / O chip packaging scheme to achieve interconnection between the first system-on-a-chip 101 and the I / O chip with a smaller packaging cost. Then, the interconnection with the second memory chip can be achieved through ordinary PCB routing process, thereby reducing the cost of the entire product.

[0085] Furthermore, there can be multiple second memory chips, and these multiple second memory chips can be connected to the first system-on-a-chip 101 through the I / O chip. More specifically, the number of second memory chips can be greater than the number of I / O chips.

[0086] I&F stands for the interface on a packaged system-on-a-chip (SoC) that interconnects with the memory chip. Figure 5-1 In the diagram, I&Fx32 / x64 represent the interfaces on the packaged device 400 that interconnect with the 32-bit / 64-bit second memory chip, respectively.

[0087] PHY stands for On-Chip Interconnect, used for data transmission between the chip and other circuit structures. Figure 5-1 In this context, PHY refers to the interface on the I / O chip used to connect the first system-on-a-chip 101 and the second memory chip.

[0088] like Figure 5-1 As shown, each I / O chip can have four interconnect interfaces (PHYs). One interface is used to connect to the first system-on-a-chip 101, and the other three interfaces are used to connect to the second memory chip. More specifically, the three interfaces of each I / O chip for connecting to the second memory chip may include two 32-bit interfaces and one 64-bit interface, which can be used to connect two 32-bit second memory chips and one 64-bit second memory chip respectively, or they can be used to connect one 32-bit second memory chip and two 64-bit second memory chips respectively by cooperating with other I / O chips. In addition, the I / O chip and the second memory chip can be arranged adjacent to each other to facilitate communication connection with shorter traces, reduce cost, and reduce latency.

[0089] Furthermore, such as Figure 5-1As shown, there can be four I / O chips and six second memory chips. The four I / O chips are respectively disposed on both sides of the first system-on-a-chip (SoC) 101, and are formed into a package device 400 with the SoC 101 using, for example, a chiplet packaging scheme. The six second memory chips are respectively disposed on both sides of the package device 400 or the package substrate, and can be disposed adjacent to the I / O chips, with interconnection with the package device 400 completed on the printed circuit board. Each I / O chip has a communicative connection with two second memory chips, and each I / O chip has one interface in an idle state.

[0090] It should be understood that the number of I / O chips and second memory chips, the interface layout, and the interface utilization or idle rate mentioned above can all be set according to actual needs. This article does not impose any restrictions.

[0091] Figure 5-2 This is yet another structural schematic diagram of an integrated circuit device 500 according to an embodiment of the present disclosure.

[0092] like Figure 5-2 As shown, the second memory chip can be configured with 10 chips, each fully connected to one of the four interfaces of the I / O chip. This ensures that there are no idle interfaces on the I / O chip, achieving 100% interface utilization. This design facilitates the expansion of storage capacity and makes full use of transmission bandwidth.

[0093] In some embodiments, this disclosure also discloses an electronic device that includes the aforementioned packaging frame 300, packaging device 400, or integrated circuit device 500.

[0094] In some embodiments, this disclosure also discloses a board that includes the aforementioned packaging frame 300, packaging device 400, or integrated circuit device 500.

[0095] Figure 6 This is a flowchart illustrating a method 600 for fabricating a chip packaging frame according to an embodiment of this disclosure.

[0096] like Figure 6 As shown, at operation 601, method 600 provides a package substrate having a first accommodating region and a second accommodating region thereon, and the first accommodating region and the second accommodating region are connected via the package substrate, wherein the first accommodating region is used to accommodate a first system-on-a-chip 101; as shown in FIG3, those skilled in the art will understand that the first and second accommodating regions here can be adapted to the size and pins of the first system-on-a-chip 101 and the I / O chip, respectively.

[0097] At operation 602, method 600 provides an I / O chip.

[0098] At operation 603, method 600 places the I / O chip provided in operation 602 into the second accommodating region described in operation 601, thereby connecting it to the first accommodating region via a package substrate.

[0099] In one implementation scenario, there can be multiple I / O chips, which are set up separately. Therefore, multiple second storage areas can be set up to accommodate multiple I / O chips respectively.

[0100] More specifically, the I / O chip can be set into the second capacitor area by means of, for example, soldering.

[0101] Figure 7 This is a flowchart illustrating a method 700 for fabricating a packaged device according to an embodiment of this disclosure.

[0102] like Figure 7 As shown, at operation 701, method 700 provides a package substrate having a first accommodating region and a second accommodating region thereon, and the first accommodating region and the second accommodating region are connected via the package substrate; as Figure 4 As shown in Figure 5, those skilled in the art will understand that the first and second capacities here can be adapted to the size and pinout of the first system-on-chip 101 and the I / O chip.

[0103] At operation 702, method 700 provides a first system-on-chip 101 and an I / O chip.

[0104] At operation 703, method 700 places the first system-on-a-chip 101 provided in operation 702 into the first accommodating area described in operation 701, and places the I / O chip provided in operation 702 into the second accommodating area described in operation 701, thereby realizing the interconnection between the first system-on-a-chip 101 and the I / O chip through the packaging substrate.

[0105] Figure 8 This is a flowchart illustrating a method 800 for fabricating an integrated circuit device according to an embodiment of this disclosure.

[0106] like Figure 8 As shown, method 800 includes the various operations in method 700 described above, and also includes operations 704, 705 and 706.

[0107] At operation 704, method 800 provides a printed circuit board having a fourth and a fifth accommodating region, and the fourth and fifth accommodating regions are connected via the printed circuit board. As shown in Figure 5, those skilled in the art will understand that the fourth and fifth accommodating regions here can be adapted to the size and pinout of the package device 400 and the second memory chip.

[0108] At operation 705, method 800 provides a second memory chip.

[0109] At operation 706, method 800 places the packaged device 400 obtained by processing method 700 into the fourth accommodating area described in operation 704, and places the second memory chip provided in operation 705 into the fifth accommodating area described in operation 704, thereby realizing the interconnection of the packaged device 400 and the second memory chip through a printed circuit board.

[0110] It is important to understand that the above Figures 6-8 The processing and assembly method described herein is merely an example, and any method that uses discrete components to form the product disclosed herein falls within the protection scope of this disclosure.

[0111] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0112] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0113] It should also be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this disclosure, those skilled in the art will understand that some operations can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

Claims

1. A packaging frame for a chip, comprising: Packaging substrate; The first system-on-a-chip (SoC) storage area is disposed on the packaging substrate and is used to store the first SoC. An input / output chip is disposed on the package substrate. The input / output chip is a data transfer chip used to realize data communication between the first system-on-a-chip and the memory chip. The input / output chip and the chip storage area are connected through the packaging substrate.

2. The packaging framework according to claim 1, wherein the first system-on-a-chip can be used to connect to the first memory chip.

3. The packaging framework according to claim 2, wherein the first memory chip is a high-bandwidth memory.

4. The packaging frame according to any one of claims 1-3, wherein the packaging substrate includes a packaging substrate and a packaging interposer, and the input / output chip is connected to the chip housing area through the packaging interposer.

5. The packaging framework according to claim 4, wherein the packaging interlayer is a silicon interlayer or a redistributed interlayer.

6. The packaging framework according to any one of claims 1-3, wherein there are multiple input / output chips, and the multiple input / output chips are disposed around the first system-on-a-chip (SoC) housing area.

7. A packaged device, comprising: The encapsulation framework according to any one of claims 1-6; The first system-on-a-chip is disposed in the chip storage area to be connected to the input / output chip through the package substrate.

8. An integrated circuit device, comprising: The packaging device as described in claim 7; Printed circuit boards; The second memory chip is disposed on the printed circuit board and connected to the packaging device through the printed circuit board, thereby realizing the connection between the second memory chip and the first system-on-a-chip.

9. The integrated circuit device according to claim 8, wherein the second memory chip is a double-rate synchronous dynamic random access memory.

10. The integrated circuit device according to claim 8 or 9, wherein there are multiple second memory chips, and the multiple second memory chips are connected to the first system-on-a-chip via the input / output chip.

11. The integrated circuit device according to any one of claims 8-9, wherein the number of the second memory chips is greater than the number of the input / output chips.

12. An electronic device comprising a packaging frame according to any one of claims 1-6, a packaging device according to claim 7, or an integrated circuit device according to any one of claims 8-11.

13. A board comprising a packaging frame according to any one of claims 1-6, a packaging device according to claim 7, or an integrated circuit device according to any one of claims 8-11.

14. A method for fabricating a chip packaging frame, comprising: A packaging substrate is provided having a first accommodating region and a second accommodating region thereon, and the first accommodating region and the second accommodating region are connected via the packaging substrate, wherein the first accommodating region is used to accommodate a first system-on-a-chip (SoC). An input / output chip is provided, wherein the input / output chip is a data transfer chip used to realize data communication between the first system-on-a-chip and the memory chip; The input / output chip is positioned in the second storage area so that the input / output chip is connected to the first storage area through the package substrate.

15. A method for processing a packaged device, comprising: A packaging substrate is provided having a first accommodating region and a second accommodating region thereon, and the first accommodating region and the second accommodating region are connected via the packaging substrate; Provide the first system-on-a-chip; An input / output chip is provided, wherein the input / output chip is a data transfer chip used to realize data communication between the first system-on-a-chip and the memory chip; The first system-on-a-chip (SoC) is placed in the first storage area, and the input / output (I / O) chip is placed in the second storage area, so that the I / O chip is connected to the first SoC through the package substrate.

16. A method for fabricating an integrated circuit device, comprising: The method for processing the packaged device according to claim 15; A printed circuit board is provided having a fourth accommodating area and a fifth accommodating area, and the fourth accommodating area and the fifth accommodating area are connected via the printed circuit board; Provide a second memory chip; The packaged device is placed in the fourth storage area, and the second memory chip is placed in the fifth storage area, so that the second memory chip is connected to the packaged device through a printed circuit board.

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