Hybrid imaging detector and method of manufacture

Abstract

The application provides a hybrid imaging detector and a preparation method, and relates to the technical field of semiconductors. The hybrid imaging detector comprises a visible light detector, an intermediate part with a cavity and an infrared detector which are sequentially stacked in a vertical direction; wherein the intermediate part is internally provided with a shielding structure, and the shielding structure is located at the periphery of the cavity; the infrared detector receives incident light and absorbs an infrared light part in the incident light, and the part of light filtered out by the infrared detector is incident on the shielding structure through the cavity and is reflected into the cavity; and the visible light detector absorbs a visible light part in the incident light. While realizing a single chip, the application can improve the absorption rate of visible light and thus improve the hybrid imaging quality.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a hybrid imaging detector and its fabrication method. Background Technology

[0002] In existing technologies, pure infrared imaging or pure visible light imaging techniques are relatively mature. For example, uncooled infrared detectors typically use MEMS (Micro Electro Mechanical System) microbridge resonant cavity structures to detect mid- and far-infrared signals; while conventional visible light detectors generally use Si-based PN junctions in CMOS (Complementary Metal Oxide Semiconductor) image sensors to detect signals in the visible light band. However, with the development of applications in fields such as autonomous driving, aerospace, and military, pure infrared imaging or pure visible light imaging techniques can no longer meet the requirements. In other words, multi-band image fusion is now required.

[0003] To achieve the fusion of multi-band images, existing technologies utilize several independent optical systems to generate visible light or infrared images, and then use techniques such as soft algorithms to achieve image fusion.

[0004] The above-mentioned solution achieves multi-band image fusion to a certain extent. However, it consists of multiple optical systems and requires multiple chips for light absorption. Therefore, the system is bulky, costly, and unfavorable for market expansion and large-scale application. Furthermore, the above solution does not consider the quality issues of hybrid imaging. Summary of the Invention

[0005] This application provides a hybrid imaging detector and its fabrication method, which can improve the absorption rate of visible light while realizing a single chip, thereby improving the quality of hybrid imaging.

[0006] According to a first aspect of this application, a hybrid imaging detector is provided, comprising: a visible light detector, an intermediate component having a cavity, and an infrared detector stacked sequentially in a vertical direction; wherein, the intermediate component has a shielding structure inside, and the shielding structure is located on the periphery of the cavity;

[0007] The infrared detector receives incident light and absorbs the infrared portion of the incident light to generate a first electrical signal for hybrid imaging.

[0008] The shielding structure reflects a portion of the light filtered out by the infrared detector back into the cavity;

[0009] The visible light detector absorbs the visible light portion of the incident light to generate a second electrical signal for hybrid imaging.

[0010] According to a second aspect of this application, a method for fabricating a hybrid imaging detector is provided, comprising:

[0011] A substrate is provided, and a first P-type region, an output terminal, and an N-type region of a visible light detector are fabricated on the upper surface of the substrate by ion implantation.

[0012] A gate dielectric layer and a polysilicon gate electrode layer are formed, and intermediate components, contact holes and leads are formed using a back-end process. The intermediate components include an interconnect dielectric layer, a pier structure for forming a shielding structure and a first dielectric layer.

[0013] A cavity is formed by etching a first dielectric layer and an interconnect dielectric layer on the intermediate component, and the polysilicon gate electrode layer, the gate dielectric layer and the surface of the first P-type region facing the cavity are etched in sequence to expose the silicon surface;

[0014] An epitaxial sacrificial layer is formed on the silicon surface until the sacrificial layer is higher than the upper surface of the first dielectric layer;

[0015] The sacrificial layer was smoothed using chemical mechanical polishing.

[0016] The support layer, sensitive layer, electrode layer and absorption layer are deposited and patterned respectively to form an infrared detector with a microbridge structure;

[0017] A second P-type region of a visible light detector is fabricated on the lower surface of the N-type region;

[0018] A through-silicon via (TSV) is fabricated so that the lead-out terminal connects the first P-type region to the second P-type region through the TSV;

[0019] The sacrificial layer is removed using a wet process to create a suspended microbridge structure between the infrared detector and the shielding structure.

[0020] This application provides a hybrid imaging detector and its fabrication method, comprising: a visible light detector, a cavity-containing intermediate component, and an infrared detector stacked sequentially along a vertical direction. This application first absorbs infrared light, then absorbs visible light. Because the intermediate component has an internal shielding structure, after the infrared detector absorbs the infrared portion of the incident light, the portion of light not absorbed by the infrared detector passes through the cavity and is incident on the shielding structure. The shielding structure reflects this portion of light back into the cavity, thereby increasing the intensity of the visible light incident on the visible light detector. Therefore, this application achieves hybrid imaging on a single chip while improving the absorption rate of visible light, thus improving the quality of hybrid imaging.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] Figure 1 This is a schematic diagram illustrating the application scenarios involved in the embodiments of this application;

[0024] Figure 2 This is a schematic diagram of the structure of a hybrid imaging detector provided in an embodiment of this application;

[0025] Figure 3 This is a schematic flowchart illustrating a method for fabricating a hybrid imaging detector according to an embodiment of this application.

[0026] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0028] To facilitate understanding, the application scenarios of the embodiments of this application will be introduced first.

[0029] Figure 1This is a schematic diagram illustrating an application scenario involved in an embodiment of this application. For example... Figure 1 As shown, this embodiment involves the application of detectors and controllers. For the visible and infrared light bands, the detector typically provides two chip structures to perform light conversion separately. The controller then fuses the two images to obtain a hybrid imaging result. On one hand, the separation of the optical paths causes significant alignment deviations between the resulting infrared and visible light image portions, severely affecting image quality. On the other hand, the above solution consists of multiple optical systems, requiring multiple chips for light absorption. Therefore, this system is bulky, costly, and hinders market expansion and large-scale application.

[0030] To address at least one of the aforementioned technical problems, this application provides a hybrid imaging detector and its fabrication method, applicable to the semiconductor field, to solve the technical problem of poor hybrid imaging quality caused by the need for multiple chips to absorb light in the prior art.

[0031] This application designs a visible light detector and an infrared detector on the same chip. Infrared light is absorbed first, followed by visible light absorption. During the absorption process, the shielding structure inside the intermediate component of the chip reflects the portion of light that is not absorbed by the infrared detector into the cavity, and then onto the visible light detector. Therefore, this application can improve the absorption rate of visible light while realizing a hybrid imaging single chip, thereby improving the quality of hybrid imaging.

[0032] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0033] Figure 2 This is a schematic diagram of a hybrid imaging detector provided in an embodiment of this application. The hybrid imaging detector of this embodiment includes: a visible light detector, an intermediate component with a cavity, and an infrared detector stacked sequentially along a vertical direction; wherein, the intermediate component has a shielding structure inside, and the shielding structure is located on the periphery of the cavity;

[0034] The infrared detector receives the first incident light (i.e. Figure 2 (The arrow in the image) and absorbs the infrared portion of the first incident light to generate a first electrical signal for hybrid imaging; wherein, a first portion of the first incident light that is not absorbed by the infrared detector is incident on the shielding structure through the cavity;

[0035] The shielding structure reflects the first portion of light into the cavity, so that the first portion of light merges with the second portion of light in the first incident light that is not absorbed by the infrared detector in the cavity to form the second incident light that is incident on the visible light detector; the angle between the emission direction of the first portion of light and the horizontal plane where the infrared detector is located is smaller than the angle between the emission direction of the second portion of light and the horizontal plane where the infrared detector is located.

[0036] The visible light detector receives the second incident light and absorbs the visible light portion of the second incident light to generate a second electrical signal for hybrid imaging.

[0037] It should be understood that the embodiments of this application can be understood using the descriptive terms "first" and "second" to refer to incident light and partial light at different locations. Specifically, the first incident light is the light incident on the infrared detector, and the second incident light is the light incident on the visible light detector. The first partial light is the light that passes through the cavity and is incident on the shielding structure, while the second partial light is the light filtered out by the infrared detector and directly incident on the visible light detector. The cavity is a resonant cavity designed in this application to ensure that after light transmission, the first partial light of the first incident light that is not absorbed by the infrared detector is reflected back to the cavity through the reflective layer (i.e., the shielding structure), forming reabsorption within the cavity. The function of the shielding structure is to prevent light from passing through the shielding layer and transmitting into the interior of other pixels, thereby causing light loss or crosstalk. It should be understood that the pixel shape of the image corresponds to the shape of the cavity. For example, if the pixels of the image are square, the cavity is also square; if the pixels of the image are circular, the cavity is also circular; if the pixels of the image are octagonal, the cavity is also octagonal. This application embodiment integrates visible light and infrared detection technologies onto a single chip to achieve image fusion, which has advantages such as low cost and high performance.

[0038] In one possible implementation, the visible light detector includes a PNP-type photosensitive area on a substrate and a first electrical connection component located on one side of the PNP-type photosensitive area;

[0039] The PNP type photosensitive areas are arranged in sequence along a direction perpendicular to the infrared detector, including a first P-type region 101, an N-type region 102, and a second P-type region 103, and the first P-type region 101 and the second P-type region 103 are connected by a first electrical connection component.

[0040] In this embodiment of the application, the substrate may refer to a P-type substrate, such as... Figure 2As shown, the peripheral region of the PNP-type photosensitive area is a P-type substrate. The PNP-type photosensitive area is also called the visible light photosensitive area. The first P-type region 101 is also called the front P-type pin layer, and the second P-type region 103 is also called the back P-type pin layer. This application forms three layers—the first P-type region 101, the N-type region 102, and the second P-type region 103—through ion doping. It should be noted that the cavity is above the PNP-type photosensitive area. The PNP-type photosensitive area forms a PNP in the vertical direction, equivalent to two PN junctions connected head-to-head. The visible light photosensitive area is mainly in the N-type region 102, which is wider than the two P-type regions. Since voltage can be applied to both the upper and lower P-type regions, the N-type region 102 can be made longer.

[0041] The first electrical connection component includes a through-silicon via (TSV) 104 and a lead-out terminal; the TSV 104 penetrates the second P-type region 103, and the bottom of the TSV 104 is flush with the bottom of the second P-type region 103; the top of the TSV 104 is higher than the top of the second P-type region 103 and is located in the substrate; the lead-out terminal includes a P-region 105; the P-region 105 is located on one side of the first P-type region 101, and the lower surface of the P-region 105 is connected to the upper surface of the TSV 104.

[0042] In this embodiment of the application, P region 105 can be a P+ region. According to... Figure 2 As can be seen, the back-side P-type pin layer is connected to the front-side P-type pin layer through the TSV (i.e., the aforementioned through-silicon via 104) and the P+ region, and then the second electrical signal is output through the contact hole 106 and the lead 107. It should be understood that the lead 107 is made of metal, allowing it to be connected to other circuits, while the N-type region is located between the two pin layers. The visible light detector designed in this embodiment has the advantages of low on-state voltage and the ability to amplify small signals.

[0043] In one possible implementation, the infrared detector includes a microbridge structure with an undulating surface on top and a second electrical connection component 301; the microbridge structure includes an absorption layer 302, a sensitive layer 303, an electrode layer 304, and a support layer 305; the two ends of the support layer 305 are mounted on the cavity, and its cross-sectional length is greater than the cross-sectional length of the cavity; the sensitive layer 303 is located above the support layer 305, and the cross-sectional length of the sensitive layer 303 is less than the cross-sectional length of the support layer 305, so that the sensitive layer 303 is surrounded by the support layer 305, the absorption layer 302, and the electrode layer 304; the electrode layer 304 covers the portion of the sensitive layer 303 away from the support layer 305 and its sidewalls, the portion of the support layer 305 away from the cavity and its sidewalls, the surface of the second electrical connection component 301, and the sidewalls of a portion of the intermediate component. Both sides of the electrode layer 304 have stepped structures, and the electrode layer 304 at the location of the bottom step covers the surface of the second electrical connection component 301. It should be understood that the electrode layer 304 can cover the entire surface of the second electrical connection component 301, or it can cover a part of the surface of the second electrical connection component 301. When the electrode layer 304 covers a part of the surface of the second electrical connection component 301, the part of the second electrical connection component 301 not covered by the electrode layer 304 can be covered by the above-mentioned dielectric upper layer 2022. Therefore, this application embodiment does not specifically limit the coverage area of ​​the surface of the second electrical connection component covered by the electrode layer 304. The absorption layer 302 covers the sensitive layer 303 and the electrode layer 304. In this application embodiment, the top of the intermediate component is first etched to form a contact trench, and then metal is deposited in the contact trench to form the above-mentioned second electrical connection component 301. The specific formation process of the above-mentioned second electrical connection component 301 is exemplary. In practical applications, this application embodiment does not specifically limit the specific formation process of the second electrical connection component 301. In this embodiment, the resistance of the sensitive layer 303 is defined by the pattern of the electrode layer 304 on the sensitive layer 303. Furthermore, in this embodiment, the electrode layers 304 at the stepped structures on both sides are sequentially connected to the surface of the second electrical connection component 301 along the upper surface of the support layer 305, the side surface of the support layer 305, and the side surface of the dielectric upper layer 2022. The bottom of the microbridge structure is in contact with the upper surface of the second electrical connection component 301 and the upper surface of the intermediate component. The microbridge structure is located at the top of the infrared detector and is used to receive incident light and absorb the infrared portion of the incident light.

[0044] Furthermore, the absorption layer 302 absorbs the infrared light portion, and the sensitive layer 303 heats the infrared signal to generate a thermal signal, which is then converted into an electrical signal, such as a resistance signal or other electrical signal, and led to the second electrical connection component 301 through the electrode layer 304. When the sacrificial layer is removed using a wet etching process, the support layer 305 and the absorption layer 302 can protect the electrode layer 304 and the sensitive layer 303, preventing them from being damaged by external processes.

[0045] In one possible implementation, the intermediate component further includes multiple interconnect dielectric layers 201 and a first dielectric layer 202. The multiple interconnect dielectric layers 201 are located on the upper surface of the visible light detector and surround the cavity. The first dielectric layer 202 is located on the top layer of the multiple interconnect dielectric layers 201 away from the visible light detector and surrounds the cavity. A shielding structure and a second electrical connection component 301 are sequentially arranged from the inside to the outside of the cavity. Furthermore, the shielding structure is a continuous shielding structure in a top view. The first dielectric layer 202 includes a lower dielectric layer 2021 and a upper dielectric layer 2022. Since the contact trench is located in the lower dielectric layer 2021, the aforementioned second electrical connection component 301 is formed in the lower dielectric layer 2021, and the surface of the second electrical connection component 301 away from the visible light detector is in contact with the electrode layer 304. In addition, the shielding structure of the top layer is also formed in the lower dielectric layer 2021, and the upper dielectric layer 2022 covers the surface of the shielding structure of the top layer and the surface of the lower dielectric layer 2021.

[0046] In one possible implementation, the lead-out terminal also includes a contact hole 106 and a lead wire 107 stacked sequentially above the P region 105; the contact hole 106 and the lead wire 107 are both located in the bottom layer of the multiple interconnect dielectric layers 201 and are located outside the shielding structure.

[0047] In this embodiment, the interconnect dielectric layer 201 is made of materials including, but not limited to, silicon oxide, while the underlying dielectric layer 2021 is made of materials including, but not limited to, silicon nitride and silicon carbide. This embodiment does not specifically limit the material of the upper dielectric layer 2022. The microbridge deck structure is supported by stacking the support layer 305 on both ends of the upper dielectric layer 2022.

[0048] In one possible implementation, the shielding structure includes a vertically connected pier structure 206, a polycrystalline gate structure 207, and a gate dielectric structure 208. The pier structure 206 is located above the polycrystalline gate structure 207. Since the top-layer shielding structure is specifically the top-layer pier structure 206, and the upper dielectric layer 2022 covers the surface of the top-layer shielding structure, the upper dielectric layer 2022 covers the upper surface of the top-layer pier structure 206. The polycrystalline gate structure 207 is located above the gate dielectric structure 208, and the lower surface of the gate dielectric structure 208 is connected to the visible light detector.

[0049] In this embodiment, the pier structure 206 can be composed of different metals. For example... Figure 2 As shown, the pier structure 206 is a structure with one layer of through holes and one layer of interconnecting wires. The shielding structure is located in the interconnecting medium layer 201. There are two implementation processes for forming the pier structure 206: one is the aluminum process and the other is the copper process. For the aluminum process, the material of the through holes is titanium (Ti), titanium carbide (TiN), or tungsten, and the material of the interconnecting wires is aluminum. For the copper process, the material of both the through holes and the interconnecting wires is copper.

[0050] In this embodiment, the pier structure 206 can be disposed outside the cavity structure. In a specific embodiment, the pier structure 206 can also serve as the cavity sidewall. In this case, the cavity sidewall includes a shielding structure made of metal. In this embodiment, the polycrystalline gate structure 207 is also referred to as a polycrystalline silicon gate electrode. Starting from the gate dielectric structure 208, through the polycrystalline gate structure 207 to the pier structure 206, these three structures are used to jointly surround the cavity. In practical applications, some light inside the cavity can be incident on the shielding structure when the angle is relatively large. Then, because the metal material on the shielding structure has a strong reflection of light, the incident light is reflected into the cavity by the shielding structure and absorbed, thereby improving the absorption rate and preventing it from being transmitted to other areas through the cavity sidewall.

[0051] Furthermore, the upper surface of the first P-type region 101 has a recessed structure. It should be understood that this recessed structure can be a triangular recessed structure formed by a wet process. To ensure process compatibility, this application designs a gate dielectric structure 208. Before subsequent processes, a gate dielectric layer is formed, meaning that a gate dielectric also exists at the bottom of the cavity. In this embodiment, a groove structure (i.e., the recessed structure on the upper surface of the first P-type region 101) is formed by etching the gate dielectric layer. The groove's function is to cause light to be reflected and absorbed again upon incident within it, thereby enhancing light absorption. Since the gate dielectric inside the cavity causes additional light loss, it can be removed after subsequent interconnect processes.

[0052] In one possible implementation, a source / drain region 108 is further disposed on the substrate, with the source / drain region 108 located on the side of the visible light detector away from the first electrical connection component. The visible light detector also includes a transmission transistor, which can be understood as a transistor (or a voltage-controlled resistor). One end of the transmission transistor is a polygate structure 207 and the source / drain region 108, and the other end is a first P-type region 101 and an N-type region 102. The channel of the transmission transistor is located on the substrate between the source / drain region 108 and the first P-type region 101. It should be understood that a CMOS transistor has both active and drain functions, capable of converting light into photoelectrons stored in the N-type region 102. The electrical signal must be extracted for further signal reading and processing. In this embodiment, by opening the gate of the transmission transistor, electrons can be transmitted to the other end and then connected to other external circuits via via interconnects.

[0053] In one possible implementation, the hybrid imaging detector further includes: a metal reflective layer 401, a second dielectric layer 402, and a protective layer 403; the metal reflective layer 401 is disposed below the visible light detector and is connected to the visible light detector through the second dielectric layer 402; the protective layer 403 is located below the metal reflective layer 401.

[0054] This application provides a hybrid imaging detector that integrates visible light and infrared detection technologies onto a single chip. It includes a visible light sensing area, an infrared detector with a MEMS microbridge structure above the visible light sensing area, and an intermediate component with a cavity and shielding structure. The visible light sensing area consists of a front P-type pin layer, a back P-type pin layer, and an N-type region 102. The pin layer on the back of the silicon wafer is formed by ion implantation and laser annealing, which avoids excessive thermal stress causing drift in the characteristics of other devices within the substrate. This enables the detection of signals across multiple wavelengths and achieves image fusion on a single chip, offering advantages such as low cost and high performance.

[0055] Figure 3 This is a schematic flowchart illustrating a method for fabricating a hybrid imaging detector according to an embodiment of this application. Figure 3 As shown, the preparation method includes the following steps:

[0056] S301, a substrate is provided, and a first P-type region, a lead-out terminal, and an N-type region of a visible light detector are formed on the upper surface of the substrate by ion implantation. In this embodiment, ion implantation is performed on the substrate, which is a doping process, using different dopants to form the first P-type region and the N-type region. The lead-out terminal includes a P+ region.

[0057] S302, forming a gate dielectric layer and a polysilicon gate electrode layer, and using a back-end process to form intermediate components, contact holes and leads, wherein the intermediate components include multiple interconnect dielectric layers, a pier structure for forming a shielding structure and a first dielectric layer.

[0058] This step first forms the gate dielectric layer, then the polysilicon gate electrode layer, followed by the interconnect dielectric layer, the pier structure, and the first dielectric layer. The interconnect dielectric layer and the pier structure are manufactured layer by layer in subsequent processes, specifically including two processes: aluminum and copper. For the aluminum process, the process flow is as follows: depositing metallic aluminum – patterning metallic aluminum to form interconnect lines – depositing the interconnect dielectric (i.e., the material of the aforementioned interconnect dielectric layer 201) and chemically mechanically polishing to form an interconnect dielectric layer – patterning to form vias – filling with titanium (Ti), titanium carbide (TiN), or tungsten (W) and chemically mechanically polishing to form metallic vias. Then, the next layer of interconnects, interconnect dielectric layers, and vias are formed sequentially, repeating the above process until multiple interconnect dielectric layers and multi-layered vias and interconnects are formed, where the multi-layered vias and interconnects constitute the pier structure. For the copper process, the process flow is as follows: depositing dielectric to form an interconnect dielectric layer - etching trenches - depositing metallic copper and chemically mechanically polishing to form a structure containing vias and interconnects - polishing the metallic copper - depositing dielectric to form the next interconnect dielectric layer, repeating the above process until multiple interconnect dielectric layers and multi-layered vias and interconnects are formed, where the multi-layered vias and interconnects constitute the pier structure. During the manufacturing process of the bottom layer of the interconnect dielectric layer, contact holes and leads can be formed by etching; these contact holes are used to connect the P+ region. After forming the interconnect dielectric layer, this application can deposit another dielectric layer to form a dielectric sublayer, which surrounds the vias in the top-layer pier structure. It should be understood that, in the embodiments of this application, the top-layer pier structure can be formed first, followed by the formation of a dielectric sublayer to surround the top-layer pier structure; alternatively, the top-layer pier structure can be formed directly within the dielectric sublayer. The embodiments of this application do not specifically limit the formation process of the top-layer pier structure. In the embodiments of this application, contact trenches are formed by etching the dielectric sublayer, and metal is deposited within the contact trenches to form a second electrical connection component. Then, an upper dielectric layer is deposited above the dielectric sublayer, the second electrical connection component, and the top-layer pier structure. The upper and lower dielectric layers constitute the first dielectric layer. The embodiments of this application can achieve the manufacturing of the interconnect dielectric layer, the pier structure, and the first dielectric layer using any of the above processes.

[0059] S303, a cavity is formed by etching the first dielectric layer and the interconnect dielectric layer on the intermediate component, and the polysilicon gate electrode layer, the gate dielectric layer and the surface of the first P-type region facing the cavity are etched in sequence to expose the silicon surface.

[0060] After S302 is completed, photolithography and multiple etching processes are performed. In this embodiment, after photolithography, a photoresist pattern is formed on the surface of the first dielectric layer (i.e., there is no photoresist on the first dielectric layer surrounding the pier structure, but there is photoresist on the first dielectric layer surrounding the pier structure). Using this pattern as a mask, carbon and fluorine gases are used to etch the first dielectric layer surrounding the pier structure and the interconnect dielectric layer below the first dielectric layer surrounding the pier structure to form a cavity. In S303, this embodiment also uses the above process to etch the first dielectric layer surrounding the cavity to provide trenches for the subsequent deposition of an electrode layer with a stepped structure.

[0061] After forming the cavity, a high-selectivity etching method is used to remove the polysilicon gate electrode layer within the cavity region until the entire polysilicon gate electrode layer within the cavity region is removed, thus forming the polysilicon gate electrode. After removing the polysilicon gate electrode layer within the cavity region, the etching process stops on the gate dielectric layer. Then, hydrogen bromide, hydrogen chloride, and other gases are used to etch away the gate dielectric layer within the cavity to form the gate dielectric structure. Using the gate dielectric structure as a mask, an alkaline solution is used to etch downwards onto the surface of the first P-type region facing the cavity, forming a triangular recessed structure. To avoid damaging the visible light photosensitive area, etching can be stopped on the polysilicon gate electrode layer after etching the cavity, and then on the gate dielectric layer after removing the polysilicon gate electrode layer within the cavity region. It is important to note that high selectivity is a parameter of the etching process, which is the ratio of the etching rates of the two materials.

[0062] S304, an epitaxial sacrificial layer is formed on the silicon surface until the sacrificial layer is higher than the upper surface of the first dielectric layer. Since the exposed silicon is monocrystalline silicon, in this embodiment, the sacrificial layer can be used to fill all areas within the cavity along the surface of the monocrystalline silicon. The material of the sacrificial layer can be germanium-silicon (SiGe).

[0063] S305, the sacrificial layer is smoothed using chemical mechanical polishing (CMP). CMP is a grinding process that can smooth out germanium-silicon (SiGe) layers higher than the top of the first dielectric layer, so that the height of the germanium-silicon (SiGe) layer is flush with the top of the first dielectric layer.

[0064] In S306, a support layer, a sensitive layer, an electrode layer, and an absorption layer are deposited and patterned to form an infrared detector with a microbridge structure. The support layer can be made of silicon carbide (SiN), silicon-oxygen-carbon thin film (SiON), etc. The sensitive layer can be made of amorphous silicon, amorphous germanium-silicon, etc. The electrode layer is a thin electrode metal layer. The absorption layer can be made of silicon dioxide (SiO2), silicon carbide (SiN), etc. Patterning can form a microbridge structure.

[0065] It should be understood that each layer undergoes deposition and patterning. For layers composed of non-metallic dielectrics, chemical vapor deposition (CVD) can be used for deposition; for electrode layers composed of metals, physical vapor deposition (PVD) can be used. Metal is injected during electrode layer deposition to connect the metallic electrode layer with the underlying contact trenches. Figure 2 In this embodiment, an electrode layer is formed first, followed by the deposition of an absorption layer. However, this embodiment does not specify a particular deposition order for the electrode layer and the absorption layer.

[0066] S307, a second P-type region of the visible light detector is prepared on the lower surface of the N-type region. That is, a back-side pin layer is formed by back-side injection and activated and repaired by laser annealing.

[0067] S308, Prepare a through-silicon via (TSV) so that the lead-out terminal connects the first P-type region to the second P-type region through the TSV.

[0068] S310, the sacrificial layer is removed using a wet process to form a suspended microbridge structure between the infrared detector and the shielding structure.

[0069] One possible implementation is, such as Figure 3 As shown, between S308 and S310, the preparation method further includes:

[0070] In step S309, a second dielectric layer and a metal reflective layer are deposited and patterned, and a protective layer is provided for the metal reflective layer. The second dielectric layer is the dielectric layer on the back side of the second P-type region, located on the upper surface of the metal reflective layer. The protective layer is located on the lower surface of the metal reflective layer to prevent the wet etching process in step S310 from etching away the metal within the metal reflective layer. Specifically, the patterning process is a back-side process, where the silicon wafer is placed upside down with the back side facing up, and photolithography is performed. After photolithography, the protective layer in the photolithographically opened area is removed using a dry process to expose the metal reflective layer. The metal reflective layer in the photolithographically opened area is then removed using a wet process. This application embodiment does not specifically limit the thickness or length of each layer.

[0071] This application provides a method for fabricating a hybrid imaging detector by integrating visible light and infrared detection technologies onto a single chip. The method includes a visible light sensing area, an infrared detector with a MEMS microbridge structure above the visible light sensing area, and an intermediate component with a cavity and shielding structure. The visible light sensing area consists of a front P-type pin layer, a back P-type pin layer, and an N-type region. The pin layer on the back of the silicon wafer is formed by ion implantation and laser annealing, which avoids excessive thermal stress causing drift in the characteristics of other devices within the substrate. This enables the detection of signals across multiple wavelengths and achieves image fusion on a single chip, offering advantages such as low cost and high performance.

[0072] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0073] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A hybrid imaging detector, characterized in that, include: A visible light detector, a cavity-containing intermediate component, and an infrared detector are stacked sequentially along a vertical direction; wherein, the intermediate component has a shielding structure inside, and the shielding structure is located on the periphery of the cavity; The infrared detector receives incident light and absorbs the infrared portion of the incident light to generate a first electrical signal for hybrid imaging. The shielding structure reflects a portion of the light filtered out by the infrared detector back into the cavity; The visible light detector absorbs the visible light portion of the incident light to generate a second electrical signal for hybrid imaging; The visible light detector includes a PNP-type photosensitive area on a substrate and a first electrical connection component located on one side of the PNP-type photosensitive area; The PNP type photosensitive area is arranged in sequence along a direction perpendicular to the infrared detector, consisting of a first P-type region, an N-type region, and a second P-type region, and the first P-type region and the second P-type region are connected by the first electrical connection component.

2. The hybrid imaging detector according to claim 1, characterized in that, The first electrical connection component includes a through-silicon via and a lead-out terminal; The through-silicon via penetrates the second P-type region, and the bottom of the through-silicon via is flush with the bottom of the second P-type region; the top of the through-silicon via is higher than the top of the second P-type region and is located in the substrate; The lead-out terminal includes a P-region, a contact hole, and a lead wire; The P-region is located on one side of the first P-type region, and the lower surface of the P-region is connected to the upper surface of the through silicon via. Contact holes and leads are stacked sequentially above the P-region. Both the contact hole and the lead wire are located on the outside of the shielding structure.

3. The hybrid imaging detector according to claim 1, characterized in that, The surface of the first P-shaped region facing the cavity has a recessed structure.

4. The hybrid imaging detector according to claim 1, characterized in that, The infrared detector includes a microbridge structure with an uneven surface on top and a second electrical connection component; the microbridge structure includes an absorption layer, a sensitive layer, an electrode layer and a support layer; The two ends of the support layer are mounted on the cavity; The sensitive layer is located above the support layer, and the length of the sensitive layer is less than the length of the support layer; The electrode layer covers a portion of the sensitive layer's surface and sidewalls away from the support layer, a portion of the support layer's surface and sidewalls away from the cavity, the surface of the second electrical connection component, and a portion of the sidewalls of the intermediate component; The absorption layer covers the sensitive layer and the electrode layer.

5. The hybrid imaging detector according to claim 1, characterized in that, The intermediate component also includes multiple interconnecting dielectric layers and a first dielectric layer; The plurality of interconnecting dielectric layers are located on the upper surface of the visible light detector and surround the outside of the cavity; The first dielectric layer is located above the top layer of the plurality of interconnecting dielectric layers away from the visible light detector and surrounds the outside of the cavity.

6. The hybrid imaging detector according to claim 5, characterized in that, The shielding structure includes a pier structure, a polycrystalline grating structure, and a grating dielectric structure; The pier structure is located above the polycrystalline grating structure, and the upper surface of the pier structure is connected to the surface of the first dielectric layer away from the infrared detector; The polycrystalline gate structure is located above the gate dielectric structure, and the lower surface of the gate dielectric structure is connected to the visible light detector.

7. The hybrid imaging detector according to claim 1, characterized in that, The substrate also has a source / drain region located on the side of the visible light detector away from the first electrical connection component.

8. The hybrid imaging detector according to claim 1, characterized in that, Also includes: Metal reflective layer, second dielectric layer, and protective layer; The metal reflective layer is disposed below the visible light detector and is connected to the visible light detector through the second dielectric layer; The protective layer is located below the metal reflective layer.

9. A hybrid imaging detector, characterized in that, include: A visible light detector, a cavity-containing intermediate component, and an infrared detector are stacked sequentially along a vertical direction; wherein, the intermediate component has a shielding structure inside, and the shielding structure is located on the periphery of the cavity; The infrared detector receives incident light and absorbs the infrared portion of the incident light to generate a first electrical signal for hybrid imaging. The shielding structure reflects a portion of the light filtered out by the infrared detector back into the cavity; The visible light detector absorbs the visible light portion of the incident light to generate a second electrical signal for hybrid imaging; The infrared detector includes a microbridge structure with an uneven surface on top and a second electrical connection component; the microbridge structure includes an absorption layer, a sensitive layer, an electrode layer and a support layer. The two ends of the support layer are mounted on the cavity; The sensitive layer is located above the support layer, and the length of the sensitive layer is less than the length of the support layer; The electrode layer covers a portion of the sensitive layer's surface and sidewalls away from the support layer, a portion of the support layer's surface and sidewalls away from the cavity, the surface of the second electrical connection component, and a portion of the sidewalls of the intermediate component; The absorption layer covers the sensitive layer and the electrode layer.

10. A hybrid imaging detector, characterized in that, include: A visible light detector, a cavity-containing intermediate component, and an infrared detector are stacked sequentially along a vertical direction; wherein, the intermediate component has a shielding structure inside, and the shielding structure is located on the periphery of the cavity; The infrared detector receives incident light and absorbs the infrared portion of the incident light to generate a first electrical signal for hybrid imaging. The shielding structure reflects a portion of the light filtered out by the infrared detector back into the cavity; The visible light detector absorbs the visible light portion of the incident light to generate a second electrical signal for hybrid imaging; It also includes: a metal reflective layer, a second dielectric layer, and a protective layer; The metal reflective layer is disposed below the visible light detector and is connected to the visible light detector through the second dielectric layer; The protective layer is located below the metal reflective layer.

11. A method for fabricating a hybrid imaging detector, characterized in that, include: A substrate is provided, and a first P-type region, an output terminal, and an N-type region of a visible light detector are fabricated on the upper surface of the substrate by ion implantation. A gate dielectric layer and a polysilicon gate electrode layer are formed, and intermediate components, contact holes and leads are formed using a back-end process. The intermediate components include an interconnect dielectric layer, a pier structure for forming a shielding structure and a first dielectric layer. A cavity is formed by etching a first dielectric layer and an interconnect dielectric layer on the intermediate component, and the polysilicon gate electrode layer, the gate dielectric layer and the surface of the first P-type region facing the cavity are etched in sequence to expose the silicon surface; An epitaxial sacrificial layer is formed on the silicon surface until the sacrificial layer is higher than the upper surface of the first dielectric layer; The sacrificial layer was smoothed using chemical mechanical polishing. The support layer, sensitive layer, electrode layer and absorption layer are deposited and patterned respectively to form an infrared detector with a microbridge structure; A second P-type region of a visible light detector is fabricated on the lower surface of the N-type region; A through-silicon via is fabricated so that the lead-out terminal connects the first P-type region to the second P-type region through the through-silicon via; The sacrificial layer is removed using a wet process to create a suspended microbridge structure between the infrared detector and the shielding structure.

Images