Solid-state nanopore array chip with microfluidic channel and preparation method thereof
By forming a nanopore array substrate on a silicon substrate and integrating microchannels, the problems of high cost and large size in nanopore sequencing chip fabrication have been solved, achieving low-cost and high-yield nanopore sequencing chip fabrication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PHOTONIC VIEW TECHNOLOGY CO LTD
- Filing Date
- 2021-03-29
- Publication Date
- 2026-06-19
AI Technical Summary
Existing nanopore sequencing chips are costly to manufacture, bulky, and have low product yield.
A nanopore array substrate is formed on a silicon substrate using photolithography and etching processes. By depositing dielectric and metal layers and combining them with wet removal processes, a monolithic self-adaptive integration of nanopores, microfluidic cavities, and microchannels is achieved.
It effectively reduces manufacturing costs, decreases chip size, improves product yield, and offers strong process controllability.
Smart Images
Figure CN115121300B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of micro-nano medical detection application technology, and in particular relates to a solid-state nanopore array chip with microfluidic channels and its preparation method. Background Technology
[0002] The base sequence of the human genome contains all the genetic information about an individual's life, aging, illness, and death. Accurately deciphering the human genetic code through gene sequencing technology is one of the key research directions in life sciences in the 21st century. As one of the main methods of third-generation sequencing technology, nanopore sequencing technology has the advantages of high throughput, low cost, label-free operation, no amplification required, and long read length, and is considered the most promising next-generation human genome sequencing technology for low cost.
[0003] The basic principle of nanopore sequencing is as follows: two electrolyte chambers are separated by an insulating membrane, forming cis and trans compartments. A single nanometer-sized pore in the membrane connects the two chambers. When a voltage is applied to the electrolyte chamber, electrolyte ions in the solution move through the nanopore via electrophoresis, forming a steady-state ionic current. When a particle slightly smaller than the pore size passes through the pore, the current flowing through the nanopore is blocked, thus interrupting the current signal, which is then restored. Adding charged biomolecules (ions, DNA, RNA, peptides, proteins, drugs, polymer macromolecules, etc.) to an electrolyte compartment causes the biomolecules to enter and exit the nanopore. This generates a series of blocking current signals within the ionic current signal. The amplitude and duration of these blocking currents convey many characteristics of the sample, including the size, concentration, and structure of the biomolecules.
[0004] Due to the problems of short lifespan, environmental sensitivity, and fixed pore size in biological nanopores, solid nanopores have attracted widespread attention because they offer advantages such as processability, device robustness, flexibility in nanopore size, and compatibility with semiconductor processes.
[0005] In nanopore sequencing chips, each nanopore corresponds to a specific microfluidic cavity or microchannel for the transport and sequencing of DNA. However, the current manufacturing cost of nanopore sequencing chips is high, their size is large, and the yield of the products is also low. Summary of the Invention
[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a solid-state nanopore array chip with microchannels and its preparation method, so as to solve the problems of high preparation cost, large chip size and low product yield of solid-state nanopore sequencing chips in the prior art.
[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a solid-state nanopore array chip with microchannels, the method comprising the following steps:
[0008] A solid nanopore array substrate is provided, the solid nanopore array substrate comprising a silicon substrate and a first dielectric layer formed on the silicon substrate, wherein a plurality of nanopores penetrating the first dielectric layer are formed therein.
[0009] A second dielectric layer is deposited on the first dielectric layer;
[0010] A plurality of microfluidic cavities and microchannels penetrating the second dielectric layer are formed in the second dielectric layer by photolithography and etching processes, wherein each microfluidic cavity corresponds to one nanopore, and each microfluidic cavity is connected to two microchannels;
[0011] Several microfluidic cavities and microfluidic channels are filled with metal to form several metal layers;
[0012] A plurality of electrodes are formed on the second dielectric layer, wherein the plurality of electrodes are correspondingly formed above the plurality of metal layers, and each electrode exposes a portion of its corresponding metal layer;
[0013] The metal layer was removed by wet method;
[0014] The back side of the silicon substrate is etched to form a cavity penetrating the silicon substrate, and the cavity exposes a plurality of nanopores.
[0015] Optionally, the back side of the silicon substrate is etched to form a cavity, and the cavity exposes a plurality of nanopores; or the back side of the silicon substrate is etched to form a plurality of cavities, and each cavity exposes a nanopore.
[0016] Optionally, the silicon substrate is a (110) silicon substrate; the first dielectric layer and the second dielectric layer are formed by chemical vapor deposition; the back side of the silicon substrate is etched by wet etching with potassium hydroxide solution to form the cavity.
[0017] Optionally, the metal layer is made of Al or Cu; the electrode is made of TiN, Au, or Pt.
[0018] Optionally, when the material of the metal layer is Cu, the metal layer is removed by wet process using concentrated sulfuric acid, aqua regia, or dilute nitric acid; when the material of the metal layer is Al, the metal layer is removed by wet process using sodium hydroxide, dilute sulfuric acid, dilute nitric acid, phosphoric acid, or hydrochloric acid.
[0019] Further, the concentration of the concentrated sulfuric acid is between 50% and 99%, the molar concentration of the dilute nitric acid is between 0.1 mol / L and 9 mol / L, the molar concentration of the sodium hydroxide is between 0.1 mol / L and 9 mol / L, the molar concentration of the dilute sulfuric acid is between 0.1 mol / L and 9 mol / L, the molar concentration of the phosphoric acid is between 0.1 mol / L and 9 mol / L, and the molar concentration of the hydrochloric acid is between 0.1 mol / L and 9 mol / L.
[0020] Optionally, the step of forming a plurality of the microfluidic cavities and microchannels includes:
[0021] A photoresist layer is coated and patterned on the surface of the second dielectric layer to form a patterned photoresist layer;
[0022] Based on the patterned photoresist layer, the second dielectric layer is wet-etched to form a plurality of microfluidic cavities and microchannels penetrating the second dielectric layer;
[0023] Remove the patterned photoresist layer.
[0024] The present invention also provides a solid nanopore array chip with microchannels, the array chip comprising, from bottom to top: a silicon substrate, a first dielectric layer, a second dielectric layer and a plurality of electrodes;
[0025] A cavity is formed in the silicon substrate that penetrates the silicon substrate;
[0026] A plurality of nanopores penetrating the first dielectric layer are formed therein;
[0027] A plurality of microfluidic cavities and microchannels are formed in the second dielectric layer, wherein each microfluidic cavity corresponds to one nanopore, and each microfluidic cavity is connected to two microchannels;
[0028] Several electrodes are disposed on top of several microfluidic cavities and formed on the surface of the second dielectric layer, with each electrode having an exposed portion corresponding to its microfluidic cavity; the cavity exposes several nanopores.
[0029] Optionally, a cavity is formed in the silicon substrate, and the cavity exposes a plurality of nanopores; or a plurality of cavities are formed in the silicon substrate, and each cavity exposes a nanopore.
[0030] Optionally, the thickness of the silicon substrate is between 500 μm and 1000 μm, the thickness of the first dielectric layer is between 10 nm and 1000 nm, and the thickness of the second dielectric layer is between 10 nm and 100 μm.
[0031] Optionally, the size of the nanopore is between 0.1 nm and 30 nm.
[0032] Optionally, several of the microfluidic cavities are identical and arranged in an array, and the spacing between two adjacent rows of microfluidic cavities and the spacing between two adjacent microfluidic cavities are equal.
[0033] Furthermore, the spacing is between 5μm and 2000μm.
[0034] Optionally, the cross-sectional shape of the microfluidic cavity is square, and the cross-sectional shape of the microfluidic channel is rectangular.
[0035] Furthermore, the width of the square is between 1 μm and 1000 μm, and the width of the rectangle is between 0.5 μm and 500 μm.
[0036] Optionally, the material of the first dielectric layer is SiN, SiO2, Al2O3, HfO2, ZnO or TiO2; the material of the second dielectric layer is SiN, SiO2, Al2O3, HfO2, ZnO or TiO2.
[0037] Optionally, the electrode is made of TiN, Au, or Pt.
[0038] As described above, the solid-state nanopore array chip with microchannels and its fabrication method of the present invention can directly realize monolithic self-adaptive integration of nanopores, microcavities and microchannels, effectively reducing the fabrication cost and reducing the chip size; in addition, it does not require alignment integration between two chips, improving alignment error and thus improving yield; furthermore, the fabrication method is based on existing mature silicon micromachining technology, with small and controllable process fluctuations. Attached Figure Description
[0039] Figure 1 The diagram shows a flow chart of the fabrication method of the solid-state nanopore array chip with microchannels according to the present invention.
[0040] Figures 2 to 19 The diagram shows the structural schematics of each step in the fabrication process of the solid-state nanopore array chip with microchannels according to the present invention. Figure 18 and Figure 19 Also shown is a schematic diagram of the structure of the solid-state nanopore array chip with microchannels of the present invention.
[0041] Component designation explanation
[0042] 10 Silicon substrate
[0043] 101 Cavity
[0044] 11 First dielectric layer
[0045] 111 nanopores
[0046] 12 Second dielectric layer
[0047] 121 Microfluidic cavity
[0048] 122 microchannels
[0049] 122a Entrance passage
[0050] 122b Exit Channel
[0051] 123 Metals
[0052] 124 Metal Layer
[0053] 125 Partial Metal Layer
[0054] 13 electrodes
[0055] 131 Electrode material layer
[0056] 132 lead wire
[0057] 141 Photoresist layer
[0058] 142 Patterned photoresist layer
[0059] D1 Nanopore Size
[0060] D2 Width of the square
[0061] D3 Width of the rectangle
[0062] L-spacing
[0063] Steps S1 to S7 Detailed Implementation
[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0065] Please see Figures 1 to 19It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be changed according to actual needs, and the layout of the components may also be more complex.
[0066] Example 1
[0067] As described in the background section, existing nanopore sequencing chips suffer from high manufacturing costs, large size, and low product yield. In nanopore sequencing chips, each nanopore corresponds to a specific microfluidic cavity or microchannel for DNA transport and sequencing. The inventors have found that currently, solid-state nanopore chips and microfluidic channel chips are fabricated separately and then integrated to form a fully functional chip. This integration process increases the manufacturing cost and size of the fully functional chip. Furthermore, because the two chips need to be aligned during integration, it increases alignment errors between the chips, thus reducing product yield.
[0068] Based on the above findings, the inventors provide a method for fabricating a solid-state nanopore array chip with microchannels in this embodiment. The fabrication method includes the following steps:
[0069] like Figures 1 to 3 As shown, where, Figure 3 yes Figure 2 The top view shows that step S1 is performed first, providing a solid nanopore array substrate. The solid nanopore array substrate includes a silicon substrate 10 and a first dielectric layer 11 formed on the silicon substrate 10. A plurality of nanopores 111 are formed in the first dielectric layer 11.
[0070] The crystal orientation of the silicon substrate 10 is not limited here, as long as it can be etched to form the cavity 101 in the subsequent etching steps (e.g., Figure 18 and Figure 19 As shown in the figure. In this embodiment, the cavity 101 is subsequently formed by wet etching with potassium hydroxide solution. Therefore, from the perspective of etching rate, the silicon substrate 10 is selected as (110) silicon substrate in this embodiment.
[0071] The first dielectric layer 11 in the solid nanopore array substrate can be formed using existing conventional deposition processes, such as chemical vapor deposition (CVD) on the silicon substrate 10. In this embodiment, CVD is chosen to form the first dielectric layer 11.
[0072] As an example, existing techniques such as ion beam drilling or feedback etching can be used to form several nanopores 111. However, other feasible methods can also be used to form several nanopores 111, as long as the required nanopores can be formed. Furthermore, the arrangement of the several nanopores 111 can be set according to actual needs. For example, it can be a random array, i.e., rows and columns without a regular arrangement, or a regular array, i.e., rows and columns with regular arrangement. To reduce the complexity of the fabrication process, this embodiment selects a regular array arrangement of several nanopores 111, wherein the spacing between adjacent rows of nanopores 111 and the spacing between two adjacent nanopores 111 are equal.
[0073] like Figures 3a to 3d As shown, Figures 3a to 3d Displayed as along Figure 3 A cross-sectional view along the AA direction is provided to show the cross-sectional structure of the nanopore 111. The longitudinal cross-sectional structure of the nanopore 111 can be any shape formed by existing nanopore fabrication processes, such as... Figure 3a The image shown is in columnar form. Figure 3b The shape shown is an inverted cone. Figure 3c It is stepped. Figure 3d It has a double inverted cone shape. In addition, the size D1 of the nanopore 111 is generally between 0.1nm and 30nm, preferably between 1nm and 2nm, and in this embodiment, it is selected to be about 1.5nm.
[0074] As an example, the thickness of the silicon substrate 10 is between 500μm and 1000μm, for example, it can be 500μm, 600μm, 700μm, 800μm, 900μm, or 1000μm, and the thickness of the first dielectric layer 11 is between 10nm and 1000nm, for example, it can be 10nm, 50nm, 100nm, 200nm, 300nm, 500nm, 700nm, 800nm, 900nm, or 1000nm. In this embodiment, the thickness of the silicon substrate 10 is selected as 700μm, and the thickness of the first dielectric layer 11 is 200nm.
[0075] As an example, the material of the first dielectric layer 11 can be any suitable existing dielectric material, such as SiN, SiO2, Al2O3, HfO2, ZnO, or TiO2. In this embodiment, the first dielectric layer 11 is selected as SiN material.
[0076] like Figure 1 and Figure 4 As shown, then step S2 is performed to deposit a second dielectric layer 12 on the first dielectric layer 11.
[0077] The second dielectric layer 12 can be formed using existing conventional deposition processes, such as chemical vapor deposition (CVD) on the first dielectric layer 11. In this embodiment, CVD is chosen to form the second dielectric layer 12. The thickness of the second dielectric layer 12 is between 10 nm and 100 μm, for example, 10 nm, 50 nm, 100 nm, 1000 nm, 10 μm, 40 μm, 60 μm, 80 μm, or 100 μm. In this embodiment, the thickness of the second dielectric layer 12 is chosen to be 500 nm. Furthermore, the material of the second dielectric layer 12 can be any suitable dielectric material, such as SiN, SiO2, Al2O3, HfO2, ZnO, or TiO2. In this embodiment, SiO2 is chosen as the material for the second dielectric layer 12. Preferably, the materials of the first dielectric layer 11 and the second dielectric layer 12 can be selected as different dielectric materials, thereby facilitating the implementation of the etching process based on different etching ratios.
[0078] It should be noted that during the deposition of the second dielectric layer 12, the material of the second dielectric layer 12 may also be formed in the nanopores 111. Figure 4 (Not shown in the image), the dielectric material formed in the nanopore 111 will be removed simultaneously when the second dielectric layer 12 is subsequently etched to form microfluidic cavities and microchannels.
[0079] like Figure 1 , Figure 8 and Figure 9 As shown, where, Figure 9 for Figure 8 Following the top view, step S3 is performed, whereby a plurality of microfluidic cavities 121 and microchannels 122 penetrating the second dielectric layer 12 are formed in the second dielectric layer 12 through photolithography and etching processes. Each microfluidic cavity 121 corresponds to one nanopore 111, and each microfluidic cavity 121 is connected to two microchannels 122 (e.g., ...). Figure 9 (As shown). This step directly achieves monolithic integration of nanopores, microfluidic cavities, and microchannels, effectively reducing fabrication costs and chip size; furthermore, it eliminates the need for alignment integration between two chips, improving alignment error and thus increasing yield.
[0080] During chip usage, the microfluidic cavity 121 typically serves as a solution-containing cavity, and the microfluidic channel 122 typically serves as the inlet and outlet channels for the solution, such as... Figure 9As shown, 122a can serve as an inlet channel, and 122b can serve as an outlet channel. The solution enters the microfluidic cavity 121 through the inlet channel 122a and flows out of the microfluidic cavity 121 through the outlet channel 122b. The layout of the microfluidic channel 122 can be set according to the layout of the nanopore 111. In principle, while realizing its function, the area occupied by the chip should be minimized as much as possible, thereby facilitating chip miniaturization. Figure 9 The diagram shows a 4×4 nanopore 111 layout, in which the microchannel 122 is arranged in a unit A with 4 nanopores 111, and the microchannel 122 in each unit A has the same layout. Figure 9 This is just one example. In practice, the layout of the microchannel 122 can be set according to actual needs, and there are no restrictions here.
[0081] like Figure 9 As shown in the figure, as an example, several identical microfluidic cavities 121 are arranged in an array, and the spacing L between adjacent rows of microfluidic cavities and the spacing L between two adjacent microfluidic cavities are equal. The spacing L is generally between 5 μm and 2000 μm, and is selected as 10 μm in this embodiment.
[0082] The cross-sectional shapes of the microfluidic cavity 121 and the microfluidic channel 122 can be set according to actual needs, and can be regular or irregular shapes. To reduce process complexity, it is preferable to set the cross-sectional shapes of the microfluidic cavity 121 and the microfluidic channel 122 to regular shapes. For example, as... Figure 9 As shown, in this embodiment, the cross-section of the microfluidic cavity 121 is set to a square, and the cross-section of the microfluidic channel 122 is set to a rectangle. In terms of size, the width D2 of the square can be set between 1μm and 1000μm, and the width D3 of the rectangle can be set between 0.5μm and 500μm.
[0083] like Figures 5 to 8 As shown, as an example, a specific method for forming a plurality of the microfluidic cavities 121 and microchannels 122 is provided, including:
[0084] 3-1), such as Figure 5 and Figure 6 As shown, a photoresist layer 141 is coated and patterned on the surface of the second dielectric layer 12 to form a patterned photoresist layer 142. The specific shape of the openings in the patterned photoresist layer 142 is implemented using a photomask according to actual needs, and is not limited here.
[0085] 3-2), such as Figure 7As shown, the second dielectric layer 12 is wet-etched based on the patterned photoresist layer 142 to form a plurality of microfluidic cavities 121 and microchannels 122 penetrating the second dielectric layer 12. In this step, when wet-etching the second dielectric layer 12, the second dielectric material formed in the nanopores 111 can also be removed simultaneously to release the nanopores 111 and avoid the risk of clogging. When the second dielectric layer 12 is selected as SiO2 material in this embodiment, wet removal with BHF solution can be used.
[0086] 3-3), such as Figure 8 As shown, the patterned photoresist layer 142 is removed.
[0087] like Figure 1 and Figure 11 As shown, step S4 is then performed, in which metal 123 is filled into several microfluidic cavities 121 and microfluidic channels 122 to form several metal layers 124. The several metal layers 124 formed in this step provide a basis for the subsequent formation of electrodes 13.
[0088] like Figure 10 and Figure 11 As shown, as an example, a specific method for forming a plurality of said metal layers 124 is provided, including:
[0089] 4-1), such as Figure 10 As shown, a layer of metal 123 is deposited on the second dielectric layer 12 using a metal deposition process, and the metal 123 completely fills the plurality of microfluidic cavities 121 and microchannels 122. A layer of metal 123 can be formed using existing conventional metal deposition processes, such as magnetron sputtering, physical vapor deposition, etc. It should be noted here that, as... Figure 10 As shown, during the deposition of the metal 123, the metal may also enter the nanopore 111, and the metal 123 that enters the nanopore 111 will be removed.
[0090] 4-2), such as Figure 11 As shown, the metal 123 on the second dielectric layer 12 is removed by chemical mechanical polishing (CMP) to form a plurality of metal layers 124.
[0091] As an example, the material of the metal layer 124 can be Al or Cu, which is low in cost and easy to remove by wet etching in the presence of electrodes.
[0092] like Figure 1 , Figure 15 and Figure 16 As shown, where, Figure 16 for Figure 15The top view is then followed by step S5, where a plurality of electrodes 13 are formed on the second dielectric layer 12, wherein the plurality of electrodes 13 are correspondingly formed above the plurality of metal layers 124, and each electrode 13 exposes a portion of the corresponding metal layer 125 (e.g., ...). Figure 16 (As shown). Each electrode 13 exposes a portion of its corresponding metal layer 125 to facilitate subsequent wet removal of the metal layer 124. This step also cleverly allows several electrodes 13 to be formed above several microfluidic cavities 121, achieving large-scale parallel fabrication of electrodes corresponding to several nanopores, with minimal process fluctuations and easy control.
[0093] like Figures 12 to 15 As shown, as an example, a specific method for forming a plurality of the electrodes 13 is provided, comprising:
[0094] 5-1), such as Figure 12 and Figure 13 As shown, a photoresist layer 141 is coated and patterned on the surface of the second dielectric layer 12 to form a patterned photoresist layer 142, wherein the patterned photoresist layer 142 exposes a portion of the metal layer 124.
[0095] 5-2), such as Figure 14 As shown, an electrode material layer 131 is deposited on the patterned photoresist layer 142 using a metal deposition process.
[0096] 5-3), such as Figure 15 As shown, the patterned photoresist layer 142 is removed, and the electrode material layer 131 is smoothed using a chemical mechanical polishing process to form a plurality of electrodes 13.
[0097] As an example, the material of the electrode 13 is TiN, Au or Pt, and TiN is selected in this embodiment.
[0098] As an example, several of the electrodes 13 will subsequently be led out via leads 132.
[0099] like Figure 1 and Figure 17 As shown, step S6 is then performed, where the metal layer 124 is wet-removed to expose the microfluidic cavity 121 and the microfluidic channel 122, combined with... Figure 16 It is known that since the metal layer 124 is partially exposed by the electrode 13, the wet etching solution can remove the metal layer 124 in the microfluidic cavity 121, and even the metal material in the nanopores 111 below the microfluidic cavity 121.
[0100] As an example, when the material of the metal layer 124 is Cu, the metal layer 124 can be removed by wet methods using concentrated sulfuric acid, aqua regia, or dilute nitric acid. Preferably, the concentration of concentrated sulfuric acid is between 50% and 99%, and the molar concentration of dilute nitric acid is between 0.1 mol / L and 9 mol / L. In this embodiment, the concentration of concentrated sulfuric acid is 70%, and the molar concentration of dilute nitric acid is 6 mol / L.
[0101] As an example, when the material of the metal layer 124 is Al, the metal layer 124 can be removed by wet cleaning with sodium hydroxide, dilute sulfuric acid, dilute nitric acid, phosphoric acid, or hydrochloric acid. Preferably, the molar concentrations of sodium hydroxide, dilute sulfuric acid, phosphoric acid, and hydrochloric acid are selected to be between 0.1 mol / L and 9 mol / L. In this embodiment, the molar concentrations of sodium hydroxide, dilute sulfuric acid, phosphoric acid, and hydrochloric acid are selected to be 6 mol / L.
[0102] like Figure 1 , Figure 18 and Figure 19 As shown, in step S7, the back side of the silicon substrate 10 is etched to form a cavity 101 penetrating the silicon substrate 10, and the cavity 101 exposes a plurality of nanopores 111. This cavity 101 serves as a container for the chip electrolyte.
[0103] As an example, the cavity 101 can be formed using either dry or wet etching. In this embodiment, the cavity 101 is formed using wet etching with potassium hydroxide solution.
[0104] like Figure 18 As shown, as an example, the back surface of the silicon substrate 10 is etched to form a cavity 101, and the cavity 101 exposes a plurality of nanopores 111; as Figure 19 As shown, as another example, the back side of the silicon substrate 10 is etched to form a plurality of cavities 101, and each cavity 101 exposes a nanopore 111.
[0105] As described above, the fabrication method of the solid nanopore array chip with microchannels in this embodiment can directly realize the monolithic self-adaptive integration of nanopores, microcavities and microchannels, effectively reducing the fabrication cost and the chip size. In addition, it does not require alignment integration between two chips, thus improving the alignment error and improving the yield. Furthermore, this fabrication method is based on existing mature silicon micromachining technology, with small and controllable process fluctuations.
[0106] Example 2
[0107] This embodiment provides a solid-state nanopore array chip with microchannels. The array chip can be prepared by the preparation method of Embodiment 1 above. The beneficial effects it can achieve can be found in Embodiment 1, and will not be repeated below.
[0108] like Figure 18 and Figure 19 As shown, the array chip comprises, from bottom to top: a silicon substrate 10, a first dielectric layer 11, a second dielectric layer 12, and a plurality of electrodes 13;
[0109] A cavity 101 is formed in the silicon substrate 10, penetrating the silicon substrate 10;
[0110] A plurality of nanopores 111 penetrating the first dielectric layer 11 are formed therein;
[0111] The second dielectric layer 12 has a plurality of microfluidic cavities 121 and microfluidic channels 122 that penetrate the second dielectric layer 12, wherein each microfluidic cavity 121 corresponds to a nanopore 111 and each microfluidic cavity 121 is connected to two microfluidic channels 122.
[0112] A plurality of electrodes 13 are disposed on top of a plurality of microfluidic cavities 121 and formed on the surface of the second dielectric layer 12, with each electrode 13 having an exposed portion of its corresponding microfluidic cavity 121; the cavity 101 exposes a plurality of nanopores 111.
[0113] like Figure 18 As shown, as an example, a cavity 101 is formed in the silicon substrate 10, and the cavity 101 exposes a plurality of nanopores 111; as Figure 19 As shown, as another example, a plurality of cavities 101 are formed in the silicon substrate 10, and each cavity 101 exposes a nanopore 111.
[0114] As an example, the thickness of the silicon substrate 10 is between 500 μm and 1000 μm, the thickness of the first dielectric layer 11 is between 10 nm and 1000 nm, and the thickness of the second dielectric layer 12 is between 10 nm and 100 μm.
[0115] As an example, the size D1 of the nanopore 111 is between 0.1 nm and 30 nm.
[0116] like Figure 9As shown, as an example, several identical microfluidic cavities 121 are arranged in an array, and the spacing L between two adjacent rows of microfluidic cavities 121 and the spacing L between two adjacent microfluidic cavities 121 are equal. Further, the spacing L is between 5 μm and 2000 μm.
[0117] like Figure 9 As shown, as an example, the cross-sectional shape of the microfluidic cavity 121 is square, and the cross-sectional shape of the microfluidic channel 122 is rectangular. Further, the width D2 of the square is between 1 μm and 1000 μm, and the width D3 of the rectangle is between 0.5 μm and 500 μm.
[0118] As an example, the material of the first dielectric layer 11 is SiN, SiO2, Al2O3, HfO2, ZnO or TiO2; the material of the second dielectric layer 12 is SiN, SiO2, Al2O3, HfO2, ZnO or TiO2.
[0119] As an example, the material of the electrode 13 is TiN, Au, or Pt.
[0120] In summary, this invention provides a solid-state nanopore array chip with microchannels and its fabrication method, which can directly achieve monolithic self-adaptive integration of nanopores, microcavities, and microchannels, effectively reducing fabrication costs and chip size. Furthermore, it eliminates the need for alignment integration between two chips, improving alignment accuracy and thus yield. Moreover, this fabrication method is based on existing mature silicon micromachining technology, resulting in minimal and controllable process fluctuations. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.
[0121] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a solid-state nanopore array chip with microchannels, characterized in that, The preparation method includes the following steps: A solid nanopore array substrate is provided, the solid nanopore array substrate comprising a silicon substrate and a first dielectric layer formed on the silicon substrate, wherein a plurality of nanopores penetrating the first dielectric layer are formed therein. A second dielectric layer is deposited on the first dielectric layer; A plurality of microfluidic cavities and microchannels penetrating the second dielectric layer are formed in the second dielectric layer by photolithography and etching processes, wherein each microfluidic cavity corresponds to one nanopore and each microfluidic cavity is connected to two microchannels; wherein the step of forming a plurality of microfluidic cavities and microchannels includes: coating a photoresist layer on the surface of the second dielectric layer and patterning it to form a patterned photoresist layer; and wet etching the second dielectric layer based on the patterned photoresist layer to form a plurality of microfluidic cavities and microchannels penetrating the second dielectric layer; Remove the patterned photoresist layer; Several microfluidic cavities and microfluidic channels are filled with metal to form several metal layers; A plurality of electrodes are formed on the second dielectric layer, wherein the plurality of electrodes are correspondingly formed above the plurality of metal layers, and each electrode exposes a portion of its corresponding metal layer; The metal layer was removed by wet method; The back side of the silicon substrate is etched to form a cavity penetrating the silicon substrate, and the cavity exposes a plurality of nanopores.
2. The method for fabricating a solid-state nanopore array chip with microchannels according to claim 1, characterized in that; The back side of the silicon substrate is etched to form a cavity, and the cavity exposes a plurality of nanopores; or the back side of the silicon substrate is etched to form a plurality of cavities, and each cavity exposes a nanopore.
3. The method for fabricating a solid-state nanopore array chip with microchannels according to claim 1, characterized in that: The silicon substrate is a (110) silicon substrate; the first dielectric layer and the second dielectric layer are formed by chemical vapor deposition; the back side of the silicon substrate is etched by wet etching with potassium hydroxide solution to form the cavity.
4. The method of claim 1, wherein the method further comprises: The metal layer is made of Al or Cu; the electrode is made of TiN, Au, or Pt.
5. The method of claim 4, wherein the method further comprises: When the material of the metal layer is Cu, the metal layer is removed by wet method using concentrated sulfuric acid, aqua regia or dilute nitric acid; when the material of the metal layer is Al, the metal layer is removed by wet method using sodium hydroxide, dilute sulfuric acid, dilute nitric acid, phosphoric acid or hydrochloric acid.
6. The method for fabricating a solid-state nanopore array chip with microchannels according to claim 5, characterized in that: The concentration of the concentrated sulfuric acid is between 50% and 99%, the molar concentration of the dilute nitric acid is between 0.1 mol / L and 9 mol / L, the molar concentration of the sodium hydroxide is between 0.1 mol / L and 9 mol / L, the molar concentration of the dilute sulfuric acid is between 0.1 mol / L and 9 mol / L, the molar concentration of the phosphoric acid is between 0.1 mol / L and 9 mol / L, and the molar concentration of the hydrochloric acid is between 0.1 mol / L and 9 mol / L.
7. A solid-state nanopore array chip with microchannels, characterized in that, The array chip comprises, from bottom to top: a silicon substrate, a first dielectric layer, a second dielectric layer, and several electrodes; A cavity is formed in the silicon substrate that penetrates the silicon substrate; A plurality of nanopores penetrating the first dielectric layer are formed therein; A plurality of microfluidic cavities and microchannels are formed in the second dielectric layer, wherein each microfluidic cavity corresponds to one nanopore, and each microfluidic cavity is connected to two microchannels; Several electrodes are disposed on top of several microfluidic cavities and formed on the surface of the second dielectric layer, with each electrode having an exposed portion corresponding to its microfluidic cavity; the cavity exposes several nanopores.
8. The solid-state nanopore array chip with microchannels according to claim 7, characterized in that: The silicon substrate has one cavity formed therein, and the cavity exposes a plurality of nanopores; or the silicon substrate has a plurality of cavities formed therein, and each cavity exposes a nanopore.
9. The solid-state nanopore array chip with microchannels according to claim 7, characterized in that: The thickness of the silicon substrate is between 500 μm and 1000 μm, the thickness of the first dielectric layer is between 10 nm and 1000 nm, and the thickness of the second dielectric layer is between 10 nm and 100 μm.
10. The solid-state nanopore array chip with microchannels according to claim 7, characterized in that: The size of the nanopores is between 0.1 nm and 30 nm.
11. The solid-state nanopore array chip with microchannels according to claim 7, characterized in that: Several microfluidic cavities are identical and arranged in an array, and the spacing between two adjacent rows of microfluidic cavities and the spacing between two adjacent microfluidic cavities are equal.
12. The solid-state nanopore array chip with microchannels according to claim 11, characterized in that: The spacing is between 5μm and 2000μm.
13. The solid-state nanopore array chip with microchannels according to claim 7, characterized in that: The cross-sectional shape of the microfluidic cavity is square, and the cross-sectional shape of the microfluidic channel is rectangular.
14. The solid-state nanopore array chip with microchannels according to claim 13, characterized in that: The width of the square is between 1 μm and 1000 μm, and the width of the rectangle is between 0.5 μm and 500 μm.
15. The solid-state nanopore array chip with microchannels according to claim 7, characterized in that: The material of the first dielectric layer is SiN, SiO2, Al2O3, HfO2, ZnO or TiO2; the material of the second dielectric layer is SiN, SiO2, Al2O3, HfO2, ZnO or TiO2.
16. The solid-state nanopore array chip with microfluidic channels of claim 7, wherein: The electrode is made of TiN, Au, or Pt.