Display substrate, display device

Abstract

Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a reset circuit, n data signal lines, a data initial signal line, and z multiplexing signal lines; the reset circuit is electrically connected to the z multiplexing signal lines, the data initial signal line, and the n data signal lines respectively, and is configured to provide the signal of the data initial signal line to the n data signal lines under the control of the z multiplexing signal lines, where n and z are positive integers greater than or equal to 2. The display substrate and the display device provided by the embodiments of the present disclosure overcome the technical problem of abnormal writing of data signals in the prior art.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and more particularly to a display substrate and a display device. Background Art

[0002] With the gradual in-depth development of MLED (including Mini-LED and Micro-LED) technology, it will be applied to mass consumer products such as mobile phones, tablet computers, smart watches, in-vehicle displays, and laptop computers in the future. MLED has more obvious advantages in terms of contrast and brightness compared to Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Active Matrix Organic Light Emitting Diode (AMLED), and is considered the most competitive next-generation display technology.

[0003] For high-resolution and tiled display products, in order to save wiring space, a multiplexing circuit is usually used to drive the display product. When the data signal driving circuit uses a multiplexing circuit, when the data signal output on the same data signal line in the multiplexing circuit switches from a high level to a low level, there is a situation where the low-level data signal cannot be normally written into the pixel driving circuit, resulting in abnormal data signal writing. Summary of the Invention

[0004] The problem to be solved by the embodiments of the present application is to provide a display substrate and a display device to solve the technical problem of abnormal data signal writing in existing display products.

[0005] To solve the above technical problem, an embodiment of the present disclosure provides a display substrate, a reset circuit, n data signal lines, a data initial signal line, and z multiplexing signal lines;

[0006] The reset circuit is electrically connected to the z multiplexing signal lines, the data initial signal line, and the n data signal lines respectively, and is configured to provide the signal of the data initial signal line to the n data signal lines under the control of the z multiplexing signal lines, where n and z are positive integers greater than or equal to 2.

[0007] In an exemplary embodiment, the display substrate further includes a multiplexing circuit and k data output lines, where k = n / z and n is an integer multiple of z;

[0008] The multiplexing circuit is connected to the n data signal lines, the z multiplexing signal lines, and the k data output lines respectively, and is configured to time-division output the data signals of the k data output lines to the n data signal lines under the control of the z multiplexing signal lines.

[0009] In an exemplary embodiment, the multiplexing circuit includes k multiplexing sub - circuits, and the reset circuit includes k reset sub - circuits;

[0010] The s - th multiplexing sub - circuit is electrically connected to the ((z(s - 1)+1))-th to the (zs)-th data signal lines, the s - th data output line, and z multiplexing signal lines, where 1 ≤ s ≤ k;

[0011] The s - th reset sub - circuit is electrically connected to the ((z(s - 1)+1))-th to the (zs)-th data signal lines, the data initial signal line, and z multiplexing signal lines.

[0012] In an exemplary embodiment, the value of z is 2, the multiplexing signal lines include a first multiplexing signal line and a second multiplexing signal line, the multiplexing circuit includes k first multiplexing transistors and k second multiplexing transistors, and the reset circuit includes k first reset transistors and k second reset transistors;

[0013] The s - th multiplexing sub - circuit includes an s - th first multiplexing transistor and an s - th second multiplexing transistor. The control electrode of the s - th first multiplexing transistor is electrically connected to the first multiplexing signal line, the first electrode of the s - th first multiplexing transistor is electrically connected to the ((2s - 1))-th data signal line, and the second electrode of the s - th first multiplexing transistor is electrically connected to the s - th data output line; the control electrode of the s - th second multiplexing transistor is electrically connected to the second multiplexing signal line, the first electrode of the s - th second multiplexing transistor is electrically connected to the (2s)-th data signal line, and the second electrode of the s - th second multiplexing transistor is electrically connected to the s - th data output line;

[0014] The s - th reset sub - circuit includes an s - th first reset transistor and an s - th second reset transistor. The control electrode of the s - th first reset transistor is electrically connected to the first multiplexing signal line, the first electrode of the s - th first reset transistor is electrically connected to the (2s)-th data signal line, and the second electrode of the s - th first reset transistor is electrically connected to the data initial signal line; the control electrode of the s - th second reset transistor is electrically connected to the second multiplexing signal line, the first electrode of the s - th second reset transistor is electrically connected to the ((2s - 1))-th data signal line, and the second electrode of the s - th second reset transistor is electrically connected to the data initial signal line.

[0015] In an exemplary embodiment, the value of z is 3, the multiplexing signal lines include a first multiplexing signal line, a second multiplexing signal line, and a third multiplexing signal line, the multiplexing circuit includes k first multiplexing transistors, k second multiplexing transistors, and k third multiplexing transistors, and the reset circuit includes k first reset transistors, k second reset transistors, and k third reset transistors;

[0016] The s-th multiplexing sub-circuit includes an s-th first multiplexing transistor, an s-th second multiplexing transistor, and an s-th third multiplexing transistor. The control electrode of the s-th first multiplexing transistor is electrically connected to the first multiplexing signal line. The first electrode of the s-th first multiplexing transistor is electrically connected to the (3s - 2)-th data signal line. The second electrode of the s-th first multiplexing transistor is electrically connected to the s-th data output line. The control electrode of the s-th second multiplexing transistor is electrically connected to the second multiplexing signal line. The first electrode of the s-th second multiplexing transistor is electrically connected to the (3s - 1)-th data signal line. The second electrode of the s-th second multiplexing transistor is electrically connected to the s-th data output line. The control electrode of the s-th third multiplexing transistor is electrically connected to the third multiplexing signal line. The first electrode of the s-th third multiplexing transistor is electrically connected to the 3s-th data signal line. The second electrode of the s-th third multiplexing transistor is electrically connected to the s-th data output line;

[0017] The s-th reset sub-circuit includes an s-th first reset transistor, an s-th second reset transistor, and an s-th third reset transistor. The control electrode of the s-th first reset transistor is electrically connected to the first multiplexing signal line. The first electrode of the s-th first reset transistor is electrically connected to the (3s - 1)-th data signal line. The second electrode of the s-th first reset transistor is electrically connected to the data initial signal line. The control electrode of the s-th second reset transistor is electrically connected to the second multiplexing signal line. The first electrode of the s-th second reset transistor is electrically connected to the 3s-th data signal line. The second electrode of the s-th second reset transistor is electrically connected to the data initial signal line. The control electrode of the s-th third reset transistor is electrically connected to the third multiplexing signal line. The first electrode of the s-th third reset transistor is electrically connected to the (3s - 2)-th data signal line. The second electrode of the s-th third reset transistor is electrically connected to the data initial signal line.

[0018] In an exemplary embodiment, the display substrate further includes pixel units arranged in m rows and n columns. Each pixel unit includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element to emit light. The pixel driving circuit includes a data signal terminal;

[0019] The i-th data signal line is located on one side of the pixel units in the i-th column. The data signal terminal of the pixel driving circuit of the pixel units in the i-th column is electrically connected to the i-th data signal line, where 1 ≤ i ≤ n.

[0020] In an exemplary embodiment, the display substrate further includes a scan driving circuit, a reset driving circuit, m row scan signal lines, and m row reset signal lines. The pixel driving circuit further includes a reset signal terminal and a scan signal terminal;

[0021] The scan driving circuit includes m scan shift registers. The output terminal of the j-th scan shift register is connected to the j-th row scan signal line, where 1 ≤ j ≤ m;

[0022] The reset driving circuit includes: m complex shift registers, and the output terminal of the j-th complex shift register is electrically connected to the j-th row of reset signal lines;

[0023] For the pixel driving circuit of each pixel unit in the j-th row, the scan signal terminal is electrically connected to the j-th row of scan signal lines, and the reset signal terminal is electrically connected to the j-th row of reset signal lines.

[0024] In an exemplary embodiment, the pixel driving circuit includes: a reset sub-circuit, a writing sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a light-emitting sub-circuit;

[0025] The reset sub-circuit is respectively connected to the initial signal terminal, the reset signal terminal, the first node, and the first pole of the light-emitting element, and is configured to write the initial signal of the initial signal terminal into the first node and the first pole of the light-emitting element under the control of the reset signal terminal;

[0026] The writing sub-circuit is respectively connected to the scan signal terminal, the data signal terminal, and the third node, and is configured to write the signal of the data signal terminal into the third node under the control of the scan signal terminal;

[0027] The compensation sub-circuit is respectively connected to the first power supply terminal, the scan signal terminal, the first node, and the second node, and is configured to provide the signal of the second node to the first node under the control of the scan signal terminal until the signal of the first node meets the threshold condition;

[0028] The driving sub-circuit is respectively connected to the first node, the second node, and the third node, and is configured to provide a driving current to the second node according to the signals of the first node and the third node;

[0029] The light-emitting sub-circuit is respectively connected to the first power supply terminal, the second node, the third node, the light-emitting signal terminal, and the first pole of the light-emitting element, and is configured to write the signal of the first power supply terminal into the third node and the signal of the second power supply terminal into the first pole of the light-emitting element under the control of the light-emitting signal terminal;

[0030] The second pole of the light-emitting element is connected to the second power supply terminal.

[0031] In an exemplary embodiment, the reset sub-circuit includes a first transistor and a seventh transistor;

[0032] The control pole of the first transistor is connected to the reset signal terminal, the first pole of the first transistor is connected to the initial signal terminal, and the second pole of the first transistor is connected to the first node;

[0033] The control pole of the seventh transistor is connected to the reset signal terminal, the first pole of the seventh transistor is connected to the initial signal terminal, and the second pole of the seventh transistor is connected to the first pole of the light-emitting element.

[0034] In an exemplary embodiment, the writing sub - circuit includes a fourth transistor;

[0035] A control electrode of the fourth transistor is connected to a scanning signal terminal, a first electrode of the fourth transistor is connected to a data signal terminal, and a second electrode of the fourth transistor is connected to a third node.

[0036] In an exemplary embodiment, the compensation sub - circuit includes a second transistor and a first capacitor;

[0037] A control electrode of the second transistor is connected to the scanning signal terminal, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the second node;

[0038] A first end of the first capacitor is connected to a first power supply terminal, and a second end of the first capacitor is connected to the first node.

[0039] In an exemplary embodiment, the driving sub - circuit includes a third transistor;

[0040] A control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the third node, and a second electrode of the third transistor is connected to the second node.

[0041] In an exemplary embodiment, the light - emitting sub - circuit includes a fifth transistor and a sixth transistor;

[0042] A control electrode of the fifth transistor is connected to a light - emitting signal terminal, a first electrode of the fifth transistor is connected to the first power supply terminal, and a second electrode of the fifth transistor is connected to the third node;

[0043] A control electrode of the sixth transistor is connected to the light - emitting signal terminal, a first electrode of the sixth transistor is connected to the second node, and a second electrode of the sixth transistor is connected to a first electrode of the light - emitting element.

[0044] In an exemplary embodiment, the reset sub - circuit includes a first transistor and a seventh transistor; the writing sub - circuit includes a fourth transistor; the compensation sub - circuit includes a second transistor and a first capacitor; the driving sub - circuit includes a third transistor; the light - emitting sub - circuit includes a fifth transistor and a sixth transistor;

[0045] A control electrode of the first transistor is connected to a reset signal terminal, a first electrode of the first transistor is connected to an initial signal terminal, and a second electrode of the first transistor is connected to the first node;

[0046] A control electrode of the seventh transistor is connected to the reset signal terminal, a first electrode of the seventh transistor is connected to the initial signal terminal, and a second electrode of the seventh transistor is connected to the first electrode of the light - emitting element;

[0047] The control electrode of the fourth transistor is connected to the scanning signal terminal, the first electrode of the fourth transistor is connected to the data signal terminal, and the second electrode of the fourth transistor is connected to the third node;

[0048] The control electrode of the second transistor is connected to the scanning signal terminal, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the second node;

[0049] The first end of the first capacitor is connected to the first power supply terminal, and the second end of the first capacitor is connected to the first node;

[0050] The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the second node;

[0051] The control electrode of the fifth transistor is connected to the light emitting signal terminal, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the third node;

[0052] The control electrode of the sixth transistor is connected to the light emitting signal terminal, the first electrode of the sixth transistor is connected to the second node, and the second electrode of the sixth transistor is connected to the first electrode of the light emitting element.

[0053] In an exemplary embodiment, the types of the first transistor to the seventh transistor are P-type transistors or N-type transistors, or the types of the first transistor to the seventh transistor include P-type transistors and N-type transistors.

[0054] In a second aspect, the present disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0055] The display substrate provided by the embodiments of the present disclosure includes a reset circuit, n data signal lines, a data initial signal line, and z multiplexed signal lines. The reset circuit is configured to provide the signal of the data initial signal line to the n data signal lines under the control of the z multiplexed signal lines. The display substrate provided by the embodiments of the present disclosure overcomes the technical problem of abnormal data signal writing in the prior art.

[0056] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0057] The drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of the present disclosure.

[0058] Figure 1 The following is a schematic structural diagram of a display device;

[0059] Figure 2 The following is a schematic structural diagram of a display substrate provided by an exemplary embodiment;

[0060] Figure 3a The following is an equivalent circuit diagram of a multiplexing circuit provided by an exemplary embodiment;

[0061] Figure 3b The following is an equivalent circuit diagram of a multiplexing circuit provided by an exemplary embodiment;

[0062] Figure 4a The following is a schematic structural diagram of a pixel driving circuit provided by an exemplary embodiment;

[0063] Figure 4b The following is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment;

[0064] Figure 5 The following is a timing diagram of the operation of a display substrate provided by an exemplary embodiment of the present disclosure. Detailed Embodiments

[0065] The embodiments in the present disclosure can be implemented in many different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation methods and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0066] In the drawings, sometimes for clarity, the sizes of components, the thicknesses of layers, or regions may be exaggerated. Therefore, any implementation of the present disclosure is not necessarily limited to the sizes shown in the figures, and the shapes and sizes of the components in the figures do not reflect the actual proportions. In addition, the drawings schematically show ideal examples, and any implementation of the present disclosure is not limited to the shapes or values shown in the drawings.

[0067] The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are set to avoid confusion of components, rather than to limit the quantity.

[0068] In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing the embodiments and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the constituent elements can be appropriately changed according to the direction of the described constituent elements. Therefore, it is not limited to the terms described in the text and can be appropriately replaced according to the circumstances.

[0069] In the present disclosure, unless otherwise clearly defined and limited, the terms "mounted", "connected" and "coupled" shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0070] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (or drain electrode terminal, drain connection region, or drain electrode) and the source electrode (or source electrode terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where current mainly flows.

[0071] In the present disclosure, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during the operation of the circuit, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged. In the present disclosure, the control pole can be the gate electrode.

[0072] In the present disclosure, "electrically connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the connectable constituent elements. The "element having a certain electrical effect" can be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, an inductor, or a capacitor.

[0073] Figure 1The following is a schematic structural diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is respectively connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is respectively connected to a plurality of data signal lines (D1 to Dn), the scan signal driving circuit is respectively connected to a plurality of scan signal lines (G1 to Gm), and the light emission signal driving circuit is respectively connected to a plurality of light emission signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light emission signal line, and the data signal line. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ……, and Dn. For example, the data signal driving circuit may sample the gray value using a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driving circuit may generate scan signals to be provided to the scan signal lines G1, G2, G3, ……, and Gm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driving circuit may sequentially provide scan signals having conductive level pulses to the scan signal lines G1 to Gm. For example, the scan signal driving circuit may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, and m may be a natural number. The light emission signal driving circuit may generate emission signals to be provided to the light emission signal lines E1, E2, E3, ……, and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emission signal driving circuit may sequentially provide emission signals having cut-off level pulses to the light emission signal lines E1 to Eo. For example, the light emission driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, and o may be a natural number.

[0074] To solve the technical problem of abnormal writing of data signals in existing display products, an embodiment of the present disclosure provides a display substrate, such as Figure 2 As shown in FIGS. 2 and 3, the display substrate may include a reset circuit 30, n data signal lines D1 to Dn, a data initial signal line Vinit, and z multiplexed signal lines MUX(1) to MUX(z);

[0075] The reset circuit is electrically connected to the z multiplexed signal lines MUX(1) to MUX(z), the data initial signal line Vinit, and the n data signal lines D1 to Dn, and is configured to provide the signal of the data initial signal line Vinit to the n data signal lines under the control of the z multiplexed signal lines, where n and z are positive integers greater than or equal to 2.

[0076] The display substrate provided by the embodiment of the present disclosure includes a reset circuit, n data signal lines, a data initial signal line, and z multiplexed signal lines. The reset circuit is configured to provide the signal of the data initial signal line to the n data signal lines under the control of the z multiplexed signal lines. The display substrate provided by the embodiment of the present disclosure overcomes the technical problem of abnormal writing of data signals in the prior art.

[0077] In an exemplary embodiment, as Figure 2 As shown in FIGS. 2 and 3, the display substrate may further include an m-row and n-column pixel unit 10. Each pixel unit 10 includes a light-emitting element and a pixel driving circuit 11 configured to drive the light-emitting element to emit light. The pixel driving circuit 11 includes a data signal terminal;

[0078] The i-th data signal line is located on one side of the pixel units in the i-th column. The data signal terminal of the pixel driving circuit of the pixel units in the i-th column is electrically connected to the i-th data signal line, where 1 ≤ i ≤ n.

[0079] Figure 2 FIG. 2 is a schematic structural diagram of a display substrate provided by an exemplary embodiment, and FIG. 3 is an equivalent circuit diagram of a multiplexing circuit provided by an exemplary embodiment; Figure 4a FIG. 4 is a schematic structural diagram of a pixel driving circuit provided by an exemplary embodiment; Figure 4b FIG. 5 is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment; Figure 5 FIG. 6 is a working timing diagram of a display substrate provided by an exemplary embodiment of the present disclosure.

[0080] As Figure 2As shown, the display substrate may include a reset circuit 30, pixel units 10 arranged in an array (an m-row and n-column array), a data initial signal line Vinit, and z multiplexing signal lines MUX(1) to MUX(z). Each pixel unit 10 includes a light-emitting element and a pixel driving circuit 11 configured to drive the light-emitting element to emit light. The pixel driving circuit 11 may include: a data signal terminal. The reset circuit 30 is connected to the data initial signal line Vinit, the z multiplexing signal lines, and the data signal terminals of the pixel driving circuits of the n columns of pixel units, and is configured to reset the data signal terminals of the pixel driving circuits of the n columns of pixel units according to the reset signal of the data initial signal line Vinit under the control of the z multiplexing signal lines.

[0081] In an exemplary embodiment, as Figure 2 shown, the display substrate provided by the embodiment of the present disclosure may further include a multiplexing circuit 20 and k data output lines DT1 to DTk, where k = n / z, n and z are positive integers greater than or equal to 2, and n is an integer multiple of z. The multiplexing circuit 20 is respectively connected to n data signal lines D1 to Dn, z multiplexing signal lines MUX(1) to MUX(z), and k data output lines DT1 to DTk. The multiplexing circuit 20 is configured to time-divisionally output the data signals of the k data output lines DT1 to DTk to the n data signal lines D1 to Dn under the control of the z multiplexing signal lines MUX(1) to MUX(z). The i-th data signal line Di is located on one side of the i-th column of pixel units 10, and the data signal terminal of the pixel driving circuit 11 of the i-th column of pixel units 10 is electrically connected to the i-th data signal line Di, where 1 ≤ i ≤ n.

[0082] In an exemplary embodiment, the display substrate provided by the embodiment of the present disclosure may further include a scan driving circuit and a reset driving circuit.

[0083] As Figure 2 shown, the display substrate provided by the embodiment of the present disclosure may include: a scan driving circuit, a reset driving circuit, a reset circuit 30, a multiplexing circuit 20, m rows and n columns of pixel units 10, n data signal lines D1 to Dn, m rows of scan signal lines G1 to Gm, m rows of reset signal lines (not shown in the figure), a data initial signal line Vinit. The pixel driving circuit 11 in each pixel unit 10 includes: a data signal terminal, a scan signal terminal, and a reset signal terminal.

[0084] In an exemplary embodiment, the scan driving circuit includes: m scan shift registers, and the output terminal of the j-th scan shift register is connected to the j-th row of scan signal lines, where 1 ≤ j ≤ m. The reset driving circuit includes: m reset shift registers, and the output terminal of the j-th reset shift register is connected to the j-th row of reset signal lines.

[0085] In an exemplary embodiment, the i-th data signal line Di is located on one side of the pixel units 10 in the i-th column, and the data signal terminal of the pixel driving circuit 11 of the pixel units in the i-th column is electrically connected to the i-th data signal line Di, where 1 ≤ i ≤ n.

[0086] In an exemplary embodiment, for the pixel driving circuit of each pixel unit in the j-th row, the scan signal terminal is electrically connected to the j-th row scan signal line Gj, and the reset signal terminal is electrically connected to the j-th row reset signal line.

[0087] In an exemplary real-time mode, the scan driving circuit and the reset driving circuit can be two independent driving circuits.

[0088] In an exemplary embodiment, the display substrate may further include m rows of light-emitting signal lines (not shown in the figure). The pixel driving circuit may further include: a light-emitting signal terminal. For the pixel driving circuit of each pixel unit in the j-th row, the light-emitting signal terminal is electrically connected to the j-th row light-emitting signal line.

[0089] In an exemplary embodiment, the s-th data output line DTs provides data signals to the (2s - 1)-th data signal line and the 2s-th data signal line in a time-division manner, where 1 ≤ s ≤ k.

[0090] In an exemplary embodiment, as Figure 3a and Figure 3b shown, the multiplexing circuit 20 includes k multiplexing sub-circuits 201, and the reset circuit 30 includes k reset sub-circuits 301; where:

[0091] The s-th multiplexing sub-circuit 201 is electrically connected to the data signal lines D[z(s - 1)+1] to D(zs) of the (z(s - 1)+1)-th to zs-th, the s-th data output line DKs, and the z multiplexing signal lines MUX(1) to MUX(z), and is electrically connected to the data output line and the multiplexing signal lines, where 1 ≤ s ≤ k;

[0092] The s-th reset sub-circuit 301 is electrically connected to the data signal lines D[z(s - 1)+1] to D(zs) of the (z(s - 1)+1)-th to zs-th, the data initial signal line Vinit, and the z multiplexing signal lines MUX(1) to MUX(z).

[0093] As Figure 3aAs shown, the value of z can be 2, the multiplexed signal lines may include a first multiplexed signal line Mux(1) and a second multiplexed signal line Mux(2), the multiplexing circuit 20 may include k first multiplexing transistors MT1 and k second multiplexing transistors MT2, and the reset circuit 30 may include k first reset transistors MR1 and k second reset transistors MR2. The multiplexing circuit 20 may be configured to output the data signals of the k data output lines DT1 to DTk to the n data signal lines D1 to Dn in a time-division manner under the control of the first multiplexed signal line Mux(1) and the second multiplexed signal line Mux(2); the reset circuit 30 may be configured to reset the data signal terminals of the pixel driving circuits of the n columns of pixel units according to the reset signal of the data initial signal line Vinit under the control of the first multiplexed signal line Mux(1) and the second multiplexed signal line Mux(2).

[0094] In an exemplary embodiment, as Figure 3a shown, the s-th multiplexing sub-circuit 201 may include an s-th first multiplexing transistor MT1 and an s-th second multiplexing transistor MT2. The control electrode of the s-th first multiplexing transistor MT1 is electrically connected to the first multiplexed signal line Mux(1), the first electrode of the s-th first multiplexing transistor MT1 is electrically connected to the (2s - 1)-th data signal line, and the second electrode of the s-th first multiplexing transistor MT1 is electrically connected to the s-th data output line DTs, where 1 ≤ s ≤ k. Exemplarily, the control electrode of the first first multiplexing transistor MT1 is electrically connected to the first multiplexed signal line Mux(1), the first electrode of the first first multiplexing transistor MT1 is electrically connected to the first data signal line D1, the second electrode of the first first multiplexing transistor MT1 is electrically connected to the first data output line DT1, the control electrode of the second first multiplexing transistor MT1 is electrically connected to the first multiplexed signal line Mux(1), the first electrode of the second first multiplexing transistor MT1 is electrically connected to the third data signal line D3, the second electrode of the second first multiplexing transistor MT1 is electrically connected to the second data output line DT2, and so on.

[0095] In an exemplary embodiment, the control electrode of the s-th second multiplexing transistor MT2 is electrically connected to the second multiplexing signal line Mux(2), the first electrode of the s-th second multiplexing transistor MT2 is electrically connected to the 2s-th data signal line, and the second electrode of the s-th second multiplexing transistor MT2 is electrically connected to the s-th data output line DTs. Exemplarily, the control electrode of the first second multiplexing transistor MT2 is electrically connected to the second multiplexing signal line Mux(2), the first electrode of the first second multiplexing transistor MT2 is connected to the second data signal line D2, the second electrode of the first second multiplexing transistor MT2 is electrically connected to the first data output line DT1, the control electrode of the second second multiplexing transistor MT2 is electrically connected to the second multiplexing signal line Mux(2), the first electrode of the second second multiplexing transistor MT2 is electrically connected to the fourth data signal line D4, and the second electrode of the second second multiplexing transistor MT2 is electrically connected to the second data output line DT2, and so on.

[0096] In an exemplary embodiment, as Figure 3a shown, the s-th reset sub-circuit 301 may include an s-th first reset transistor MR1 and an s-th second reset transistor MR2. The control electrode of the s-th first reset transistor MR1 is electrically connected to the first multiplexing signal line Mux(1), the first electrode of the s-th first reset transistor MR1 is electrically connected to the 2s-th data signal line D(2s), and the second electrode of the s-th first reset transistor MR1 is electrically connected to the data initial signal line Vinit; the control electrode of the s-th second reset transistor MR2 is electrically connected to the second multiplexing signal line Mux(2), the first electrode of the s-th second reset transistor MR2 is electrically connected to the (2s - 1)-th data signal line D(2s - 1), and the second electrode of the s-th second reset transistor MR2 is electrically connected to the data initial signal line Vinit.

[0097] In Figure 3a the shown display substrate, while the first multiplexing transistor MT1 in the s-th multiplexing sub-circuit 201 transfers the signal written to the s-th data output line DTs to the (2s - 1)-th data signal line under the control of the first multiplexing signal line Mux(1), the first reset transistor MR1 in the s-th reset sub-circuit 301 writes the signal of the data initial signal line Vinit to the 2s-th data signal line D(2s) under the control of the first multiplexing signal line Mux(1), so that the data signal terminal of the pixel driving circuit connected to the 2s-th data signal line D(2s) is reset, avoiding the situation where the high-level data signal of the previous row cannot be written and the low-level data signal of the next row cannot be written.

[0098] As Figure 3bAs shown, the value of z can be 3. The multiplexed signal lines may include a first multiplexed signal line Mux(1), a second multiplexed signal line Mux(2), and a third multiplexed signal line Mux(3). The multiplexing circuit 20 includes k first multiplexing transistors MT1, k second multiplexing transistors MT2, and k third multiplexing transistors MT3. The reset circuit 30 may include k first reset transistors MR1, k second reset transistors MR2, and k third reset transistors MR3;

[0099] The s-th multiplexing sub-circuit 201 may include an s-th first multiplexing transistor MT1, an s-th second multiplexing transistor MT2, and an s-th third multiplexing transistor MT3. The control electrode of the s-th first multiplexing transistor MT1 is electrically connected to the first multiplexed signal line Mux(1). The first electrode of the s-th first multiplexing transistor MT1 is electrically connected to the (3s - 2)-th data signal line. The second electrode of the s-th first multiplexing transistor MT1 is electrically connected to the s-th data output line. The control electrode of the s-th second multiplexing transistor MT2 is electrically connected to the second multiplexed signal line Mux(2). The first electrode of the s-th second multiplexing transistor MT2 is electrically connected to the (3s - 1)-th data signal line. The second electrode of the s-th second multiplexing transistor MT2 is electrically connected to the s-th data output line DTs. The control electrode of the s-th third multiplexing transistor MT3 is electrically connected to the third multiplexed signal line Mux(3). The first electrode of the s-th third multiplexing transistor MT3 is electrically connected to the 3s-th data signal line. The second electrode of the s-th third multiplexing transistor MT3 is electrically connected to the s-th data output line DTs;

[0100] The s-th reset sub-circuit 301 may include an s-th first reset transistor MR1, an s-th second reset transistor MR2, and an s-th third reset transistor MR3. The control electrode of the s-th first reset transistor MR1 is electrically connected to the first multiplexed signal line Mux(1). The first electrode of the s-th first reset transistor MR1 is electrically connected to the (3s - 1)-th data signal line D(3s - 1). The second electrode of the s-th first reset transistor MR1 is electrically connected to the data initial signal line Vinit. The control electrode of the s-th second reset transistor MR2 is electrically connected to the second multiplexed signal line Mux(2). The first electrode of the s-th second reset transistor MR2 is electrically connected to the 3s-th data signal line D(3s). The second electrode of the s-th second reset transistor MR2 is electrically connected to the data initial signal line Vinit. The control electrode of the s-th third reset transistor MR3 is electrically connected to the third multiplexed signal line Mux(3). The first electrode of the s-th third reset transistor MR3 is electrically connected to the (3s - 2)-th data signal line D(3s - 2). The second electrode of the s-th third reset transistor MR3 is electrically connected to the data initial signal line Vinit.

[0101] At Figure 3bFor the display substrate shown, while the first multiplexing transistor MT1 in the s-th multiplexing sub-circuit 201 writes the s-th data output line DTs to the (3s - 2)-th data signal line under the control of the first multiplexing signal line Mux(1), the first reset transistor MR1 in the s-th reset sub-circuit 301 writes the data initial signal line Vinit signal to the (3s - 1)-th data signal line D(3s - 1) under the control of the first multiplexing signal line Mux(1), so as to reset the data signal terminal of the pixel driving circuit connected to the (3s - 1)-th data signal line D(3s - 1), avoiding the situation that after writing a high-level data signal in the previous line, it is impossible to write a low-level data signal in the next line.

[0102] In an exemplary embodiment, the first multiplexing transistor MT1, the second multiplexing transistor MT2, and the third multiplexing transistor MT3 can be switching transistors. The first multiplexing transistor MT1, the second multiplexing transistor MT2, and the third multiplexing transistor MT3 can all be P-type transistors, or can all be N-type transistors; or a part of the first multiplexing transistor MT1, the second multiplexing transistor MT2, and the third multiplexing transistor MT3 is an N-type transistor, and the other part is a P-type transistor.

[0103] In an exemplary embodiment, the first reset transistor MR1, the second reset transistor MR2, and the third reset transistor MR3 can be switching transistors. The first reset transistor MR1, the second reset transistor MR2, and the third reset transistor MR3 can all be P-type transistors, or can all be N-type transistors; or a part of the first reset transistor MR1, the second reset transistor MR2, and the third reset transistor MR3 is an N-type transistor, and the other part is a P-type transistor.

[0104] In Figure 3a In the structure shown, taking the first multiplexing sub-circuit 201 and the first reset sub-circuit 301 as an example for illustration: The first multiplexing transistor MT1 in the first multiplexing sub-circuit 201 outputs the signal of the first data output line DT1 to the first data signal line D1 under the control of the first multiplexing signal line MUX(1). At the same time, the first reset transistor MR1 in the first reset sub-circuit 301 resets the signal of the second data signal line D2 according to the reset signal of the data initial signal line Vinit under the control of the first multiplexing signal line MUX(1). In this way, it is possible to avoid writing the data voltage of the previous line remaining in the data signal terminal of the pixel driving circuit before writing the data signal of the next line, so that the data voltage can be smoothly written into the pixel driving circuit during the data writing stage. Moreover, even if the data voltage is written after the t time period when the scan signal terminal is at a low level, it will not be affected by the data voltage of the previous line, increasing the flexibility of the driving timing control and at the same time reducing the influence of the interlayer capacitance of adjacent data signal lines.

[0105] It is understandable that the display substrate may further include a substrate, and the pixel units are disposed on the substrate.

[0106] In one exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. Among them, the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyaryl ester, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0107] In one exemplary embodiment, the pixel unit may be any one of a red (R) pixel unit, a green (G) pixel unit, a blue (B) pixel unit, and a white pixel unit, and the present disclosure does not limit this here. When the display substrate includes a red (R) pixel unit, a green (G) pixel unit, and a blue (B) pixel unit, the three pixel units may be arranged in a horizontal side-by-side, vertical side-by-side, or staggered manner. When the display substrate includes a red (R) pixel unit, a green (G) pixel unit, a blue (B) pixel unit, and a white pixel unit, the four pixel units may be arranged in a horizontal side-by-side, vertical side-by-side, or array manner, and the present disclosure does not limit this here.

[0108] In one exemplary embodiment, the light-emitting element may be a light-emitting diode. In one exemplary embodiment, the light-emitting element includes a current-driven device and may be a current-type light-emitting diode, such as a micro light-emitting diode (abbreviated as Micro LED) or a mini light-emitting diode (abbreviated as Mini LED) or an organic light-emitting diode (abbreviated as OLED) or a quantum dot light-emitting diode (abbreviated as QLED).

[0109] In one exemplary embodiment, the light-emitting element in the red pixel unit is a red light-emitting diode, the light-emitting element in the blue pixel unit is a blue light-emitting diode, the light-emitting element in the green pixel unit is a green light-emitting diode, or the light-emitting elements in the red pixel unit, the blue pixel unit, the green pixel unit, and the white pixel unit are all blue light-emitting diodes, and by cooperating with color conversion materials (such as quantum dots, phosphors, etc.), light emission of corresponding colors such as red, blue, green, and white is achieved.

[0110] In an exemplary embodiment, such as Figure 4aAs shown, the pixel driving circuit 11 may include: a reset sub - circuit 11, a writing sub - circuit 12, a compensation sub - circuit 13, a driving sub - circuit 14, and a light - emitting sub - circuit 15;

[0111] The reset sub - circuit 11 is respectively connected to the initial signal terminal Vint, the reset signal terminal RST, the first node N1, and the first pole of the light - emitting element, and is configured to write the initial signal of the initial signal terminal Vint into the first node N1 and the first pole of the light - emitting element under the control of the reset signal terminal RST;

[0112] The writing sub - circuit 12 is respectively connected to the scan signal terminal Gate, the data signal terminal Data, and the third node N3, and is configured to write the signal of the data signal terminal Data into the third node N3 under the control of the scan signal terminal Gate;

[0113] The compensation sub - circuit 13 is respectively connected to the first power supply terminal VDD, the scan signal terminal Gate, the first node N1, and the second node N2, and is configured to provide the signal of the second node N2 to the first node N1 under the control of the scan signal terminal Gate until the signal of the first node N1 meets the threshold condition;

[0114] The driving sub - circuit 14 is respectively connected to the first node N1, the second node N2, and the third node N3, and is configured to provide a driving current to the second node N2 according to the signals of the first node N1 and the third node N3;

[0115] The light - emitting sub - circuit 15 is respectively connected to the first power supply terminal VDD, the second node N2, the third node N3, the light - emitting signal terminal EM, and the first pole of the light - emitting element, and is configured to write the signal of the first power supply terminal VDD into the third node N3 and write the signal of the second power supply terminal VSS into the first pole of the light - emitting element under the control of the light - emitting signal terminal EM;

[0116] The second pole of the light - emitting element is connected to the second power supply terminal VSS.

[0117] In an exemplary embodiment, as Figure 4b shown, the reset sub - circuit 11 may include a first transistor T1 and a seventh transistor T7;

[0118] The control pole of the first transistor T1 is connected to the reset signal terminal RST, the first pole of the first transistor T1 is connected to the initial signal terminal Vint, and the second pole of the first transistor T1 is connected to the first node N1;

[0119] The control pole of the seventh transistor T7 is connected to the reset signal terminal RST, the first pole of the seventh transistor T7 is connected to the initial signal terminal Vint, and the second pole of the seventh transistor T7 is connected to the first pole of the light - emitting element.

[0120] In an exemplary embodiment, the writing sub - circuit 12 may include a fourth transistor T4;

[0121] The control electrode of the fourth transistor T4 is connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0122] In an exemplary embodiment, the compensation sub - circuit 13 may include a second transistor T2 and a first capacitor C1;

[0123] The control electrode of the second transistor T2 is connected to the scan signal terminal Gate, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second node N2;

[0124] The first end of the first capacitor C1 is connected to the first power supply terminal VDD, and the second end of the first capacitor C1 is connected to the first node N1.

[0125] In an exemplary embodiment, the driving sub - circuit 14 may include a third transistor T3;

[0126] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the second node N2.

[0127] In an exemplary embodiment, the light - emitting sub - circuit 15 may include a fifth transistor T5 and a sixth transistor T6;

[0128] The control electrode of the fifth transistor T5 is connected to the light - emitting signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3;

[0129] The control electrode of the sixth transistor T6 is connected to the light - emitting signal terminal EM, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light - emitting element OLED.

[0130] In an exemplary embodiment, as Figure 4a and Figure 4b shown, in the pixel driving circuit 11, the reset sub - circuit 11 includes a first transistor T1 and a seventh transistor T7; the writing sub - circuit 12 includes a fourth transistor T4; the compensation sub - circuit 13 includes a second transistor T2 and a first capacitor C1; the driving sub - circuit 14 includes a third transistor T3; the light - emitting sub - circuit 15 includes a fifth transistor T5 and a sixth transistor T6;

[0131] The control electrode of the first transistor T1 is connected to the reset signal terminal RST, the first electrode of the first transistor T1 is connected to the initial signal terminal Vint, and the second electrode of the first transistor T1 is connected to the first node N1;

[0132] The control electrode of the seventh transistor T7 is connected to the reset signal terminal RST, the first electrode of the seventh transistor T7 is connected to the initial signal terminal Vint, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element;

[0133] The control electrode of the fourth transistor T4 is connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the third node N3;

[0134] The control electrode of the second transistor T2 is connected to the scan signal terminal Gate, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second node N2;

[0135] The first terminal of the first capacitor C1 is connected to the first power supply terminal VDD, and the second terminal of the first capacitor C1 is connected to the first node N1;

[0136] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the second node N2;

[0137] The control electrode of the fifth transistor T5 is connected to the light-emitting signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3;

[0138] The control electrode of the sixth transistor T6 is connected to the light-emitting signal terminal EM, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element OLED.

[0139] As Figure 4b shown, the pixel driving circuit 11 in each pixel unit 10 may include: 7 transistors (T1 to T7), 1 capacitor unit (C1), 5 signal input terminals (RST, EM, Gate, Data, and Vint), 3 nodes (N1 to N3), and 2 power supply terminals (VDD and VSS).

[0140] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit 11 may be of the same type of transistor. For example, they may all be P-type transistors or all be N-type transistors, so as to simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0141] In an exemplary embodiment, the signal of the second power supply terminal VSS is a low-level signal, and the signal of the first power supply terminal VDD is a continuously provided high-level signal.

[0142] Taking the multiplexing circuit 20 including a first multiplexing transistor MT1, a second multiplexing transistor MT2, and a third multiplexing transistor MT3, and the first multiplexing transistor MT1, the second multiplexing transistor MT2, the third multiplexing transistor MT3, and the first transistor T1 to the seventh transistor T7 all being P-type transistors as an example, the working process of the display substrate will be described below. Figure 5 It represents the timing diagram of the pixel driving circuits 11 of adjacent columns in the same row. As Figure 5 shown, Data(n - 1) is the data signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n - 1)-th column, Data(n) is the data signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the n-th column, and Data(n + 1) is the data signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n + 1)-th column; DTh is the data output line (i.e., the h-th data output line) connected to the data signal lines of the (n - 1)-th column, the n-th column, and the (n + 1)-th column in the i-th row, where h = n / 3, n is a positive integer greater than or equal to 3, and n is a multiple of 3; RST(n - 1) is the reset signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n - 1)-th column, RST(n) is the reset signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the n-th column, and RST(n + 1) is the reset signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n + 1)-th column; EM(n - 1) is the light emitting signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n - 1)-th column, EM(n) is the light emitting signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the n-th column, and EM(n + 1) is the light emitting signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n + 1)-th column; Gate(n - 1) is the scan signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n - 1)-th column, Gate(n) is the scan signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the n-th column, and Gate(n + 1) is the scan signal terminal of the pixel driving circuit in the pixel unit of the i-th row and the (n + 1)-th column; Mux(1) is the first multiplexing signal line in the multiplexing circuit, Mux(2) is the second multiplexing signal line in the multiplexing circuit, and Mux(3) is the third multiplexing signal line in the multiplexing circuit.

[0143] AsFigure 5 As shown, the working process of a display substrate provided by an exemplary embodiment may include: a first stage P1 to a third stage P3.

[0144] First stage P1: It can be called a reset stage. The signals of the reset signal terminals RST(n - 1) / RST(n) / RST(n + 1) are low-level signals, and the signals of the scan signal terminals Gate(n - 1) / Gate(n) / Gate(n + 1), the light-emitting signal terminals EM(n - 1) / EM(n) / EM(n + 1), the first multiplexed signal line Mux(1), the second multiplexed signal line Mux(2), and the third multiplexed signal line Mux(3) are high-level signals. The low-level signals of the reset signal terminals RST(n - 1) / RST(n) / RST(n + 1) turn on the first transistor T1 and the seventh transistor T7 of the pixel driving circuits in the (n - 1)th column, the nth column, and the (n + 1)th column. The initial signal of the initial signal terminal Vint is provided to the first node N1 and the first pole of the light-emitting element, initializing the first capacitor C1, the control pole of the third transistor T3, and the first pole of the light-emitting element, and clearing the original data voltage in the first capacitor C1, the control pole of the three-transistor T3, and the first pole of the light-emitting element. The high-level signals of the scan signal terminals Gate(n - 1) / Gate(n) / Gate(n + 1), the light-emitting signal terminals EM(n - 1) / EM(n) / EM(n + 1), the first multiplexed signal line Mux(1), the second multiplexed signal line Mux(2), and the third multiplexed signal line Mux(3) turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 of the pixel driving circuits in the (n - 1)th column, the nth column, and the (n + 1)th column, and the first multiplexed transistor MT1, the second multiplexed transistor MT2, and the third multiplexed transistor MT3 in the multiplexing circuit. The signal of the data output line DTh cannot be written into the data signal terminals Data(n - 1), Data(n), Data(n + 1) of the pixel driving circuits in the (n - 1)th column, the nth column, and the (n + 1)th column via the first multiplexed transistor MT1, the second multiplexed transistor MT2, and the third multiplexed transistor MT3. In this stage, the light-emitting elements OLED driven by the pixel driving circuits in the (n - 1)th column, the nth column, and the (n + 1)th column do not emit light.

[0145] The second stage P2: It can be called the data writing stage. The signals of the reset signal terminals RST(n - 1) / RST(n) / RST(n + 1) and the emission signal terminals EM(n - 1) / EM(n) / EM(n + 1) are high-level signals, and the signals of the scan signal terminals Gate(n - 1) / Gate(n) / Gate(n + 1) are low-level signals. Since the signals of the reset signal terminals RST(n - 1) / RST(n) / RST(n + 1) and the emission signal terminals EM(n - 1) / EM(n) / EM(n + 1) are high-level signals, the first transistors T1, the seventh transistors T7, the fifth transistors T5, and the sixth transistors T6 in the pixel driving circuits of the (n - 1)-th column, the n-th column, and the (n + 1)-th column are all cut off; since the signals of the scan signal terminals Gate(n - 1) / Gate(n) / Gate(n + 1) are low-level signals, the second transistors T2 and the fourth transistors T4 in the pixel driving circuits of the (n - 1)-th column, the n-th column, and the (n + 1)-th column are turned on; since the first transistor T1 is cut off, the initial signal of the initial signal terminal Vint cannot be written into the first node N1. Since the voltage across the first capacitor C1 does not change suddenly, the first node N1 maintains the low level of the previous frame, and the third transistor T3 is turned on.

[0146] In this stage, it can be divided into three sub-stages according to the signals of the first multiplexing signal line Mux(1), the second multiplexing signal line Mux(2), and the third multiplexing signal line Mux(3):

[0147] The first sub-phase P21: It can be called the data writing phase of the pixel driving circuit in the (n-1)-th column. The signal of the first multiplexing signal line Mux(1) is a low-level signal, and the signals of the second multiplexing signal line Mux(2) and the third multiplexing signal line Mux(3) are high-level signals. Since the signal of the first multiplexing signal line Mux(1) is a low-level signal, the first multiplexing transistor MT1 and the first reset transistor MR1 are turned on. The data voltage on the data output line DTh is written into the data signal terminal Data(n-1) of the pixel driving circuit in the (n-1)-th column through the first multiplexing transistor MT1. The data voltage on the data signal terminal Data(n-1) is written into the first node N1 through the turned-on fourth transistor T4, third transistor T3, and second transistor T2, and the difference between the data voltage on the data signal terminal Data(n-1) and the threshold voltage of the third transistor T3 is charged into the first capacitor C1. The voltage at the second terminal (the first node N1) of the first capacitor C1 is Vd+Vth, where Vd is the data voltage on the data signal terminal Data(n-1) and Vth is the threshold voltage of the third transistor T3. Since the first reset transistor MR1 is turned on, the signal on the data initial signal line vinit is written into the data signal terminal Data(n) of the n-th column through the first reset transistor MR1 to reset the signal on the data signal terminal Data(n) of the n-th column. Since the signals of the second multiplexing signal line Mux(2) and the third multiplexing signal line Mux(3) are high-level signals, the second multiplexing transistor MT2, the second reset transistor MR2, the third multiplexing transistor MT3, and the third reset transistor MR3 are turned off. The signal on the data output line DTh cannot be written into the data signal terminals Data(n) and Data(n+1) of the pixel driving circuits in the n-th and (n+1)-th columns through the second multiplexing transistor MT2 and the third multiplexing transistor MT3, and the signal on the data initial signal line vinit cannot be written into the data signal terminals Data(n+1) and Data(n-1) of the (n+1)-th and (n-1)-th columns through the second reset transistor MR2 and the third reset transistor MR3.

[0148] The second sub-stage P22: It can be called the data writing stage of the pixel driving circuit in the n-th column. The signals of the first multiplexing signal line Mux(1) and the third multiplexing signal line Mux(3) are high-level signals, and the signal of the second multiplexing signal line terminal Mux(2) is a low-level signal. Since the signal of the second multiplexing signal line Mux(2) is a low-level signal, the second multiplexing transistor MT2 and the second reset transistor MR2 are turned on. The data voltage of the data output line DTh is written into the data signal terminal Data(n) of the n-th column pixel driving circuit through the second multiplexing transistor MT2. The data voltage of the data signal terminal Data(n) is written into the first node N1 through the turned-on fourth transistor T4, third transistor T3, and second transistor T2, and the difference between the data voltage of the data signal terminal Data(n) and the threshold voltage of the third transistor T3 is charged into the first capacitor C1. The voltage at the second end (the first node N1) of the first capacitor C1 is Vd + Vth, where Vd is the data voltage of the data signal terminal Data(n), and Vth is the threshold voltage of the third transistor T3. Since the second reset transistor MR2 is turned on, the signal of the data initial signal line vinit is written into the data signal terminal Data(n + 1) of the (n + 1)-th column through the second reset transistor MR2 to reset the signal of the data signal terminal Data(n + 1) of the (n + 1)-th column. Since the signals of the first multiplexing signal line Mux(1) and the third multiplexing signal line Mux(3) are high-level signals, the first multiplexing transistor MT1, the first reset transistor MR1, the third multiplexing transistor MT3, and the third reset transistor MR3 are turned off. The signal of the data output line DTh cannot be written into the data signal terminals Data(n - 1) and Data(n + 1) of the pixel driving circuits in the (n - 1)-th column and the (n + 1)-th column through the first multiplexing transistor MT1 and the third multiplexing transistor MT3, and the signal of the data initial signal line vinit cannot be written into the data signal terminals Data(n) and Data(n - 1) of the n-th column and the (n - 1)-th column through the first reset transistor MR1 and the third reset transistor MR3.

[0149] The third sub-phase P23: It can be called the data writing phase of the pixel driving circuit of the (n + 1)-th column. The signals of the first multiplexing signal line Mux(1) and the second multiplexing signal line terminal Mux(2) are high-level signals, and the signal of the third multiplexing signal line Mux(3) is a low-level signal. Since the signal of the third multiplexing signal line Mux(3) is a low-level signal, the third multiplexing transistor MT3 and the third reset transistor MR3 are turned on. The data voltage of the data output line DTh is written into the data signal terminal Data(n + 1) of the pixel driving circuit of the (n + 1)-th column through the third multiplexing transistor MT3. The data voltage of the data signal terminal Data(n + 1) is written into the first node N1 through the turned-on fourth transistor T4, third transistor T3, and second transistor T2, and the difference between the data voltage of the data signal terminal Data(n + 1) and the threshold voltage of the third transistor T3 is charged into the first capacitor C1. The voltage at the second end (the first node N1) of the first capacitor C1 is Vd + Vth, where Vd is the data voltage of the data signal terminal Data(n + 1), and Vth is the threshold voltage of the third transistor T3. Since the third reset transistor MR3 is turned on, the signal of the data initial signal line vinit is written into the data signal terminal Data(n - 1) of the (n - 1)-th column through the third reset transistor MR3 to reset the signal of the data signal terminal Data(n - 1) of the (n - 1)-th column. Since the signals of the first multiplexing signal line Mux(1) and the second multiplexing signal line Mux(2) are high-level signals, the first multiplexing transistor MT1, the first reset transistor MR1, the second multiplexing transistor MT2, and the second reset transistor MR2 are turned off. The signal of the data output line DTh cannot be written into the data signal terminals Data(n - 1) and Data(n) of the pixel driving circuits of the (n - 1)-th and n-th columns through the first multiplexing transistor MT1 and the second multiplexing transistor MT2, and the signal of the data initial signal line vinit cannot be written into the data signal terminals Data(n) and Data(n + 1) of the n-th and (n + 1)-th columns through the first reset transistor MR1 and the second reset transistor MR2.

[0150] The third stage P3: It can be called the light-emitting stage. The signals of the reset signal terminals RST(n-1) / RST(n) / RST(n+1), the scan signal terminals Gate(n-1) / Gate(n) / Gate(n+1), the first multiplexed signal line Mux(1), the second multiplexed signal line Mux(2), and the third multiplexed signal line Mux(3) are high-level signals, and the signals of the light-emitting signal terminals EM(n-1) / EM(n) / EM(n+1) are low-level signals. The signals of the light-emitting signal terminals EM(n-1) / EM(n) / EM(n+1) being low-level signals causes the fifth transistors T5 and the sixth transistors T6 in the pixel driving circuits of the (n-1)th column, the nth column, and the (n+1)th column to conduct. The voltage signal of the first power supply terminal VDD is written into the third node N3 (i.e., the first pole of the third transistor) via the fifth transistor T5. The signals of the reset signal terminals RST(n-1) / RST(n) / RST(n+1), the scan signal terminals Gate(n-1) / Gate(n) / Gate(n+1), the first multiplexed signal line Mux(1), the second multiplexed signal line Mux(2), and the third multiplexed signal line Mux(3) being high-level signals causes the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7 in the pixel driving circuits of the (n-1)th column, the nth column, and the (n+1)th column, as well as the first multiplexed transistor MT1, the second multiplexed transistor MT2, the third multiplexed transistor MT3, the first reset transistor MR1, the second reset transistor MR2, and the third reset transistor MR3 in the multiplexing circuit 20 to all be cut off. The first node N1 maintains the voltage Vd+Vth of the previous frame (i.e., the control pole voltage of the third transistor T3). The voltage difference Vgs between the control pole and the first pole of the third transistor T3 is Vd+Vth-VDD. Therefore, the third transistor T3 conducts, and the power supply output by the first power supply terminal VDD provides a driving voltage to the first pole of the light-emitting element via the conducting fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element to emit light.

[0151] During the operation of the pixel driving circuit provided by the embodiment of the present disclosure, in the data writing stage, the reset transistor is controlled by the multiplexed signal line to reset the data signal terminals of the next column according to the signal of the data initial signal line, and the reset transistor of the last column resets the data signal terminals of the first column according to the signal of the data initial signal line, realizing the alternate reset of different columns. After the data signals of one row are written, the data signal terminals of this row are all reset, avoiding writing the data voltage of the previous row remaining in the data signal terminals into the pixel driving circuit before writing the data signals of the next row, so that the data voltage can be smoothly written into the pixel driving circuit during the data writing stage. Moreover, even if the data voltage is written after the t time period when the scan signal terminal is at a low level, it will not be affected by the data voltage of the previous row, increasing the flexibility of the driving timing control and at the same time reducing the influence of the interlayer capacitance of adjacent data signal lines.

[0152] Taking the pixel driving circuit at the nth column of the ith row as an example for illustration: If the data voltage written by the pixel driving circuit in the previous row (i.e., the nth column of the (i - 1)th row) is the high level DH, assuming that the reset transistor is not used to reset the signal of the data signal terminal in the next column (after the data in the (i - 1)th row is written, the signals of all data signal terminals corresponding to the (i - 1)th row are reset), then in the data writing stage of the pixel driving circuit at the nth column of the ith row, the third node N3 in the pixel driving circuit at the nth column of the ith row will maintain the high level DH of the previous row, and in the data writing stage of the pixel driving circuit at the (n - 1)th column of the ith row, the high level DH of the previous row retained by the third node N3 in the pixel driving circuit at the nth column of the ith row is written into the first node N1 via the third transistor T3 and the second transistor T2. Then the potential of the first node N1 in the pixel driving circuit at the nth column of the ith row is: DH + Vth. When the low level DL is written in the data writing stage at the nth column of the ith row, the potential of the third node N3 is DL. Using Vgs to represent the voltage difference between the control electrode voltage (the first node N1) and the first pole voltage (the third node N3) of the third transistor T3, then Vgs - Vth = (DH + Vth) - DL - Vth = DH - DL. Since DH > DL, the third transistor T3 is turned off. Therefore, the low level DL of the third node N3 cannot be written into the first node N1. In the embodiments of the present disclosure, after the data signal writing of each column is completed, the signal of the data signal terminal in the next column will be reset. After the data signal of any row is written, the signals of all column data signal terminals corresponding to this row have been reset. Before the data writing stage of the next row, the third node N3 is initialized to make the voltage of the third node N3 in the pixel driving circuit at the nth column of the ith row become the initial signal voltage, clearing the data voltage retained by the third node N3 in the previous row. In the data writing stage of the (n - 1)th column, the third node N3 in the pixel driving circuit at the nth row is the initial signal voltage, and there will be no situation where the high level DH of the previous row is written into the first node N1, which can effectively avoid the problem that the low level data voltage signal cannot be written.

[0153] An embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0154] The display substrate is the display substrate provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, which will not be elaborated here.

[0155] In an exemplary embodiment, the display device may be a liquid crystal display device (LCD for short), an organic light emitting diode (OLED for short), or a light emitting diode (LED for short) display device. The display device may be any product or component with a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED for short) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0156] The display substrate and the display device provided by the embodiments of the present disclosure. The display substrate includes a reset circuit, n data signal lines, a data initial signal line, and z multiplexed signal lines. The reset circuit is configured to provide the signal of the data initial signal line to the n data signal lines under the control of the z multiplexed signal lines. The display substrate provided by the embodiments of the present disclosure overcomes the technical problem of abnormal data signal writing in the prior art.

[0157] Although the disclosed embodiments are as above, the above content is only an embodiment adopted for the convenience of understanding the present disclosure and is not used to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, Including: n columns of pixel driving circuits, a reset circuit, n data signal lines, a data initial signal line, and z multiplexing signal lines; the pixel driving circuit includes a data signal terminal and a scan signal terminal, and the n data signal lines are respectively electrically connected to the data signal terminals of the n columns of pixel driving circuits; The reset circuit is respectively electrically connected to the z multiplexing signal lines, the data initial signal line, and the n data signal lines, and is configured to provide the signal of the data initial signal line to the n data signal lines under the control of the z multiplexing signal lines, where n and z are positive integers greater than or equal to 2; The reset circuit includes multiple reset sub-circuits. One reset sub-circuit is electrically connected to the data signal terminals of z columns of pixel driving circuits through z adjacent data signal lines. Among the data signal terminals of the z columns of pixel driving circuits connected to the same reset sub-circuit: during the data writing stage of one column of data signal terminals, the reset sub-circuit is controlled by the multiplexing signal line to reset the data signal terminal of the next column according to the signal of the data initial signal line. During the data writing stage of the last column of data signal terminals, the reset sub-circuit resets the data signal terminal of the first column according to the signal of the data initial signal line, realizing the alternate reset of different columns. After the data signal writing of one row is completed, the data signal terminals of this row are all reset, avoiding writing the data voltage of the previous row remaining in the data signal terminal into the pixel driving circuit before the data signal of the next row is written, so that the data voltage can be smoothly written into the pixel driving circuit during the data writing stage.

2. The display substrate according to claim 1, wherein Further including: A multiplexing circuit and k data output lines, where k = n / z and n is an integer multiple of z; The multiplexing circuit is respectively connected to the n data signal lines, the z multiplexing signal lines, and the k data output lines, and is configured to output the data signals of the k data output lines to the n data signal lines in a time-division manner under the control of the z multiplexing signal lines.

3. The display substrate according to claim 2, wherein The multiplexing circuit includes k multiplexing sub-circuits, and the reset circuit includes k reset sub-circuits; The s-th multiplexing sub-circuit is electrically connected to the (z(s - 1)+1)-th to the zs-th data signal lines, the s-th data output line, and z multiplexing signal lines, 1 s k; The s-th reset sub-circuit is electrically connected to the (z(s - 1) + 1)-th data signal line to the zs-th data signal line, the data initial signal line, and the z multiplexing signal lines.

4. The display substrate according to claim 3, wherein, The value of z is 2, the multiplexing signal lines include a first multiplexing signal line and a second multiplexing signal line, the multiplexing circuit includes k first multiplexing transistors and k second multiplexing transistors, and the reset circuit includes k first reset transistors and k second reset transistors; The s-th multiplexing sub-circuit includes the s-th first multiplexing transistor and the s-th second multiplexing transistor. The control electrode of the s-th first multiplexing transistor is electrically connected to the first multiplexing signal line, the first electrode of the s-th first multiplexing transistor is electrically connected to the (2s - 1)-th data signal line, and the second electrode of the s-th first multiplexing transistor is electrically connected to the s-th data output line; the control electrode of the s-th second multiplexing transistor is electrically connected to the second multiplexing signal line, the first electrode of the s-th second multiplexing transistor is electrically connected to the 2s-th data signal line, and the second electrode of the s-th second multiplexing transistor is electrically connected to the s-th data output line; The s-th reset sub-circuit includes an s-th first reset transistor and an s-th second reset transistor. The control electrode of the s-th first reset transistor is electrically connected to the first multiplexed signal line. The first electrode of the s-th first reset transistor is electrically connected to the 2s-th data signal line. The second electrode of the s-th first reset transistor is electrically connected to the data initial signal line. The control electrode of the s-th second reset transistor is electrically connected to the second multiplexed signal line. The first electrode of the s-th second reset transistor is electrically connected to the (2s - 1)-th data signal line. The second electrode of the s-th second reset transistor is electrically connected to the data initial signal line.

5. The display substrate according to claim 3, wherein, The value of z is 3. The multiplexed signal lines include a first multiplexed signal line, a second multiplexed signal line, and a third multiplexed signal line. The multiplexing circuit includes k first multiplexing transistors, k second multiplexing transistors, and k third multiplexing transistors. The reset circuit includes k first reset transistors, k second reset transistors, and k third reset transistors. The s-th multiplexing sub-circuit includes an s-th first multiplexing transistor, an s-th second multiplexing transistor, and an s-th third multiplexing transistor. The control electrode of the s-th first multiplexing transistor is electrically connected to the first multiplexed signal line. The first electrode of the s-th first multiplexing transistor is electrically connected to the (3s - 2)-th data signal line. The second electrode of the s-th first multiplexing transistor is electrically connected to the s-th data output line. The control electrode of the s-th second multiplexing transistor is electrically connected to the second multiplexed signal line. The first electrode of the s-th second multiplexing transistor is electrically connected to the (3s - 1)-th data signal line. The second electrode of the s-th second multiplexing transistor is electrically connected to the s-th data output line. The control electrode of the s-th third multiplexing transistor is electrically connected to the third multiplexed signal line. The first electrode of the s-th third multiplexing transistor is electrically connected to the 3s-th data signal line. The second electrode of the s-th third multiplexing transistor is electrically connected to the s-th data output line. The s-th reset sub-circuit includes an s-th first reset transistor, an s-th second reset transistor, and an s-th third reset transistor. The control electrode of the s-th first reset transistor is electrically connected to the first multiplexed signal line. The first electrode of the s-th first reset transistor is electrically connected to the (3s - 1)-th data signal line. The second electrode of the s-th first reset transistor is electrically connected to the data initial signal line. The control electrode of the s-th second reset transistor is electrically connected to the second multiplexed signal line. The first electrode of the s-th second reset transistor is electrically connected to the 3s-th data signal line. The second electrode of the s-th second reset transistor is electrically connected to the data initial signal line. The control electrode of the s-th third reset transistor is electrically connected to the third multiplexed signal line. The first electrode of the s-th third reset transistor is electrically connected to the (3s - 2)-th data signal line. The second electrode of the s-th third reset transistor is electrically connected to the data initial signal line.

6. The display substrate according to any one of claims 1 to 5, characterized in that, It further includes pixel units arranged in m rows and n columns. Each pixel unit includes a light-emitting element and the pixel driving circuit. The pixel driving circuit is configured to drive the light-emitting element to emit light. The i-th data signal line is located on one side of the pixel units in the i-th column, and the data signal terminals of the pixel driving circuits of the pixel units in the i-th column are electrically connected to the i-th data signal line, 1 i n.

7. The display substrate according to claim 6, wherein It further includes a scan driving circuit, a reset driving circuit, m row scan signal lines, and m row reset signal lines. The pixel driving circuit further includes a reset signal terminal. The scanning driving circuit includes: m scanning shift registers, and the output end of the j-th scanning shift register is connected to the j-th row scanning signal line, 1 ≤ j ≤ m; The reset driving circuit includes: m complex shift registers, and the output terminal of the j-th complex shift register is electrically connected to the reset signal line of the j-th row; For the pixel driving circuit of each pixel unit in the j-th row, the scan signal terminal is electrically connected to the scan signal line of the j-th row, and the reset signal terminal is electrically connected to the reset signal line of the j-th row.

8. The display substrate according to claim 6, characterized in that, The pixel driving circuit includes: a reset sub-circuit, a writing sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a light-emitting sub-circuit; The reset sub-circuit is respectively connected to the initial signal terminal, the reset signal terminal, the first node, and the first pole of the light-emitting element, and is configured to write the initial signal of the initial signal terminal into the first node and the first pole of the light-emitting element under the control of the reset signal terminal; The writing sub-circuit is respectively connected to the scan signal terminal, the data signal terminal, and the third node, and is configured to write the signal of the data signal terminal into the third node under the control of the scan signal terminal; The compensation sub-circuit is respectively connected to the first power supply terminal, the scan signal terminal, the first node, and the second node, and is configured to provide the signal of the second node to the first node under the control of the scan signal terminal until the signal of the first node meets the threshold condition; The driving sub-circuit is respectively connected to the first node, the second node, and the third node, and is configured to provide a driving current to the second node according to the signals of the first node and the third node; The light-emitting sub-circuit is respectively connected to the first power supply terminal, the second node, the third node, the light-emitting signal terminal, and the first pole of the light-emitting element, and is configured to write the signal of the first power supply terminal into the third node and write the signal of the second power supply terminal into the first pole of the light-emitting element under the control of the light-emitting signal terminal; The second pole of the light-emitting element is connected to the second power supply terminal.

9. The display substrate according to claim 8, wherein The reset sub-circuit includes a first transistor and a seventh transistor; The control pole of the first transistor is connected to the reset signal terminal, the first pole of the first transistor is connected to the initial signal terminal, and the second pole of the first transistor is connected to the first node; The control pole of the seventh transistor is connected to the reset signal terminal, the first pole of the seventh transistor is connected to the initial signal terminal, and the second pole of the seventh transistor is connected to the first pole of the light-emitting element.

10. The display substrate according to claim 8, wherein The writing sub-circuit includes a fourth transistor; The control pole of the fourth transistor is connected to the scan signal terminal, the first pole of the fourth transistor is connected to the data signal terminal, and the second pole of the fourth transistor is connected to the third node.

11. The display substrate according to claim 8, wherein The compensation sub-circuit includes a second transistor and a first capacitor; The control pole of the second transistor is connected to the scan signal terminal, the first pole of the second transistor is connected to the first node, and the second pole of the second transistor is connected to the second node; The first end of the first capacitor is connected to the first power supply terminal, and the second end of the first capacitor is connected to the first node.

12. The display substrate according to claim 8, wherein, The driving sub-circuit includes a third transistor; The control pole of the third transistor is connected to the first node, the first pole of the third transistor is connected to the third node, and the second pole of the third transistor is connected to the second node.

13. The display substrate according to claim 8, wherein The light-emitting sub-circuit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected to the light-emitting signal terminal, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the third node; The control electrode of the sixth transistor is connected to the light-emitting signal terminal, the first electrode of the sixth transistor is connected to the second node, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting element.

14. The display substrate according to claim 8, wherein The reset sub-circuit includes a first transistor and a seventh transistor; the writing sub-circuit includes a fourth transistor; the compensation sub-circuit includes a second transistor and a first capacitor; the driving sub-circuit includes a third transistor; the light-emitting sub-circuit includes a fifth transistor and a sixth transistor; The control electrode of the first transistor is connected to the reset signal terminal, the first electrode of the first transistor is connected to the initial signal terminal, and the second electrode of the first transistor is connected to the first node; The control electrode of the seventh transistor is connected to the reset signal terminal, the first electrode of the seventh transistor is connected to the initial signal terminal, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting element; The control electrode of the fourth transistor is connected to the scan signal terminal, the first electrode of the fourth transistor is connected to the data signal terminal, and the second electrode of the fourth transistor is connected to the third node; The control electrode of the second transistor is connected to the scan signal terminal, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the second node; The first end of the first capacitor is connected to the first power supply terminal, and the second end of the first capacitor is connected to the first node; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the second node; The control electrode of the fifth transistor is connected to the light-emitting signal terminal, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the third node; The control electrode of the sixth transistor is connected to the light-emitting signal terminal, the first electrode of the sixth transistor is connected to the second node, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting element.

15. The display substrate according to claim 14, wherein The types of the first transistor to the seventh transistor are P-type transistors or N-type transistors, or the types of the first transistor to the seventh transistor include P-type transistors and N-type transistors.

16. A display device, characterized in that, Comprising the display substrate according to any one of claims 1 to 15.

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