Display device and electronic equipment

Abstract

The application discloses a display device and electronic equipment, and belongs to the technical field of display. The display device comprises a plurality of scanning lines and a plurality of pixels. By arranging a first scanning line and a second scanning line on both sides of a pixel row in a first direction, the first scanning line and / or the second scanning line can be prevented from overlapping the pixel row in the thickness direction of the display device, so that the voltages of the sub-pixel electrodes of two adjacent pixels in the same row can be kept the same.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and electronic equipment. BACKGROUND

[0002] As shown in the prior art display product, a pixel row is driven by two scanning lines, that is, a left pixel in the pixel row is connected with a scanning line GLN-1, and a right pixel in the pixel row is connected with a scanning line GLN. Figure 1

[0003] The left pixel includes a first main pixel electrode MP1, a first sub-pixel electrode SP1, a first main thin film transistor T11, a first sub-thin film transistor T12 and a first shared thin film transistor T13. The right pixel includes a second main pixel electrode MP2, a second sub-pixel electrode SP2, a second main thin film transistor, a second sub-thin film transistor and a second shared thin film transistor. The common electrode line COM is connected with the first shared thin film transistor T13 and the second shared thin film transistor. The data line DL is connected with the first main thin film transistor T11, the first sub-thin film transistor T12, the second main thin film transistor and the second sub-thin film transistor.

[0004] The scanning line GLN extends across the first sub-thin film transistor T12, and the cross-line condition causes a parasitic capacitance Cgs2 between the scanning line GLN and the first sub-pixel electrode SP1.

[0005] As shown in the prior art display product, the scanning line GLN-1 is used for transmitting a scanning signal GN-1, and the scanning line GLN is used for transmitting a scanning signal GN. VSP1 represents the voltage of the first sub-pixel electrode SP1. When the potential of the scanning signal GN is switched from a high potential to a low potential, due to the existence of the parasitic capacitance Cgs2, the voltage of the first sub-pixel electrode SP1 is pulled down twice, resulting in a difference between the voltage of the first sub-pixel electrode SP1 and the voltage of the second sub-pixel electrode SP2. At this time, the brightness of the area where the first sub-pixel electrode SP1 is located is lower than the brightness of the area where the second sub-pixel electrode SP2 is located, causing a display uneven phenomenon. Figure 1 SUMMARY Figure 2 The present application provides a display device and electronic equipment to alleviate the technical problem that the voltages of the sub-pixel electrodes of two adjacent pixels in the same row are different.

[0006] The present application provides a display device and electronic equipment to alleviate the technical problem that the voltages of the sub-pixel electrodes of two adjacent pixels in the same row are different.

[0007] ​​In a first aspect, the present application provides a display device, comprising a plurality of scan lines and a plurality of pixels, the plurality of scan lines comprising at least one group of scan lines, each group of scan lines comprising a first scan line and a second scan line arranged in a first direction in sequence; the plurality of pixels comprising at least one pixel row, each pixel row comprising at least one pixel group, each pixel group comprising a first pixel and a second pixel arranged in a second direction in sequence; wherein the pixel row is located between the first scan line and the second scan line in the first direction, the first scan line is electrically connected to the first pixel of each pixel group in the pixel row, and the second scan line is electrically connected to the second pixel of each pixel group in the pixel row.

[0008] In some embodiments, the first pixel comprises a first main thin film transistor, a first thin film transistor, a first shared thin film transistor, a first main pixel electrode, a first pixel electrode, and a first connection line, one of the source / drain of the first main thin film transistor is connected to the first main pixel electrode, the first pixel electrode is connected to one of the source / drain of the first thin film transistor and one of the source / drain of the first shared thin film transistor; the first main pixel electrode and the first pixel electrode are arranged in the first direction in sequence, the first main thin film transistor is located between the first scan line and the first pixel electrode in the first direction, the first thin film transistor and the first shared thin film transistor are located between the first main pixel electrode and the second scan line in the first direction; the gate of the first main thin film transistor is directly connected to the first scan line; the first scan line is connected to the gate of the first thin film transistor and the gate of the first shared thin film transistor through the first connection line, and the first connection line surrounds the first main pixel electrode.

[0009] In some embodiments, the display device further comprises a data line and a first common electrode line, the data line is located between the first pixel and the second pixel in the second direction, the data line is close to the first main thin film transistor and the first thin film transistor in the second direction, the data line is connected to the other of the source / drain of the first main thin film transistor and the other of the source / drain of the first thin film transistor; the first common electrode line and the data line are arranged in the second direction in sequence and are located on both sides of the first pixel in the second direction respectively, the first common electrode line is close to the first shared thin film transistor in the second direction, and the first common electrode line is connected to the other of the source / drain of the first shared thin film transistor.

[0010] In some embodiments, the first connection line comprises a first wire and a second wire, the first wire is located between the first common electrode line and the first main pixel electrode in the second direction, and the first wire is connected to the first scan line; the second wire is connected to the first wire, the gate of the first thin film transistor, and the gate of the first shared thin film transistor, and the second wire is located between the first main pixel electrode and the first thin film transistor and / or the first shared thin film transistor in the first direction.

[0011] In some embodiments, the second pixel comprises a second main thin film transistor, a second secondary thin film transistor, a second shared thin film transistor, a second main pixel electrode, a second secondary pixel electrode and a second connecting line, one of the source / drain of the second main thin film transistor is connected with the second main pixel electrode, the other of the source / drain of the second main thin film transistor is connected with the data line, the second secondary pixel electrode is connected with one of the source / drain of the second secondary thin film transistor and one of the source / drain of the second shared thin film transistor, the other of the source / drain of the second secondary thin film transistor is connected with the data line; the second secondary pixel electrode and the second main pixel electrode are arranged in the second direction in sequence, the second main thin film transistor is located between the second scan line and the second secondary pixel electrode in the second direction, the second secondary thin film transistor and the second shared thin film transistor are located between the second main pixel electrode and the first scan line in the second direction; the gate of the second main thin film transistor is directly connected with the second scan line; the second scan line is connected with the gate of the second secondary thin film transistor and the gate of the second shared thin film transistor through the second connecting line, and the second connecting line surrounds the second main pixel electrode.

[0012] In some embodiments, the display device further comprises a second common electrode line, the data line and the second common electrode line are arranged in the second direction in sequence and are respectively located on two sides of the second pixel in the second direction, the second common electrode line is close to the second shared thin film transistor in the second direction, and the second common electrode line is connected with the other of the source / drain of the second shared thin film transistor; wherein the data line is close to the second main thin film transistor and the second secondary thin film transistor in the second direction.

[0013] In some embodiments, the second connecting line comprises a first wiring and a second wiring, the first wiring is connected with the second scan line, and the first wiring is located between the second main pixel electrode and the second common electrode line in the second direction; the second wiring is connected with the first wiring, the gate of the second secondary thin film transistor and the gate of the second shared thin film transistor, and the second wiring is located between the second main pixel electrode and the second secondary thin film transistor and / or the second shared thin film transistor in the first direction.

[0014] In some embodiments, the display device further comprises a gate drive circuit and at least one multiplexing circuit, the gate drive circuit is used for outputting at least one scan signal; the input end of the multiplexing circuit is connected with the output end of the gate drive circuit, the first output end of the multiplexing circuit is connected with the first scan line, the second output end of the multiplexing circuit is connected with the second scan line, and the multiplexing circuit is used for outputting the first scan signal and the second scan signal according to a scan signal; wherein the first scan line is used for transmitting the first scan signal, the second scan line is used for transmitting the second scan signal; and the pulse of the first scan signal is earlier than the pulse of the second scan signal in a frame.

[0015] In some embodiments, the multiplexing circuit includes a first transistor and a second transistor, one of the source / drain of the first transistor is connected with an output terminal of the gate driving circuit, the other of the source / drain of the first transistor is connected with the first scan line, the gate of the first transistor is connected with the first control terminal; one of the source / drain of the second transistor is connected with one of the source / drain of the first transistor, the other of the source / drain of the second transistor is connected with the second scan line, the gate of the second transistor is connected with the second control terminal or the first control terminal.

[0016] In a second aspect, the present application provides an electronic device, comprising the display device in any of the above embodiments.

[0017] The display device and the electronic device provided by the present application can avoid the first scan line and / or the second scan line overlapping with the pixel row in the thickness direction of the display device by arranging the first scan line and the second scan line on both sides of the pixel row in the first direction, so that the voltage of the sub-pixel electrode of the first pixel is not affected by the potential change of the scanning signal, i.e., the secondary feed voltage, and the voltage of the sub-pixel electrode of the two adjacent pixels in the same row is kept the same, thereby improving the brightness uniformity of the sub-pixel opening area of the two adjacent pixels in the same row. BRIEF DESCRIPTION OF DRAWINGS

[0018] The technical solutions and other advantages of the present application will be apparent from the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings.

[0019] Figure 1 FIG. 1 is a structural schematic diagram of a display device in the related art.

[0020] Figure 2 FIG. 2 is a voltage change schematic diagram of some signals in the display device shown in FIG. 1. Figure 1

[0021] FIG. 3 is a structural schematic diagram of a display device provided by an embodiment of the present application. Figure 3 DETAILED DESCRIPTION

[0022] The technical solutions and other advantages of the present application will be apparent from the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings.

[0023] ​In view of the technical problem that there is a difference in the voltage of the sub-pixel electrodes of two adjacent pixels in the same row mentioned above, the embodiment provides a display device, as shown in the figure, which comprises a plurality of scan lines and a plurality of pixels. The plurality of scan lines can be arranged in sequence along a first direction DR1, for example, the scan line GLN-1, the scan line GLN, the scan line GLN+1, the scan line GLN+2, and the like arranged in sequence along the first direction DR1. Figure 3

[0024] Among them, the scan line GLN-1 is used to transmit the scan signal GN-1, the scan line GLN is used to transmit the scan signal GN, the scan line GLN+1 is used to transmit the scan signal GN+1, and the scan line GLN+2 is used to transmit the scan signal GN+2.

[0025] In a frame, the pulses of the scan signal GN-1, the pulses of the scan signal GN, the pulses of the scan signal GN+1, and the pulses of the scan signal GN+2, and the like appear in sequence in order, that is, the display device can but not limited to realize line-by-line scanning in a forward scanning manner, and at the same time, scanning in two batches in a pixel row is also carried out in sequence.

[0026] In one embodiment, the plurality of scan lines comprises at least one group of scan lines.

[0027] It should be noted that the embodiment can group the plurality of scan lines, and each group of scan lines is used to drive a pixel row. Compared with driving a pixel row by a single scan line, the load of each scan line can be reduced, and therefore, each scan line in the embodiment can be smaller in width and / or thickness.

[0028] Among them, each group of scan lines comprises a first scan line and a second scan line arranged in sequence along the first direction DR1, for example, the first scan line can be the scan line GLN, and the second scan line can be the scan line GLN+1, that is, the scan line GLN and the scan line GLN+1 used to drive the same pixel row can constitute a group of scan lines, and other groups of scan lines can be deduced in the same way.

[0029] Among them, the plurality of pixels can be arranged in an array in the display device.

[0030] The plurality of pixels comprises at least one pixel row, for example, the pixel row where the first pixel P1 and the second pixel P2 are located, and the like.

[0031] ​Each pixel row includes at least one pixel group, and each pixel group includes a first pixel P1 and a second pixel P2 arranged in sequence along a second direction DR2. That is, one pixel group in the embodiment can include two pixels, and it can be understood that this is the minimum composition of one pixel group. In other embodiments, one pixel group can include three pixels, four pixels, and the like.

[0032] In the embodiment, a pixel row is located between a first scan line GLN and a second scan line GLN+1 in the first direction DR1, the first scan line GLN is electrically connected to the first pixel P1 of each pixel group in the pixel row, and the second scan line GLN+1 is electrically connected to the second pixel P2 of each pixel group in the pixel row.

[0033] It can be understood that the display device provided in the embodiment can avoid the first scan line GLN and / or the second scan line GLN+1 overlapping the pixel row in the thickness direction of the display device by arranging the first scan line GLN and the second scan line GLN+1 on both sides of the pixel row in the first direction DR1, can avoid the first pixel electrode SP1 of the first pixel P1 being affected by the potential change of the scan signal, that is, the secondary feed voltage, and can further keep the voltages of the sub-pixel electrodes of two adjacent pixels in the same row the same, thereby improving the brightness uniformity of the sub-pixel opening area of the two adjacent pixels in the same row.

[0034] In one of the embodiments, the first pixel P1 includes a first main thin film transistor T11, a first sub-thin film transistor T12, a first shared thin film transistor T13, a first main pixel electrode MP1, a first sub-pixel electrode SP1, and a first connection line ZL1. One of the source / drain electrodes of the first main thin film transistor T11 is connected to the first main pixel electrode MP1, and the first sub-pixel electrode SP1 is connected to one of the source / drain electrodes of the first sub-thin film transistor T12 and one of the source / drain electrodes of the first shared thin film transistor T13.

[0035] The first main pixel electrode MP1 and the first sub-pixel electrode SP1 are arranged in sequence along the first direction DR1, the first main thin film transistor T11 is located between the first scan line GLN and the first sub-pixel electrode SP1 in the first direction DR1, and the first sub-thin film transistor T12 and the first shared thin film transistor T13 are located between the first main pixel electrode MP1 and the second scan line in the first direction DR1.

[0036] It should be noted that the embodiment can reasonably arrange the positions of the first main thin film transistor T11, the first sub-thin film transistor T12, and the first shared thin film transistor T13 in the first pixel P1, which not only reduces the connection paths therebetween, but also maximally reduces the coupling phenomenon caused by the intersection between the connection paths.

[0037] The gate of the first main thin film transistor T11 is directly connected with the first scan line GLN; the first scan line GLN is connected with the gate of the first thin film transistor T12 and the gate of the first shared thin film transistor T13 through the first connecting line ZL1, and the first connecting line ZL1 surrounds the first main pixel electrode MP1.

[0038] It should be noted that the gate of the first main thin film transistor T11 can be integrally formed with the first scan line GLN to reduce the preparation process; similarly, the first scan line GLN, the first connecting line ZL1, the gate of the first thin film transistor T12 and the gate of the first shared thin film transistor T13 can also be integrally formed or constructed in the same film layer to reduce the preparation process. The first connecting line ZL1 surrounds the first main pixel electrode MP1 can avoid the first connecting line ZL1 and the first main pixel electrode MP1 overlap in the thickness direction of the display device to generate the corresponding parasitic capacitance. Wherein, the thickness direction can be perpendicular to the first direction DR1 and / or the second direction DR2.

[0039] In one of the embodiments, the display device further comprises a data line DL and a first common electrode line COM1, the data line DL is located between the first pixel P1 and the second pixel P2 in the second direction DR2, the data line DL is close to the first main thin film transistor T11 and the first thin film transistor T12 in the second direction DR2, and the data line DL is connected with the other one of the source / drain of the first main thin film transistor T11 and the other one of the source / drain of the first thin film transistor T12.

[0040] Wherein, the data line DL is used for transmitting a data signal DATA.

[0041] It can be understood that reasonably setting the positional relationship among the data line DL, the first main thin film transistor T11 and the first thin film transistor T12 can maximize the reduction of the connection path among them and reduce the transmission loss.

[0042] The first common electrode line COM1 and the data line DL are arranged in the second direction DR2 in sequence and are respectively located on both sides of the first pixel P1 in the second direction DR2, the first common electrode line COM1 is close to the first shared thin film transistor T13 in the second direction DR2, and the first common electrode line COM1 is connected with the other one of the source / drain of the first shared thin film transistor T13.

[0043] It can be understood that reasonably setting the position of the first common electrode line COM1 can reduce the connection path of the first common electrode line COM1 to the other one of the source / drain of the first shared thin film transistor T13 and reduce the transmission loss.

[0044] In one of the embodiments, the first connection line ZL1 includes a first trace ZL11 and a second trace ZL12, the first trace ZL11 is located between the first common electrode line COM1 and the first main pixel electrode MP1 in the second direction DR2, and the first trace ZL11 is connected with the first scan line; the second trace ZL12 is connected with the first trace ZL11, the gate of the first thin film transistor T12, and the gate of the first shared thin film transistor T13, and the second trace ZL12 is located between the first main pixel electrode MP1 and the first thin film transistor T12 and / or the first shared thin film transistor T13 in the first direction DR1.

[0045] It should be noted that the specific trace path of the first connection line ZL1 is arranged in this way to avoid overlapping or crossing with other metal traces or electrodes, so as to reduce the mutual coupling or parasitic capacitance.

[0046] In one of the embodiments, the second pixel P2 includes a second main thin film transistor T21, a second secondary thin film transistor T22, a second shared thin film transistor T23, a second main pixel electrode MP2, a second secondary pixel electrode SP2, and a second connection line ZL2, one of the source / drain electrodes of the second main thin film transistor T21 is connected with the second main pixel electrode MP2, the other of the source / drain electrodes of the second main thin film transistor T21 is connected with the data line DL, the second secondary pixel electrode SP2 is connected with one of the source / drain electrodes of the second secondary thin film transistor T22 and one of the source / drain electrodes of the second shared thin film transistor T23, and the other of the source / drain electrodes of the second secondary thin film transistor T22 is connected with the data line DL.

[0047] The second secondary pixel electrode SP2 and the second main pixel electrode MP2 are arranged in sequence in the second direction DR2, the second main thin film transistor T21 is located between the second scan line and the second secondary pixel electrode SP2 in the second direction DR2, and the second secondary thin film transistor T22 and the second shared thin film transistor T23 are located between the second main pixel electrode MP2 and the first scan line in the second direction DR2.

[0048] It should be noted that the embodiments can reasonably arrange the positions of the second main thin film transistor T21, the second secondary thin film transistor T22, and the second shared thin film transistor T23 in the second pixel P2, not only reducing the connection paths therebetween, but also minimizing the coupling phenomenon caused by the crossing of the connection paths.

[0049] The gate of the second main thin film transistor T21 is directly connected with the second scan line GLN+1; the second scan line GLN+1 is connected with the gate of the second secondary thin film transistor T22 and the gate of the second shared thin film transistor T23 through the second connecting line ZL2, and the second connecting line ZL2 surrounds the second main pixel electrode MP2.

[0050] It should be noted that the gate of the second main thin film transistor T21 can be integrally formed with the second scan line GLN+1 to reduce the preparation process; similarly, the second scan line GLN+1, the second connecting line ZL2, the gate of the second secondary thin film transistor T22 and the gate of the second shared thin film transistor T23 can also be integrally formed or constructed in the same film layer to reduce the preparation process. The second connecting line ZL2 surrounds the second main pixel electrode MP2 can avoid the second connecting line ZL2 and the second main pixel electrode MP2 overlap in the thickness direction of the display device to generate the corresponding parasitic capacitance.

[0051] In one of the embodiments, the display device further comprises a second common electrode line COM2, the data line DL and the second common electrode line COM2 are arranged in the second direction DR2 in sequence and are respectively located on two sides of the second pixel P2 in the second direction DR2, the second common electrode line COM2 is close to the second shared thin film transistor T23 in the second direction DR2, and the second common electrode line COM2 is connected with the other of the source / drain of the second shared thin film transistor T23; wherein the data line DL is close to the second main thin film transistor T21 and the second secondary thin film transistor T22 in the second direction DR2.

[0052] It should be noted that the present embodiment can reasonably arrange the positions of the second main thin film transistor T21, the second secondary thin film transistor T22 and the second shared thin film transistor T23 in the second pixel P2 to realize that the first pixel P1 and the second pixel P2 share the same data line DL.

[0053] In one of the embodiments, the second connecting line ZL2 comprises a first wiring ZL21 and a second wiring ZL22, the first wiring ZL21 is connected with the second scan line GLN+1, and the first wiring ZL21 is located between the second main pixel electrode MP2 and the second common electrode line COM2 in the second direction DR2; the second wiring ZL22 is connected with the first wiring ZL21, the gate of the second secondary thin film transistor T22 and the gate of the second shared thin film transistor T23, and the second wiring ZL22 is located between the second main pixel electrode MP2 and the second secondary thin film transistor T22 and / or the second shared thin film transistor T23 in the first direction DR1.

[0054] It should be noted that the specific routing path of the second connection line ZL2 can avoid overlapping or crossing with other metal routing lines or electrodes, so as to reduce the mutual coupling or parasitic capacitance.

[0055] In one of the embodiments, the display device further comprises a gate driving circuit 20 for outputting at least one scanning signal, and at least one multiplexing circuit 10, an input end of the multiplexing circuit 10 is connected with an output end of the gate driving circuit 20, a first output end of the multiplexing circuit 10 is connected with the first scanning line GLN, and a second output end of the multiplexing circuit 10 is connected with the second scanning line GLN+1, for outputting the first scanning signal and the second scanning signal according to a scanning signal; wherein the first scanning line GLN is used for transmitting the first scanning signal, the second scanning line GLN+1 is used for transmitting the second scanning signal, and the pulse of the first scanning signal is earlier than the pulse of the second scanning signal in a frame.

[0056] It should be noted that the embodiment can multiplex one scanning signal into the first scanning signal and the second scanning signal, so as to reduce the number of scanning signals output by the gate driving circuit 20, and further to reduce the structure of the gate driving circuit 20 and / or the frame space. When the gate driving circuit 20 comprises a plurality of gate driving chips, the number of gate driving chips used can also be reduced.

[0057] In one of the embodiments, the multiplexing circuit 10 comprises a first transistor MT1 and a second transistor MT2, one of the source / drain of the first transistor MT1 is connected with an output end of the gate driving circuit 20, the other of the source / drain of the first transistor MT1 is connected with the first scanning line GLN, the gate of the first transistor MT1 is connected with the first control end, one of the source / drain of the second transistor MT2 is connected with one of the source / drain of the first transistor MT1, the other of the source / drain of the second transistor MT2 is connected with the second scanning line GLN+1, and the gate of the second transistor MT2 is connected with the second control end or the first control end.

[0058] It should be noted that when the gate of the first transistor MT1 and the gate of the second transistor MT2 are both connected with the first control end, the channel type of the first transistor MT1 is different from the channel type of the second transistor MT2, for example, the channel type of the first transistor MT1 is one of N channel or P channel, and the channel type of the second transistor MT2 is the other of N channel or P channel, so as to ensure that the first transistor MT1 and the second transistor MT2 are opened or turned on at different times, and avoid the error that the same data line DL simultaneously charges two pixels in a pixel row.

[0059] The channel type of the first transistor MT1 and the channel type of the second transistor MT2 can be the same when the gate of the first transistor MT1 is connected with the first control end and the gate of the second transistor MT2 is connected with the second control end, for example, the channel type of the first transistor MT1 and the channel type of the second transistor MT2 can both be one of N channel or P channel, and the first transistor MT1 and the second transistor MT2 are respectively controlled by different control ends and can be opened or turned on at different times to avoid errors caused by the same data line DL charging two pixels in a pixel row at the same time.

[0060] The first control end is configured to provide a first control signal MUX1, and the second control end is configured to provide a second control signal MUX2.

[0061] In one of the embodiments, the present embodiment provides an electronic device including the display device in at least one of the embodiments, wherein the first scan line in one of the scan line groups and the second scan line in another of the scan line groups are arranged on both sides of the pixel row in the first direction DR1.

[0062] It can be understood that the electronic device provided in the present embodiment can avoid the first scan line and / or the second scan line overlapping the pixel row in the thickness direction of the display device by arranging the first scan line and the second scan line on both sides of the pixel row in the first direction DR1, and can avoid the sub-pixel electrode of the first pixel P1 being affected by the potential change of the scan signal, i.e., the secondary feed voltage, and thus can keep the voltages of the sub-pixel electrodes of two adjacent pixels in the same row the same, and improve the brightness uniformity of the sub-pixel opening area of the two adjacent pixels in the same row.

[0063] The area where the pixel electrode is located can correspond to a pixel opening area, for example, the area where the sub-pixel electrode is located is a sub-pixel opening area, and the area where the main pixel electrode is located is a main pixel opening area.

[0064] It should be noted that the present embodiment can arrange each scan line between different pixels without crossing or passing through the pixels, and thus each pixel can maintain the brightness uniformity without being adversely affected by the secondary feed voltage.

[0065] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0066] The display device and the electronic equipment provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and the modification or replacement does not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized in that, include: Multiple scan lines, wherein the multiple scan lines include at least one group of scan lines, and each group of scan lines includes a first scan line and a second scan line arranged sequentially along a first direction; and Multiple pixels, the multiple pixels including at least one pixel row, each pixel row including at least one pixel group, each pixel group including a first pixel and a second pixel arranged sequentially along a second direction; In this configuration, a pixel row is located between the first scan line and the second scan line in the first direction. The first scan line is electrically connected to the first pixel of each pixel group in the pixel row, and the second scan line is electrically connected to the second pixel of each pixel group in the pixel row. The first pixel includes a first main thin-film transistor, a first thin-film transistor, a first shared thin-film transistor, a first main pixel electrode, a first pixel electrode, and a first connecting line. One of the source / drain of the first main thin-film transistor is connected to the first main pixel electrode, and the first pixel electrode is connected to one of the source / drain of the first thin-film transistor and one of the source / drain of the first shared thin-film transistor. The first main pixel electrode and the first pixel electrode are arranged sequentially along the first direction. The first main thin film transistor is located between the first scan line and the first pixel electrode in the first direction. The first thin film transistor and the first shared thin film transistor are located between the first main pixel electrode and the second scan line in the first direction. The gate of the first main thin-film transistor is directly connected to the first scan line; the first scan line is connected to the gate of the first thin-film transistor and the gate of the first shared thin-film transistor through the first connecting line, and the first connecting line surrounds the first main pixel electrode.

2. The display device according to claim 1, characterized in that, The display device further includes: A data line, the data line being located between the first pixel and the second pixel in the second direction, the data line being close to the first main thin-film transistor and the first thin-film transistor in the second direction, the data line being connected to the other of the source / drain of the first main thin-film transistor and the other of the source / drain of the first thin-film transistor; and The first common electrode line and the data line are arranged sequentially along the second direction and are respectively located on both sides of the first pixel in the second direction. The first common electrode line is close to the first shared thin film transistor in the second direction, and the first common electrode line is connected to the other of the source / drain of the first shared thin film transistor.

3. The display device according to claim 2, characterized in that, The first connecting line includes: A first trace, located in the second direction between the first common electrode line and the first main pixel electrode, is connected to the first scan line; and The second trace is connected to the first trace, the gate of the first thin-film transistor, and the gate of the first shared thin-film transistor. The second trace is located in the first direction between the first main pixel electrode and the first thin-film transistor and / or the first shared thin-film transistor.

4. The display device according to claim 3, characterized in that, The second pixel includes a second main thin-film transistor, a second thin-film transistor, a second shared thin-film transistor, a second main pixel electrode, a second pixel electrode, and a second connecting line. One of the source / drain electrodes of the second main thin-film transistor is connected to the second main pixel electrode, and the other of the source / drain electrodes of the second main thin-film transistor is connected to the data line. The second pixel electrode is connected to one of the source / drain electrodes of the second thin-film transistor and one of the source / drain electrodes of the second shared thin-film transistor. The other of the source / drain electrodes of the second thin-film transistor is connected to the data line. The second pixel electrode and the second main pixel electrode are arranged sequentially along the second direction. The second main thin-film transistor is located between the second scan line and the second pixel electrode in the second direction. The second thin-film transistor and the second shared thin-film transistor are located between the second main pixel electrode and the first scan line in the second direction. The gate of the second main thin-film transistor is directly connected to the second scan line; the second scan line is connected to the gate of the second thin-film transistor and the gate of the second shared thin-film transistor through the second connecting line, and the second connecting line surrounds the second main pixel electrode.

5. The display device according to claim 4, characterized in that, The display device further includes a second common electrode line. The data line and the second common electrode line are arranged sequentially along the second direction and are respectively located on both sides of the second pixel in the second direction. The second common electrode line is close to the second shared thin film transistor in the second direction. The second common electrode line is connected to the other of the source / drain of the second shared thin film transistor. The data line is located close to the second main thin-film transistor and the second thin-film transistor in the second direction.

6. The display device according to claim 5, characterized in that, The second connecting line includes: A first wiring, the first wiring being connected to the second scan line, the first wiring being located in the second direction between the second main pixel electrode and the second common electrode line; and The second wiring is connected to the first wiring, the gate of the second thin-film transistor, and the gate of the second shared thin-film transistor. The second wiring is located in the first direction between the second main pixel electrode and the second thin-film transistor and / or the second shared thin-film transistor.

7. The display device according to any one of claims 1 to 6, characterized in that, The display device further includes: Gate drive circuit for outputting at least one scan signal; and At least one multiplexing circuit, wherein the input terminal of the multiplexing circuit is connected to an output terminal of the gate driving circuit, the first output terminal of the multiplexing circuit is connected to the first scan line, and the second output terminal of the multiplexing circuit is connected to the second scan line, for outputting a first scan signal and a second scan signal according to a scan signal; Wherein, the first scan line is used to transmit the first scan signal, and the second scan line is used to transmit the second scan signal; and in a frame, the pulse of the first scan signal is earlier than the pulse of the second scan signal.

8. The display device according to claim 7, characterized in that, The multiplexing circuit includes: A first transistor, one of its source / drain terminals connected to an output terminal of the gate driving circuit, the other of its source / drain terminal connected to the first scan line, and the gate of the first transistor connected to a first control terminal; and The second transistor has one of its source / drain terminals connected to one of the source / drain terminals of the first transistor, the other of its source / drain terminal connected to the second scan line, and its gate connected to either the second control terminal or the first control terminal.

9. An electronic device, characterized in that, The display device includes any one of claims 1 to 8, wherein a first scan line in a scan line group and a second scan line in another scan line group are disposed between two adjacent pixel rows.

Images