High flatness sampling display system based on arbitrary amplitude fir filter and correction method
By adopting a high-flatness sampling correction method based on arbitrary amplitude FIR filters, the flatness problem of analog-to-digital converters in high-bandwidth signals is solved, achieving low flatness and high signal-to-noise ratio for high-bandwidth signals, thus improving the signal processing performance of radar and communication systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN XIRUI INTELLIGENT ELECTRICAL TECH CO LTD
- Filing Date
- 2022-07-18
- Publication Date
- 2026-07-07
AI Technical Summary
In high-bandwidth signal sampling, the in-band flatness of analog-to-digital converters is difficult to guarantee, affecting the signal processing performance of radar and communication systems. In particular, flatness problems caused by mismatches in circuit technology, component performance, and connections are difficult to solve in high-bandwidth signals.
A high-flatness sampling correction method based on an arbitrary amplitude FIR filter is adopted. By windowing, discrete Fourier transform, spectral peak detection and flatness error calculation, an arbitrary amplitude FIR filter is designed. Data correction is implemented using an FPGA chip, and data is transmitted to a host computer for real-time analysis through fiber optic interface and PCIe module.
It achieves low flatness of high-bandwidth signals, improves the signal-to-noise ratio, significantly improves the signal processing effect of radar and communication systems, increases the data sampling correction rate and reduces flatness, and is suitable for signal spectrum analysis of radar and communication equipment.
Smart Images
Figure CN115189674B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital signal processing technology, and specifically relates to a high flatness sampling and display system and correction method based on an arbitrary amplitude FIR filter. Background Technology
[0002] With the rapid development of digital signal processing technology and the increasingly demanding requirements of data processing systems, the requirements for analog-to-digital converters (ADCs) in terms of high processing speed and high sampling accuracy are becoming increasingly stringent. In-band flatness has long been used as an important indicator of linear distortion in the transmission link. However, in high-bandwidth (greater than 1 GHz) signal sampling, it is difficult to guarantee bandwidth flatness. This is due to factors such as circuit fabrication, the performance of electronic components, and impedance mismatches between various devices; and also to the quality of the signal generator. In the radar field, for radar receivers, flatness affects the pulse compression output waveform and signal-to-noise ratio, thus impacting the processing effects of moving target display, moving target detection, and radar imaging in subsequent signal processing. In the communications field, with the increasing bandwidth of 5G and the under-development 6G communication technologies, the quality of flatness directly affects the quality of call and image transmission.
[0003] When process conditions cannot meet the requirement of achieving high flatness at high bandwidth data frequencies, back-end flatness correction of analog-to-digital converter sampling data is of positive significance. Summary of the Invention
[0004] To address the shortcomings of the aforementioned technologies, this invention proposes a high-flatness sampling and display system and a correction method based on an arbitrary amplitude FIR filter.
[0005] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:
[0006] A high-flatness sampling correction method based on an arbitrary amplitude FIR filter includes the following implementation steps:
[0007] Step 1: Send the original signal into the analog-to-digital converter (ADC) to convert the analog signal into a digital signal, thereby achieving data sampling;
[0008] Step 2: Perform windowing, discrete Fourier transform, peak detection, and flatness error calculation on the collected data. Fit the peak values of 51 point frequency signals in the frequency range of 500MHz-1500MHz into an amplitude-frequency response curve. Take the inverse Fourier transform of the fitted curve to obtain the coefficients of the arbitrary amplitude filter.
[0009] Step 3: Convolve the filter coefficients generated in Step 2 with the original data sampled by the ADC in MATLAB. After performing a Discrete Fourier Transform on the convolution result, the theoretical performance value of the FIR filter with arbitrary amplitude can be obtained.
[0010] Step 4: Design an FIR filter in the FPGA chip based on the filter coefficients generated in Step 2. Considering the limited resources of the DSP48 in the FPGA, the original acquired data needs to be buffered in a FIFO, and the transmission clock needs to be doubled. The parallel 40 data streams are reduced to 20 parallel data streams, thus halving the resource usage of the DSP48. Acquiring the 20 parallel data streams output by the filter yields the actual effect value of the FIR filter with any amplitude.
[0011] Step 5: Verify the effect of the filter coefficients. Compare the theoretical effect value of the arbitrary amplitude FIR filter obtained in Step 3 with the actual effect value of the arbitrary amplitude FIR filter obtained in Step 4. After eliminating the influence of environmental noise and calculation method, if the effect error is on the order of 10⁻¹, the flatness correction can be considered successful.
[0012] Step 6: After summarizing the 20 data streams output in Step 4, forward them to both the GTX module and the PCIE module. The GTX module sends the data to the fiber optic ports QSFP1-QSFP8; the PCIE module transmits the data to the ARM, and the ARM forwards the data to the host computer via the RJ45 network port for real-time signal spectrum analysis.
[0013] Furthermore, the window addition process in step 2 uses a flat-top window.
[0014] Furthermore, the signal in step 2 is a superposition of point frequency signals with a bandwidth of 1GHz, a center frequency of 1GHz, and a step of 20MHz.
[0015] Furthermore, the fitting method in step 2 is the least squares method.
[0016] The system used in the above-mentioned high flatness sampling correction method based on arbitrary amplitude FIR filters includes an FPGA, an ARM, a clock chip, a crystal oscillator, an ADC, an optical fiber interface (QSFP1-8), an RJ45 network port, a USB interface, a trigger unit, a DDR memory unit, an SD interface, and a host computer. The crystal oscillator is connected to the FPGA, the ARM and DDR memory unit are connected to the FPGA, the QSFP1-8 is connected to the FPGA, the FPGA is connected to the trigger unit and the ADC, the FPGA is connected to the clock chip, the clock chip is connected to the ADC, the RJ45 network port, the USB interface, and the SD interface are respectively connected to the ARM, and the host computer is connected to the RJ45 network port and the USB interface respectively.
[0017] Furthermore, the clocks of the FPGA, ARM, and ADC chips are all from the same source and in phase, and high-speed data transmission and processing between the chips are achieved through fiber optic interfaces (QSFP1-8), RJ45 Ethernet ports, and USB interfaces.
[0018] Compared with the prior art, the advantages of the present invention are:
[0019] 1. The method of this invention utilizes an ADC+FPGA+FIR filter to achieve flatness compensation of the sampled data at the back end. This invention can achieve flatness of less than 0.1dB for digital signals with a bandwidth of 1GHz and a center frequency of 1GHz.
[0020] 2. Because the system employs multi-channel parallel input arbitrary amplitude digital filters to sample and correct high-bandwidth data, the data sampling and correction rate is increased by 20 times, and the flatness is reduced to 0.1 dB, thus achieving low flatness for broadband digital signals at high carrier frequencies. In the radar field, low flatness significantly improves the signal-to-noise ratio of the signal-matched output waveform, enhancing the processing effects of moving target display, moving target detection, and radar imaging. In the communications field, reduced flatness also directly improves the quality of voice calls and image transmission.
[0021] 3. This invention fully considers the design of each module and interface of the sampling system. Through simulation and the construction of an actual hardware platform, a high flatness sampling and display system is completed, which significantly improves the flatness of broadband signals and makes the spectrum analysis of the sampled data visible.
[0022] 4. The method of the present invention has a wide range of applications and can be widely used in sampling and signal spectrum analysis of radar receivers and communication equipment front-ends. Attached Figure Description
[0023] Figure 1 This is a block diagram of a high flatness sampling and display system based on an arbitrary amplitude FIR filter proposed in this invention.
[0024] Figure 2 This is a block diagram of the data acquisition and correction within the FPGA chip in this invention;
[0025] Figure 3 This is a peak spectrum diagram of the uncorrected 1GHz bandwidth signal acquired by the ADC in this invention;
[0026] Figure 4 This is the fitted amplitude-frequency response curve of the filter in this invention;
[0027] Figure 5 This is a flatness magnitude plot of the uncorrected data after filtering (80th order) in MATLAB in this invention.
[0028] Figure 6 This is a flatness amplitude diagram of the uncorrected data after filtering (80th order) in the FPGA chip in this invention;
[0029] Figure 7 This is the host computer display and control interface of the present invention. Detailed Implementation
[0030] The embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.
[0031] See Figure 1 This invention provides a high-flatness sampling and display system based on an arbitrary amplitude FIR filter, comprising an FPGA, an ARM, a clock chip, a crystal oscillator, an ADC, a QSFP1-8 fiber optic interface, an RJ45 network port, a USB interface, a trigger unit (CX1-4), a DDR memory unit, an SD interface, and a host computer. The FPGA is a Virtex7-690T, and the ARM is a CortexA9. The crystal oscillator is connected to the FPGA. The ARM, DDR memory unit, and QSFP1-8 are connected to the FPGA. The FPGA is connected to the trigger unit and the ADC. The FPGA is connected to the clock chip, and the clock chip is connected to the ADC. The RJ45 network port, USB interface, and SD interface are respectively connected to the ARM. The host computer is connected to the RJ45 network port and USB interface. The clocks of the FPGA, ARM, and ADC chips are of the same source and in phase, and high-speed data transmission and processing between the chips are achieved through interfaces such as the fiber optic interface, RJ45 network port, and USB interface.
[0032] The functions of each module in this system are as follows: the FPGA is responsible for digital signal acquisition and processing; the ARM is responsible for data control and transmission; the clock chip provides the operating clock for the ARM and ADC; the crystal oscillator provides the global clock for the FPGA chip; the ADC samples the raw analog signal and sends it to the FPGA; the fiber optic interface composed of QSFP1-8 chips transmits data via fiber optic cable; the RJ45 network port transmits data to the host computer; the USB Host1 interface handles communication between the host computer and the ARM; the trigger unit composed of CX1-4 chips synchronizes the clock signal; the DDR memory unit stores filtered data; and the SD interface starts the system program. Data is sampled by the ADC and sent to the FPGA. After processing by the internal modules of the FPGA, the data is transmitted in two ways: one through the QSFP1-8 fiber optic interface, and the other through the PCIe interface to the ARM. The ARM can transmit data to the host computer via the RJ45 network port, enabling real-time spectrum analysis on the host computer.
[0033] Reference Figure 2This is a block diagram of the data acquisition and correction within the FPGA chip of this invention. The FPGA chip is configured with various modules to complete data acquisition and correction, and to achieve real-time spectrum analysis. The clock module configures the clock chip, generating the sampling clock for the ADC and the operating clock for the ARM. The reset module initializes and resets each module within the FPGA chip. The ADC module configures the ADC and sends the configuration data to the ADC via the SPI interface. The data acquisition module acquires and integrates the ADC sampling data, dividing the acquired data into 20 parallel channels for transmission to the data correction module. The data correction module performs FIR filtering on the data and reassembles it. The integrated data is then transmitted to the PCIe link module and the fiber optic interface module. The PCIe link module transmits the data to the ARM via the PCIe interface. The fiber optic interface module transmits the data to the server via the GTX interface.
[0034] The specific configuration of the system of this invention is as follows:
[0035] (1) Configuring the clocks and resets of each chip and module: The on-board FPGA acts as the main processor, using the 156.25MHz clock generated by the crystal oscillator as the main clock for the FPGA chips. The clock chip is mainly used for the ADC and ARM operating clocks, the GTX reference clock, and the PCIe reference clock. The ADC device clock is set to 1.96608GHz (sampling at both rising and falling edges), and the FPGA reference clock is 196.608MHz. The GTX and PCIe reference clocks are set to 125MHz. An internal reset module is generated within the FPGA to perform power-on initialization for each internal module.
[0036] (2) Configure the ADC module and data acquisition module. The FPGA chip is configured via the Serial Peripheral Interface (SPI) protocol. The register configuration order is as follows:
[0037] 1. Reset register;
[0038] 2. Apply a stable device CLK signal at the required frequency;
[0039] 3. Set JESD_EN=0 to stop the JESD204B state machine and allow settings changes;
[0040] 4. Set CAL_EN=0 to stop the calibration state machine and allow setting changes;
[0041] 5. Set JMODE to 0;
[0042] 6. Set the value of KM1, KM1 = K – 1.
[0043] 7. Configure SYNC_SEL as needed, and select SYNCSE or timestamp differential input;
[0044] 8. Configure device calibration settings as needed. Select foreground or background calibration mode and offset calibration as required;
[0045] 9. Set CAL_EN=1 to enable the calibration state machine;
[0046] 10. Enable the over-limit function via OVR_EN and adjust the settings as needed;
[0047] 11. Set JESD_EN=1 to restart the JESD204B state machine and allow link restarts.
[0048] 12. The JESD204B interface operates in response to synchronization signals from the application of the receiver.
[0049] 13. Set CAL_SOFT_TRIG = 0.
[0050] 14. Set CAL_SOFT_TRIG=1 to start calibration.
[0051] The data acquisition module consists of an Integrated Logic Analysis (ILA) IP core. The module receives data in 8-bit packets, with the first bit of lane0 being the least significant bit. The JESD core receives four 8-bit array packets from each lane at a time, totaling 8*8*4 = 256 bits per packet. Therefore, the FPGA needs to receive two 256-bit packets to complete one full data transmission for the AD converter (40 sampling points across two channels, each sampling point being 12 bits).
[0052] Example: The high flatness sampling correction method based on an arbitrary amplitude FIR filter provided by the present invention includes the following steps:
[0053] Step 1: Send the original signal into the ADC (Analog-to-Digital Converter) to convert the analog signal into a digital signal, thereby achieving data sampling.
[0054] Step 2: After completing Step 1, the data acquisition module sends the uncorrected ADC sampled data to MATLAB software for flatness analysis. The data undergoes windowing (using a flat-top window, which is more accurate for spectral amplitude analysis), Discrete Fourier Transform, peak detection, and flatness error calculation.
[0055] See Figure 3 As can be seen from the blue line in the graph, the spectral peaks of the uncorrected 1GHz bandwidth signal are irregular, with a flatness of 1.73dB. The orange line in the graph represents the reference value, with a flatness of 0dB.
[0056] See Figure 4The peak values of the spectrum at 51 single frequency points are fitted into an amplitude-frequency response curve that minimizes the error. The inverse Fourier transform of the fitted curve is then performed to obtain the coefficients (filter order) of the filter with arbitrary amplitude.
[0057] The principle for calculating filter coefficients is as follows:
[0058] Assume the ideal frequency response function of the ADC sampling system is H idle (jw), the actual frequency response is H real (jw), the frequency response of the compensation filter is H fir (jw), the relationship between the three satisfies:
[0059] H idle (jw)=H real (jw)*H fir (jw)
[0060] The principle of filtering is essentially convolving the ADC sampled data with the filter coefficients. x(n) represents the sampled data, a(n) represents the filter coefficients, and y(n) represents the output after filtering. This embodiment collects signals at 51 frequency points, k = 1, 2...51. A single frequency point is defined as a signal with a bandwidth of 1 GHz, a center frequency of 1 GHz, and a step size of 20 MHz. After performing a Fourier transform on the sampled data and taking the logarithm, the actual peak frequency of the spectrum is obtained as H. real (k) Select the minimum value H among the spectral peaks of 51 frequency points. real (k)| min As a correction reference value, the peak frequency of the ideal data is
[0061] H idel (k)=H real (k)| min
[0062] The peak spectral density of the compensation filter H fir (k)=H idle (k)-H real (k).
[0063] From the inverse Fourier transform formula The filter coefficients can be obtained.
[0064] The higher the selected filter order, the more accurate the flatness-corrected amplitude-frequency response curve fitted by these coefficients, and the better the flatness correction effect. Considering the limited resources of the DSP48 digital signal processing unit on the FPGA, only the 80th order filter coefficients are used for flatness correction in the FPGA.
[0065] Step 3: First, convolve the filter coefficients generated in Step 2 with the original data sampled by the ADC in MATLAB. After performing a Fourier transform on the convolution result, the theoretical performance value of the 80th order arbitrary amplitude FIR filter can be obtained.
[0066] See Figure 5 After processing with an 80th-order floating-point filter, the flatness of the original data decreased from 1.73 dB to 0.23 dB, fluctuating within the range of -0.1187 to 0.1134 dB. The error between the theoretical value obtained from MATLAB correction and the actual data on the board is within 10. -1 Within the order of magnitude, this is because actual testing involves noise and FPGA operations use fixed-point arithmetic, while MATLAB uses floating-point arithmetic, which reduces the performance of on-board testing by 10%. -1 Increasing the filter order to 100 or higher in MATLAB can improve the flatness to within 0.1 dB.
[0067] Step 4: Send the filter coefficients generated in Step 2 into the data correction module in the FPGA chip. In this embodiment, considering the resources of DSP48E, the original acquired data is buffered in FIFO, the parallel 40-channel sampling data transmission link is reduced to a parallel 20-channel data link, and the transmission clock is increased from 98.304MHz to 196.608MHz.
[0068] Step 5: Transmit the 20 parallel data streams output by the filter to the data acquisition module, and compare the filtering in Step 3 with that in Step 4 on the FPGA chip. This embodiment considers the influence of noise in the actual environment and the fact that the FPGA processes data in fixed-point arithmetic while MATLAB uses floating-point arithmetic. If the error is on the order of 10⁻¹, the flatness correction can be considered successful.
[0069] See Figure 6 As can be seen, the flatness after processing by the FPGA's internal correction module is -0.21295 to 0.21713 dB. The result after filtering on the upper board meets the expected value, and the correction effect is obvious.
[0070] Step 6: Configure the fiber optic interface module and PCIe link interface module. Transmit the data from the data correction module in Step 5 to the server and ARM respectively through the fiber optic interface module and PCIe link interface module. The host computer then controls the ARM to forward the data back to the host computer, where real-time signal spectrum analysis is performed. For example... Figure 7 As shown, the host computer reads the data after sampling and filtering from the two ADCs by issuing commands, performs Fourier transform on the data, and displays the amplitude-frequency response curve.
Claims
1. A high-flatness sampling correction method based on an arbitrary amplitude FIR filter, characterized in that, The implementation steps include the following: Step 1: Send the original signal into the analog-to-digital converter (ADC) to convert the analog signal into a digital signal, thereby achieving data sampling; Step 2: Perform windowing, discrete Fourier transform, peak detection, and flatness error calculation on the collected data. Fit the peak values of 51 point frequency signals in the frequency range of 500MHz-1500MHz into an amplitude-frequency response curve. Take the inverse Fourier transform of the fitted curve to obtain the coefficients of the arbitrary amplitude filter. Step 3: Convolve the filter coefficients generated in Step 2 with the original data sampled by the ADC in MATLAB. After performing a Discrete Fourier Transform on the convolution result, the theoretical performance value of the FIR filter with arbitrary amplitude can be obtained. Step 4: Design an FIR filter in the FPGA chip based on the filter coefficients generated in Step 2. Considering the limited resources of the DSP48 in the FPGA, the original acquired data needs to be buffered in a FIFO. At the same time, the transmission clock is doubled, and the parallel 40 data channels are reduced to parallel 20 data channels, thereby halving the resources used by the DSP48. By acquiring the parallel 20 data channels output by the filter, the actual effect value of the FIR filter with arbitrary amplitude can be obtained. Step 5: Verify the effect of the filter coefficients; compare the theoretical effect value of the arbitrary amplitude FIR filter obtained in Step 3 with the actual effect value of the arbitrary amplitude FIR filter obtained in Step 4. After eliminating the influence of environmental noise and calculation method, if the effect error is within 10... -1 If the flatness correction is within the order of magnitude, it can be considered successful. Step 6: After summarizing the 20 data streams output in Step 4, forward them to both the GTX module and the PCIE module. The GTX module will then send the data to the fiber optic ports QSFP1-QSFP8. The PCIe module transmits data to the ARM, which then forwards the data to the host computer via the RJ45 network port, where real-time signal spectrum analysis is performed.
2. The high flatness sampling correction method based on an arbitrary amplitude FIR filter according to claim 1, characterized in that: The window addition process in step 2 uses a flat-top window.
3. The high flatness sampling correction method based on an arbitrary amplitude FIR filter according to claim 1, characterized in that: The signal in step 2 is a superposition of point frequency signals with a bandwidth of 1GHz, a center frequency of 1GHz, and a step of 20MHz.
4. The high flatness sampling correction method based on an arbitrary amplitude FIR filter according to claim 1 or 2, characterized in that: The fitting method in step 2 is the least squares method.
5. The system used in the high flatness sampling correction method based on an arbitrary amplitude FIR filter according to claim 1 includes an FPGA and an ARM, characterized in that: It also includes a clock chip, crystal oscillator, ADC, fiber optic interface (QSFP1-8), RJ45 network port, USB interface, trigger unit, DDR memory unit, SD interface, and host computer. The crystal oscillator is connected to the FPGA, ARM, and DDR memory unit. The QSFP1-8 is connected to the FPGA. The FPGA is connected to the trigger unit and ADC. The FPGA is connected to the clock chip. The clock chip is connected to the ADC. The RJ45 network port, USB interface, and SD interface are respectively connected to the ARM. The host computer is connected to the RJ45 network port and USB interface respectively.
6. The system used in the high flatness sampling correction method based on an arbitrary amplitude FIR filter according to claim 5 is characterized in that: The clocks of the FPGA, ARM, and ADC chips are all from the same source and in phase, and high-speed data transmission and processing between the chips are achieved through fiber optic interfaces (QSFP1-8), RJ45 network ports, and USB interfaces.