Array substrate and display device

Abstract

The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of initialization signal lines and a plurality of connection lines. The initialization signal lines are arranged on a conductive layer, extending along a first direction and arranged at intervals along a second direction, and are used to provide initialization signals to each sub-pixel; the connection lines are arranged on another conductive layer, extending along a second direction and arranged at intervals along the first direction; wherein the projections of at least one initialization signal line and at least one connection line on the base substrate intersect and are connected through vias, so that the projections of the initialization signal lines and the connection lines on the base substrate form a grid-like structure. The present disclosure can improve the problem of excessive IR drop and reduce the pressure on the wiring space.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display technology is recognized by the industry as the third generation display technology for its advantages such as light weight, self-luminescence, wide viewing angle, fast response speed, low brightness and low power consumption. It has been widely used in the field of high-performance displays.

[0003] As the requirements for the PPI (pixel density) of display panels become higher and higher, the wiring pressure on the panel is also increasing. It is necessary to consider both the tight arrangement of various lines and the minimization of the mutual influence between various lines. Therefore, higher requirements are put forward for wiring design.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0005] Public Content

[0006] The purpose of the present disclosure is to provide an array substrate and a display device.

[0007] According to one aspect of the present disclosure, an array substrate is provided, wherein a plurality of pixel units are arranged in an array, wherein the pixel unit includes a plurality of sub-pixels, and the array substrate includes:

[0008] A plurality of initialization signal lines are provided in a conductive layer, extending along a first direction and arranged at intervals along a second direction, and are used to provide initialization signals to each of the sub-pixels; the first direction and the second direction intersect;

[0009] A plurality of connecting lines, provided in another conductive layer, extending along the second direction and arranged at intervals along the first direction;

[0010] The projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate intersect and are connected through vias, so that the projections of the initialization signal lines and the connection lines on the base substrate form a grid structure.

[0011] In an exemplary embodiment of the present disclosure, the array substrate includes a base substrate and a first gate line layer, a second gate line layer, a source and drain layer, and an anode layer stacked in sequence on the base substrate; the first direction is a row direction, and the second direction is a column direction; the initialization signal line is arranged in the second gate layer; the connecting line is arranged in the source and drain layer or the anode layer.

[0012] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0013] A plurality of scanning lines, provided in the first gate line layer, extending along the row direction and arranged at intervals along the column direction, for providing scanning signals to each of the sub-pixels;

[0014] A plurality of reset signal lines are arranged in the first gate line layer, extending along the row direction and arranged at intervals along the column direction, and are used to provide reset signals to each of the sub-pixels.

[0015] In an exemplary embodiment of the present disclosure, in the sub-pixel area, the projection of the initialization signal line on the base substrate is located between the projection of the reset signal line and the scanning line of the previous level sub-pixel, and the projections of the initialization signal line, the reset signal line and the scanning line do not overlap.

[0016] In an exemplary embodiment of the present disclosure, in the sub-pixel area, the projection of the initialization signal line on the substrate is located on the side of the projection of the reset signal line away from the scanning line of the previous level sub-pixel, and the projections of the initialization signal line, the reset signal line and the scanning line do not overlap.

[0017] In an exemplary embodiment of the present disclosure, in the sub-pixel area, the reset signal line and the scan line of the previous level sub-pixel are connected as a whole; the projection of the initialization signal line on the base substrate intersects with the projection of the reset signal line.

[0018] In an exemplary embodiment of the present disclosure, the initialization signal line includes a plurality of signal segments separated from each other, each of the signal segments corresponding to each of the pixel units; wherein each of the signal segments has no overlap with the projection of the reset signal line in at least one of the sub-pixel regions within the corresponding pixel unit, and intersects with the projection of the reset signal line in the remaining sub-pixel regions.

[0019] In an exemplary embodiment of the present disclosure, the number of the connecting lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal line is electrically connected to each of the connecting lines through a via in each sub-pixel region; or, the number of the connecting lines is less than the number of sub-pixels in the row direction, and in the row direction, the initialization signal line is electrically connected to each of the connecting lines through a via in a part of the sub-pixel region.

[0020] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0021] A plurality of power lines, provided in the source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, for providing power signals to each of the sub-pixels;

[0022] A plurality of data lines are arranged in the source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, and are used to provide data signals to each of the sub-pixels.

[0023] In an exemplary embodiment of the present disclosure, the sub-pixel includes an anode, the connection line and the anode are both provided in the anode layer, and the connection line is insulated from the anode.

[0024] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of first conductive connection portions, which are provided in the source-drain electrode layer and distributed in the sub-pixel region where the projection of the initialization signal line and the connection line intersect;

[0025] In the sub-pixel area where the first conductive connection part is distributed, the projection of the first conductive connection part on the base substrate has overlapping areas with the initialization signal line and the connection line respectively, the first conductive connection part is connected to the initialization signal line through a via hole, and the first conductive connection part is connected to the connection line through a via hole.

[0026] In an exemplary embodiment of the present disclosure, the connecting line is arranged in the source and drain layer; in the sub-pixel area, the initialization signal line includes a main section and an extension section that are connected to each other, the main section of the initialization signal line extends along the row direction, and the extension section of the initialization signal line is different from the extension direction of the main section; wherein the projection of the extension section of the initialization signal line on the substrate overlaps with the projection of the connecting line, and the extension section of the initialization signal line and the connecting line are connected through a via in the overlapping area.

[0027] In an exemplary embodiment of the present disclosure, the array substrate also includes a plurality of light-emitting control signal lines, which are provided in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used to provide light-emitting control signals to each of the sub-pixels; in the sub-pixel area, the light-emitting control signal line is located on a side of the reset signal line away from the scanning line of the previous level sub-pixel, and does not overlap with the projection of the initialization signal line.

[0028] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of power leads, which are arranged in the second gate line layer, extend along the row direction and are arranged at intervals along the column direction, and each of the power leads in the same row is connected to one of the power leads through a via.

[0029] In an exemplary embodiment of the present disclosure, the sub-pixel further includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes:

[0030] A capacitor, comprising a first electrode plate and a second electrode plate, wherein the first electrode plate is arranged on the first gate line layer, and the second electrode plate is arranged on the second gate line layer;

[0031] A driving transistor, wherein the first plate of the capacitor is multiplexed as a gate of the driving transistor, and the first stage of the driving transistor is connected to the power line;

[0032] a first transistor, wherein a gate of the first transistor is connected to the scan line, a first stage of the first transistor is connected to the data line, and a second stage of the first transistor is connected to a second plate of the capacitor;

[0033] A second transistor, a gate of the second transistor is connected to the scan line, a first stage of the second transistor is connected to the second stage of the driving transistor, and a second stage of the first transistor is connected to the first plate of the capacitor.

[0034] A fourth transistor, wherein a gate of the fourth transistor is connected to the reset signal line, a first stage of the fourth transistor is electrically connected to the initialization signal line, and a second stage of the fourth transistor is electrically connected to the first plate of the capacitor.

[0035] A fifth transistor, wherein a gate of the fifth transistor is connected to the reset signal line, a first stage of the fifth transistor is electrically connected to the initialization signal line, and a second stage of the fifth transistor is electrically connected to the second plate of the capacitor.

[0036] A sixth transistor, wherein a gate of the sixth transistor is connected to the light emitting control signal line, a first stage of the sixth transistor is electrically connected to the initialization signal line, and a second stage of the sixth transistor is electrically connected to the second plate of the capacitor.

[0037] A seventh transistor, wherein a gate of the seventh transistor is connected to the light emitting control signal line, a first level of the seventh transistor is electrically connected to a second level of the driving transistor, and a second level of the seventh transistor is electrically connected to an anode of the sub-pixel.

[0038] An eighth transistor, wherein a gate of the eighth transistor is connected to the reset signal line, a first stage of the eighth transistor is electrically connected to the initialization signal line, and a second stage of the eighth transistor is electrically connected to the anode of the sub-pixel.

[0039] A ninth transistor, wherein a gate of the ninth transistor is connected to the light emitting control signal line, and a first stage of the ninth transistor is electrically connected to a first plate of the capacitor.

[0040] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0041] A plurality of second conductive connection portions, disposed in the source-drain electrode layer and distributed in each of the sub-pixel regions;

[0042] A plurality of third conductive connection portions, disposed in the source-drain electrode layer and distributed in each of the sub-pixel regions;

[0043] In the sub-pixel area, the second conductive connection portion is respectively connected to the second level of the first transistor, the second level of the fifth transistor, the second level of the sixth transistor and the second plate of the capacitor through vias, and the second level of the first transistor, the second level of the fifth transistor and the second level of the sixth transistor are all electrically connected to the second plate of the capacitor through the second conductive connection portion.

[0044] In the sub-pixel area, the third conductive connection portion is respectively connected to the second level of the fourth transistor, the first level of the ninth transistor and the first plate of the capacitor through vias, and the second level of the fourth transistor and the first level of the ninth transistor are both electrically connected to the first plate of the capacitor through the third conductive connection portion.

[0045] In an exemplary embodiment of the present disclosure, the array substrate further includes a plurality of fifth conductive connection portions, which are disposed in the source-drain electrode layer and distributed in each of the sub-pixel regions;

[0046] The fifth conductive connection portion is connected to the first level of the fifth transistor through a via, and the fifth conductive connection portion is also connected to the initialization signal line through another via, so that the first level of the fifth transistor is connected to the initialization signal line; the connection line is arranged in the source and drain layer, and the connection line is connected to the fifth conductive connection portion, so as to be connected to the initialization signal line through the fifth conductive connection portion.

[0047] According to another aspect of the present disclosure, a display device is provided, comprising the array substrate described above.

[0048] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0050] Figure 1 A schematic diagram of the positional relationship between the initialization signal line and the connection line in one implementation manner;

[0051] Figure 2 It is a schematic diagram of a 9T1C sub-pixel circuit structure;

[0052] Figure 3 for Figure 2 A timing diagram of the sub-pixel circuit structure shown;

[0053] Figure 4 It is a structural schematic diagram of the arrangement of multiple sub-pixel arrays in the first embodiment;

[0054] Figure 5 for Figure 4 The film layer stacking structure of a sub-pixel in FIG.

[0055] Figure 6 for Figure 5 Schematic diagram of the structure of the active layer;

[0056] Figure 7 for Figure 5 Schematic diagram of the film stacking of the active layer and the first gate line layer;

[0057] Figure 8 for Figure 5 Schematic diagram of film stacking of active layer, first gate line layer and second gate line layer;

[0058] Fig. 9 for Figure 5 Schematic diagram of the stacking of active layer, first gate line layer, second gate line layer, source and drain electrode layer;

[0059] Fig.10 for Figure 5 A schematic diagram of the structure of the first gate line layer;

[0060] Fig.11 for Figure 5 A schematic diagram of the structure of the second gate line layer;

[0061] Fig.12 for Figure 5 Schematic diagram of the structure of the middle source and drain layer;

[0062] Fig.13 is a schematic diagram of the structure of an anode layer;

[0063] Fig.14 for Fig.12 Sectional view along the AA direction;

[0064] Fig.15 is a schematic structural diagram of an arrangement of multiple sub-pixel arrays in a second implementation manner;

[0065] Fig.16 This is a schematic diagram of the position relationship between the initialization signal line and the connection line in the second implementation mode;

[0066] Fig.17 A perspective view of a stack of an anode layer and a second gate line layer according to a second embodiment;

[0067] Fig.18 A schematic diagram of the structure of a plurality of sub-pixel array arrangements in a third embodiment;

[0068] Fig.19 for Fig.18 The film layer stacking structure of a sub-pixel in FIG.

[0069] Fig. 20 for Fig.19 A schematic diagram of the structure of the first gate line layer;

[0070] Fig.21 for Fig.19 Schematic diagram of film stacking of active layer, first gate line layer and second gate line layer;

[0071] Fig. 22 for Fig.19 Schematic diagram of the stacking of active layer, first gate line layer, second gate line layer, source and drain electrode layer;

[0072] Fig.23 for Fig.19 A schematic diagram of the structure of the first gate line layer;

[0073] Fig.24 for Fig.19 A schematic diagram of the structure of the second gate line layer;

[0074] Fig.25 for Fig.19 Schematic diagram of the structure of the middle source and drain layer;

[0075] Fig.26 for Fig.25 Cross-section along the middle BB direction;

[0076] Fig. 27 It is a schematic structural diagram of the arrangement of multiple sub-pixel arrays in the fourth implementation manner;

[0077] Fig.28 for Fig. 27 The film layer stacking structure of a sub-pixel in FIG.

[0078] Fig.29 for Fig. 27 Schematic diagram of the active layer and the first gate line layer film stacking;

[0079] Fig.30 for Fig. 27 Schematic diagram of the stacking of active layer, first gate line layer, second gate line layer, source and drain electrode layer;

[0080] Fig.31 for Fig. 27 A schematic diagram of the structure of the second gate line layer;

[0081] Fig.32 for Fig. 27 Schematic diagram of the structure of the middle source and drain layer;

[0082] Fig.33 for Fig.32 Cross-sectional view along CC direction.

[0083] In the figure: active layer 100, active layer; 200, first gate insulating layer; 300, first gate line layer; 400, second gate insulating layer; 500, second gate line layer; 500', second gate line layer; 600, dielectric layer; 700, source and drain electrode layer; 700', source and drain electrode layer; 800, passivation layer; 900, anode layer;

[0084] 31. Scan line; 32. Reset signal line; 33. Light-emitting control signal line; 51. Initialization signal line; 510. Signal segment; 511. Main segment; 512. Extension segment; 52. Power lead; 71. Data line; 72. Power line; 73. First conductive connection part; 74. Second conductive connection part; 75. Third conductive connection part; 76. Fourth conductive connection part; 77. Fifth conductive connection part; 80. Via hole; 91. Anode; 10. Connecting line. DETAILED DESCRIPTION

[0085] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0086] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0087] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0088] In an embodiment of the present disclosure, an array substrate is provided. Figure 1 , the array substrate is arrayed with a plurality of pixel units along the row direction and the column direction, and the pixel unit includes a plurality of sub-pixels. The array substrate includes a plurality of initialization signal lines 51 and a plurality of connection lines 10. Taking the first direction in the figure as the row direction and the second direction as the column direction as an example, a plurality of initialization signal lines 51 are arranged on a conductive layer, extending along the row direction and arranged at intervals along the column direction, and each initialization signal line 51 is used to provide an initialization signal to each sub-pixel located in the same row in the row direction. A plurality of connection lines 10 are arranged on another conductive layer, extending along the column direction and arranged at intervals along the row direction. Among them, at least one initialization signal line 51 and at least one connection line 10 intersect with each other on the substrate and are connected through vias, so that the projections of the initialization signal line 51 and the connection line 10 on the substrate intersect to form a grid structure.

[0089] The horizontal initialization signal lines 51 are connected into a grid structure through the vertical connection lines 10, which increases the paths of the initialization signal. The initialization signal can be transmitted to each sub-pixel through more paths, thereby reducing the problem of excessive IR drop caused by a single current transmission path. Compared with wiring in one layer, the entire grid structure is divided into two layers of wiring, which can reduce the wiring space pressure, reduce the initialization signal from being susceptible to the jump of other signals (such as scanning signals) due to the tight single-layer wiring, reduce the impact on the luminous performance, and improve the display uniformity of the panel.

[0090] It should be noted that the horizontal arrangement of the initialization signal line 51 means that the main structure of the initialization signal line 51 extends in the horizontal direction. In actual products, there may be parts that are not completely horizontally arranged, such as turning to avoid other circuit structures, or extending in other directions to facilitate connection with other lines, etc., as long as the overall direction of the initialization signal line 51 is in the horizontal direction. Similarly, the longitudinal arrangement of the connection line 10 means that the main structure of the connection line 10 extends in the longitudinal direction, and the overall direction is in the longitudinal direction.

[0091] The array substrate of this embodiment is described in detail below:

[0092] In this implementation, each pixel unit is composed of four sub-pixels of RGBG, and each sub-pixel is driven by a separate sub-pixel driving circuit.

[0093] Figure 2 A 9T1C sub-pixel circuit structure is shown, which includes a capacitor and nine TFT transistors T1 to T9. In this embodiment, all TFTs are P-type TFTs, wherein the third transistor T3 is a driving transistor, and the other transistors are switch transistors.

[0094] refer to Figure 2 , the capacitor includes a first plate Cst1 and a second plate Cst2, the first plate Cst1 is arranged on the first gate line layer 300, and the second plate Cst2 is arranged on the second gate line layer 500. The first plate Cst1 is connected to the node N2, and the second plate Cst2 is connected to the node N1. The gate 3g of the driving transistor T3 (the third transistor) is reused by the first plate Cst1 of the capacitor, and the source 3s is connected to the power line 72; the gate 1g of the first transistor T1 is connected to the scan line 31, the source 1s is connected to the data line 71, and the drain 1d is connected to the node N1. The gate 2g of the second transistor T2 is connected to the scan line 31, the source 2s is connected to the drain 3d of the driving transistor T3, and the drain 2d is connected to the node N2. The gate 4g of the fourth transistor T4 is connected to the reset signal line 32, the source 4s is electrically connected to the initialization signal line 51, and the drain 4d is connected to the node N2. The gate 5g of the fifth transistor T5 is connected to the reset signal line 32, the source 5s is electrically connected to the initialization signal line 51, and the drain 5d is connected to the node N1. The gate 6g of the sixth transistor T6 is connected to the light emission control signal line 33, the source 6s is electrically connected to the initialization signal line 51, and the drain 6d is connected to the node N1. The gate 7g of the seventh transistor T7 is connected to the light emission control signal line 33, the source 7s is electrically connected to the drain 3d of the driving transistor T3, and the drain 7d is electrically connected to the anode 91 of the sub-pixel. The gate 8g of the eighth transistor T8 is connected to the reset signal line 32, the source 8s is electrically connected to the initialization signal line 51, and the drain 8d is electrically connected to the anode 91 of the sub-pixel. The gate 9g of the ninth transistor T9 is connected to the light emission control signal line 33, and the source 9s is connected to the node N2.

[0095] Among them, the initialization signal provided by the initialization signal line 51 is Vint, the reset signal provided by the reset signal line 32 is Reset, the light control signal provided by the light control signal line 33 is EM, the scanning signal provided by the scanning line 31 is gate, the data signal provided by the data line 71 is data, and the power signal provided by the power line 72 is ELVDD.

[0096] refer to Figure 3 As shown in the timing diagram, the specific working principle of the sub-pixel compensation circuit is as follows:

[0097] In the first stage, the reset signal Reset is at a low level. The fourth transistor T4 is turned on, and the initial signal Vint initializes the N2 point. At this time, the potential of the N2 point is the initial signal Vint. The fifth transistor T5 is turned on, and the initial signal Vint is written to the N1 point. The eighth transistor T8 is turned on to release the residual charge displayed in the previous frame. The initial signal Vint is written to reduce the voltage difference between the anode and cathode of the OLED device, reduce the brightness of the OLED device at low grayscale, and improve the contrast of the pixel.

[0098] In the second stage, the signal Gate of the scanning line 31 is at a low level. The first transistor T1 is turned on, and the potential of the N1 point is Vdata, and the data signal voltage is written into the N1 point. The second transistor T2 is turned on, and the diode connection of the driving transistor T3 is sampled. The potential of the N2 point rises to ELVDD+Vth, and the driving transistor T3 gradually changes from the on state to the off state, and the threshold voltage Vth of the driving transistor T3 is compensated.

[0099] In the third stage, the light-emitting control signal EM is at a low level. The sixth transistor T6 is turned on, and the potential of the N1 point is the initial signal Vint. The ninth transistor T9 is turned on, and the leakage of the N2 point is reduced during the light-emitting stage. As the potential of the N1 point jumps, the potential of the N2 point becomes ELVDD+Vth+Vint-Vdata. The seventh transistor T7 is turned on, the driving current is output, and the OLED device emits light. The current calculation formula of the OLED device is:

[0100]

[0101] Through the above circuit, the threshold voltage Vth of the driving transistor T3 can be compensated in the sampling stage, thereby eliminating the influence of the difference in DTFT threshold voltage Vth of different pixels on the uniformity of display brightness.

[0102] In this embodiment, Vint can be used as an initialization signal or as a reference signal when writing data.

[0103] In this embodiment, the sub-pixel driving circuit of each sub-pixel is prepared on a substrate. The substrate is stacked with an active layer 100, a first gate line layer 300, a second gate line layer 500, and a source-drain electrode layer 700. These film layers are used to form various signal lines or wires to provide corresponding electrical signals to each sub-pixel driving circuit. The two film layers are insulated by an insulating layer. For example, a first gate insulating layer 200 is arranged between the active layer 100 and the first gate layer 300, a second gate insulating layer 400 is arranged between the first gate line layer 300 and the second gate line layer 500, a dielectric layer 600 is arranged between the second gate line layer 500 and the source-drain electrode layer 700, and a passivation layer 800 and other film layers are further arranged above the source-drain electrode layer 700. The anode layer 900, organic light-emitting layer, cathode layer and other film layers of the sub-pixel are arranged above the passivation layer 800 to form an OLED light-emitting device, and the OLED light-emitting device of each sub-pixel is spaced by a pixel defining layer.

[0104] Figure 4 A schematic diagram of a structure of a plurality of sub-pixel arrays arranged in one embodiment is shown. Figure 5 It is a stacked structure of a sub-pixel driving circuit and various signal lines of a sub-pixel on an array substrate. Figure 6-Figure 9 The schematic diagram of the film layer stacking of the active layer 100, the first gate line layer 300, the second gate line layer 500, and the source and drain electrode layer 700 is shown. Figure 10-12 The schematic diagram of the structure of each layer of the first gate line layer 300 , the second gate line layer 500 , and the source and drain electrode layer 700 is shown.

[0105] refer to Figure 6 The active layer 100 is used to set the channel region (1g-9g), the first level (1s-9s) and the second level (1d-9d) of each TFT transistor.

[0106] refer to Figure 7 and Fig.10The first gate line layer 300 is used to set the gates (such as 1g to 9g) of each transistor in the sub-pixel driving circuit, the first electrode Cst1 of the capacitor, and multiple scan lines 31, multiple reset signal lines 32, multiple light-emitting control signal lines 33 and other structures. Multiple scan lines 31 are arranged at intervals along the column direction and extend along the row direction, and are used to provide scan signals to each sub-pixel located in the same row in the row direction. Multiple reset signal lines 32 are arranged at intervals along the column direction and extend along the row direction, and are used to provide reset signals to each sub-pixel located in the same row in the row direction. Multiple light-emitting control signal lines 33 extend along the row direction and are arranged at intervals along the column direction, and are used to provide light-emitting control signals to each sub-pixel located in the same row in the row direction. Among them, in each sub-pixel area, the reset signal line 32 is located at the top, the scan line 31 is located at the bottom, the light-emitting control signal line 33 is located between the reset signal line 32 and the scan line 31, and the first electrode Cst1 of the capacitor is located between the light-emitting control signal line 33 and the scan line 31. In the column direction, the reset signal line 32 of the next level sub-pixel can be connected to the scan line 31 of the previous level sub-pixel, so that the scan signal of the previous level sub-pixel can be used as the reset signal of the next level sub-pixel, thereby avoiding the introduction of a dedicated signal line for the reset signal and effectively reducing the wiring space.

[0107] refer to Figure 8 and Fig.11 , the second gate line layer 500 is used to set structures such as the second plate Cst2 of the capacitor, and in this embodiment, the initialization signal line 51 is also set in the second gate line layer 500. Among them, the second plate Cst2 of the capacitor corresponds to the first plate Cst1 in the thickness direction of the array substrate, and the projection of the initialization signal line 51 on the array substrate is located on the side of the projection of the second plate Cst2 close to the projection of the reset signal line 32. In this embodiment, the projections of the initialization signal line 51 and the reset signal line 32 on the base substrate overlap, which greatly saves wiring space.

[0108] refer to Fig. 9 and Fig.12 The source-drain electrode layer 700 is used to set a longitudinal power line 72, a data line 71 and other structures. The power line 72 extends along the column direction and is arranged at intervals along the row direction, and is used to provide a power signal to each sub-pixel located in the same column. The data line 71 extends along the column direction and is arranged at intervals along the row direction, and is used to provide a data line 71 signal to each sub-pixel located in the same column. Among them, the projections of the power line 72 and the data line 71 on the array substrate do not overlap with the first plate Cst1 and the second plate Cst2 of the capacitor.

[0109] refer to Figure 8 and Fig.11In one embodiment, the second gate line layer 500 further includes a plurality of power leads 52, which extend in the row direction and are arranged at intervals in the column direction. Each power line 72 in the same row is connected to a power lead 52 through a via provided in the dielectric layer 600, thereby forming a grid structure with the power leads 52 and the power lines 72, which can reduce the voltage drop of the power supply voltage.

[0110] refer to Fig. 9 and Fig.12 In one embodiment, the source-drain electrode layer 700 further includes a plurality of second conductive connection portions 74, each of which is disposed in the source-drain electrode layer 700 and distributed in each sub-pixel region. In each sub-pixel region, the projection of the second conductive connection portion 74 on the substrate overlaps with the projection of the drain 1d of the first transistor T1, the drain 5d of the fifth transistor T5, and the drain 6d of the sixth transistor T6, and is connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the dielectric layer 600. The projection of the second conductive connection portion 74 on the substrate also overlaps with the projection of the second electrode plate Cst2 of the capacitor, and is electrically connected through a via hole penetrating the dielectric layer 600. That is, 1d, 5d, and 6d are all electrically connected to the second electrode plate Cst2 of the capacitor through the second conductive connection portion 74.

[0111] refer to Fig. 9 and Fig.12 In one embodiment, the source-drain electrode layer 700 further includes a plurality of third conductive connection portions 75, each of which is disposed in the source-drain electrode layer 700 and distributed in each sub-pixel region. In each sub-pixel region, the projection of the third conductive connection portion 75 on the substrate overlaps with the projection of 2d of the second transistor T2 and the projection of the first stage 9s of the ninth transistor T9, and is connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the dielectric layer 600. The projection of the third conductive connection portion 75 on the substrate also overlaps with the projection of the first electrode plate Cst1 of the capacitor, and is electrically connected through a via hole penetrating the second gate insulating layer 400 and the dielectric layer 600. That is, 2d and 9s are both electrically connected to the first electrode plate Cst1 of the capacitor through the third conductive connection portion 75.

[0112] refer to Fig. 9 and Fig.12 In one embodiment, the source-drain electrode layer 700 further includes a plurality of fourth conductive connection portions 76, each of which is disposed in the source-drain electrode layer 700 and distributed in each sub-pixel region. In each sub-pixel region, the projection of the fourth conductive connection portion 76 on the substrate overlaps with 8d of the eighth transistor T8, and is electrically connected through a via hole penetrating the first gate insulating layer 200, the second gate insulating layer 400, and the dielectric layer 600, that is, 8d is electrically connected to the anode 91 through the fourth conductive connection portion 76.

[0113] refer to Fig. 9 and Fig.12 In one embodiment, the source-drain electrode layer 700 further includes a plurality of fifth conductive connection portions 77, each of which is disposed in the source-drain electrode layer 700 and distributed in each sub-pixel region, and is used to connect the source electrodes of T4, T5, T6, and T8 and the initialization signal line 51. Specifically, the fifth conductive connection portion 77 is connected to the source electrode 5s of the fifth transistor T5 of the active layer 100 through a via hole penetrating the first gate insulation layer 200, the second gate insulation layer 400, and the dielectric layer 600, and the fifth conductive connection portion 77 is also connected to the initialization signal line 51 of the second gate layer through another via hole penetrating the dielectric layer 600, so that the source electrode 5s of the fifth transistor T5 is electrically connected to the initialization signal line 51. At the same time, referring to Figure 4 Since the source 5s of the fifth transistor T5 and the source 6s of the sixth transistor T6 are commonly connected to the source 8s of the eighth transistor T8 and the source 4s of the fourth transistor T4 in the sub-pixel on the right side in the row direction, the sources of T4, T5, T6, and T8 are all connected to the initialization signal line 51, thereby simplifying the number of vias.

[0114] An OLED light-emitting device is also provided on the array substrate. A pixel definition layer is provided above the source and drain electrode layer 700. The pixel definition layer has a plurality of openings for defining each sub-pixel. The anode layer 900 is used to provide an anode 91 of the OLED light-emitting device, which is located in the opening of the pixel definition layer. Furthermore, an organic light-emitting layer and a cathode layer are also provided in the opening. The film layer structure of the OLED light-emitting device can adopt a conventional structure, which will not be described in detail here. Fig.13 , which is a schematic diagram of the structure of an anode layer 900 of an RGBG pixel structure.

[0115] In this embodiment, reference Fig.13 The connection line 10 is provided in the anode layer 900, passes through the gap between two anodes 91 in the longitudinal direction, and is insulated from any anode 91. The connection line 10 is covered by the pixel definition layer to avoid contact with other film layers above.

[0116] It should be noted that since the connecting line 10 is formed in the anode layer 900 by etching the anode 91 material (such as ITO / Ag / ITO), and the anode 91 material is usually etched by wet etching, it is more difficult to etch for panels with a higher PPI. Therefore, it is necessary to avoid having too many connecting lines 10 in the horizontal direction as much as possible, and ensure that the overall wiring is along the vertical direction. If a grid-like closed pattern is formed in the anode layer 900, poor etching is likely to occur.

[0117] In this embodiment, the number of connection lines 10 is less than the number of sub-pixels in the row direction, that is, in the row direction, the initialization signal line 51 is electrically connected to each connection line 10 in a part of the sub-pixel region through a via hole. Figure 1 and Figure 4 , the number of connection lines 10 is half the number of sub-pixels in the row direction, and one connection line is provided for each sub-pixel, then for each sub-pixel, the initialization signal line 51 is connected to a connection line 10 through a via. Therefore, one of every two adjacent sub-pixels in the row direction is provided with a connection line 10 and a via, while the other is not. In other embodiments, when the number of connection lines 10 is less than the number of sub-pixels in the row direction, different numbers of sub-pixels may be spaced between two adjacent connection lines 10.

[0118] In other embodiments, reference Fig. 27 , the number of connecting lines 10 and the number of sub-pixels in the row direction may also be equal. That is to say, in the row direction, the initialization signal line 51 is electrically connected to each connecting line 10 in each sub-pixel area through a via. Therefore, each sub-pixel in the row direction is provided with a connecting line 10 and a via. As long as the projections of the plurality of connecting lines 10 and the plurality of initialization signal lines 51 on the substrate can form a grid-like structure. It is understandable that the more connecting lines 10 there are, the denser the grid, the more transmission paths for the initialization signal, the more the IR drop can be reduced, but the spatial pressure of the wiring will also be greater, and the difficulty of the preparation process will also be greater. Therefore, the specific number can be set according to actual conditions.

[0119] In order to realize the connection between the initialization signal line 51 and the connection line 10, refer to Fig. 9 and Fig.12 The array substrate further includes a plurality of first conductive connection portions 73 disposed on the source-drain electrode layer 700, and the plurality of first conductive connection portions 73 are distributed in the sub-pixel region where the projection of the initialization signal line 51 and the connection line 10 intersects. Fig. 9 (a) shows a stacked structure where the projection of the initialization signal line 51 intersects with the connection line 10, Fig. 9 (b) shows a stacked structure in which the initialization signal line 51 does not intersect the projection of the connection line 10. In other words, the source-drain layer 700 of not all sub-pixels is provided with the first conductive connection part 73, but the initialization signal line 51 is provided in the sub-pixel where the connection line 10 is connected. Fig.12700 indicates a source-drain electrode layer structure provided with a first conductive connection portion 73, and 700' indicates a source-drain electrode layer structure not provided with the first conductive connection portion 73. In the sub-pixel region provided with the first conductive connection portion 73, the projection of the first conductive connection portion 73 on the substrate has overlapping regions with the initialization signal line 51 and the connection line 10, respectively. The first conductive connection portion 73 is connected to the initialization signal line 51 through a via penetrating the dielectric layer 600, and the first conductive connection portion 73 is connected to the connection line 10 through a via penetrating the passivation layer 800, thereby making the initialization signal line 51 and the connection line 10 electrically connected through the first conductive connection portion 73.

[0120] In this embodiment, Fig.12 As shown, the first conductive connection part 73 and the fifth conductive connection part 77 are connected as a whole, which simplifies the preparation of the conductive connection part of the source-drain layer 700. Since the first conductive connection part 73 and the fifth conductive connection part 77 are connected as a whole, the projection of the first conductive connection part 73 on the substrate substrate has an overlapping area with the initialization signal line 51, and it can also be understood that the projection of the fifth conductive connection part 77 on the substrate substrate has an overlapping area with the initialization signal line 51, and both can realize the connection between the fifth conductive connection part 77 and the initialization signal line 51. Correspondingly, the first conductive connection part 73 is connected to the connection line 10 through a via, and it can also be understood that the fifth conductive connection part 77 is connected to the connection line 10 through a via. The shape in which the first conductive connection part 73 and the fifth conductive connection part 77 are connected as a whole includes but is not limited to Fig.12 L-shape shown. Fig.14 A cross-sectional view of the first conductive connection portion 73 and the fifth conductive connection portion 77 is shown. Fig.12 The cross-sectional view along the AA direction shows that when setting the vias, the multiple vias are staggered in the thickness direction.

[0121] Figure 4 In the illustrated embodiment, the reset signal line 32 is connected to the previous level scan line 31, the initialization signal line 51 overlaps with the reset signal line 32, and the connecting line 10 is wired in the anode layer 900, which greatly saves wiring space and is suitable for panels with higher PPI, such as panels with a PPI greater than 410.

[0122] In another specific embodiment, in order to minimize the impact of cross static electricity generated by the overlap of the initialization signal line 51 and the reset signal line 32 on the panel, Figure 1 , Figure 5 The structure has been improved, refer to Fig.15 and Fig.16The initialization signal line 51 is no longer a whole continuous signal line, but includes a plurality of mutually separated signal segments 510, that is, the initialization signal line 51 is divided into a plurality of small segments in the horizontal direction, each signal segment 510 corresponds to each pixel unit one by one, and each signal segment 510 has no overlap with the projection of the reset signal line 32 in at least one sub-pixel area in the corresponding pixel unit, and intersects with the projection of the reset signal line 32 in the remaining sub-pixel areas.

[0123] For example, Fig.15 As shown, each signal segment 510 spans across a pixel unit, and within a pixel unit, the signal segment 510 overlaps with the projection of the reset signal line 32 in three sub-pixel regions, but does not overlap with the projection of the reset signal line 32 in the sub-pixel region at one end, and ends at one side of the reset signal line 32. In this way, the probability of cross static electricity generated within the pixel unit can be reduced, and the cross static electricity within one pixel unit will not affect other pixel units.

[0124] It should be noted that even if the initialization signal line 51 is divided into a plurality of signal segments 510, each longitudinal connection line 10 is connected to a signal segment 510, so it can be considered that each initialization signal line 51 is connected to each connection line 10. In addition, although the horizontal initialization signal line 51 of this embodiment is disconnected, it is still crossed with the longitudinal connection line, so it is also regarded as a grid structure. That is to say, the grid structure described in the present disclosure includes Figure 1 The complete grid structure shown also includes Fig.16 The grid structure is shown as a disconnected grid in the middle. Fig.17 It is a perspective view showing the connection line 10 provided in the anode layer 900 and the initialization signal line 51 provided in the second gate layer.

[0125] Fig.18 FIG. 4 shows a schematic diagram of a structure in which multiple sub-pixel arrays are arranged in another embodiment. Fig.19 It is a stacked structure of a sub-pixel driving circuit and various signal lines of a sub-pixel on an array substrate. Figure 20-Figure 22 Schematic diagram of the film layer stacking of the first gate line layer 300, the second gate line layer 500, and the source and drain electrode layer 700 is shown. Figure 23-Figure 25 The schematic diagram of the structure of each layer of the first gate line layer 300, the second gate line layer 500, and the source and drain electrode layer 700 is shown. Figure 6 The structures are the same, so the related drawings are omitted here. In this embodiment, the connecting wire 10 is also provided in the anode layer 900. Fig. 22 (a) shows a stacked structure where the projection of the initialization signal line 51 intersects with the connection line 10, Fig. 22 (b) shows a stacked structure in which the initialization signal line 51 does not intersect with the projection of the connection line 10 . Fig.25In the figure, 700 indicates a source-drain electrode layer structure provided with a first conductive connection portion 73 , and 700 ′ indicates a source-drain electrode layer structure not provided with the first conductive connection portion 73 .

[0126] refer to Fig. 20 and Fig.21 , in a sub-pixel area, the projection of the initialization signal line 51 on the substrate is located between the projection of the reset signal line 32 of the sub-pixel at this level and the projection of the scan line 31 of the sub-pixel at the previous level, and the projections of the initialization signal line 51, the reset signal line 32 of the sub-pixel at this level, and the scan line 31 of the sub-pixel at the previous level do not overlap. In other words, the projections of the initialization signal line 51, the reset signal line 32 of the sub-pixel at this level, and the scan line 31 of the sub-pixel at the previous level are spaced apart from each other. The reset signal line 32 of the sub-pixel at the next level and the scan line 31 of the sub-pixel at the previous level can be connected in the peripheral area of ​​the array substrate so that the scan signal of the sub-pixel in the previous row is input into the reset signal line 32 of the sub-pixel in the next row in the peripheral area. This structure can avoid the generation of cross static electricity between the initialization signal line 51 and the reset signal line 32 and the scan line 31, and can also avoid the initialization signal being susceptible to the influence of the scan signal jump due to the initialization signal line 51 being too close to the scan line 31. Under this structure, compared Figure 5 As shown in the structure, the wiring method of this embodiment will occupy a larger area, and therefore is suitable for panels with a slightly lower PPI, such as a panel with a PPI less than 4.10.

[0127] In this embodiment, the wiring arrangement of the source-drain layer 700 is the same as that of the previous embodiment, that is, it includes the first to fifth conductive connection parts. And similarly, in this embodiment, the connection line 10 is provided in the anode layer 900, and the connection line 10 is connected to the initialization signal line 51 through the fifth conductive connection part 77. The shape in which the first conductive connection part 73 and the fifth conductive connection part 77 are connected as one body includes but is not limited to Fig.25 The T-shaped first conductive connection portion 73 and the fifth conductive connection portion 77 are in Fig.25 The cross-section along the BB direction is shown in Fig.26 As shown, when the via holes are arranged, the plurality of via holes are staggered with respect to each other in the thickness direction.

[0128] Fig. 27 FIG. 4 shows a schematic diagram of a structure in which multiple sub-pixel arrays are arranged in another embodiment. Fig.28 It is a stacked structure of a sub-pixel driving circuit and various signal lines of a sub-pixel on an array substrate. Figure 29-Figure 30 Schematic diagram of the film layer stacking of the second gate line layer 500 and the source and drain electrode layer 700 is shown. Figure 31-Figure 32 The structure of each layer of the second gate line layer 500 and the source and drain electrode layer 700 is shown in FIG. Figure 6 , Figure 7The structures are the same, so the related drawings are omitted here.

[0129] refer to Fig.29 and Fig.31 , different from the previous embodiment, the initialization signal line 51 also includes a main section 511 and an extension section 512. The main section 511 of the initialization signal line 51 extends along the row direction, and its projection on the substrate is located on the side of the reset signal line 32 away from the previous level scanning line 31, and is located on the side of the power lead 52 close to the previous level sub-pixel. The extension section 512 of the initialization signal line 51 bypasses the reset signal line 32 and extends between the reset signal line 32 and the previous level scanning line 31. This structure can avoid the generation of cross static electricity between the initialization signal line 51 and the reset signal line 32 and the scanning line 31, and is also convenient for connection with the connecting line 10.

[0130] refer to Fig.30 and Fig.32 , which is different from the previous embodiment, is that the connection line 10 is provided in the source-drain electrode layer 700. As shown in the figure, in the sub-pixel region, the connection line 10 is located on the side of the power line 72 away from the data line 71, for example, it can be located on the side of the second conductive connection part 74 and the third conductive connection part 75 away from the power line 72. The connection line 10 extends along the column direction as a whole, and a part of it is bent to the right to avoid the fourth conductive connection part 76. Since the connection line 10 does not need to be connected to the anode layer 900, the first conductive connection part 73 is not included. For details, refer to Fig.33 The cross-sectional view of the connecting line 10 and the fifth conductive connecting portion 77 is shown in FIG. Fig.32 In the cross-sectional view taken along the CC direction, the connection line 10 can be connected to the fifth conductive connection part 77 as a whole, and connected to the initialization signal line 51 through the fifth conductive connection part. In this way, other line structures can be avoided, cross-layer connection can be achieved, and the connection structure can be simplified. Figure 5 and Fig.17 In the structure shown, wiring on the source and drain layer 700 will occupy a large area, so it is suitable for panels with lower PPI, such as panels with PPI less than 385. However, since the source and drain layer 700 is dry-etched, compared with the anode layer 900 using wet etching, the risk of defects when etching the anode 91 material can be reduced. Moreover, the source and drain layer 700 material has lower resistance than the anode layer 900 material, which is conducive to improving IR drop.

[0131] In this embodiment, the wiring arrangement of other lines of the source and drain layer 700 is the same as that of the previous embodiment. Figure 5 and Fig.17Another difference of the structure shown is that the number of connecting lines 10 is equal to the number of sub-pixels in the row direction, that is, each sub-pixel has an initialization signal line 51 and a connecting line 10 intersecting and connected through a via, that is, the internal structure of all sub-pixels is the same.

[0132] The above embodiments give a variety of setting positions and connection methods of the initialization signal lines and connecting lines of the present disclosure. The various structures of the present disclosure can take into account the requirements of PPI and performance of different products while reasonably wiring. It can be understood that the setting positions and connection methods of the initialization signal lines and connecting lines can be arbitrarily combined to adapt to the requirements of PPI, process feasibility and display performance of the display panel. In addition, the above embodiments are described with the pixel circuit structure of 9T1C as an example. When the array substrate adopts other pixel circuit structures, the initialization signal lines and connecting lines can also be layered and connected in a grid shape, which can also reduce IR drop and relieve wiring pressure. In addition, each of the above pixel units is composed of four RGBG sub-pixels, and only one algorithm is used as an example for arrangement. The structure of the initialization signal lines and connecting lines layered and connected in a grid shape disclosed in the present disclosure can also be applied to RGBG pixel structures arranged by other algorithms. Further, when the pixel unit adopts other settings, such as RGB, RGBW, etc., the initialization signal lines and connecting lines can also be layered and connected in a grid shape, which can also reduce IR drop and relieve wiring pressure.

[0133] The embodiment of the present disclosure further provides a display device, which includes the array substrate of the above embodiment. Since the display device includes the above array substrate, it has the same beneficial effects, and the present disclosure will not repeat them here.

[0134] The present disclosure does not impose any specific restrictions on the applicability of display devices, which can be any product or component with flexible display function, such as televisions, laptops, tablet computers, wearable display devices, mobile phones, car displays, navigation, e-books, digital photo frames, advertising light boxes, etc.

[0135] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein a plurality of pixel units are arranged in an array, wherein the pixel unit comprises a plurality of sub-pixels, wherein: The array substrate comprises: A plurality of initialization signal lines are provided on a conductive layer on the base substrate, extending along a first direction and arranged at intervals along a second direction, and are used to provide initialization signals to each of the sub-pixels; the first direction and the second direction intersect; A plurality of connecting lines, provided on another conductive layer on the base substrate, extending along the second direction and arranged at intervals along the first direction; The projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate intersect and are connected through vias, so that the projections of the initialization signal lines and the connection lines on the base substrate form a grid structure; The array substrate comprises a base substrate and a first gate line layer, a second gate line layer, a source-drain electrode layer, and an anode layer which are sequentially stacked on the base substrate; the first direction is a row direction, and the second direction is a column direction; The initialization signal line is arranged on the second gate layer; The connecting line is arranged on the source-drain layer or the anode layer; The array substrate further includes: A plurality of scanning lines, provided in the first gate line layer, extending along the row direction and arranged at intervals along the column direction, for providing scanning signals to each of the sub-pixels; A plurality of reset signal lines are provided in the first gate line layer, extending along the row direction and arranged at intervals along the column direction, and are used to provide a reset signal to each of the sub-pixels; In the sub-pixel region, the reset signal line and the scan line of the previous sub-pixel are connected as one; The projection of the initialization signal line on the base substrate intersects with the projection of the reset signal line; The initialization signal line includes a plurality of signal segments separated from each other, and each of the signal segments corresponds to each of the pixel units one by one; Each of the signal segments has no overlap with the projection of the reset signal line in at least one of the sub-pixel regions in the corresponding pixel unit, and intersects with the projection of the reset signal line in the remaining sub-pixel regions.

2. The array substrate according to claim 1, wherein: In the sub-pixel region, the projection of the initialization signal line on the base substrate is located between the projection of the reset signal line and the scanning line of the previous sub-pixel, and the projections of the initialization signal line, the reset signal line and the scanning line do not overlap.

3. The array substrate according to claim 1, wherein: In the sub-pixel area, the projection of the initialization signal line on the substrate is located on the side of the projection of the reset signal line away from the scanning line of the previous sub-pixel, and the projections of the initialization signal line, the reset signal line and the scanning line do not overlap.

4. The array substrate according to any one of claims 1 to 3, wherein: The number of the connection lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal line and each of the connection lines are electrically connected through a via hole in each sub-pixel region; Alternatively, the number of the connection lines is less than the number of sub-pixels in the row direction, and in the row direction, the initialization signal line is electrically connected to each of the connection lines in a partial sub-pixel region through a via hole.

5. The array substrate according to claim 4, wherein: The array substrate further includes: A plurality of power lines, provided in the source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, for providing power signals to each of the sub-pixels; A plurality of data lines are arranged in the source-drain electrode layer, extending along the column direction and arranged at intervals along the row direction, and are used to provide data signals to each of the sub-pixels.

6. The array substrate according to claim 5, wherein: The sub-pixel includes an anode, the connection line and the anode are both arranged in the anode layer, and the connection line is insulated from the anode.

7. The array substrate according to claim 6, wherein: The array substrate further includes: A plurality of first conductive connection parts are provided in the source-drain electrode layer and distributed in the sub-pixel region where the projections of the initialization signal line and the connection line intersect; In the sub-pixel area where the first conductive connection part is distributed, the projection of the first conductive connection part on the base substrate has overlapping areas with the initialization signal line and the connection line respectively, the first conductive connection part is connected to the initialization signal line through a via hole, and the first conductive connection part is connected to the connection line through a via hole.

8. The array substrate according to claim 7, wherein: The connecting line is arranged on the source-drain layer; In the sub-pixel region, the initialization signal line comprises a main section and an extension section connected to each other, the main section of the initialization signal line extends along the row direction, and the extension section of the initialization signal line extends in a different direction from the main section; The projection of the extended section of the initialization signal line on the base substrate overlaps with the projection of the connection line, and the extended section of the initialization signal line and the connection line are connected through a via in the overlapping area.

9. The array substrate according to claim 5, wherein: The array substrate further includes: A plurality of light-emitting control signal lines are provided in the first gate line layer, extending along the row direction and arranged at intervals along the column direction, and are used to provide light-emitting control signals to each of the sub-pixels; In the sub-pixel region, the light emitting control signal line is located at a side of the reset signal line away from the scanning line of the previous sub-pixel, and does not overlap with the projection of the initialization signal line.

10. The array substrate according to claim 9, wherein: The array substrate further includes: A plurality of power leads are arranged in the second gate line layer, extending along the row direction and arranged at intervals along the column direction, and each of the power leads in the same row is connected to one of the power leads through a via hole.

11. The array substrate according to claim 10, wherein: The sub-pixel further includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes: A capacitor, comprising a first electrode plate and a second electrode plate, wherein the first electrode plate is arranged on the first gate line layer, and the second electrode plate is arranged on the second gate line layer; A driving transistor, wherein the first plate of the capacitor is multiplexed as a gate of the driving transistor, and the first stage of the driving transistor is connected to the power line; a first transistor, wherein a gate of the first transistor is connected to the scan line, a first stage of the first transistor is connected to the data line, and a second stage of the first transistor is connected to a second plate of the capacitor; a second transistor, wherein a gate of the second transistor is connected to the scan line, a first stage of the second transistor is connected to a second stage of the driving transistor, and a second stage of the second transistor is connected to a first plate of the capacitor; a fourth transistor, wherein a gate of the fourth transistor is connected to the reset signal line, a first stage of the fourth transistor is electrically connected to the initialization signal line, and a second stage of the fourth transistor is electrically connected to the first plate of the capacitor; a fifth transistor, wherein a gate of the fifth transistor is connected to the reset signal line, a first stage of the fifth transistor is electrically connected to the initialization signal line, and a second stage of the fifth transistor is electrically connected to the second plate of the capacitor; a sixth transistor, wherein a gate of the sixth transistor is connected to the light emitting control signal line, a first stage of the sixth transistor is electrically connected to the initialization signal line, and a second stage of the sixth transistor is electrically connected to the second plate of the capacitor; a seventh transistor, wherein a gate of the seventh transistor is connected to the light emitting control signal line, a first stage of the seventh transistor is electrically connected to a second stage of the driving transistor, and a second stage of the seventh transistor is electrically connected to an anode of the sub-pixel; an eighth transistor, a gate of the eighth transistor being connected to the reset signal line, a first stage of the eighth transistor being electrically connected to the initialization signal line, and a second stage of the eighth transistor being electrically connected to the anode of the sub-pixel; A ninth transistor, wherein a gate of the ninth transistor is connected to the light emitting control signal line, and a first stage of the ninth transistor is electrically connected to a first plate of the capacitor.

12. The array substrate according to claim 11, wherein: The array substrate further includes: A plurality of second conductive connection portions, disposed in the source-drain electrode layer and distributed in each of the sub-pixel regions; A plurality of third conductive connection portions, disposed in the source-drain electrode layer and distributed in each of the sub-pixel regions; In the sub-pixel region, the second conductive connection portion is respectively connected to the second stage of the first transistor, the second stage of the fifth transistor, the second stage of the sixth transistor, and the second plate of the capacitor through via holes, and the second stage of the first transistor, the second stage of the fifth transistor, and the second stage of the sixth transistor are all electrically connected to the second plate of the capacitor through the second conductive connection portion; In the sub-pixel area, the third conductive connection portion is respectively connected to the second level of the fourth transistor, the first level of the ninth transistor and the first plate of the capacitor through vias, and the second level of the fourth transistor and the first level of the ninth transistor are both electrically connected to the first plate of the capacitor through the third conductive connection portion.

13. The array substrate according to claim 12, wherein: The array substrate further includes: A plurality of fifth conductive connection portions, disposed in the source-drain electrode layer and distributed in each of the sub-pixel regions; The fifth conductive connection portion is connected to the first stage of the fifth transistor through a via hole, and the fifth conductive connection portion is also connected to the initialization signal line through another via hole, so that the first stage of the fifth transistor is connected to the initialization signal line; The connection line is disposed in the source-drain layer, and the connection line is connected to the fifth conductive connection portion, so as to be connected to the initialization signal line through the fifth conductive connection portion.

14. A display device, wherein: The invention comprises the array substrate according to any one of claims 1 to 13.

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