Superconducting single-flux quantum cross-clock domain communication method and system based on asynchronous FIFO

Abstract

This invention proposes a superconducting single-flux quantum cross-clock domain communication method and system based on asynchronous FIFO, comprising: initializing the FIFO; an external write circuit inputting a write signal to the FIFO; the FIFO generating a write address and a write flag based on the write signal, and comparing them with the read address and read flag; if the read address and write address are equal, but the write flag and read flag are opposite, the system waits for the external read circuit to read data and generate a new read flag and read address, and then writes the data to be written to the FIFO according to the write address; otherwise, the system writes the data to be written to the FIFO according to the write address. The external read circuit inputs a read signal to the FIFO and generates a read address and read flag, comparing them with the write address and write flag; if the read address and write address are the same, and the read flag and write flag are also the same, the system waits for the external write circuit to write data and generate a new write address and write flag, and then reads the data according to the read address and returns to the external read circuit; otherwise, the system reads the data according to the read address and returns to the external read circuit.

Description

Technical Field

[0001] This invention relates to the field of superconducting single flux quantum (RSFQ) microprocessors in computer systems, and particularly to cross-clock domain communication of superconducting single flux quantum processors. Background Technology

[0002] When performing asynchronous clock domain communication, the clock frequencies and phases of different clock domains may differ, potentially leading to issues such as data loss and unpredictable states. One solution in the semiconductor field is to use an asynchronous FIFO. This works by having the source clock domain circuitry write data sequentially into the asynchronous FIFO, and the destination clock domain circuitry read the data sequentially. The asynchronous FIFO serves to store data, determine if the data is full or empty, and prevent data errors in unpredictable states.

[0003] Currently, there is no asynchronous FIFO in the RSFQ circuit field that can be used for cross-clock domain communication. Furthermore, due to the differences between semiconductor circuits and RSFQ circuits, directly implementing an asynchronous FIFO in a semiconductor circuit using an RSFQ circuit presents several problems: First, when the number of registers is small, generating addresses and converting them into Hamming codes for decoding consumes too many resources. Second, semiconductor FIFOs convert addresses into Hamming codes to ensure that only one address bit changes each time an address is generated, thus reducing the probability of errors. However, due to the differences between RSFQ and semiconductor circuits, this design is not used in RSFQ circuits.

[0004] Because the signal in the circuit changes when the address changes, and asynchronous FIFOs need to cross clock domains, the fewer the number of changing signals, the better, as fewer signals reduce the probability of indeterminate states. In semiconductor circuits, one-hot encoding causes two signal lines to flip each time the address changes, while Hamming encoding only causes one signal line to flip. Furthermore, with the same number of signal lines, Hamming encoding can represent a larger address range, so semiconductors generally use Hamming encoding. However, the signals in RSFQ circuits are not level signals but pulse signals. The presence or absence of a pulse between two clock cycles represents 1 and 0; a pulse indicates 1, and no pulse indicates 0. Therefore, in cross-clock domain communication, RSFQ circuits prioritize a small number of pulses, as fewer pulses reduce the likelihood of errors, hence the use of one-hot encoding with only one 1. Therefore, asynchronous FIFOs in the semiconductor field cannot be directly applied to the RSFQ field.

[0005] Therefore, an asynchronous FIFO that can be used in an RSFQ circuit environment is needed to match the clock frequency and phase of different clock domains. Summary of the Invention

[0006] The purpose of this invention is to solve the problem of cross-clock domain communication in RSFQ circuits, and to propose an asynchronous FIFO suitable for RSFQ circuits.

[0007] To address the shortcomings of existing technologies, this invention proposes a superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO, which includes:

[0008] Step 1: Initialize the FIFO. The external write circuit inputs a write signal to the FIFO. The FIFO generates a write address and a write flag based on the write signal and compares them with the read address and read flag. If the read address and write address are equal, but the write flag and read flag are reversed, proceed to step 2; otherwise, write the data to be written to the FIFO according to the write address.

[0009] Step 2: At this point, the FIFO is full. After the external read circuit reads the data and generates a new read flag and read address, the data to be written is written to the FIFO according to the write address.

[0010] Step 3: The external read circuit inputs a read signal to the FIFO and generates a read address and a read flag. It compares the read address and the write flag with the write address and the write flag. If the read address and the write address are the same, and the read flag and the write flag are also the same, then step 4 is executed. Otherwise, the data is read according to the read address and returned to the external read circuit.

[0011] Step 4: At this point, the FIFO is empty. After the external write circuit writes data and generates a new write address and write flag, the data is read out according to the read address and returned to the external read circuit.

[0012] 2. The superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO as described in claim 1, wherein the FIFO includes a register file, a read control circuit, and a write control circuit;

[0013] The write control circuit consists of an address generator, an address register, a data register, a full-time detection circuit, and a clock gating circuit.

[0014] This address generator consists of multiple D flip-flops, an rtffl, and a non-destructive read unit. When a reset signal arrives, it clears all cells within the address generator and inputs a pulse to the least significant D flip-flop. With each clock cycle, this pulse shifts upwards by one bit. Simultaneously with the arrival of the clock, the outputs of all D flip-flops form an address group, where only the D flip-flop containing the pulse outputs 1, and the rest output 0. After the pulse reaches the most significant D flip-flop, the next clock cycle outputs a pulse to the clear input of the rtffl and non-destructive read unit, clearing the non-destructive read unit. If this is the odd-numbered pulse arriving at the rtffl, the rtffl will output a pulse to the non-destructive read unit; otherwise, it will not output. When there is a pulse in the non-destructive read unit, it will output a pulse with each clock cycle. The output of this address generator is the address output by all D flip-flops and the address flag output by the non-destructive read unit.

[0015] This address register consists of multiple D flip-flops. Its input is the address output by the address generator, and it outputs the stored address when the clock arrives.

[0016] This data register consists of multiple D flip-flops. The input is a multi-bit data provided externally, and the multi-bit data will be output when the clock arrives.

[0017] The full-value detection circuit consists of an address comparison circuit, a flag comparison circuit, and a full flag generation circuit.

[0018] The address comparison circuit consists of multiple non-destructive readout units and a multi-layer fusion buffer. The input of the non-destructive readout unit is the read address of the read control circuit, the clock is the write address of the write control circuit, and the clear signal is the read clock transmitted by the control circuit. When the read and write addresses are equal, after the read control circuit generates the address, it first clears all the non-destructive readout units in the address comparison circuit. Then, the read address is sent to all the non-destructive readout units in the address comparison circuit. After the write address generator outputs a set of addresses, it sends the address to the clock circuit of all the non-destructive readout units in the address comparison circuit. When the read and write addresses are equal, one of the non-destructive readout units in the address comparison circuit will have both data and clock, so it will output a pulse. This pulse is output after passing through the multi-layer fusion buffer.

[0019] The flag comparison circuit consists of a non-destructive readout unit and an XOR gate. The input of the non-destructive readout unit is the read address flag of the read control circuit, the clock of the non-destructive readout unit is the write clock, and the clear circuit is the read clock. The inputs of the XOR gate are the write address flag and the output of the non-destructive readout unit, respectively, and the clock is the write clock. After the read control circuit generates a read flag, it sends it to the non-destructive readout unit of the flag comparison circuit. After the write clock arrives, it reads the non-destructive readout unit of the flag comparison circuit. By controlling the delay, the clock of the XOR gate arrives at the XOR gate after all the inputs of the XOR gate have arrived. When the inputs of the XOR gate are different, that is, when the read and write address flags are different, an output is generated.

[0020] The data input to the full flag generation circuit is the output of the flag comparison circuit, the clock is the output of the address comparison circuit, and the clear circuit is the write clock. The write clock first arrives at the D flip-flop of the full flag generation circuit to clear it once, then the output of the flag comparison circuit arrives, and then the output of the address comparison circuit arrives. If the data and the clock arrive within one write clock cycle, an output will be generated.

[0021] The clock-gated circuit consists of multiple D flip-flops and non-destructive readout units. The inputs of the non-destructive readout units are a reset signal and a full flag signal after passing through two stages of D flip-flops. The clock is a directly input write clock, and the clear signal is the full flag signal. The non-destructive readout units of the clock-gated circuit directly control the clock. When there is data in the non-destructive readout unit, the clock can be applied to the D flip-flops that store the write signal after passing through the non-destructive readout unit. When there is no data in the non-destructive readout unit, the clock is shielded, and the write circuit stops working.

[0022] The read control circuit consists of an address generation circuit, an address register, a null detection circuit, and a clock gating circuit.

[0023] The address generation circuit, address register, and clock gating circuit of the read control circuit are composed of the same components and working principle as the address generation circuit, address register, and clock gating circuit of the write control circuit described above.

[0024] The empty circuit has an additional NOT gate in its flag comparison circuit. The write address flag is inverted once before entering the non-destructive read unit. The NOT gate clock is the write clock. The rest of the empty circuit is the same as the full circuit of the write control circuit.

[0025] The superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO, wherein...

[0026] The process of generating the write address and write flag based on the write signal in step 1 is as follows: the write flag and write address are reset according to the initialization signal. After that, the write address is incremented by one every time the FIFO receives a write signal. After the write address is incremented a specified number of times, the write flag is inverted and the write address is reset.

[0027] The process of generating the read address and read flag in step 3 is as follows: the read flag and read address are reset according to the initialization signal. After that, the read address is incremented by one every time the FIFO receives a read signal. After the read address is incremented a specified number of times, the read flag is inverted and the read address is reset.

[0028] The superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO, wherein both the write address and the read address are one-hot encoded.

[0029] This invention also proposes a superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO, including:

[0030] The write module is used to initialize the FIFO. An external write circuit inputs a write signal to the FIFO. The FIFO generates a write address and a write flag based on the write signal and compares them with the read address and read flag. If the read address and write address are equal, but the write flag and read flag are opposite, the first waiting module is called; otherwise, the data to be written is written to the FIFO according to the write address.

[0031] The first waiting module is used to wait for the external read circuit to read data and generate a new read flag and read address, and then write the data to be written into the FIFO according to the write address.

[0032] The read module is used by the external read circuit to input a read signal to the FIFO and generate a read address and a read flag. It compares the read address and the write flag with the write address and the write flag. If the read address and the write address are the same, and the read flag and the write flag are also the same, the second waiting module is called. Otherwise, the data is read according to the read address and returned to the external read circuit.

[0033] The second waiting module is used to wait for the external write circuit to write data and generate a new write address and write flag, and then read the data according to the read address and return to the external read circuit.

[0034] The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO includes a register file, a read control circuit, and a write control circuit.

[0035] The write control circuit consists of an address generator, an address register, a data register, a full-time detection circuit, and a clock gating circuit.

[0036] This address generator consists of multiple D flip-flops, an rtffl, and a non-destructive read unit. When a reset signal arrives, it clears all cells within the address generator and inputs a pulse to the least significant D flip-flop. With each clock cycle, this pulse shifts upwards by one bit. Simultaneously with the arrival of the clock, the outputs of all D flip-flops form an address group, where only the D flip-flop containing the pulse outputs 1, and the rest output 0. After the pulse reaches the most significant D flip-flop, the next clock cycle outputs a pulse to the clear input of the rtffl and non-destructive read unit, clearing the non-destructive read unit. If this is the odd-numbered pulse arriving at the rtffl, the rtffl will output a pulse to the non-destructive read unit; otherwise, it will not output. When there is a pulse in the non-destructive read unit, it will output a pulse with each clock cycle. The output of this address generator is the address output by all D flip-flops and the address flag output by the non-destructive read unit.

[0037] This address register consists of multiple D flip-flops. Its input is the address output by the address generator, and it outputs the stored address when the clock arrives.

[0038] This data register consists of multiple D flip-flops. The input is a multi-bit data provided externally, and the multi-bit data will be output when the clock arrives.

[0039] The full-value detection circuit consists of an address comparison circuit, a flag comparison circuit, and a full flag generation circuit.

[0040] The address comparison circuit consists of multiple non-destructive readout units and a multi-layer fusion buffer. The input of the non-destructive readout unit is the read address of the read control circuit, the clock is the write address of the write control circuit, and the clear signal is the read clock transmitted by the control circuit. When the read and write addresses are equal, after the read control circuit generates the address, it first clears all the non-destructive readout units in the address comparison circuit. Then, the read address is sent to all the non-destructive readout units in the address comparison circuit. After the write address generator outputs a set of addresses, it sends the address to the clock circuit of all the non-destructive readout units in the address comparison circuit. When the read and write addresses are equal, one of the non-destructive readout units in the address comparison circuit will have both data and clock, so it will output a pulse. This pulse is output after passing through the multi-layer fusion buffer.

[0041] The flag comparison circuit consists of a non-destructive readout unit and an XOR gate. The input of the non-destructive readout unit is the read address flag of the read control circuit, the clock of the non-destructive readout unit is the write clock, and the clear circuit is the read clock. The inputs of the XOR gate are the write address flag and the output of the non-destructive readout unit, respectively, and the clock is the write clock. After the read control circuit generates a read flag, it sends it to the non-destructive readout unit of the flag comparison circuit. After the write clock arrives, it reads the non-destructive readout unit of the flag comparison circuit. By controlling the delay, the clock of the XOR gate arrives at the XOR gate after all the inputs of the XOR gate have arrived. When the inputs of the XOR gate are different, that is, when the read and write address flags are different, an output is generated.

[0042] The data input to the full flag generation circuit is the output of the flag comparison circuit, the clock is the output of the address comparison circuit, and the clear circuit is the write clock. The write clock first arrives at the D flip-flop of the full flag generation circuit to clear it once, then the output of the flag comparison circuit arrives, and then the output of the address comparison circuit arrives. If the data and the clock arrive within one write clock cycle, an output will be generated.

[0043] The clock-gated circuit consists of multiple D flip-flops and non-destructive readout units. The inputs of the non-destructive readout units are a reset signal and a full flag signal after passing through two stages of D flip-flops. The clock is a directly input write clock, and the clear signal is the full flag signal. The non-destructive readout units of the clock-gated circuit directly control the clock. When there is data in the non-destructive readout unit, the clock can be applied to the D flip-flops that store the write signal after passing through the non-destructive readout unit. When there is no data in the non-destructive readout unit, the clock is shielded, and the write circuit stops working.

[0044] The read control circuit consists of an address generation circuit, an address register, a null detection circuit, and a clock gating circuit.

[0045] The address generation circuit, address register, and clock gating circuit of the read control circuit are composed of the same components and working principle as the address generation circuit, address register, and clock gating circuit of the write control circuit described above.

[0046] The empty circuit has an additional NOT gate in its flag comparison circuit. The write address flag is inverted once before entering the non-destructive read unit. The NOT gate clock is the write clock. The rest of the empty circuit is the same as the full circuit of the write control circuit.

[0047] The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO, wherein...

[0048] The write module is used to generate a write address and a write flag based on the write signal. Specifically, the write flag and write address are reset according to the initialization signal. After that, the write address is incremented by one every time the FIFO receives a write signal. After the write address is incremented a specified number of times, the write flag is inverted and the write address is reset.

[0049] The process of generating the read address and read flag in this read module is as follows: the read flag and read address are reset according to the initialization signal. After that, the read address is incremented by one every time the FIFO receives a read signal. After the read address is incremented a specified number of times, the read flag is inverted and the read address is reset.

[0050] The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO, wherein both the write address and the read address are one-hot encoded.

[0051] The present invention also proposes a storage medium for storing a program for executing any of the above-described asynchronous FIFO-based superconducting single-flux quantum cross-clock domain communication methods.

[0052] The present invention also proposes a client for any of the above-mentioned asynchronous FIFO-based superconducting single flux quantum cross-clock domain communication systems.

[0053] As can be seen from the above solutions, the advantages of the present invention are:

[0054] This invention can solve the problem of cross-clock domain communication in RSFQ circuits. Specifically, it proposes a new address comparison circuit that can reduce the probability of timing errors occurring across clock domains and prevent data errors when timing errors occur; it also proposes an address generation circuit that can generate a set of one-hot encoded addresses and generate a flag bit that changes once every clock cycle. Attached Figure Description

[0055] Figure 1 A schematic diagram of the address generator circuit for the write control section;

[0056] Figure 2 This is a schematic diagram of the address register circuit structure in the write control section;

[0057] Figure 3 A schematic diagram of the circuit structure for writing to the data register in the control section;

[0058] Figure 4 This is a schematic diagram of the circuit structure for the full-scale detection part in the control section;

[0059] Figure 5 This is a schematic diagram of the circuit structure of the address comparison section in the full detection part;

[0060] Figure 6This is a schematic diagram of the circuit structure of the flag comparison part in the full-threshold judgment section;

[0061] Figure 7 This is a schematic diagram of the circuit structure of the register file. Detailed Implementation

[0062] The inventors discovered that by directly using one-hot encoding as the address, resource consumption in the RSFQ circuit can be reduced, the probability of clock collisions can be lowered, and the complexity of address generation can be reduced. This can be achieved using only an improved shift register, eliminating the need for a decoding circuit. Both the read and write operations use the address generated by the other party as data. The address generated by the other party is placed into a set of ndro (non-destructive readout units), and the clock is generated using the self-generated address. If the two sets of addresses are the same, one ndro will have both data and clock simultaneously, producing an output. If the two sets of addresses are different, no ndro will have both data and clock, so there will be no ndro output. Furthermore, each address set has only one pulse, further reducing the probability of clock collisions.

[0063] This invention provides a superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO, comprising a write section and a read section, wherein the write section includes:

[0064] Step W1: Initialize the FIFO with a restart signal. After that, the FIFO will send a readable signal to the read circuit and a writeable signal to the write circuit, indicating that reading and writing can be performed respectively.

[0065] Step W2: The external write circuit inputs a write signal to the FIFO. "External" refers to circuits outside the FIFO, as data in the FIFO needs to be written to and read from externally. Therefore, the circuit that writes data to the FIFO is called the external write circuit, and the circuit that reads data from the FIFO is called the external read circuit.

[0066] Step W3: Return a writeable signal to the external write circuit, indicating that the external write circuit can output the data written this time to the FIFO and can provide a write signal for the next write operation; simultaneously, generate a write address and write flag, and compare them with the current read address and read flag. If the addresses are equal and the flags are opposite, it means the FIFO is full, and proceed to step W6; otherwise, proceed to step W4. The write address and write flag are generated based on the write signal and the previous write address and write flag. Each time a write signal arrives, the write address increments by one (because it's one-hot, it's actually shifted left by one bit). After every seven left shifts, the write address becomes 1000_0000. The next left shift will invert the write flag, and the write address becomes 0000_0001. Initially, the write flag and write address are initialized to 0 and 0000_0001 by the restart signal. The read address and read flag are initially initialized to 0 and 0000_0001 by the restart signal. Restart will not only be completed in the read circuit, but also in the comparison section of the write circuit, where the initial read flag and read address will be input.

[0067] Step W4: The external write circuit inputs the data to be written to the FIFO and can input the next write signal.

[0068] Step W5: Write the data to the corresponding write address. If the next write signal was input in step W4, a writeable signal is returned to the external write circuit, indicating that the data written this time can be output to the FIFO and the next write signal can be given. At the same time, a write address and a write flag are generated and compared with the current read address and read flag. If the address is equal and the flag is opposite, it means that the FIFO is full, and go to step W6; otherwise, go to step W4. If no write signal was input in step W4, wait for the input of the write signal, and after input, go to step W3.

[0069] Step W6: At this point, the FIFO is full. We need to wait for the read section to read out a set of data and generate a new read flag and read address before proceeding to step W4.

[0070] Reading section:

[0071] Step R1: Initialize the FIFO with a restart signal. After that, the FIFO will send a readable signal to the read circuit and a writeable signal to the write circuit, indicating that reading and writing can be performed respectively.

[0072] Step R2: The external read circuit inputs a read signal to the FIFO;

[0073] Step R3: If the external circuit previously input a read signal to the FIFO but has not yet read the corresponding data, then read the data according to the current read address and return to the external read circuit; if the external circuit did not previously input a read signal to the FIFO, then the data to be read will not be output. A readable signal is returned to the external read circuit, indicating that the next read can proceed. A read address and read flag are generated and compared with the current write address and write flag. If the addresses and flags are the same, it means the FIFO is empty and reading cannot continue; proceed to step R4; otherwise, proceed to step R2.

[0074] The FIFO circuit proposed in this invention does not generate read data when the first read signal arrives. Starting from the second read signal, each read outputs one data, which is equivalent to a pipeline with a depth of 2. Therefore, each time a read signal arrives, the data to be read by the previous read signal will be read and returned to the external read circuit.

[0075] Step R4: At this point, the FIFO is empty. We need to wait for the write part to write a set of data to generate a new write address and write flag before proceeding to step R2.

[0076] Through the above read and write process, the data of the original clock domain circuit can be written into the FIFO, and the target clock domain circuit can read the data from the FIFO, thus realizing cross-clock domain data transmission and communication.

[0077] To make the above features and effects of the present invention clearer and easier to understand, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings.

[0078] This asynchronous FIFO consists of three parts: register file, read control section, and write control section.

[0079] The write control section consists of an address generation section, an address register, a data register, a full check section, and a clock gating section.

[0080] like Figure 1 As shown, the address generator consists of eight rdff (D flip-flops with reset ports), one rtffl (T flip-flop with reset port, where l indicates that a pulse output occurs when an odd number of pulses are input), and one ndro. First, upon the arrival of the reset signal, the cache is cleared. Figure 1The address generator uses all units, including 8 rdffs, 1 ndro, and 1 rtffl, and inputs a pulse to the least significant rdff bit. Afterward, with each clock cycle, this pulse shifts up one bit, so only one of the eight rdffs will contain the pulse. Simultaneously with the clock cycle, the outputs of these eight rdffs will form an address set, with only the rdff that originally contained the pulse outputting a 1, and the rest outputting 0. After the pulse reaches the eighth rdff, if another clock cycle arrives, a pulse will be output to the clear inputs of rtffl and ndro, clearing ndro. If this is an odd number of pulses to rtffl, then rtffl will output a pulse to ndro; otherwise, it will not. When there is a pulse in ndro, ndro will output a pulse with each clock cycle. The output of the address generator is the 8-bit address output from the eight rdffs and the address flag output from ndro.

[0081] like Figure 2 As shown, the address register consists of eight dff (D flip-flops). The input is the address output by the address generator, and the stored address is output when the clock arrives.

[0082] like Figure 3 As shown, the data register consists of 16 dffs. The input is a 16-bit data given externally, and the 16-bit data will be output when the clock arrives.

[0083] like Figure 4 As shown, the full determination part consists of an address comparison part, a flag comparison part, and a full flag generation part.

[0084] like Figure 5 As shown, the address comparison section consists of 8 NDROs and 7 CBs (fusion buffers) across 3 layers. The input to the NDROs is the read address from the read control section, the clock is the write address from the write control section, and the clear signal is the read clock from the read control section. Working principle: The read and write addresses have the same format, both being 8 bits, with only one bit set to 1 and the rest to 0. When the bit set to 1 in both the read and write addresses is the same, the read and write addresses are equal. After generating the address, the read control section first clears these 8 NDROs, and then sends the read address to these 8 NDROs. After the write address generator outputs a set of addresses, it sends the address to the clock section of these 8 NDROs. At this point, when the read and write addresses are not equal, these NDROs either have no data, no clock, or neither, so there will be no output. When the read and write addresses are equal, one NDRO will have both data and clock, so it will output a pulse. This pulse is then output after passing through three CBs.

[0085] like Figure 6As shown, the flag comparison section consists of an ndro and an XOR gate. The input to the ndro is the read address flag sent by the read control section, the clock of the ndro is the write clock, and the clearing section is the read clock. The inputs of the XOR gate are the write address flag and the output of the ndro, and the clock is the write clock. The operation is as follows: after the read control section generates a read flag, it first clears the ndro, then sends the read flag into the ndro. When the write clock arrives, it reads the ndro and, through control delay, ensures that the clock of the XOR gate arrives after all its inputs have arrived. When the inputs of the XOR gate are different (i.e., the read and write address flags are different), an output is generated.

[0086] The full flag generation section is an rdff, the data input is the output of the flag comparison section, the clock is the output of the address comparison section, and the clear section is the write clock. The operation is as follows: the write clock arrives at the rdff first to clear it, then the output of the flag comparison section arrives (if any), followed by the output of the address comparison section (if any). If both the data and clock arrive within one write clock cycle, an output will be generated.

[0087] The clock gating section consists of four DFFs and one NDRO. The NDRO's inputs are the restart signal and a full flag signal after passing through two DFF stages. The clock is the direct write clock input, and the clear signal is the full flag signal. This NDRO directly controls the clock; when there is data on the NDRO, the clock can pass through it and affect the DFF storing the write signal. When there is no data on the NDRO, the clock is masked, and the write operation stops. The full flag reaching the NDRO data input port passes through two DFF stages. The clock of the first DFF is the read clock, indicating that a new read address has been generated, meaning the register file is no longer full and write operations can continue. The second DFF clock is the ungated write clock, which acts as a delay to prevent timing errors. After the write signal is input, it first enters the first DFF stage. Upon the arrival of the write clock, it is output to the address generation and comparison sections, and simultaneously enters the next DFF stage and is output to the external circuitry to notify external circuits that data can be input and the next write signal can be input. The signal to enter the next stage of DFF will be output after the write clock arrives, serving as the clock for the address register and data register.

[0088] The read control section consists of an address generation section, an address register, a null detection section, and a clock gating section.

[0089] The address generation section, address register, clock gating section, and write control section are the same.

[0090] The null check section has an additional NOT gate in its flag comparison section. The write address flag is inverted once before entering ndro. The NOT gate clock is the write clock. The rest of the section is the same as the write control section.

[0091] like Figure 7 As shown, the register file consists of eight 16-bit registers, each composed of two groups of sixteen bytes (rdff). When writing data, the data is first placed into the first group of rdff. Then, the write address determines which register to write to. The selected register receives a clock signal in the first group of rdff, and the data is written to the second rdff. Afterward, each register receives a clear signal, clearing the first group of rdff. When reading data, the register selected by the read address receives a clock signal, and the data is read out.

[0092] Regarding the clock collision issue across clock domains: Because the read and write pointers use one-hot encoding, at any given moment there is only one ndro with clock and only one ndro with data. Timing conflicts will only occur when the ndro with clock and data is the same.

[0093] Let the read pointer be r_addr, the read flag be r_sign, the write pointer be w_addr, and the write flag be w_sign. Assume a timing conflict occurs at time t1, before the FIFO was functioning normally. Then, r_addr1 = w_addr1, r_sign1 = ! w_sign1, and the time interval between r_addr1, r_sign1, and w_addr1, w_sign1 reaching the full checkpoint is extremely small, less than the device hold time or setup time. Now consider the previous state: r_addr0 and w_addr0 are also equal, r_sign0 and w_sign0 are opposite, and r_addr0 and r_sign0 must arrive first. If w_addr0 and w_sign0 arrived first, it would mean the write address has exceeded the read address by one cycle, indicating a FIFO error, which is unlikely. Therefore, r_addr0 and r_sign0 must arrive first. When w_addr0 and w_sign0 arrive, the part that should be full will be judged as full, and the generation of write addresses will stop. A new write address will not be generated until the next read pointer arrives after a one-write-cycle delay. Therefore, it is assumed that this situation will not occur. There will be no error where a full condition should be met but is not.

[0094] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0095] This invention also proposes a superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO, including:

[0096] The write module is used to initialize the FIFO. An external write circuit inputs a write signal to the FIFO. The FIFO generates a write address and a write flag based on the write signal and compares them with the read address and read flag. If the read address and write address are equal, but the write flag and read flag are opposite, the first waiting module is called; otherwise, the data to be written is written to the FIFO according to the write address.

[0097] The first waiting module is used to wait for the external read circuit to read data and generate a new read flag and read address, and then write the data to be written into the FIFO according to the write address.

[0098] The read module is used by the external read circuit to input a read signal to the FIFO and generate a read address and a read flag. It compares the read address and the write flag with the write address and the write flag. If the read address and the write address are the same, and the read flag and the write flag are also the same, the second waiting module is called. Otherwise, the data is read according to the read address and returned to the external read circuit.

[0099] The second waiting module is used to wait for the external write circuit to write data and generate a new write address and write flag, and then read the data according to the read address and return to the external read circuit.

[0100] The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO includes a register file, a read control circuit, and a write control circuit.

[0101] The write control circuit consists of an address generator, an address register, a data register, a full-time detection circuit, and a clock gating circuit.

[0102] This address generator consists of multiple D flip-flops, an rtffl, and a non-destructive read unit. When a reset signal arrives, it clears all cells within the address generator and inputs a pulse to the least significant D flip-flop. With each clock cycle, this pulse shifts upwards by one bit. Simultaneously with the arrival of the clock, the outputs of all D flip-flops form an address group, where only the D flip-flop containing the pulse outputs 1, and the rest output 0. After the pulse reaches the most significant D flip-flop, the next clock cycle outputs a pulse to the clear input of the rtffl and non-destructive read unit, clearing the non-destructive read unit. If this is the odd-numbered pulse arriving at the rtffl, the rtffl will output a pulse to the non-destructive read unit; otherwise, it will not output. When there is a pulse in the non-destructive read unit, it will output a pulse with each clock cycle. The output of this address generator is the address output by all D flip-flops and the address flag output by the non-destructive read unit.

[0103] This address register consists of multiple D flip-flops. Its input is the address output by the address generator, and it outputs the stored address when the clock arrives.

[0104] This data register consists of multiple D flip-flops. The input is a multi-bit data provided externally, and the multi-bit data will be output when the clock arrives.

[0105] The full-value detection circuit consists of an address comparison circuit, a flag comparison circuit, and a full flag generation circuit.

[0106] The address comparison circuit consists of multiple non-destructive readout units and a multi-layer fusion buffer. The input of the non-destructive readout unit is the read address of the read control circuit, the clock is the write address of the write control circuit, and the clear signal is the read clock transmitted by the control circuit. When the read and write addresses are equal, after the read control circuit generates the address, it first clears all the non-destructive readout units in the address comparison circuit. Then, the read address is sent to all the non-destructive readout units in the address comparison circuit. After the write address generator outputs a set of addresses, it sends the address to the clock circuit of all the non-destructive readout units in the address comparison circuit. When the read and write addresses are equal, one of the non-destructive readout units in the address comparison circuit will have both data and clock, so it will output a pulse. This pulse is output after passing through the multi-layer fusion buffer.

[0107] The flag comparison circuit consists of a non-destructive readout unit and an XOR gate. The input of the non-destructive readout unit is the read address flag of the read control circuit, the clock of the non-destructive readout unit is the write clock, and the clear circuit is the read clock. The inputs of the XOR gate are the write address flag and the output of the non-destructive readout unit, respectively, and the clock is the write clock. After the read control circuit generates a read flag, it sends it to the non-destructive readout unit of the flag comparison circuit. After the write clock arrives, it reads the non-destructive readout unit of the flag comparison circuit. By controlling the delay, the clock of the XOR gate arrives at the XOR gate after all the inputs of the XOR gate have arrived. When the inputs of the XOR gate are different, that is, when the read and write address flags are different, an output is generated.

[0108] The data input to the full flag generation circuit is the output of the flag comparison circuit, the clock is the output of the address comparison circuit, and the clear circuit is the write clock. The write clock first arrives at the D flip-flop of the full flag generation circuit to clear it once, then the output of the flag comparison circuit arrives, and then the output of the address comparison circuit arrives. If the data and the clock arrive within one write clock cycle, an output will be generated.

[0109] The clock-gated circuit consists of multiple D flip-flops and non-destructive readout units. The inputs of the non-destructive readout units are a reset signal and a full flag signal after passing through two stages of D flip-flops. The clock is a directly input write clock, and the clear signal is the full flag signal. The non-destructive readout units of the clock-gated circuit directly control the clock. When there is data in the non-destructive readout unit, the clock can be applied to the D flip-flops that store the write signal after passing through the non-destructive readout unit. When there is no data in the non-destructive readout unit, the clock is shielded, and the write circuit stops working.

[0110] The read control circuit consists of an address generation circuit, an address register, a null detection circuit, and a clock gating circuit.

[0111] The address generation circuit, address register, and clock gating circuit of the read control circuit are composed of the same components and working principle as the address generation circuit, address register, and clock gating circuit of the write control circuit described above.

[0112] The empty circuit has an additional NOT gate in its flag comparison circuit. The write address flag is inverted once before entering the non-destructive read unit. The NOT gate clock is the write clock. The rest of the empty circuit is the same as the full circuit of the write control circuit.

[0113] The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO, wherein...

[0114] The write module is used to generate a write address and a write flag based on the write signal. Specifically, the write flag and write address are reset according to the initialization signal. After that, the write address is incremented by one every time the FIFO receives a write signal. After the write address is incremented a specified number of times, the write flag is inverted and the write address is reset.

[0115] The process of generating the read address and read flag in this read module is as follows: the read flag and read address are reset according to the initialization signal. After that, the read address is incremented by one every time the FIFO receives a read signal. After the read address is incremented a specified number of times, the read flag is inverted and the read address is reset.

[0116] The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO, wherein both the write address and the read address are one-hot encoded.

[0117] The present invention also proposes a storage medium for storing a program for executing any of the above-described asynchronous FIFO-based superconducting single-flux quantum cross-clock domain communication methods.

[0118] The present invention also proposes a client for any of the above-mentioned asynchronous FIFO-based superconducting single flux quantum cross-clock domain communication systems.

Claims

1. A superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO, characterized in that, include: Step 1: Initialize the FIFO. The external write circuit inputs a write signal to the FIFO. The FIFO generates a write address and a write flag based on the write signal and compares them with the read address and read flag. If the read address and write address are equal, but the write flag and read flag are reversed, proceed to step 2. Otherwise, write the data to be written to the FIFO according to the write address; Step 2: At this point, the FIFO is full. After the external read circuit reads the data and generates a new read flag and read address, the data to be written is written to the FIFO according to the write address. Step 3: The external read circuit inputs a read signal to the FIFO and generates a read address and a read flag. It compares the read address and the write flag with the write address and the write flag. If the read address and the write address are the same, and the read flag and the write flag are also the same, then step 4 is executed. Otherwise, the data is read according to the read address and returned to the external read circuit. Step 4: At this point, the FIFO is empty. After the external write circuit writes data and generates a new write address and write flag, the data is read out according to the read address and returned to the external read circuit. The FIFO includes a register file, a read control circuit, and a write control circuit. The write control circuit consists of an address generator, an address register, a data register, a full-time detection circuit, and a clock gating circuit. This address generator consists of multiple D flip-flops, an rtffl, and a non-destructive read unit. When a reset signal arrives, it clears all cells within the address generator and inputs a pulse to the least significant D flip-flop. With each clock cycle, this pulse shifts upwards by one bit. Simultaneously with the arrival of the clock, the outputs of all D flip-flops form an address group, where only the D flip-flop containing the pulse outputs 1, and the rest output 0. After the pulse reaches the most significant D flip-flop, the next clock cycle outputs a pulse to the clear input of the rtffl and non-destructive read unit, clearing the non-destructive read unit. If this is the odd-numbered pulse arriving at the rtffl, the rtffl will output a pulse to the non-destructive read unit; otherwise, it will not output. When there is a pulse in the non-destructive read unit, it will output a pulse with each clock cycle. The output of this address generator is the address output by all D flip-flops and the address flag output by the non-destructive read unit. This address register consists of multiple D flip-flops. Its input is the address output by the address generator, and it outputs the stored address when the clock arrives. This data register consists of multiple D flip-flops. The input is a multi-bit data provided externally, and the multi-bit data will be output when the clock arrives. The full-value detection circuit consists of an address comparison circuit, a flag comparison circuit, and a full flag generation circuit. The address comparison circuit consists of multiple non-destructive readout units and a multi-layer fusion buffer. The input of the non-destructive readout unit is the read address of the read control circuit, the clock is the write address of the write control circuit, and the clear signal is the read clock transmitted by the control circuit. When the read and write addresses are equal, after the read control circuit generates the address, it first clears all the non-destructive readout units in the address comparison circuit. Then, the read address is sent to all the non-destructive readout units in the address comparison circuit. After the write address generator outputs a set of addresses, it sends the address to the clock circuit of all the non-destructive readout units in the address comparison circuit. When the read and write addresses are equal, one of the non-destructive readout units in the address comparison circuit will have both data and clock, so it will output a pulse. This pulse is output after passing through the multi-layer fusion buffer. The flag comparison circuit consists of a non-destructive readout unit and an XOR gate. The input of the non-destructive readout unit is the read address flag of the read control circuit, the clock of the non-destructive readout unit is the write clock, and the clear circuit is the read clock. The inputs of the XOR gate are the write address flag and the output of the non-destructive readout unit, respectively, and the clock is the write clock. After the read control circuit generates a read flag, it sends it to the non-destructive readout unit of the flag comparison circuit. After the write clock arrives, it reads the non-destructive readout unit of the flag comparison circuit. By controlling the delay, the clock of the XOR gate arrives at the XOR gate after all the inputs of the XOR gate have arrived. When the inputs of the XOR gate are different, that is, when the read and write address flags are different, an output is generated. The data input to the full flag generation circuit is the output of the flag comparison circuit, the clock is the output of the address comparison circuit, and the clear circuit is the write clock. The write clock first arrives at the D flip-flop of the full flag generation circuit to clear it once, then the output of the flag comparison circuit arrives, and then the output of the address comparison circuit arrives. If the data and the clock arrive within one write clock cycle, an output will be generated. The clock-gated circuit consists of multiple D flip-flops and non-destructive readout units. The inputs of the non-destructive readout units are a reset signal and a full flag signal after passing through two stages of D flip-flops. The clock is a directly input write clock, and the clear signal is the full flag signal. The non-destructive readout units of the clock-gated circuit directly control the clock. When there is data in the non-destructive readout unit, the clock can be applied to the D flip-flops that store the write signal after passing through the non-destructive readout unit. When there is no data in the non-destructive readout unit, the clock is shielded, and the write circuit stops working. The read control circuit consists of an address generation circuit, an address register, a null detection circuit, and a clock gating circuit. The address generation circuit, address register, and clock gating circuit of the read control circuit are composed of the same components and working principle as the address generation circuit, address register, and clock gating circuit of the write control circuit described above. The empty circuit has an additional NOT gate in its flag comparison circuit. The write address flag is inverted once before entering the non-destructive read unit. The NOT gate clock is the write clock. The rest of the empty circuit is the same as the full circuit of the write control circuit.

2. The superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO as described in claim 1, characterized in that, The process of generating the write address and write flag based on the write signal in step 1 is as follows: the write flag and write address are reset according to the initialization signal. After that, the write address is incremented by one every time the FIFO receives a write signal. After the write address is incremented a specified number of times, the write flag is inverted and the write address is reset. The process of generating the read address and read flag in step 3 is as follows: the read flag and read address are reset according to the initialization signal. After that, the read address is incremented by one every time the FIFO receives a read signal. After the read address is incremented a specified number of times, the read flag is inverted and the read address is reset.

3. The superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO as described in claim 1, characterized in that, Both the write address and the read address use one-hot encoding.

4. A superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO, characterized in that, include: The write module is used to initialize the FIFO. An external write circuit inputs a write signal to the FIFO. The FIFO generates a write address and a write flag based on the write signal and compares them with the read address and read flag. If the read address and write address are equal, but the write flag and read flag are reversed, the first waiting module is called. Otherwise, write the data to be written to the FIFO according to the write address; The first waiting module is used to wait for the external read circuit to read data and generate a new read flag and read address, and then write the data to be written into the FIFO according to the write address. The read module is used by the external read circuit to input a read signal to the FIFO and generate a read address and a read flag. It compares the read address and the write flag with the write address and the write flag. If the read address and the write address are the same, and the read flag and the write flag are also the same, the second waiting module is called. Otherwise, the data is read according to the read address and returned to the external read circuit. The second waiting module is used to wait for the external write circuit to write data and generate a new write address and write flag, and then read the data according to the read address and return to the external read circuit. The FIFO includes a register file, read control circuitry, and write control circuitry. The write control circuit consists of an address generator, an address register, a data register, a full-time detection circuit, and a clock gating circuit. This address generator consists of multiple D flip-flops, an rtffl, and a non-destructive read unit. When a reset signal arrives, it clears all cells within the address generator and inputs a pulse to the least significant D flip-flop. With each clock cycle, this pulse shifts upwards by one bit. Simultaneously with the arrival of the clock, the outputs of all D flip-flops form an address group, where only the D flip-flop containing the pulse outputs 1, and the rest output 0. After the pulse reaches the most significant D flip-flop, the next clock cycle outputs a pulse to the clear input of the rtffl and non-destructive read unit, clearing the non-destructive read unit. If this is the odd-numbered pulse arriving at the rtffl, the rtffl will output a pulse to the non-destructive read unit; otherwise, it will not output. When there is a pulse in the non-destructive read unit, it will output a pulse with each clock cycle. The output of this address generator is the address output by all D flip-flops and the address flag output by the non-destructive read unit. This address register consists of multiple D flip-flops. Its input is the address output by the address generator, and it outputs the stored address when the clock arrives. This data register consists of multiple D flip-flops. The input is a multi-bit data provided externally, and the multi-bit data will be output when the clock arrives. The full-value detection circuit consists of an address comparison circuit, a flag comparison circuit, and a full flag generation circuit. The address comparison circuit consists of multiple non-destructive readout units and a multi-layer fusion buffer. The input of the non-destructive readout unit is the read address of the read control circuit, the clock is the write address of the write control circuit, and the clear signal is the read clock transmitted by the control circuit. When the read and write addresses are equal, after the read control circuit generates the address, it first clears all the non-destructive readout units in the address comparison circuit. Then, the read address is sent to all the non-destructive readout units in the address comparison circuit. After the write address generator outputs a set of addresses, it sends the address to the clock circuit of all the non-destructive readout units in the address comparison circuit. When the read and write addresses are equal, one of the non-destructive readout units in the address comparison circuit will have both data and clock, so it will output a pulse. This pulse is output after passing through the multi-layer fusion buffer. The flag comparison circuit consists of a non-destructive readout unit and an XOR gate. The input of the non-destructive readout unit is the read address flag of the read control circuit, the clock of the non-destructive readout unit is the write clock, and the clear circuit is the read clock. The inputs of the XOR gate are the write address flag and the output of the non-destructive readout unit, respectively, and the clock is the write clock. After the read control circuit generates a read flag, it sends it to the non-destructive readout unit of the flag comparison circuit. After the write clock arrives, it reads the non-destructive readout unit of the flag comparison circuit. By controlling the delay, the clock of the XOR gate arrives at the XOR gate after all the inputs of the XOR gate have arrived. When the inputs of the XOR gate are different, that is, when the read and write address flags are different, an output is generated. The data input to the full flag generation circuit is the output of the flag comparison circuit, the clock is the output of the address comparison circuit, and the clear circuit is the write clock. The write clock first arrives at the D flip-flop of the full flag generation circuit to clear it once, then the output of the flag comparison circuit arrives, and then the output of the address comparison circuit arrives. If the data and the clock arrive within one write clock cycle, an output will be generated. The clock-gated circuit consists of multiple D flip-flops and non-destructive readout units. The inputs of the non-destructive readout units are a reset signal and a full flag signal after passing through two stages of D flip-flops. The clock is a directly input write clock, and the clear signal is the full flag signal. The non-destructive readout units of the clock-gated circuit directly control the clock. When there is data in the non-destructive readout unit, the clock can be applied to the D flip-flops that store the write signal after passing through the non-destructive readout unit. When there is no data in the non-destructive readout unit, the clock is shielded, and the write circuit stops working. The read control circuit consists of an address generation circuit, an address register, a null detection circuit, and a clock gating circuit. The address generation circuit, address register, and clock gating circuit of the read control circuit are composed of the same components and working principle as the address generation circuit, address register, and clock gating circuit of the write control circuit described above. The empty circuit has an additional NOT gate in its flag comparison circuit. The write address flag is inverted once before entering the non-destructive read unit. The NOT gate clock is the write clock. The rest of the empty circuit is the same as the full circuit of the write control circuit.

5. The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO as described in claim 4, characterized in that, The write module is used to generate a write address and a write flag based on the write signal. Specifically, the write flag and write address are reset according to the initialization signal. After that, the write address is incremented by one every time the FIFO receives a write signal. After the write address is incremented a specified number of times, the write flag is inverted and the write address is reset. The process of generating the read address and read flag in this read module is as follows: the read flag and read address are reset according to the initialization signal. After that, the read address is incremented by one every time the FIFO receives a read signal. After the read address is incremented a specified number of times, the read flag is inverted and the read address is reset.

6. The superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO as described in claim 5, characterized in that, Both the write address and the read address use one-hot encoding.

7. A storage medium for storing a program for executing the superconducting single-flux quantum cross-clock domain communication method based on asynchronous FIFO as described in any one of claims 1 to 3.

8. A client for the superconducting single-flux quantum cross-clock domain communication system based on asynchronous FIFO as described in any one of claims 4 to 6.

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