Display panel and display device

Abstract

The present disclosure relates to a display panel and a display device, the display panel comprising: a silicon-based substrate, a driving layer, a first electrode layer, an organic light-emitting layer, a second electrode layer, and a plurality of pads. The driving layer is formed in the silicon-based substrate and comprises a plurality of first transistors located in the display area; each first electrode is electrically connected to each first transistor; the second electrode layer is on the side of the organic light-emitting layer away from the driving layer; a plurality of pads are located in the peripheral area of ​​at least one side of the display area, the plurality of pads comprise a display signal access pad and a test signal access pad, the display signal access pad is arranged along a first direction, the display signal access pad comprises a first end and a second end along the first direction, the test signal access pad is located in the end area of ​​the display signal access pad in the first direction; the test signal access pad comprises at least a first pad and a third pad, and in the first direction, the first pad and the third pad do not overlap.

Description

[0001] This application is a divisional application. The application number of the original application is 202080000385.5, the application date is March 27, 2020, and the name of the invention is “Display panel and display device”. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] OLED (Organic Light Emitting Display) display devices have many advantages such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, nearly 180° viewing angle, wide operating temperature range, flexible display and large-area full-color display, etc., and are considered to be the most promising new generation display technology. However, OLED display devices are developing in the direction of miniaturization.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure aims to provide a display panel and a display device.

[0006] According to one aspect of the present disclosure, there is provided a display panel, the display panel comprising:

[0007] A silicon-based substrate, comprising a display area and a peripheral area surrounding the display area;

[0008] A driving layer, formed in the silicon-based substrate and comprising a plurality of first transistors located in the display area;

[0009] A first electrode layer is provided on a side of the driving layer away from the silicon-based substrate, and comprises a plurality of first electrodes located in the display area, each of the first electrodes being electrically connected to each of the first transistors;

[0010] an organic light-emitting layer, disposed on a side of the first electrode layer away from the driving layer;

[0011] A second electrode layer is disposed on a side of the organic light emitting layer away from the driving layer;

[0012] A plurality of pads are located in the peripheral area on at least one side of the display area, the plurality of pads include display signal access pads and test signal access pads, the display signal access pads are arranged along a first direction, the display signal access pads include a first end and a second end along the first direction, and the test signal access pads are located in the end area of ​​the display signal access pads in the first direction; the test signal access pads include at least a first pad and a third pad, and in the first direction, the first pad and the third pad do not overlap.

[0013] In an exemplary embodiment of the present disclosure, in the first direction, the third pad overlaps with the display signal access pad.

[0014] In an exemplary embodiment of the present disclosure, the area of ​​the first pad is smaller than the area of ​​the display signal access pad.

[0015] In an exemplary embodiment of the present disclosure, an area of ​​the first pad is smaller than an area of ​​the third pad.

[0016] In an exemplary embodiment of the present disclosure, in a second direction perpendicular to the first direction, a distance between the third pad and an edge of the silicon-based substrate is smaller than a distance between the first pad and an edge of the silicon-based substrate.

[0017] In an exemplary embodiment of the present disclosure, the test signal access pad includes a first group of test phase access pads, the first group of test phase access pads includes the first pad and the second pad; the second electrode layer includes a second electrode located in the display area and an electrode ring located in the peripheral area, the electrode ring surrounds the second electrode and is connected to the second electrode; the first pad is electrically connected to the electrode ring, and the second pad is electrically connected to the silicon-based substrate.

[0018] In an exemplary embodiment of the present disclosure, the test signal access pad also includes a second group of test phase access pads, and the second group of test phase access pads includes the third pad and the fourth pad; in the first direction, the second pad and the fourth pad do not overlap, and the fourth pad overlaps with the display signal access pad; the third pad is electrically connected to the electrode ring, and the fourth pad is electrically connected to the silicon-based substrate.

[0019] In an exemplary embodiment of the present disclosure, the first pad and the third pad are located at the first end of the display signal access pad, and the second pad and the fourth pad are located at the second end of the display signal access pad.

[0020] In an exemplary embodiment of the present disclosure, the third pad and the fourth pad are respectively disposed adjacent to the display signal access pad.

[0021] In an exemplary embodiment of the present disclosure, the peripheral area includes a binding region, and the third pad, the fourth pad, and the display signal access pad are located in the binding region.

[0022] In an exemplary embodiment of the present disclosure, the display panel is provided with one first pad and one second pad.

[0023] In an exemplary embodiment of the present disclosure, the third pad is electrically connected to the first pad, and the fourth pad is electrically connected to the second pad.

[0024] In an exemplary embodiment of the present disclosure, the test signal access pad is arranged in the same layer as the first electrode.

[0025] In an exemplary embodiment of the present disclosure, the driving layer further includes:

[0026] A connecting line electrically connected to the second pad and the fourth pad;

[0027] A plurality of detection lines are connected to the connection lines, and each of the detection lines is electrically connected to an active region of a column of the transistors.

[0028] In an exemplary embodiment of the present disclosure, the first pad is electrically connected to the electrode ring through a wire.

[0029] In an exemplary embodiment of the present disclosure, each of the first transistors includes an active area formed in the silicon-based substrate, two doped regions located in the active area, a channel region located between the two doped regions, and a gate located on the channel region, the two doped regions respectively form a first pole and a second pole, and the second pad is electrically connected to the active area of ​​each of the first transistors.

[0030] In an exemplary embodiment of the present disclosure, the driving layer further includes:

[0031] A gate insulating layer, disposed on the channel region on one side of the silicon-based substrate;

[0032] A gate layer, disposed on a side of the gate insulating layer away from the silicon-based substrate;

[0033] A first planar layer, disposed on one side of the silicon-based substrate and covering the gate insulating layer and the gate layer;

[0034] A first conductive layer, disposed on a side of the first planar layer away from the silicon-based substrate;

[0035] a dielectric layer, disposed on a side of the first planar layer away from the silicon-based substrate and covering the first conductive layer;

[0036] A second conductive layer is provided on a side of the dielectric layer away from the silicon-based substrate;

[0037] The second planar layer is arranged on a side of the dielectric layer away from the silicon-based substrate and covers the second conductive layer. The first electrode layer is located on a side of the second planar layer away from the silicon-based substrate.

[0038] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0039] The second transistor is formed in the peripheral area of ​​the silicon-based substrate and includes an active area formed in the silicon-based substrate, two doped areas located in the active area, a channel area located between the two doped areas, and a gate located on the channel area, and the two doped areas respectively form a first electrode and a second electrode; the second electrode of the second transistor is electrically connected to the electrode ring, and the first pad is electrically connected to the first electrode and the gate of the second transistor.

[0040] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0041] A first encapsulation layer is provided on a side of the second electrode layer away from the organic light-emitting layer;

[0042] A color filter layer, disposed on a side of the first packaging layer away from the second electrode layer;

[0043] The second packaging layer is disposed on a side of the color filter layer away from the first packaging layer, and the third pad and the fourth pad are exposed from the second packaging layer.

[0044] According to another aspect of the present disclosure, a display device is provided. The display device includes the above-mentioned display panel.

[0045] The display panel provided by the present disclosure is connected to the electrode ring through the first pad, thereby realizing the connection with the second electrode; each first electrode is connected to a first transistor, and the silicon-based substrate corresponding to each first transistor is connected to the second pad; a test signal is input through the first pad and the second pad to form a voltage difference between the first electrode and the second electrode, thereby lighting up the pixel unit, performing IVL test and collecting test data, and achieving the purpose of ILV test. In addition, when performing ILV test, it is only necessary to input the test signal to the first pad and the second pad. The first pad and the second pad are arranged in the peripheral area on the silicon-based substrate, occupying less space, which can meet the design of miniaturized silicon-based display panels.

[0046] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0048] Figure 1 A schematic diagram of a display panel provided for an embodiment of the present disclosure;

[0049] Figure 2 for Figure 1 A magnified part of the middle A area;

[0050] Figure 3 for Figure 1 Magnified part of the middle B area;

[0051] Figure 4 An embodiment of the present disclosure provides Figure 1 Sectional view of the middle CC plane;

[0052] Figure 5 Another embodiment of the present disclosure provides Figure 1 Sectional view of the middle CC plane;

[0053] Figure 6 A schematic diagram of connecting a test signal access pad to a first electrode and a second electrode provided by an embodiment of the present disclosure;

[0054] Figure 7 A schematic diagram of a circuit in which a first pad is electrically connected to an electrode ring according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0056] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0057] The terms "a", "an", "the", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second" are used merely as labels and are not intended to limit the quantity of their objects.

[0058] The applicant has found that with the increasing advancement of VR (Virtual Reality) / AR (Augmented Reality) technology and the rapid growth of the market, display panels suitable for the VR / AR field are also accelerating their pace towards miniaturization, high PPI, fast response and high color gamut, and silicon-based OLED display panels are becoming a new focus in the VR / AR field due to their advantages of miniaturization and high PPI.

[0059] However, existing IVL test (characteristic curve test of current, voltage and brightness) and other test methods are difficult to implement on miniaturized display panels. Specifically, after the OLED is evaporated, an Inline IVL (characteristic curve test of intracavity current, voltage and brightness) test is required. The probe of the Probe Board can be inserted into the Pin of the CP (Chip Probe, chip probe), and the test signal is input for IVL test; however, there are multiple pairs of pads on the CP, and the IVL test is only one of the pairs of pads. Due to the limitation of the layout, there is no area for designing the CP. In addition, in the existing design, after completing the IVL test, it is necessary to go through a primary encapsulation, color glue, secondary encapsulation and CG (cover glass) patch. The CP is covered with multiple layers of organic and inorganic materials, and the test signal cannot be input through the Pin on the CP. In addition, MIT (module detection) can only be tested by inserting the probe of the Probe Board into the 5 pads on the FPC / PCB bonding (binding pads) used to achieve normal display.

[0060] In this exemplary embodiment, a display panel is first provided. Figure 1-Figure 7 As shown, the display panel 10 includes: a silicon-based substrate 20, a driving layer 30, a first electrode layer, an organic light-emitting layer 60, a second electrode layer 70, and a plurality of pads. The silicon-based substrate 20 includes a display area and a peripheral area surrounding the display area; the driving layer 30 is formed in the silicon-based substrate 20 and includes a plurality of first transistors located in the display area; the first electrode layer is arranged on the side of the driving layer 30 away from the silicon-based substrate 20, and includes a plurality of first electrodes 40 located in the display area, each first electrode 40 being electrically connected to each first transistor; the organic light-emitting layer 60 is arranged on the side of the first electrode layer away from the driving layer 30; the second electrode layer 70 is arranged on the side of the organic light-emitting layer 60 away from the driving layer 30; a plurality of pads are located in the peripheral area of ​​at least one side of the display area, the plurality of pads include a display signal access pad and a test signal access pad, the display signal access pad is arranged along the first direction X, the display signal access pad includes a first end and a second end along the first direction X, and the test signal access pad is located in the end area of ​​the display signal access pad in the first direction X; as shown Figure 2 As shown, the test signal access pads at least include a first pad 51 and a third pad 53. In the first direction X, the first pad 51 and the third pad 53 do not overlap.

[0061] Among them, Figure 2 As shown, in the first direction X, the third pad 53 overlaps with the display signal access pad (binding pad 41 ).

[0062] Among them, Figure 2 As shown, the area of ​​the first pad 51 is smaller than the area of ​​the display signal access pad (binding pad 41).

[0063] Among them, Figure 2 As shown, in the second direction Y perpendicular to the first direction X, the distance between the third pad 53 and the edge of the silicon-based substrate 20 is smaller than the distance between the first pad 51 and the edge of the silicon-based substrate 20, that is, the third pad 53 is closer to the edge of the silicon-based substrate 20 than the first pad 51.

[0064] The display signal access pad is configured to access the display signal in the display phase, the test signal access pad is configured to access the test signal in the test phase, and the test signal access pad includes at least a first group of test phase access pads. Figure 3 As shown, the first group of test phase access pads includes a first pad 51 and a second pad 52. The second electrode layer 70 includes a second electrode 720 located in the display area and an electrode ring 710 located in the peripheral area, the electrode ring 710 surrounds the second electrode 720 and is connected to the second electrode 720, the first pad 51 is electrically connected to the electrode ring 710, and the second pad 52 is electrically connected to the silicon-based substrate.

[0065] For example, when the display panel is subjected to IVL test, the second pad 52 is connected to the VDD (+5V DC voltage) test signal and the first pad 51 is connected to the Vcom (-2.5V DC voltage) test signal, wherein VDD is connected to the silicon-based substrate area corresponding to each first transistor through a wiring, and the PN junction is turned on by forward bias, so that the VDD test signal is given to the first electrode 40; at the same time, Vcom gives the test signal to the second electrode 720 through the electrode ring 710, so that a voltage difference is formed between the first electrode 40 and the second electrode 720, thereby lighting up the pixel unit, so as to perform IVL test and collect test data, thereby achieving the purpose of ILV test.

[0066] The display panel provided by the present disclosure is connected to the electrode ring 710 through the first pad 51, thereby realizing the connection with the second electrode 720; each first electrode 40 is connected to a first transistor, and the silicon-based substrate corresponding to each first transistor is connected to the second pad 52; a test signal is input through the first pad 51 and the second pad 52, so that a voltage difference is formed between the first electrode 40 and the second electrode 720, thereby lighting up the pixel unit, performing IVL test and collecting test data, and achieving the purpose of ILV test. In addition, when performing ILV test, it is only necessary to input the test signal to the first pad 51 and the second pad 52. The first pad 51 and the second pad 52 are arranged in the peripheral area on the silicon-based substrate 20, occupying less space, which can meet the design of miniaturized silicon-based display panels.

[0067] Specifically, Figure 4 As shown, the silicon-based substrate 20 constitutes a silicon-based OLED display panel. The embodiment of the present disclosure provides a top-emitting silicon-based OLED display panel. C1 in the figure refers to a first transistor. Each first transistor includes an active area 380 formed in the silicon-based substrate, two doping regions located in the active area 380, a channel area located between the two doping regions, and a gate 320 located on the channel area. The two doping regions form a first electrode 310 and a second electrode 330, respectively. The second pad 52 is electrically connected to the active area 380 of each first transistor.

[0068] For example, the first transistor is a P-type MOS transistor, the active area 380 is an N-type doped area, the first electrode 310 and the second electrode 320 are P-type doped areas on the silicon-based substrate, the second electrode 330 of the first transistor is a drain, and the first electrode 310 is a source. The silicon-based substrate corresponding to each first transistor is the active area 380 of the first transistor, and the VDD test signal is connected to the active area 380 of the first transistor through the second pad 52, and the PN junction is turned on by forward bias, so that the VDD test signal is given to the anode. Among them, the electrode ring 710 is a cathode ring, and the cathode ring is a ring-shaped wiring that provides a cathode common voltage (negative) on the periphery of the display area. When the cathode is evaporated, it covers the display area and is overlapped on the cathode ring, thereby providing a negative voltage for the common cathode of the entire display area.

[0069] For example, Figure 4 As shown, the drain of the first transistor is connected to the first electrode 40 through the second conductive layer 350 and the first conductive layer 340. The arrangement of the second conductive layer 350 and the first conductive layer 340 can reduce the wiring area and improve the resolution. The first electrode 40 and the second conductive layer 350, the second conductive layer 350 and the first conductive layer 340, and the first conductive layer 340 and the second electrode 330, the gate 320 and the first electrode 310 are electrically connected through contact holes 360, respectively. Optionally, the contact holes 360 are tungsten holes.

[0070] Specifically, Figure 4 C2 refers to a second transistor electrically connected to the electrode ring 710. The second transistor is formed in the peripheral area of ​​the silicon-based substrate, including an active area formed in the silicon-based substrate, two doping areas located in the active area, a channel area located between the two doping areas, and a gate 393 located on the channel area. The two doping areas form a first electrode 391 and a second electrode 392, respectively. Figure 7 As shown, the second electrode 392 of the second transistor is electrically connected to the electrode ring 710, and the first pad 51 is electrically connected to the first electrode 391 and the gate 393 of the second transistor. The first pad 51 is electrically connected to the first electrode 391 and the gate 393 of the second transistor, so that Vcom is transmitted to the second electrode 720 through the electrode ring 710, so that a voltage difference is formed between the first electrode 40 and the second electrode 720, and then the pixel unit is lit to perform IVL test and collect test data, so as to achieve the purpose of ILV test. Among them, the first electrode 391 can be a source electrode, and the second electrode 392 can be a drain electrode.

[0071] For example, the first pad 51 can also be electrically connected to the electrode ring 710 through a wire, so that Vcom is transmitted to the second electrode 720 through the electrode ring 710, so that a voltage difference is formed between the first electrode 40 and the second electrode 720, and then the pixel unit is lit to perform IVL testing and collect test data, thereby achieving the purpose of ILV testing. In addition, the first pad 51 is directly electrically connected to the electrode ring 710 through a wire, which reduces the process difficulty.

[0072] like Figure 4 As shown, the test signal access pad also includes a second group of test phase access pads, and the second group of test phase access pads includes a third pad 53 and a fourth pad 54 , the third pad 53 is electrically connected to the electrode ring 710 , and the fourth pad 54 is electrically connected to the silicon-based substrate 20 .

[0073] Among them, Figure 3 As shown, in the first direction X, the second pad 52 and the fourth pad 54 do not overlap, and the fourth pad 54 overlaps with the display signal access pad (binding pad 41).

[0074] Among them, Figure 2 and Figure 3 As shown, the first pad 51 and the third pad 53 are located at the first end of the display signal access pad, and the second pad 52 and the fourth pad 54 are located at the second end of the display signal access pad.

[0075] The display panel provided by the present disclosure has a third pad 53 and a fourth pad 54 located in the peripheral area and can be exposed from the packaging layer of the display panel. Only the third pad 53 and the fourth pad 54 are required for MIT testing of the display panel, thereby reducing the pin angle required for MIT testing, thereby reducing the required probes and reducing costs.

[0076] Specifically, the peripheral area of ​​the silicon-based substrate 20 includes a binding area, and the third pad 53, the fourth pad 54 and a plurality of display signal access pads are located in the binding area, and the display signal access pad is the binding pad (Bonding Pad) 41. Since the display panel is covered with multiple layers of organic and inorganic materials during the packaging process, the first pad 51 and the second pad 52 will be covered, and the MIT test cannot be performed through the first pad 51 and the second pad 52 after packaging. Therefore, the third pad 53, the fourth pad 54 and a plurality of display signal access pads can be formed in the binding area at the same time, and the third pad 53 and the fourth pad 54 should be made into a photoresist layer together with other binding pads 41, and then the photoresist layer is ablated cleanly together with the organic and inorganic materials in the evaporation and packaging process by laser ablation, so that the metal on the surface of each pad is exposed to meet the need of the MIT test probe card. The third pad 53 is electrically connected to the electrode ring 710 , and the fourth pad 54 is electrically connected to the silicon-based substrate, so that the MIT test is performed through the third pad 53 and the fourth pad 54 .

[0077] like Figure 1-Figure 3 As shown, the third pad 53 and the fourth pad 54 are respectively arranged adjacent to the display signal access pad. A plurality of binding pads 41 are arranged on the binding area on one side of the silicon-based substrate 20, and each binding pad 41 is located between the third pad 53 and the fourth pad 54. The third pad 53 and the fourth pad 54 are arranged in the binding area and at both ends of the binding pad 41, which will not affect the layout of the binding pad 41. The third pad 53 and the fourth pad 54 can be exposed with the binding pad 41 through the same laser ablation process, which reduces the process difficulty and process cost.

[0078] like Figure 1 As shown, the first pad 51, the second pad 52, the third pad 53 and the fourth pad 54 are located between the binding pad 41 and the FPC Mark (flexible circuit board reference point), and the Mark provides a common locatable circuit pattern for all steps in the FPC flexible circuit board assembly process.

[0079] Specifically, Figure 1 As shown, the display panel 10 is provided with only one first pad 51 and one second pad 52, and the second pad 52 is electrically connected to the active area of ​​each MOS transistor. IVL testing can be implemented with only two pads, so that the number of pads is minimized, which facilitates the arrangement of the first pad 51 and the second pad 52 on the silicon-based substrate 20.

[0080] Specifically, Figure 1 As shown, the display panel 10 is provided with only one third pad 53 and one fourth pad 54, and the fourth pad 54 is electrically connected to the active area of ​​each MOS transistor. The MIT test can be implemented by only two pads, so that the number of pads is minimized, which facilitates the arrangement of the third pad 53 and the fourth pad 54 on the silicon-based substrate 20.

[0081] Specifically, the third pad 53 is connected to the first pad 51. Figure 2 As shown, the third pad 53 and the first pad 51 can be located on the same side of the silicon-based substrate 20. After the first pad 51 is connected to the electrode ring 710 through a wire, the third pad 53 can be connected to the first pad 51 through a wire, thereby indirectly connecting to the electrode ring 710, which can reduce the wires connecting the electrode ring 710, thereby reducing the difficulty of the manufacturing process of the display panel 10.

[0082] Specifically, the fourth pad 54 is connected to the second pad 52. Figure 3 As shown, the fourth pad 54 and the second pad 52 can be located on the same side of the silicon-based substrate 20. After the second pad 52 is connected to each first electrode 40 through a wire, the fourth pad 54 can be connected to the second pad 52 through a wire, thereby indirectly connecting to each first electrode 40, which can reduce the wires connecting each first electrode 40, thereby reducing the difficulty of the manufacturing process of the display panel 10.

[0083] Specifically, Figure 4 As shown, the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 are arranged in the same layer as the first electrode 40. By making the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 and the first electrode 40 in the same layer, the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 and the first electrode 40 can be formed by the same process, which facilitates the formation of the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54, and reduces the difficulty of the manufacturing process of the display panel 10.

[0084] Specifically, Figure 6As shown, the driving layer 30 also includes: a connecting line 381 and a plurality of detection lines 382. The connecting line 381 is electrically connected to the second pad 52 and the fourth pad 54; a plurality of detection lines 382 are connected to the connecting line 381, and each detection line 382 is electrically connected to the active area of ​​a column of first transistors. Among them, the plurality of detection lines 382 are arranged in a mesh, which can reduce the impact of loading.

[0085] Specifically, the driving layer 30 includes: a gate insulating layer 370, a gate layer, a first flat layer, a first conductive layer 340, a dielectric layer, a second conductive layer 350 and a second flat layer. The gate insulating layer 370 is arranged on one side of the silicon-based substrate 20; the gate layer is arranged on the side of the gate insulating layer 370 away from the silicon-based substrate 20; the first flat layer is arranged on one side of the silicon-based substrate 20 and covers the gate insulating layer 370 and the gate layer; the first conductive layer 340 is arranged on the side of the first flat layer away from the silicon-based substrate 20; the dielectric layer is arranged on the side of the first flat layer away from the silicon-based substrate 20 and covers the first conductive layer 340; the second conductive layer 350 is arranged on the side of the dielectric layer away from the silicon-based substrate 20; the second flat layer is arranged on the side of the dielectric layer away from the silicon-based substrate 20 and covers the second conductive layer 350, and the first electrode layer is located on the side of the second flat layer away from the silicon-based substrate 20. Among them, the connecting line 381 and each detection line 382 can be arranged on the same layer as the first conductive layer 340. Of course, the connecting line 381 and each detection line 382 may be arranged in layers, and each detection line 382 may be arranged in the same layer as the first conductive layer 340; or, the connecting line 381, each detection line 382 and the first conductive layer 340 may be arranged in layers separately, which is not limited in the present disclosure.

[0086] Specifically, Figure 4 As shown, the display panel further includes a pixel definition layer (PDL) 42, and the pixel definition layer 42 is formed with a plurality of openings, and each first electrode 40 is disposed in each opening in a one-to-one correspondence. In addition, a PDL is disposed between the electrode for connecting the second transistor and the electrode ring 710 and the adjacent first electrode 40 to insulate the electrode from the adjacent first electrode 40.

[0087] For example, the silicon-based OLED display panel provided by the present disclosure may be a white light OLED display panel, and the organic light emitting layer 60 includes a red light emitting layer, a green light emitting layer, and a blue light emitting layer stacked in sequence. Of course, the stacking order of the red light emitting layer, the green light emitting layer, and the blue light emitting layer may be changed.

[0088] Specifically, Figure 5As shown, the display panel 10 further includes a first encapsulation layer 81, a color filter layer 90 and a second encapsulation layer 82. A photoresist layer is provided on the third pad 53 and the fourth pad 54, and then laser ablation is performed to burn out the photoresist layer together with the first encapsulation layer 81, the color filter layer 90 and the second encapsulation layer 82, so that the surfaces of the third pad 53 and the fourth pad 54 are exposed, meeting the need for piercing of the MIT test probe card.

[0089] Specifically, the display panel 10 further includes a cover glass (not shown in the figure), and the cover glass is disposed on a side of the second encapsulation layer 82 away from the color filter layer 90 .

[0090] The embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel. The beneficial effects of the display device can refer to the beneficial effects of the above-mentioned display panel, which will not be repeated here. The display device can be, for example, a head-mounted display device such as VR / AR.

[0091] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that: include: A silicon-based substrate, comprising a display area and a peripheral area surrounding the display area; A driving layer, formed in the silicon-based substrate and comprising a plurality of first transistors located in the display area; A first electrode layer is provided on a side of the driving layer away from the silicon-based substrate, and comprises a plurality of first electrodes located in the display area, each of the first electrodes being electrically connected to each of the first transistors; an organic light-emitting layer, disposed on a side of the first electrode layer away from the driving layer; A second electrode layer is provided on a side of the organic light-emitting layer away from the driving layer; the second electrode layer comprises a second electrode located in the display area and an electrode ring located in the peripheral area, the electrode ring surrounds the second electrode and is connected to the second electrode; A plurality of pads are located in the peripheral area on at least one side of the display area, the plurality of pads include a display signal access pad and a test signal access pad, the display signal access pads are arranged along a first direction, the display signal access pads include a first end and a second end along the first direction, and the test signal access pads are located in the end area of ​​the display signal access pads in the first direction; the test signal access pads include at least a first pad and a third pad, and in the first direction, the first pad and the third pad do not overlap; the first pad is electrically connected to the electrode ring and is connected in the first test stage; the third pad is electrically connected to the electrode ring and is connected in the second test stage; in the first direction, the third pad overlaps with the display signal access pad.

2. The display panel according to claim 1, characterized in that: The area of ​​the first pad is smaller than the area of ​​the display signal access pad.

3. The display panel according to claim 1, characterized in that: An area of ​​the first pad is smaller than an area of ​​the third pad.

4. The display panel according to claim 1, characterized in that: In a second direction perpendicular to the first direction, a distance between the third pad and an edge of the silicon-based substrate is smaller than a distance between the first pad and an edge of the silicon-based substrate.

5. The display panel according to claim 1, characterized in that: The test signal access pads include a first group of test phase access pads, the first group of test phase access pads include the first pad and a second pad; the second pad is electrically connected to the silicon-based substrate.

6. The display panel according to claim 5, characterized in that: The test signal access pad also includes a second group of test phase access pads, and the second group of test phase access pads includes the third pad and the fourth pad; in the first direction, the second pad and the fourth pad do not overlap, and the fourth pad overlaps with the display signal access pad; the fourth pad is electrically connected to the silicon-based substrate.

7. The display panel according to claim 6, characterized in that: The first pad and the third pad are located at the first end of the display signal access pad, and the second pad and the fourth pad are located at the second end of the display signal access pad.

8. The display panel according to claim 7, characterized in that: The third pad and the fourth pad are respectively disposed adjacent to the display signal access pad.

9. The display panel according to claim 6, characterized in that: The peripheral area includes a binding region, and the third pad, the fourth pad, and the display signal access pad are located in the binding region.

10. The display panel according to claim 6, characterized in that: The display panel is provided with a first pad and a second pad.

11. The display panel according to claim 6, characterized in that: The third pad is electrically connected to the first pad, and the fourth pad is electrically connected to the second pad.

12. The display panel according to claim 1, characterized in that: The test signal access pad is arranged in the same layer as the first electrode.

13. The display panel according to claim 6, characterized in that: The driving layer also includes: A connecting line electrically connected to the second pad and the fourth pad; A plurality of detection lines are connected to the connection lines, and each of the detection lines is electrically connected to an active region of a column of the transistors.

14. The display panel according to claim 5, characterized in that: The first pad is electrically connected to the electrode ring through a wire.

15. The display panel according to claim 5, characterized in that: Each of the first transistors includes an active area formed in the silicon-based substrate, two doped regions located in the active area, a channel region located between the two doped regions, and a gate located on the channel region, the two doped regions respectively form a first pole and a second pole, and the second pad is electrically connected to the active area of ​​each of the first transistors.

16. The display panel according to claim 15, characterized in that: The driving layer also includes: A gate insulating layer, disposed on the channel region on one side of the silicon-based substrate; A gate layer, disposed on a side of the gate insulating layer away from the silicon-based substrate; A first planar layer, disposed on one side of the silicon-based substrate and covering the gate insulating layer and the gate layer; A first conductive layer, disposed on a side of the first planar layer away from the silicon-based substrate; a dielectric layer, disposed on a side of the first planar layer away from the silicon-based substrate and covering the first conductive layer; A second conductive layer is provided on a side of the dielectric layer away from the silicon-based substrate; The second planar layer is arranged on a side of the dielectric layer away from the silicon-based substrate and covers the second conductive layer. The first electrode layer is located on a side of the second planar layer away from the silicon-based substrate.

17. The display panel according to claim 5, characterized in that: The display panel further includes: The second transistor is formed in the peripheral area of ​​the silicon-based substrate and includes an active area formed in the silicon-based substrate, two doped areas located in the active area, a channel area located between the two doped areas, and a gate located on the channel area, and the two doped areas respectively form a first electrode and a second electrode; the second electrode of the second transistor is electrically connected to the electrode ring, and the first pad is electrically connected to the first electrode and the gate of the second transistor.

18. The display panel according to claim 6, characterized in that: The display panel further includes: A first encapsulation layer is provided on a side of the second electrode layer away from the organic light-emitting layer; A color filter layer, disposed on a side of the first packaging layer away from the second electrode layer; The second packaging layer is disposed on a side of the color filter layer away from the first packaging layer, and the third pad and the fourth pad are exposed from the second packaging layer.

19. A display device, characterized in that: A display panel comprising any one of claims 1-18.

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