A trench super-junction diode with mixed trench schottky and method of manufacture

Abstract

A hybrid trench Schottky trench-type superbarrier diode and its fabrication method are disclosed. This relates to the field of semiconductor technology. From bottom to top, the diode comprises: a cathode electrode layer, an N+ substrate layer, an N- epitaxial layer, wherein the N- epitaxial layer has a plurality of spaced-apart P-type implantation regions; each P-type implantation region includes conductive channels and P-body regions spaced-apart from top to bottom; a dielectric layer, a silicon dioxide layer, wherein the silicon dioxide layer has a plurality of trenches extending downward from its top to the P-body regions; and an anode electrode layer, the bottom of which extends to the P-body regions through trenches. This invention improves the on-resistance characteristics of the device during forward operation, thereby enhancing the device's performance and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a trench-type superbarrier diode of hybrid trench Schottky and its fabrication method. Background Technology

[0002] Super-barrier rectifiers (SBRs) are a new type of rectifier device that utilizes the MOSFET conduction principle to further reduce the forward voltage drop, while using a pn junction as the reverse cutoff, resulting in low reverse leakage current. Furthermore, SBRs only involve electron conduction, making them unipolar devices with short reverse recovery times and the ability to operate over a higher voltage range. Therefore, SBRs can achieve higher energy efficiency by replacing Schottky diodes and pn junction diodes over a wider voltage range. However, traditional SBR devices, due to the presence of only one type of charge carrier, have a higher on-resistance, leading to a higher voltage current (VF) at high currents. Summary of the Invention

[0003] To address the above problems, this invention provides a hybrid trench Schottky trench-type super-barrier diode that improves the on-resistance characteristics of the device during forward operation while ensuring reverse leakage current.

[0004] The technical solution of this invention is: a trench-type super-barrier diode of hybrid trench Schottky, comprising, from bottom to top:

[0005] Cathode electrode layer,

[0006] N+ substrate layer

[0007] An N-epitaxial layer is provided with a plurality of spaced P-type implantation regions; the P-type implantation regions include conductive channels and P-body regions spaced from top to bottom.

[0008] Dielectric layer,

[0009] A silicon dioxide layer, wherein the silicon dioxide layer has a plurality of trenches extending downward from its top to the P-body region; and

[0010] An anode electrode layer, the bottom of which extends into the P-body region via a trench.

[0011] Specifically, the middle part of the anode electrode layer extends downward into the N-epipolar layer to form an electrode layer extension.

[0012] Specifically, the electrode layer extension has an M-shaped structure.

[0013] Specifically, the spacing between the P-type injection regions is not less than 1.3 μm.

[0014] Specifically, the trench has a rectangular structure.

[0015] A method for fabricating a hybrid trench Schottky trench-type superbarrier diode includes the following steps:

[0016] 100) Provide an N+ substrate layer, and form an N-type lightly doped N- epitaxial layer on the surface of the N+ substrate layer;

[0017] 200) A dielectric layer is formed on the surface of the N-epitaxial layer;

[0018] 300) Deposit a phosphorus-doped polycrystalline silicon layer on the dielectric layer;

[0019] 400) The phosphorus-doped polycrystalline silicon layer is etched downwards through photolithography to extend to the top surface of the N-epitaxial layer, forming several side trenches.

[0020] 500) A P-type implantation region is formed in the side upper trench using boron difluoride and boron ion implantation processes; the P-type implantation region includes a conductive channel and a P-body region;

[0021] 600) Several central upper trenches are etched on the upper surface of the phosphorus-doped polycrystalline silicon layer using an etching process.

[0022] 700) Using an etching process, the side upper trench and the middle upper trench are etched downwards respectively, with the etching extending to the P-body region;

[0023] 800) An anode electrode layer is prepared on top of a phosphorus-doped polycrystalline silicon layer by a metal deposition process, and extends into the N-epitaxial layer through corresponding side upper trenches and middle upper trenches;

[0024] 900), a cathode electrode layer is prepared on the back side and thinned to form a surface contact.

[0025] Step 500) The specific preparation steps are as follows:

[0026] 510) Boron is formed through multiple high-energy ion implantations of different energies.

[0027] 520) A p-type doped conductive channel is formed by low-energy ion implantation of boron difluoride, followed by thermal annealing.

[0028] Specifically, the thickness of the phosphorus-doped polysilicon layer is 2000 Å, which forms a MOS structure with the dielectric layer and the P-type doped channel.

[0029] The present invention has the following advantages:

[0030] 1. The introduction of a superjunction design in the P-body region (introducing the PN junction into the N-epitaxial layer region, breaking the silicon limit) reduces the reverse leakage current and at the same time reduces the forward conduction resistance and the forward conduction voltage.

[0031] 2. Introducing a Schottky structure into the trench sidewall increases the effective area of ​​the product. Furthermore, the parallel addition of the trench Schottky structure effectively reduces VF under high current. Compared with conventional products, VF can be reduced by about 10%, thus reducing the product's power consumption.

[0032] 3. Since the Schottky diode is also a unipolar device, it does not affect the device's dynamic characteristics. Therefore, compared to ordinary super-barrier diodes, the new structure improves the on-resistance characteristics during forward operation while ensuring reverse leakage current, thus enhancing the device's performance and reliability.

[0033] 4. This structure is as follows Figure 1 First, reverse leakage current is reduced by injecting through a PN junction. Then, a Schottky structure is added by adding parallel connections after trench etching, which effectively reduces VF under high current. At the same time, Schottky is also a unipolar device, so it does not affect the dynamic characteristics of the device. Attached Figure Description

[0034] Figure 1 This is a structural diagram of step 200.

[0035] Figure 2 This is a structural diagram of step 300.

[0036] Figure 3 This is a structural diagram of step 400.

[0037] Figure 4 This is a structural diagram of step 500.

[0038] Figure 5 This is a structural diagram of step 600.

[0039] Figure 6 This is a structural diagram of step 700.

[0040] Figure 7 This is a structural diagram of step 800.

[0041] Figure 8 This is a structural diagram of step 900.

[0042] In the figure, 1 is the anode electrode layer, 2 is the dielectric layer, 3 is the N- epitaxial layer, 4 is the N+ substrate layer, 5 is the cathode electrode layer, 6 is the conductive channel, 7 is the trench, 8 is the P-body region, 9 is the electrode layer extension, and 11 is the phosphorus-doped polycrystalline silicon layer. Detailed Implementation

[0043] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] The present invention is as follows Figure 1-8 As shown;

[0045] A hybrid trench Schottky trench-type super-barrier diode, comprising, from top to bottom:

[0046] Cathode electrode layer 5,

[0047] N+ substrate layer 4,

[0048] N-epitaxy layer 3, wherein a plurality of P-type implantation regions are provided on the N-epitaxy layer 3 at intervals; the P-type implantation regions include conductive channels 6 and P-body regions 8 arranged at intervals from top to bottom;

[0049] P-type doped conductive channels form a super-barrier MOS structure; while the P-body region is a PN junction, which can effectively reduce reverse leakage current and improve breakdown voltage. P-type doped conductive channels require short channel length and shallow junction depth to reduce the threshold voltage. The P-body region requires high doping concentration and high junction depth to reduce reverse leakage current and improve device breakdown voltage. For example, the trench depth of a 45V product is 1µm and the junction depth is about 1µm. Different optimizations are made according to different breakdown voltage products.

[0050] Dielectric layer 2,

[0051] A silicon dioxide layer, wherein the silicon dioxide layer has a plurality of trenches 7 extending downward from its top to the P-body region 8; and

[0052] Anode electrode layer 1, the bottom of which extends to P-body region 8 through trench 7.

[0053] The width of the trench is selected according to the photolithography precision, usually 0.35um-0.45um; the trench spacing is selected to be 5 times the trench width; this ensures a lower threshold voltage and less leakage current.

[0054] Further specified, the middle portion of the anode electrode layer 1 extends downward into the N-epipolar layer 3 to form an electrode layer extension 9.

[0055] Further defining the electrode layer extension, it has an M-shaped structure. The main addition of this novel hybrid trench Schottky trench-type superbarrier diode is the M-shaped Schottky contact, which increases the area of ​​the active region, while the Schottky contact reduces VF under high current.

[0056] Furthermore, the spacing between the aforementioned P-type injection regions is not less than 1.3 μm. Too small a spacing will result in parasitic transistors; this requirement aims to prevent parasitic effects.

[0057] A method for fabricating a hybrid trench Schottky trench-type superbarrier diode includes the following steps:

[0058] 100) Provide an N+ substrate layer 4, and form an N-type lightly doped N- epitaxial layer 3 on the surface of the N+ substrate layer 4;

[0059] 200) A dielectric layer 2 is formed on the surface of the N-epitaxial layer 3; in this case, the dielectric layer 2 is an ultrathin silicon dioxide layer; see reference. Figure 1 As shown;

[0060] 300) A phosphorus-doped polycrystalline silicon layer 11 (or D-Poly layer) is deposited on dielectric layer 2, as shown in the figure. Figure 2 As shown;

[0061] 400) Using photolithography, the top surface of the phosphorus-doped polysilicon layer 11 is etched downwards, extending to the top surface of the N-epitaxial layer 3, forming several side trenches, as shown in the figure. Figure 3 As shown;

[0062] 500) A P-type implantation region is formed in the side upper trench by boron difluoride and boron ion implantation processes; the P-type implantation region includes a conductive channel 6 and a P-body region 8;

[0063] 600) Several central upper trenches are etched on the upper surface of the phosphorus-doped polycrystalline silicon layer 11 using an etching process, extending to the top surface of the N-epitaxial layer 3, as shown in the figure. Figure 5 As shown;

[0064] 700) Using an etching process, the side upper trench and the middle upper trench are etched downwards respectively, extending the etching to the P-body region 8, as shown in the reference. Figure 6 As shown;

[0065] The upper groove and the middle upper groove are etched downwards to the same depth. The upper groove is formed by etching downwards.

[0066] 800) An anode electrode layer 1 is prepared above the phosphorus-doped polycrystalline silicon layer 11 by a metal deposition process, and extends into the N-epitaxial layer 3 through corresponding side upper trenches and center upper trenches, as shown in the figure. Figure 7 As shown;

[0067] 900), a cathode electrode layer 5 is prepared on the back side and thinned to form a surface contact, as shown in the figure. Figure 8 As shown.

[0068] Further specifying step 500, the specific preparation steps are as follows:

[0069] 510) Boron is formed through multiple high-energy ion implantations of different energies 8;

[0070] In this case, boron was injected three times at energies of 1 MeV, 900 KeV, and 800 KeV, respectively, using a sequentially decreasing injection method.

[0071] 520) A p-type doped conductive channel 6 is formed by low-energy (30 keV) ion implantation of boron difluoride, followed by thermal annealing.

[0072] Further specified, the thickness of the phosphorus-doped polysilicon layer is 2000 Å, forming a MOS structure with the dielectric layer 2 and the P-type doped channel.

[0073] Furthermore, the dielectric layer 2 has a thickness of 50 Å and is prepared using a low-temperature oxidation process, which not only improves the film quality but also serves as a good insulating dielectric layer.

[0074] The spacing between the P-body region 8 and the conductive channel 6 is a Schottky contact combining metal and semiconductor, increasing the effective contact area of ​​the chip. In this design, multiple trenches are formed on the upper surface of the N-epitaxial layer, and P-type (ion) implantation regions are formed inside the trench structures. The spacing between the trenches is equal, and the shapes and sizes of the multiple P-type implantation regions are identical. By setting multiple trench structures, new Schottky contacts are added within the trenches. First Schottky contact regions are formed between the N-epitaxial layer and the anode electrode layer, and between the electrode layer extension and the N-epitaxial layer, respectively. Each P-type implantation region forms a metal-oxide-semiconductor (MOS) contact structure with the anode electrode layer. An ohmic contact is formed between the P-type implantation region at the bottom of the electrode layer extension and the anode electrode layer; a Schottky contact region is formed in the longitudinal region.

[0075] This invention relates to a trench-type superbarrier diode of hybrid trench Schottky, which includes, from top to bottom, an anode electrode layer, a dielectric layer, an N-epitaxial layer, an N+ substrate layer and a cathode electrode layer. A window (or trench) is formed on the upper surface of the N-epitaxial layer to perform P-type implantation with different energies and doses to form a P-body region and a channel. After P-type implantation, trench etching is performed.

[0076] The trenches formed between two superbarrier cells are used to form Schottky contacts through metal deposition. These trench Schottky contacts and trench-type superbarrier diodes are mixed to form a novel hybrid trench Schottky trench-type superbarrier diode structure.

[0077] Regarding the information disclosed in this case, the following points need to be clarified:

[0078] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.

[0079] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0080] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A trench-type super-barrier diode with a hybrid trench Schottky design, characterized in that, From bottom to top, they include: Cathode electrode layer (5), N+ substrate layer (4), The N-epitaxial layer (3) has a plurality of spaced P-type injection regions on it; the P-type injection regions include conductive channels (6) and P-body regions (8) spaced from top to bottom. Dielectric layer (2), A silicon dioxide layer having a plurality of trenches (7) extending downward from its top to the P-body region (8); and an anode electrode layer (1) having its bottom extending to the P-body region (8) through the trenches (7). The middle part of the anode electrode layer (1) extends downward into the N-epi-epi-layer (3) to form an electrode layer extension (9). The electrode layer extension (9) has an M-shaped structure; The spacing between several of the P-type injection regions is not less than 1.3 μm.

2. The trench-type super-barrier diode of a hybrid trench Schottky diode according to claim 1, characterized in that, The trench has a rectangular structure.

3. A method for fabricating a hybrid trench Schottky trench-type superbarrier diode, used to fabricate the hybrid trench Schottky trench-type superbarrier diode as described in claim 1, characterized in that, Includes the following steps: 100) Provide an N+ substrate layer (4) and form an N-type lightly doped N- epitaxial layer (3) on the surface of the N+ substrate layer (4); 200), A dielectric layer (2) is formed on the surface of the N-epitaxial layer (3); 300), deposit a phosphorus-doped polycrystalline silicon layer on the dielectric layer (2); 400) The phosphorus-doped polycrystalline silicon layer is etched downwards through photolithography to extend to the top surface of the N-epitaxial layer (3), forming several side trenches. 500) A P-type implantation region is formed in the side upper trench by boron difluoride and boron ion implantation processes; the P-type implantation region includes a conductive channel (6) and a P-body region (8). 600) Several central upper trenches are etched on the upper surface of the phosphorus-doped polycrystalline silicon layer using an etching process. 700) Using an etching process, the side upper trench and the middle upper trench are etched downwards respectively, and the etching extends to the P-body region (8). 800) An anode electrode layer (1) is prepared above the phosphorus-doped polycrystalline silicon layer by metal deposition process, and extends into the N-epitaxial layer (3) through corresponding side upper trench and middle upper trench; 900), a cathode electrode layer (5) is prepared on the back side and thinned to form a surface contact.

4. The method for fabricating a hybrid trench Schottky trench-type superbarrier diode according to claim 3, characterized in that, Step 500) The specific preparation steps are as follows: 510) Boron is formed by multiple high-energy ion injections of different energies (8). 520) A p-type doped conductive channel is formed by low-energy ion implantation of boron difluoride (6), and then thermal annealing is performed.

5. The method for fabricating a hybrid trench Schottky trench-type superbarrier diode according to claim 3, characterized in that, The thickness of the phosphorus-doped polysilicon layer is 2000 Å, which together with the dielectric layer (2) and the P-type doped channel form a MOS structure.

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