Bit line voltage compensation circuit for in-memory computation
By introducing a bit line voltage compensation circuit into the in-memory computing circuit and using a low-threshold PMOS transistor to compensate for the bit line voltage, the read interference problem caused by the 6T computing unit is solved, and the accuracy and reliability of the calculation are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING INST OF INTELLIGENT TECH INST OF MICROELECTRONICS OF THE CHINESE ACAD OF
- Filing Date
- 2022-08-02
- Publication Date
- 2026-06-16
AI Technical Summary
Existing in-memory computing circuits based on 6T computing units are prone to data write errors during computation, causing read interference problems.
Design a bit line voltage compensation circuit that uses a low-threshold PMOS transistor to compensate for the bit line voltage, ensuring that the bit line voltage remains within a set range and avoiding accidental write operations.
This effectively avoids read interference problems, ensures stable bit line voltage during calculation, and improves the accuracy and reliability of in-memory calculations.
Smart Images
Figure CN115223618B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of in-memory computing, and in particular to a bit line voltage compensation circuit for in-memory computing. Background Technology
[0002] To improve the inference accuracy of deep convolutional neural networks (DCNNs), deep learning is shifting towards edge computing. This development is driving the work on low-resource machine learning algorithms and their acceleration hardware. The most common operation in DCNNs is multiplication and accumulation (MAC), which controls power and latency. MAC operations are highly regular and parallel, making them well-suited for hardware acceleration. However, memory access demands severely limit the energy efficiency of traditional digital accelerators. Therefore, in-memory computing (CIM) is becoming increasingly attractive for accelerating DCNNs.
[0003] Currently, in-memory computing designs can be categorized by storage medium into SRAM-based designs and designs based on novel non-volatile memories. While SRAM-based designs are technically mature, they also have certain limitations. For example, in-memory computing circuits based on 6T computing units may accidentally write data to the storage cells during computation. Summary of the Invention
[0004] The purpose of this invention is to provide a bit line voltage compensation circuit for in-memory computing, which can compensate for bit line voltage and solve the problem of read interference.
[0005] To achieve the above objectives, the present invention provides the following solution:
[0006] A bit-line voltage compensation circuit for in-memory computing includes: a computing cell array and a voltage compensation circuit.
[0007] In the computing unit array, bit line BL and bit line BLB are connected to the voltage compensation circuit;
[0008] The voltage compensation circuit is used to compensate the voltage of bit line BL and bit line BLB, so that the voltage of bit line BL and bit line BLB are kept within a set range.
[0009] Optionally, the voltage compensation circuit includes: transistors P1, P2, P3, P4, and P5;
[0010] The sources of transistors P1, P2, P3, and P4 are all connected to the drain of transistor P5. The gate of transistor P1 is connected to the gates of transistors P2, P3, and P4, the drain of transistors P1, P2, P3, and P4, bit line BL, and bit line BLB. The source of transistor P5 is connected to the power supply VDD, and the gate of transistor P5 is connected to the control signal CLK_RB.
[0011] Optionally, P1, P2, P3, P4 and P5 are all PMOS transistors.
[0012] Optionally, the computing unit array includes 64 computing units.
[0013] Optionally, the computing unit is a 6T SRAM.
[0014] Optionally, the 6T SRAM includes: tube T1, tube T2, tube T3, tube T4, tube T5 and tube T6;
[0015] The source of transistor T1 and the source of transistor T2 are both connected to power supply VDD. The gate of transistor T1, the gate of transistor T3, the drain of transistor T2, the drain of transistor T4, and the drain of transistor T6 are all connected to weighted storage node QB. The drain of transistor T1, the gate of transistor T2, the drain of transistor T3, the gate of transistor T4, and the drain of transistor T5 are all connected to weighted storage node Q. The source of transistor T3 and the source of transistor T4 are both grounded. The source of transistor T5 is connected to bit line BL, the gate of transistor T5 is connected to word line WLL, the source of transistor T6 is connected to bit line BLB, and the gate of transistor T6 is connected to word line WLR.
[0016] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0017] The present invention provides a bit line voltage compensation circuit for in-memory computation. The bit line voltage is compensated during computation by the voltage compensation circuit, so that the bit line voltage is kept within a set range and read interference problems are avoided during computation. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A schematic diagram of a bit line voltage compensation circuit structure for in-memory computing provided by the present invention;
[0020] Figure 2 This is a schematic diagram of the computing unit. Detailed Implementation
[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0022] The purpose of this invention is to provide a bit line voltage compensation circuit for in-memory computing, which can compensate for bit line voltage and solve the problem of read interference.
[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0024] Figure 1 This is a schematic diagram of a bit line voltage compensation circuit structure for in-memory computing provided by the present invention, as shown below. Figure 1 As shown, the present invention provides a bit-line voltage compensation circuit for in-memory computing, comprising: a computing unit array and a voltage compensation circuit.
[0025] In the computing unit array, bit lines BL and BLB are connected to the voltage compensation circuit.
[0026] The voltage compensation circuit is used to compensate the voltage of bit line BL and bit line BLB, so that the voltage of bit line BL and bit line BLB is kept within a set range. The voltage in this range is greater than a set threshold range, so as to avoid read interference problems during calculation.
[0027] The voltage compensation circuit includes transistors P1, P2, P3, P4, and P5; all transistors P1, P2, P3, P4, and P5 are PMOS transistors; transistors P1, P2, P3, and P4 are low-threshold PMOS transistors, which, when turned on, expand the gate voltage range. The voltage compensation circuit uses the low-threshold PMOS transistors to pull up the bit line voltage, preventing accidental write operations.
[0028] The sources of transistors P1, P2, P3, and P4 are all connected to the drain of transistor P5. The gate of transistor P1 is connected to the gates of transistors P2, P3, and P4, the drain of transistors P1, P2, P3, and P4, bit line BL, and bit line BLB. The source of transistor P5 is connected to the power supply VDD, and the gate of transistor P5 is connected to the control signal CLK_RB.
[0029] The calculation begins when the control signals CLK_RB, word line WLL, and word line WLR are enabled. The calculation unit pulls up and down the bit lines through the transmission transistors controlled by word lines WLL and WLR. When the bit line voltage is at a high level, the compensation circuit is not enabled. Since transistors P1, P2, P3, and P4 are low-threshold PMOS transistors, they turn on before reaching 0V. When the bit line voltage is below a certain value, transistors P1, P2, P3, and P4 are turned on, and the power supply VDD pulls up the bit line voltage through transistors P1, P2, P3, P4, and P5. Throughout the calculation process, the bit line voltage remains at a high level, avoiding read interference.
[0030] The computing unit array comprises 64 computing units. Each computing unit is a 6T SRAM.
[0031] like Figure 2 As shown, the 6T SRAM includes: transistors T1, T2, T3, T4, T5, and T6.
[0032] The source of transistor T1 and the source of transistor T2 are both connected to power supply VDD. The gate of transistor T1, the gate of transistor T3, the drain of transistor T2, the drain of transistor T4, and the drain of transistor T6 are all connected to weighted storage node QB. The drain of transistor T1, the gate of transistor T2, the drain of transistor T3, the gate of transistor T4, and the drain of transistor T5 are all connected to weighted storage node Q. The source of transistor T3 and the source of transistor T4 are both grounded. The source of transistor T5 is connected to bit line BL, the gate of transistor T5 is connected to word line WLL, the source of transistor T6 is connected to bit line BLB, and the gate of transistor T6 is connected to word line WLR.
[0033] When the weight value is "+1", the stored value is 1; when the weight value is "-1", the stored value is 0. When computation is enabled, 64 inputs drive the word lines WLL and WLR of the 64 6T SRAMs. When the input is "+1", word line WLL is driven high and word line WLR is driven low, and transistor T5 is selected; when the input is "-1", word line WLL is driven low and word line WLR is driven high, and transistor T6 is selected.
[0034] When the input is "+1" and the weight is "+1", the voltage on bit line BL is pulled high through transistor T5; when the input is "+1" and the weight is "-1", the voltage on bit line BL is pulled low through transistor T5; when the input is "-1" and the weight is "+1", the voltage on bit line BLB is pulled low through transistor T6; when the input is "-1" and the weight is "-1", the voltage on bit line BLB is pulled high through transistor T6. The final 64 calculation results are accumulated onto the bit lines in the form of voltages, thus completing the multiplication and accumulation operation of one series of inputs and weights.
[0035] During calculation, the weight storage nodes in the 6T SRAM are connected to the corresponding bit lines. If the bit line voltage is too low, it will pull the "1" stored in some storage cells down to "0", which results in an erroneous write operation.
[0036] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0037] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A bit line voltage compensation circuit for in-memory computing, the bit line voltage compensation circuit comprising: include: Computational unit array and voltage compensation circuit; In the computing unit array, bit line BL and bit line BLB are connected to the voltage compensation circuit; The voltage compensation circuit is used to compensate the voltage of bit line BL and bit line BLB, so that the voltage of bit line BL and bit line BLB are kept within a set range. The voltage compensation circuit includes transistors P1, P2, P3, P4, and P5. The sources of transistors P1, P2, P3, and P4 are all connected to the drain of transistor P5. The gate of transistor P1 is connected to the gates of transistors P2, P3, and P4, the drain of transistor P1, P2, P3, and P4, bit line BL, and bit line BLB. The source of transistor P5 is connected to the power supply VDD, and the gate of transistor P5 is connected to the control signal CLK_RB. When the control signal CLK_RB, word line WLL, and word line WLR are turned on, the calculation is enabled. The calculation unit pulls up and down the bit line through the transmission tube controlled by word line WLL and word line WLR. When the bit line voltage is at a high level, the compensation circuit is not turned on.
2. The bit line voltage compensation circuit for in-memory computing of claim 1, wherein, The transistors P1, P2, P3, P4, and P5 are all PMOS transistors.
3. The bit line voltage compensation circuit for in-memory calculation according to claim 1, characterized in that, The computing unit array comprises 64 computing units.
4. A bit line voltage compensation circuit for in-memory computation according to claim 3, characterized in that, The computing unit is a 6T SRAM.
5. A bit line voltage compensation circuit for in-memory computation according to claim 4, characterized in that, The 6TSRAM includes: transistors T1, T2, T3, T4, T5, and T6; The source of transistor T1 and the source of transistor T2 are both connected to power supply VDD. The gate of transistor T1, the gate of transistor T3, the drain of transistor T2, the drain of transistor T4, and the drain of transistor T6 are all connected to weighted storage node QB. The drain of transistor T1, the gate of transistor T2, the drain of transistor T3, the gate of transistor T4, and the drain of transistor T5 are all connected to weighted storage node Q. The source of transistor T3 and the source of transistor T4 are both grounded. The source of transistor T5 is connected to bit line BL, the gate of transistor T5 is connected to word line WLL, the source of transistor T6 is connected to bit line BLB, and the gate of transistor T6 is connected to word line WLR.