Memory devices, memory systems including memory devices, and test operations for memory devices

Abstract

The present technology includes memory devices, memory systems including memory devices, and test operations of memory devices. A memory device includes a memory block connected to a word line and a select line, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected one of the word line and the select line, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block based on the test data.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0051250, filed on April 20, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a memory device, a memory system including the memory device, and test operations of the memory device, and more specifically, to a memory device configured to test for defects in a memory device included in a memory system, a memory system including the memory device, and test operations of the memory device. Background Technology

[0004] A memory system may include a memory device configured to store data and a controller configured to control the memory device.

[0005] A memory device may include a memory block in which data is stored and peripheral circuitry configured to perform programming, reading, or erasing operations. The memory block may include multiple strings connected between bit lines and source lines, and the multiple strings may include memory cells capable of storing data. The multiple memory cells may be programmed, read, or erased based on voltages applied to the word lines and bit lines.

[0006] As the storage capacity and integration of memory systems increase, the size and spacing of the memory cells included in memory devices decrease. With the reduction in the size and spacing of memory cells, the size of the wires connecting the memory cells also decreases, and therefore, short-circuit or open-circuit defects may occur during the manufacturing process of memory devices. A short-circuit defect is a defect where components that should be electrically isolated are connected to each other, while an open-circuit defect is a defect where components that should be electrically connected are isolated from each other. Summary of the Invention

[0007] According to one embodiment of this disclosure, a memory device may include: a memory block connected to word lines and select lines; bit lines connected to the memory block; a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and select lines; a page buffer configured to sense the voltage of the bit lines to store and output test data; and control logic circuitry configured to determine, based on the test data, the presence of a first defect in the memory block. The page buffer includes: a sense latch configured to store test data determined based on the voltage of a sense node during a test operation for detecting a first defect in the memory block; a sense discharge circuit configured to discharge the sense node; and a bit line selection circuit configured to block the connection between the sense node and the bit lines when the test data is determined based on the voltage of the sense node. When the test operation begins and there is no first defect in the memory block, the test data is held as reset data in the sense latch, and when a first defect is present in the memory block, the test data is changed.

[0008] According to one embodiment of this disclosure, a memory system may include: a memory device including a page buffer connected to a memory block via bit lines; and a controller configured to transmit a test command to the memory device and determine the presence of a defect based on test data output from the memory device during a test operation for detecting defects in the memory block. The memory device is configured to: store initial data in a sense latch of the page buffer in response to the test command; discharge a sense node connected between the bit lines and the sense latch; store test data in the sense latch according to a voltage change in the sense node caused by the test operation; and output the test data to the controller. The controller is configured to determine that a first defect exists in the memory block when the test data differs from the initial data.

[0009] According to one embodiment of this disclosure, a method for performing a test operation on a memory device can be provided. The method may include: resetting a sense latch; discharging a sense node connected between the sense latch and a bit line; applying a test voltage to a selected line among word lines and select lines in a memory block connected to the bit line; transmitting the voltage of the bit line to the sense node; and storing the test voltage in the sense latch according to the voltage of the sense node. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0011] Figure 2 It is a diagram illustrating a memory device.

[0012] Figure 3It is a diagram illustrating a memory cell array.

[0013] Figure 4 This is a diagram illustrating a memory block.

[0014] Figure 5 This is a diagram illustrating a defect that occurs in a memory block.

[0015] Figure 6 This diagram illustrates the connection configuration between the page buffer group and the memory block.

[0016] Figure 7A and Figure 7B This is a diagram illustrating the principle of a test operation according to an embodiment of the present disclosure.

[0017] Figure 8 This is a circuit diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0018] Figure 9 This is a timing diagram illustrating a test operation of a memory device according to a first embodiment of the present disclosure.

[0019] Figure 10 This is a timing diagram illustrating a test operation of a memory device according to a second embodiment of the present disclosure.

[0020] Figure 11 This is a timing diagram illustrating a test operation of a memory device according to a third embodiment of the present disclosure.

[0021] Figure 12 This is a diagram illustrating a controller according to an embodiment of the present disclosure.

[0022] Figure 13 This is a diagram illustrating a memory system including the memory devices of this disclosure.

[0023] Figure 14 This is a diagram illustrating another memory system that includes the memory devices disclosed herein. Detailed Implementation

[0024] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are for illustrative purposes only. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0025] One embodiment of this disclosure provides a memory device capable of detecting short-circuit defects among defects occurring in a memory device, a memory system including the memory device, and test operations of the memory device.

[0026] According to this technology, short-circuit defects, which may occur in memory devices, can be detected.

[0027] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0028] refer to Figure 1 The memory system 1000 can be configured to store, erase, or output data in response to a request from the host. For example, the memory system 1000 may include a memory device 1100 capable of storing data, and a controller 1200 capable of communicating between the host and the memory device 1100. Although in Figure 1 The diagram illustrates a memory system 1000 including a memory device 1100, but the memory system 1000 may include two or more memory devices.

[0029] When a request is received from the host, the controller 1200 can generate commands for controlling the memory device 1100 based on the received request. The controller 1200 can be configured to manage logical addresses used in the host and physical addresses used in the memory device 1100. For example, during a programming operation, the controller 1200 can map logical addresses used in the host and physical addresses used in the memory device 1100 to each other. During a read operation, the controller 1200 can search for the physical address mapped to the logical address requested by the host and output the data read according to the physical address to the host.

[0030] According to this embodiment, the controller 1200 can be configured to: transmit a test command CMD_T to the memory device 1100 during a test operation of the memory device 1100, and determine whether a short-circuit defect exists based on the test data DATA_T output from the memory device 1100.

[0031] When a test request is received from the host, the controller 1200 can perform the test operation. However, even if there is no request from the host, the test operation can be performed while performing background operations.

[0032] Figure 2 It is a diagram illustrating a memory device.

[0033] refer to Figure 2 The memory device 1100 may include: an array of memory cells 110 in which data is stored, and peripheral circuitry 120 to 170 capable of performing programming, reading, or erasing operations.

[0034] The memory cell array 110 may include multiple memory blocks in which data is stored. Each memory block includes multiple memory cells, and the multiple memory cells may be implemented in a two-dimensional structure or a three-dimensional structure, in which the memory cells are arranged in parallel on a substrate, and in which the memory cells are stacked on a substrate in a vertical direction.

[0035] The peripheral circuits 120 to 170 may include a row decoder 120, a voltage generator 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control logic circuit 170.

[0036] The row decoder 120 can select a memory block from the memory blocks included in the memory cell array 110 according to the row address RADD, and transmit the operating voltage Vop to the selected memory block.

[0037] Voltage generator 130 can generate and output the operating voltage Vop required for various operations in response to opcode OPCD. For example, voltage generator 130 can generate test voltage, programming voltage, read voltage, erase voltage, pass voltage, verification voltage, negative voltage, etc. in response to opcode OPCD, and selectively output the generated voltage.

[0038] Page buffer group 140 can be connected to memory cell array 110 via bit lines. For example, page buffer group 140 may include page buffers connected to each bit line in the bit lines. Page buffers can operate simultaneously in response to page buffer control signal PBSIG and can temporarily store data during programming or read operations. During a read or verification operation, page buffers can sense the voltage of the bit lines, which varies according to a threshold voltage of the memory cell. That is, the threshold voltage of the memory cell can be determined as a result of a sensing operation performed in the page buffer, whether it is lower or higher than the read or verification voltage. In one embodiment of this disclosure, page buffers can sense the voltage of the bit lines and maintain the data stored in the latch as initial data or change the data stored in the latch according to the sensed voltage. As used herein, the terms “simultaneous” and “at the same time” regarding processes mean that the processes occur on overlapping time intervals. For example, if a first process occurs on a first time interval and a second process occurs simultaneously on a second time interval, the first and second time intervals overlap at least partially, such that there is a time when both the first and second processes are occurring.

[0039] The column decoder 150 can transmit data based on the column address CADD by connecting the data lines DL of the input / output circuitry 160 and the page buffer group 140.

[0040] The input / output circuit 160 can be connected via the input / output line IO. Figure 1 The controller 1200. Input / output circuitry 160 can input / output commands (CMD), addresses (ADD), and data via input / output lines (IO). For example, input / output circuitry 160 can transmit commands (CMD) and addresses (ADD) received from controller 1200 via input / output lines (IO) to control logic circuitry 170, and transmit data received from controller 1200 via input / output lines (IO) to page buffer group 140. Input / output circuitry 160 can output data received from page buffer group 140 to controller 1200 via input / output lines (IO). According to this embodiment, test data output from page buffer group 140 during test operations can be output to controller 1200 via input / output circuitry 160.

[0041] Control logic circuit 170 can output opcode OPCD, row address RADD, page buffer control signal PBSIG, and column address CADD in response to command CMD and address ADD. For example, control logic circuit 170 may include software that executes an algorithm in response to command CMD, and hardware configured to output various signals based on address ADD and the algorithm. Control logic circuit 170 can control row decoder 120, voltage generator 130, page buffer group 140, and column decoder 150 to perform test operations according to test commands. During the test operation, control logic circuit 170 can determine whether a selected memory block is defective based on test data read from memory cell array 110.

[0042] Figure 3 It is a diagram illustrating a memory cell array.

[0043] refer to Figure 3 The memory cell array 110 can be configured as a single-plane or multi-plane array. A single-plane array refers to a configuration in which the memory cell array 110 includes only one plane, and a multi-plane array refers to a configuration in which the memory cell array 110 includes multiple planes. Figure 3A memory cell array 110 configured as a multi-plane array is shown. For example, first planes to fourth planes P1 to P4 can be included in the memory cell array 110. First planes to fourth planes P1 to P4 can be defined as memory regions in which different row decoders and different page buffer groups are connected. Each of the first planes to fourth planes P1 to P4 can include first memory blocks to i-th memory blocks BLK1 to BLKi (i is a positive integer). First memory blocks to i-th memory blocks BLK1 to BLKi included in different planes can be connected to different row decoders and different page buffer groups, and first memory blocks to i-th memory blocks BLK1 to BLKi included in the same plane can be connected to the same row decoder and the same page buffer group. First memory blocks to i-th memory blocks BLK1 to BLKi can be configured with the same structure.

[0044] Figure 4 This is a diagram illustrating a memory block.

[0045] refer to Figure 4 , Figure 3 The memory block BLKi among the multiple memory blocks BLK1 to BLKi shown is illustrated as an example.

[0046] The memory block BLKi may include multiple strings ST connected between the first bit line to the m-th bit lines BL1 to BLm and the source line SL. Each string ST may include a source selection transistor SST, a first memory cell to the n-th memory cell C1 to Cn, and a drain selection transistor DST connected in series between the source line SL and the first bit line to the m-th bit lines BL1 to BLm (m is a positive integer).

[0047] because Figure 4 The memory block BLKi shown is a diagram illustrating the configuration of the memory block; therefore, the number of source selection transistors SST, first memory cells C1 to Cn, and drain selection transistors DST is not limited to... Figure 4 The number shown.

[0048] The gate of the source selection transistor SST connected to different string STs can be connected to the source selection line SSL, the gate of each memory cell from the first memory cell to the nth memory cell C1 to Cn can be connected to the first word line to the nth word line WL1 to WLn, and the gate of the drain selection transistor DST can be connected to the drain selection line DSL.

[0049] A group of memory cells connected to the same word line and included in different strings ST can constitute a page PG. Programming and reading operations can be performed on a per-page PG basis. In the test operation according to this embodiment, page PGs can be selected one by one, or multiple page PGs can be selected simultaneously.

[0050] The memory cells included in the memory block BLKi can be programmed differently depending on the programming method. For example, programming operations can be performed using the Single-Level Cell (SLC), Multi-Level Cell (MLC), Three-Level Cell (TLC), or Quadruple-Level Cell (QLC) methods. The SLC method stores one bit of data in one memory cell. The MLC method stores two bits of data in one memory cell. The TLC method stores three bits of data in one memory cell. The QLC method stores four bits of data in one memory cell. Additionally, five or more bits of data can be stored in one memory cell.

[0051] Figure 5 This is a diagram illustrating a defect that occurs in a memory block.

[0052] refer to Figure 5 The diagram schematically illustrates a portion of a string ST. A string ST may include multiple memory cells, and these memory cells may be connected to different word lines WLn-2, ​​WLn-1, and WLn.

[0053] When a defect occurs within the string ST, it may result in a short-circuit defect DE_SH or an open-circuit defect DE_OP. A short-circuit defect DE_SH can be a defect where the word line and channel CH are electrically connected to each other, while an open-circuit defect DE_OP can be a defect where a region within the channel CH is electrically disconnected. In other words, a short-circuit defect DE_SH is a defect where components that should be electrically disconnected are connected to each other, and an open-circuit defect DE_OP is a defect where components that should be electrically connected are disconnected from each other.

[0054] Assuming there is no open-circuit defect DE_OP in string ST, but a short-circuit defect DE_SH occurs in the memory cell connected to the (n-2)th word line WLn-2, ​​the voltage applied to the (n-2)th word line WLn-2 can be directly transmitted to channel CH during programming, reading, or erasing operations. In this case, the reliability of programming, reading, or erasing operations may be reduced because the voltage or current of bit line BL is altered.

[0055] Assuming there is no short-circuit defect DE_SH in string ST, but an open-circuit defect DE_OP occurs in channel CH between word line n WLn and (n-1) word line WLn-1, then during programming, reading, or erasing operations, regardless of the voltage applied to the word lines, the voltage or current of bit line BL may be continuously maintained at its initial value. In this case, the reliability of programming, reading, or erasing operations may be reduced because the state of the memory cells may not be detectable.

[0056] In this embodiment, a method for detecting short-circuit defects DE_SH is described.

[0057] Figure 6 This diagram illustrates the connection configuration between the page buffer group and the memory block.

[0058] refer to Figure 6 Page buffer group 140 may include first page buffers to m-th page buffers PB1 to PBm connected to the first bit lines to the m-th bit lines BL1 to BLm. Since the first page buffers to the m-th page buffers PB1 to PBm respectively sense the voltage of the first bit lines to the m-th bit lines BL1 to BLm, the number of bit lines in which short-circuit defects occur can be counted during the test operation according to this embodiment. That is, the number and location of columns in which short-circuit defects occur can be detected from the results of the test operation.

[0059] Figure 7A and Figure 7B This is a diagram illustrating the principle of a test operation according to an embodiment of the present disclosure, with the portion where the string ST is connected to the first page buffer PB1 shown as an example.

[0060] Figure 7A This diagram illustrates the cases where there are no defects in the string ST or an open-circuit defect DE_OP is present. Figure 7B This diagram illustrates the situation where a short-circuit defect DE_SH occurs in the string ST.

[0061] refer to Figure 7AThe first page buffer PB1 may include a precharge circuit PRE, a bit line selection circuit BSEL, a discharge circuit DIS, and a sense latch Ls connected around the sense node SO. The precharge circuit PRE, bit line selection circuit BSEL, discharge circuit DIS, and sense latch Ls can be used during test operations. The precharge circuit PRE can be configured to precharge the first bit line BL1. The bit line selection circuit BSEL can be configured to connect or disconnect the first bit line BL1 and the first page buffer PB1 from each other. The discharge circuit DIS can be configured to discharge the sense node SO. For example, the voltage of the discharged sense node SO can be 0V. The sense latch Ls can be configured to store test data determined during test operations based on the voltage of the sense node SO.

[0062] During the test operation according to this embodiment, the sensing node SO can be discharged and initialized to 0V, and the first bit line BL1 and the sensing node SO can be connected to each other via the bit line select circuit BSEL. Therefore, the first bit line BL1 can also be discharged and initialized to 0V. The initial data "1" can be stored in the sensing latch Ls. In this embodiment, the initial data is set to "1", but depending on the memory device, the initial data can be set to "0". In one embodiment, resetting the sensing latch Ls may include storing the initial data in the sensing latch.

[0063] like Figure 7A As shown, in the case of an open-circuit defect DE_OP in channel CH or the absence of such a defect, when a positive test voltage Vtest is applied to the selected word line Sel_WL, the test data of the sense latch Ls can be maintained as "1" data, which is the initial data. A positive voltage is a voltage greater than zero. More specifically, even if a positive test voltage Vtest is applied to the selected word line Sel_WL, the voltage of the first line BL1 does not increase because the test voltage Vtest is not transmitted to the first line BL1. That is, since the voltage of the first line BL1 is maintained at 0V, the voltage of the sense node SO can also be maintained at 0V, and therefore the data stored in the sense latch Ls will not change.

[0064] When the test data "1" stored in the sensor latch Ls is output to... Figure 1 When the controller 1200 is in operation, based on the "1" data, the controller 1200 can determine that there is no defect in the string ST or that even if there is a defect in the string ST, it is an open circuit defect DE_OP.

[0065] refer to Figure 7BIn the case of a short-circuit defect DE_SH in string ST, when a positive test voltage Vtest is applied to the selected word line Sel_WL, the initial data "1" stored in the sense latch Ls can be changed to "0". Alternatively, when the initial data is set to "0", the initial data "0" stored in the sense latch Ls can be changed to "1". More specifically, when a positive test voltage Vtest is applied to the selected word line Sel_WL, the voltage of the first line BL1 can be increased because the selected word line Sel_WL and channel CH are electrically connected to each other due to the short-circuit defect DE_SH. That is, since the voltage of the first line BL1 increases to a positive voltage, the voltage of the sense node SO can also increase to a positive voltage, and therefore the data stored in the sense latch Ls is changed.

[0066] When the test data "0" stored in the sensor latch Ls is output to... Figure 1 When the controller 1200 is in use, the controller 1200 can determine that there is a short circuit defect DE_SH in the string ST based on the "0" data.

[0067] Figure 8 This is a circuit diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0068] Because multiple page buffers are configured identically to each other, therefore in Figure 8 The first page buffer, PB1, is shown among multiple page buffers.

[0069] refer to Figure 8 The first page buffer PB1 may include a bit line precharge circuit PRE, a bit line discharge circuit BDIS, a bit line selection circuit BSEL, a selection precharge circuit SEL_PC, a sensing discharge circuit DIS, a sensing latch Ls, a setting circuit SET, and a latch group LG. The bit line precharge circuit PRE, bit line discharge circuit BDIS, bit line selection circuit BSEL, selection precharge circuit SEL_PC, sensing discharge circuit DIS, sensing latch Ls, setting circuit SET, and latch group LG can respond to... Figure 2 The page buffer control signal PBSIG is used for operation. That is, the page buffer control signal PBSIG can be a signal used to turn on or off the switches included in all page buffers, including the first page buffer PB1.

[0070] The bit line precharge circuit PRE can be configured to precharge the first bit line BL1 during programming, reading, or erasing operations. In a test operation according to this embodiment, the bit line precharge circuit PRE is deactivated. The bit line precharge circuit PRE may include a first switch S1 configured to provide a power supply voltage VCC to the first bit line BL1 in response to the bit line precharge signal BL_PRE. The first switch S1 can be implemented using an NMOS transistor. In a test operation according to this embodiment, since the bit line precharge circuit PRE is deactivated, the bit line precharge signal BL_PRE can be held low.

[0071] The bit line discharge circuit BDIS can be configured to discharge the first bit line BL1. The bit line discharge circuit BDIS may include a second switch S2 that connects or disconnects the first bit line BL1 and the ground terminal GND in response to the bit line discharge signal BL_DIS. The second switch S2 can be implemented using an NMOS transistor that operates in response to the bit line discharge signal BL_DIS.

[0072] The bit line selection circuit BSEL may include a third switch S3 configured to connect or disconnect the first bit line BL1 and the current sensing node CSO in response to the page sensing signal PBSENSE. The third switch S3 may be implemented using an NMOS transistor that connects or disconnects the first bit line BL1 and the current sensing node CSO in response to the page sensing signal PBSENSE.

[0073] The precharge selection circuit SEL_PC can be connected between the first node N1 and the current sensing node CSO, with the power supply voltage VCC provided to the first node N1. The precharge selection circuit SEL_PC can be configured to precharge either the current sensing node CSO or the sensing node SO to connect or disconnect them from each other. The precharge selection circuit SEL_PC may include a fourth to a ninth switch S4 to S9 connected between the first node N1 and the current sensing node CSO. For example, the fourth switch S4 and the fifth switch S5 can be connected in parallel between the first node N1 and the second node N2, and a sixth switch S6 can be connected between the second node N2 and the current sensing node CSO. The fourth switch S4 can be implemented using a PMOS transistor that is turned on or off in response to an inverted sensing precharge signal SA_PRE_N, and the fifth switch S5 can be implemented using a PMOS transistor that is turned on or off according to data stored in the sensing latch node QS. The sixth switch S6 can be implemented using an NMOS transistor that is turned on or off in response to a current sensing signal SA_CSOC. Switches S7 to S9 (seventh to ninth) can be connected in series between the first node N1 and the current sensing node CSO, and can be connected in parallel to switches S4 to S6. Switch S7 (seventh) can be implemented using a PMOS transistor that is turned on or off according to data stored in the sensing latch node QS. Switch S8 (eighth) can be implemented using a PMOS transistor that is turned on or off in response to an inverted sensing precharge signal SA_PRE_N. Switch S9 (ninth) can be implemented using an NMOS transistor that is turned on or off in response to a sensing signal SA_SENSE. The sensing node SO can be connected between switch S8 (eighth) and switch S9 (ninth).

[0074] The sensing discharge circuit DIS can be configured to discharge the sensing node SO. The sensing discharge circuit DIS may include a tenth switch S10 and an eleventh switch S11 connected in series between the sensing node SO and the ground terminal GND. The tenth switch S10 can be implemented using an NMOS transistor that is turned on or off in response to the sensing discharge signal SA_DIS. The eleventh switch S11 can be implemented using an NMOS transistor that is turned on or off according to data stored in the sensing latch node QS. The sensing node SO can be discharged when the sensing discharge signal SA_DIS is logic high and "1" data is stored in the sensing latch node QS.

[0075] In this embodiment, "1" data refers to a state where the voltage of the sensed latch node QS is high, and "0" data refers to a state where the voltage of the sensed latch node QS is 0V or a negative voltage. Discharging refers to reducing the voltage of the node to 0V or a negative voltage, and precharging refers to increasing the voltage of the node to a positive voltage.

[0076] The sensing latch Ls may include a first inverter I1 and a second inverter I2 connected between the sensing latch node QS and the inverting sensing latch node QS_N. For example, the input terminal of the first inverter I1 may be connected to the sensing latch node QS, and the output terminal may be connected to the inverting sensing latch node QS_N. The input terminal of the second inverter I2 may be connected to the inverting sensing latch node QS_N, and the output terminal may be connected to the sensing latch node QS. The sensing latch Ls can store sensed data during sensing operations of the selected memory cell. For example, the voltage of the sensing node SO can be determined when the voltage of the first bit line BL1 is determined by the selected memory cell and the first bit line BL1 and the sensing node SO are connected to each other. When the voltage of the sensing node SO is determined, the data of the sensing latch node QS can be determined by the operation of the setting circuit SET. During test operations, test data can be stored in the sensing latch node QS.

[0077] The setting circuit SET can be configured to reset or change the data stored in the sensing latch Ls based on the voltage of the sensing node SO. For example, the setting circuit SET may include: a twelfth switch S12 and a thirteenth switch S13 connected in series between the sensing latch node QS and the ground terminal GND; and a fourteenth switch S14 and a fifteenth switch S15 connected in series between the inverting sensing latch node QS_N and the ground terminal GND. The twelfth switch S12 can be implemented using an NMOS transistor that is turned on or off in response to the latch reset signal LRST. The thirteenth switch S13 can be implemented using an NMOS transistor that is turned on or off in response to the page buffer reset signal PBRST. The fourteenth switch S14 can be implemented using an NMOS transistor that is turned on or off in response to the latch setting signal LSET. The fifteenth switch S15 can be implemented using an NMOS transistor that is turned on or off based on the voltage of the sensing node SO. The common node COM can be connected between the twelfth switch S12 and the thirteenth switch S13, and between the fourteenth switch S14 and the fifteenth switch S15. The setting circuit SET can transmit the data stored in the sense latch Ls to the latch group LG through the common node COM.

[0078] The latch group LG may include first latches to k-th latches L1 to Lk. First latches to k-th latches L1 to Lk may temporarily store data used during programming or reading operations, and will output data received from the setup circuit SET during reading or testing operations to the first data line DL1. First latches to k-th latches L1 to Lk may exchange data with the sensing node SO. Assuming that first latch L1 is connected to the setup circuit SET and k-th latch Lk is connected to the first data line DL1, test data stored in the sensing latch Ls during testing operations can be transferred to first latch L1. The test data transferred to first latch L1 can be transferred to k-th latch Lk, and the test data transferred to k-th latch Lk can be output via the first data line D1. Figure 2 Input / output circuit 160.

[0079] Figure 9 This is a timing diagram illustrating a test operation of a memory device according to a first embodiment of the present disclosure.

[0080] refer to Figure 8 and Figure 9 The test operation can be performed after the erase operation on the memory cell. The test operation may include a setup step (S91), a discharge step (S92), a test step (S93), an evaluation step (S94), and a sensing step (S95) that are executed sequentially.

[0081] Setting step S91 is the step of initializing the sensing latch Ls. For example, in setting step S91, the initial data "1" can be stored in the sensing latch node QS of the sensing latch Ls. For example, when the page buffer reset signal PBRST turns high (H) and the thirteenth switch S13 is turned on, the latch setting signal LSET can turn high (H) for a predetermined time period. When both the page buffer reset signal PBRST and the latch setting signal LSET have a high (H) value, the thirteenth switch S13 and the fourteenth switch S14 can be turned on, and thus a current path can be formed between the inverting sensing latch node QS_N and the ground terminal GND. Therefore, "0" data can be stored in the inverting sensing latch node QS_N, and "1" data can be stored in the sensing latch node QS. When the "1" data is stored in the sensing latch node QS, the latch setting signal LSET turns low (L), and the page buffer reset signal PBRST also turns low (L). The term "scheduled" (such as "scheduled time") used in this document to refer to a parameter means that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0082] When discharge step S92 begins, the sensing discharge signal SA_DIS, bit line discharge signal BL_DIS, sensing signal SA_SENSE, and page sensing signal PBSENSE can transition to logic high to discharge the sensing node SO, and thus the tenth switch S10, the second switch S2, the ninth switch S9, and the third switch S3 can be turned on. Therefore, the sensing node SO and the first bit line BL1 can be connected to the ground terminal GND to be discharged. For example, the voltage between the sensing node SO and the first bit line BL1 can be 0V. In discharge step S92, the turn-on voltage Von can be applied to... Figure 4 The drain select line (DSL) and source select line (SSL) are connected. At this time, a voltage of 0V can be applied to... Figure 4 The source line SL. In discharge step S92, all word lines can be floated or discharged.

[0083] When test step S93 begins, a test voltage Vtest with a positive voltage can be applied to the selected word line Sel_WL. During test step S93, even though the test voltage Vtest is applied to the selected word line Sel_WL, the voltage of the sensing node SO can be maintained at a discharge level (e.g., 0V) because the sensing discharge signal SA_DIS and the bit line discharge signal BL_DIS are kept high. Alternatively, even if the voltage of the sensing node SO increases to a positive voltage, the voltage of the sensing node SO can increase slightly at a low level.

[0084] When evaluation step S94 begins, the sensed discharge signal SA_DIS and the bit line discharge signal BL_DIS can transition to logic low L. The turn-on voltage Von can be continuously supplied to the drain select line DSL and the source select line SSL, or 0V as the turn-off voltage can be applied.

[0085] When the sensing discharge signal SA_DIS and the bit line discharge signal BL_DIS change to logic low L, the current path between the sensing node SO, the first bit line BL1 and the ground terminal GND can be blocked because the tenth switch S10 and the second switch S2 are turned off.

[0086] When there is no short-circuit defect between the selected word line Sel_WL, the selected memory cell connected to the selected word line Sel_WL, and the channel formed in the selected memory cell, the voltage of the sensing node SO can be maintained at a discharge level (e.g., 0V). When there is a short-circuit defect between the selected word line Sel_WL, the selected memory cell connected to the selected word line Sel_WL, and the channel formed in the selected memory cell, a pre-charge voltage Vpre can be applied to the sensing node SO. Here, the pre-charge voltage Vpre can be the voltage of the test voltage Vtest applied to the selected word line Sel_WL. For example, when a short-circuit defect exists in the region of the selected word line Sel_WL, the test voltage Vtest applied to the selected word line Sel_WL can be provided to the first line BL1 through the serial channel. When the voltage of the first line BL1 increases with the test voltage Vtest, the voltage of the sensing node SO connected to the first line BL1 can also increase. Therefore, the pre-charge voltage Vpre applied to the sensing node SO can have a positive voltage level that is lower than the switching threshold voltage Vtest.

[0087] At this time, in order to increase the difference between the level of the test voltage Vtest applied to the sensing node SO and the discharge level (e.g., 0V), a current sensing signal SA_CSOC with a compensation voltage Vcom can be applied to the sixth switch S6. In other words, the current sensing signal SA_CSOC used to weakly turn on the sixth switch S6 can be applied to the gate of the sixth switch S6. When the sixth switch S6 is fully turned on, since the power supply voltage VCC applied to the second node N2 can be provided to the current sensing node CSO even if there is no short-circuit defect, the current sensing signal SA_CSOC can have a compensation voltage Vcom lower than the power supply voltage VCC, so that the compensation voltage Vcom lower than the power supply voltage VCC is transmitted. Since the ninth switch S9 is turned on, when the compensation voltage Vcom is applied to the current sensing node CSO, the pre-charge voltage can also be applied to the sensing node SO. Since the fifteenth switch S15 is turned on or off by the voltage applied to the sensing node SO, the positive voltage can be set to a level at which the fifteenth switch S15 can remain off. The current sensing signal SA_CSOC with compensation voltage Vcom can be activated only during a predetermined time period in evaluation step S94 and can be deactivated before the end of evaluation step S94.

[0088] When sensing step S95 begins, the selected word line Sel_WL can be discharged. The drain select line DSL can also be discharged while the on-state voltage Von is applied to it until sensing step S95 begins. The sensing signal SA_SENSE and the page sensing signal PBSENSE can transition to logic low L.

[0089] Subsequently, when the latch reset signal LRST transitions to logic high H, the twelfth switch S12 can be turned on, and thus the sensing latch node QS and sensing node SO can be connected to each other. When the voltage of sensing node SO is 0V or the compensation voltage Vcom, the fifteenth switch S15 is turned off. Therefore, even if the twelfth switch S12 is turned on, the data in sensing latch node QS can be maintained as "1". That is, when the test data stored in sensing latch node QS is "1", Figure 1 The controller 1200 can determine that there is no short-circuit defect between the selected word line Sel_WL and the channel. When the voltage of the sensing node SO is the pre-charge voltage Vpre, the fifteenth switch S15 is turned on, and therefore the data in the sensing latch node QS can change from "1" to "0". That is, when the test data stored in the sensing latch node QS becomes "0", Figure 1 The controller 1200 can determine that there is a short circuit defect between the selected word line Sel_WL and the channel.

[0090] Figure 10This is a timing diagram illustrating a test operation of a memory device according to a second embodiment of the present disclosure.

[0091] refer to Figure 10 Due to the test operation and reference according to the second embodiment of this disclosure Figure 9 The first embodiment described is similarly performed, therefore descriptions of steps that are repeated in the first embodiment are omitted.

[0092] In the test operation according to the second embodiment, the test voltage Vtest can be applied simultaneously to all word lines WL connected to the selected memory block. For example, in the setup step S91 and the discharge step S92, all word lines WL can be floated or discharged. When the test step S93 begins, the test voltage Vtest can be applied to all word lines WL.

[0093] In the second embodiment, when the test voltage Vtest is applied to all word lines WL, the page location where the short circuit defect occurs may not be accurately determined, but it is possible to quickly check whether a short circuit defect occurs in the selected memory block.

[0094] Figure 11 This is a timing diagram illustrating a test operation of a memory device according to a third embodiment of the present disclosure.

[0095] refer to Figure 11 Due to the test operation and reference according to the third embodiment of this disclosure Figure 9 The first embodiment described is similarly performed, therefore descriptions of steps that are repeated in the first embodiment are omitted.

[0096] In the test operation according to the third embodiment, a short-circuit defect can be checked in the area to which the drain select line DSL is connected. For example, when the test operation is performed, all word lines WL can be floated or discharged, and 0V corresponding to the turn-off voltage can be applied to the source select line SSL. When test step S93 begins, the test voltage Vtest or the turn-on voltage Von can be applied to the drain select line DSL, and when sensing step S95 begins, the drain select line DSL can be discharged.

[0097] Additionally, by applying the third embodiment, a short-circuit defect can be checked in the area to which the source select line SSL is connected by applying a test voltage Vtest or a conduction voltage Von to the source select line SSL.

[0098] In the third embodiment, a short-circuit defect is checked by applying a test voltage Vtest to the line. Even if the line is not a word line WL connected to a memory cell, a short-circuit defect can be checked for each line.

[0099] Figure 12 It's a diagram. Figure 1 The diagram shows the controller 1200.

[0100] refer to Figure 12 The controller 1200 may include a flash memory conversion layer 101, a central processing unit 102, an error correction circuit 103, a defect detector 104, and a system buffer 105. Additionally, the controller 1200 may also include devices that perform various functions.

[0101] The flash translation layer 101 can be configured to map logical addresses used in the host and physical addresses used in the memory device to each other, and to manage the mapped addresses.

[0102] The central processing unit 102 can be configured to control the flash memory translation layer 101, error correction circuitry 103, defect detector 104, and system buffer 105 included in the controller 1200. For example, the central processing unit 102 can generate commands for controlling the memory device based on a request from the host, and can perform various operations for managing the memory device. For example, the central processing unit 102 can be configured to output a test command CMD_T to perform test operations on the memory device.

[0103] The error correction circuit 103 can be configured to detect errors in the data read from the memory device during a read operation and correct the detected errors.

[0104] The defect detector 104 can be configured to receive test data read from the memory device during a test operation of the memory device, and determine whether the memory device has a defect based on the received test data. For example, when "0" data is included in the test data read from the memory device, the defect detector 104 can determine that a short-circuit defect exists in the string corresponding to the "0" data.

[0105] The system buffer 105 can be configured to store various system data used in the storage controller 1200. For example, the system buffer 105 can store an address mapping table generated by the flash translation layer 101 and temporarily store data read from the memory device.

[0106] Figure 13 It's a diagram. Figure 1 The diagram illustrates a memory system 1000, which includes a memory device 1100 and a controller 1200 as disclosed herein. In one embodiment, the memory device 1100 and the controller 1200 may be as described above. Figure 1 The memory device 1100 and controller 1200 are discussed.

[0107] refer to Figure 13 The memory system 1000 may include a memory device 1100 in which data is stored, and a controller 1200 for communicating between the memory device 1100 and the host 2000.

[0108] The memory device 1100 can be configured with Figure 1 The memory device 1100 shown.

[0109] The memory system 1000 may include a plurality of memory devices 1100, and the memory devices 1100 may be connected to the controller 1200 via at least one channel. For example, the plurality of memory devices 1100 may be connected to one channel, and even if multiple channels are connected to the controller 1200, the plurality of memory devices 1100 may be connected to each channel.

[0110] Controller 1200 can communicate between host 2000 and memory device 1100. Controller 1200 can control memory device 1100 based on requests from host 2000, or it can perform background operations to improve the performance of memory system 1000 even without requests from host 2000. Host 2000 can generate requests for various operations and output these requests to memory system 1000. For example, requests may include: programming requests that control programming operations, read requests that control read operations, erase requests that control erase operations, and so on.

[0111] The host 2000 can communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Rapid (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Rapid (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Digital Disk Interface (ESDI), or Electronic Integrated Drive (IDE).

[0112] Figure 14 This is a diagram illustrating another memory system that includes the memory devices disclosed herein.

[0113] refer to Figure 14 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a controller 1200, and a card interface 7100.

[0114] In one embodiment, the memory device 1100 may be configured with Figure 1The memory device 1100 shown is illustrated. In one embodiment, the controller 1200 may be configured with... Figure 1 The controller 1200 shown is shown.

[0115] The controller 1200 can control the data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited thereto.

[0116] Card interface 7100 can provide an interface for data exchange between host 60000 and controller 1200 according to the protocol of host 60000. According to one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Here, card interface 7100 can refer to hardware capable of supporting the protocol used by host 60000, software installed in the hardware, or signal transmission method.

[0117] When the memory system 70000 is connected to the host interface 6200 of the host 60000, the interface 6200 can communicate with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor (μP) 6100. The host 60000 is such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box.

Claims

1. A memory device, comprising: The memory block is connected to the word line and select line; Bit lines are connected to the memory block; A voltage generator is configured to generate a test voltage to be applied to a selected line among the word lines and the selection lines; Page buffers are configured to sense the voltage of the bit lines to store and output test data; as well as Control logic circuitry is configured to determine, based on the test data, whether a first defect exists in the memory block. The page buffer mentioned above includes: A sensing latch is configured to store test data determined based on the voltage of a sensing node during a test operation for detecting the first defect in the memory block; A sensing discharge circuit is configured to discharge the sensing node; and The bit line selection circuit is configured to block the connection between the sensing node and the bit line when determining the test data based on the voltage of the sensing node, and When the test operation begins and the first defect is not present in the memory block, the test data is held as reset data in the sensing latch, and when the first defect is present in the memory block, the test data is changed.

2. The memory device of claim 1, wherein the voltage generator is configured to generate the test voltage as a positive voltage.

3. The memory device of claim 1, wherein the sensing latch is configured to be reset at the start of the test operation.

4. The memory device of claim 3, wherein the sensing discharge circuit is configured to discharge the sensing node when the sensing latch is reset.

5. The memory device of claim 1, wherein the bit line selection circuit is configured to: connect the bit line and the sensing node to each other when the sensing node is discharged and the test voltage is applied to the selected line, and disconnect the connection between the bit line and the sensing node before the test data is determined based on the voltage of the sensing node.

6. The memory device according to claim 1, further comprising: The bit line discharge circuit is configured to discharge the bit line simultaneously when the sensing node is discharged.

7. The memory device of claim 1, wherein the selected line is all word lines of the word lines, some word lines of the word lines, word lines selected from the word lines, all selected lines of the selected lines, some selected lines of the selected lines, or selected lines selected from the selected lines.

8. The memory device of claim 1, wherein the first defect is a short-circuit defect, in which the selected line is electrically connected to a memory cell or selection transistor connected to the selected line.

9. The memory device of claim 8, wherein when the first defect is not present in the memory block, it is either when there is no defect in the memory block or when there is a second defect different from the first defect.

10. The memory device of claim 9, wherein the second defect is an open-circuit defect in which a portion of a channel comprising the memory cell and the string of the select transistor is electrically disconnected.

11. A memory system, comprising: Memory devices, including page buffers connected to a block of memory via bit lines; as well as The controller is configured to transmit test commands to the memory device and determine the presence of the defect based on test data output from the memory device during a test operation for detecting defects in the memory block. The memory device is configured to store initial data in the sense latch of the page buffer in response to the test command; Discharge the sensing node connected between the bit line and the sensing latch; store the test data in the sensing latch according to the voltage of the sensing node changed by the test operation; And output the test data to the controller, and The controller is configured to determine that a first defect has occurred in the memory block when the test data is different from the initial data.

12. The memory system of claim 11, wherein the memory device is configured to: when the sensing node is discharged, after applying a test voltage to a selected line among the word lines and select lines connected to the memory block, transmit a voltage of the bit line changed by the test voltage to the sensing node, and store the test data in the sensing latch according to the voltage of the sensing node.

13. The memory system of claim 12, wherein the controller comprises: The central processing unit is configured to generate the test commands; as well as A defect detector is configured to detect the first defect based on the test data.

14. A method for performing test operations on a memory device, the method comprising: Reset the sensor latch; Discharge the sensing node connected between the sensing latch and the bit line; A test voltage is applied to the selected line of the word lines and select lines in the memory block connected to the bit lines; Transmit the voltage of the bit line to the sensing node; as well as The test voltage is stored in the sensing latch based on the voltage of the sensing node.

15. The method of claim 14, wherein resetting the sensing latch comprises: The initial data is stored in the sensor latch.

16. The method of claim 14, wherein discharging the sensing node comprises: The sensing node and the bit line are discharged by forming a current path between the sensing node and the bit line and the ground terminal.

17. The method of claim 14, wherein applying the test voltage comprises: The test voltage applied to the selected line is set to a positive voltage.

18. The method of claim 14, wherein transmitting the voltage of the bit line to the sensing node comprises: When a short circuit defect exists between the selected line and the memory cell or selection transistor connected to the selected line, the voltage of the bit line is increased, and when the short circuit defect does not exist between the selected line and the memory cell or selection transistor, the bit line is maintained at a discharge level.

19. The method of claim 16, wherein transmitting the voltage of the bit line to the sensing node comprises: Block the current path.

20. The method of claim 14, wherein storing the test voltage in the sensing latch according to the voltage of the sensing node comprises: When the voltage of the sensing node is maintained at a discharge level, test data with the same value as the initial data is stored in the sensing latch, and when the voltage of the sensing node is increased to a positive voltage, test data with a value different from the initial data is stored in the sensing latch.

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