Method and apparatus for seamless switching between command mode and video mode, and display device

Abstract

The present disclosure relates to a method and apparatus for seamlessly switching between a command mode and a video mode when driving a display, and a display device. The method includes: receiving a command for switching from the command mode to the video mode; generating a sampling value by measuring a time interval between a time point of an internal synchronization signal used in the command mode and a time point of an external synchronization signal received in the video mode; generating a parameter for shifting the internal synchronization signal based on the sampling value; shifting the internal synchronization signal based on the parameter to synchronize with the external synchronization signal; and switching from the command mode to the video mode when the internal synchronization signal of the command mode is synchronized with the external synchronization signal.

Description

Technical Field

[0001] The present disclosure relates to a method and apparatus for seamless mode conversion between a command mode and a video mode, and a display device, and more particularly, to a method and apparatus for switching between a command mode and a video mode without screen flickering when driving a display, and a display device. Background Art

[0002] Conventionally, video is generally driven at a frame rate of 60 Hz. However, in order to more realistically implement virtual reality (VR), augmented reality (AR), etc., video needs to be driven at a higher frame rate, such as 90 Hz, 120 Hz, etc. In this case, since read / write access to the frame memory is continuously performed when driving the video, power is consumed.

[0003] Both the video mode and the command mode comply with display standards. In the command mode, the synchronization signal required to drive the display panel is generated based on an internal synchronization signal generated by a built-in internal oscillator of a display driver integrated circuit (DDI). In the video mode, the synchronization signal is generated based on an external synchronization signal of a synchronization packet from a host.

[0004] In this process, it is difficult to obtain seamless conversion between the command mode and the video mode when driving a display because the clock sources for the internal synchronization signal and the external synchronization signal are different from each other and are thus asynchronous, and due to limitations on the processor and devices of the host, the synchronization signals for the two modes may occur at different times. Therefore, a method for switching between modes without screen flickering when driving a display needs to be proposed.

[0005] Methods for switching between modes without screen flickering when driving a display have been proposed. One method is to use a vertical / horizontal counter to have a count value for a period in the video mode and store the last video frame in a memory, and then generate an internal synchronization signal based on the count value for the vertical / horizontal period. Another method is to hold the current frame until the current frame is completed in the command mode and wait for an external vertical synchronization signal input in the video mode. Yet another method is to use a logic device in the host to receive an adjusted tearing effect (TE) signal and error information, and adjust the time point for sending a synchronization packet, etc.

[0006] However, when a delay or waiting time occurs due to limitations on the processor or devices of the host, such methods cannot prevent the flickering phenomenon. Summary of the Invention

[0007] Accordingly, the present disclosure relates to a method and apparatus for seamless mode conversion between a command mode and a video mode, which substantially eliminates one or more problems caused by the above limitations and disadvantages.

[0008] More specifically, the present disclosure provides a dynamic synchronization method and an apparatus for performing the dynamic synchronization method. The dynamic synchronization method gradually shifts the time point of an internal synchronization signal generated by an internal oscillator of a display driver integrated circuit (DDI) through a horizontal front porch (HFP) control method and a fine tuning control method to synchronize with the time point of an external synchronization signal received from a host. Through this dynamic synchronization method, the time points of the asynchronous internal synchronization signal and the external synchronization signal are synchronized with each other.

[0009] The problems to be solved in the present disclosure are not limited to those mentioned above, and those skilled in the art to which the present disclosure pertains can clearly understand other unmentioned problems through the following description.

[0010] According to an embodiment of the present disclosure, a method for seamless switching between a command mode and a video mode may include: receiving a command for switching from the command mode to the video mode; generating a sampling value by measuring a time interval between the time point of an internal synchronization signal used in the command mode and the time point of an external synchronization signal received in the video mode; generating a parameter for shifting the internal synchronization signal based on the sampling value; shifting the internal synchronization signal based on the parameter to synchronize with the external synchronization signal; and switching from the command mode to the video mode when the internal synchronization signal in the command mode is synchronized with the external synchronization signal.

[0011] According to an embodiment of the present disclosure, generating the sampling value may include: obtaining a first sampling value indicating the number of clocks from the time point of the internal synchronization signal to the time point of the external synchronization signal; obtaining a second sampling value indicating the number of clocks from the time point of the external synchronization signal to the time point of the internal synchronization signal; and selecting a smaller value between the first sampling value and the second sampling value.

[0012] According to an embodiment of the present disclosure, generating a parameter for shifting the internal synchronization signal based on the sampling value may include: generating a quotient and a remainder obtained by dividing the sampling value by the number of buses of a display panel; setting the quotient as a horizontal front porch (HFP) adjustment amount; and generating a fine tuning (FT) adjustment amount by multiplying the remainder by an adjustment parameter and dividing the product of the multiplication by the number of buses.

[0013] According to an embodiment of the present disclosure, synchronizing an internal synchronization signal based on parameter shifting with an external synchronization signal may include: identifying whether the internal synchronization signal and the external synchronization signal are synchronized; and when it is identified that the internal synchronization signal and the external synchronization signal are not synchronized, performing at least one of an HFP control operation and a fine-tuning control operation, wherein in the HFP control operation, the internal synchronization signal is shifted by modifying the HFP (waiting time after the output of valid data of the horizontal part) size for all horizontal parts in a frame based on an HFP adjustment amount, and in the fine-tuning control operation, the internal synchronization signal is shifted by adjusting a horizontal part end point value (H end point value) for a horizontal part in which an overflow occurs, the overflow occurring when a cumulative value obtained by accumulating an FT adjustment amount in each horizontal part is greater than an adjustment parameter.

[0014] According to an embodiment of the present disclosure, when the remainder is not 0, a fine-tuning control operation may be performed, and when the HFP adjustment amount is not 0, an HFP control operation may be performed.

[0015] According to an embodiment of the present disclosure, the HFP control operation may include: when the HFP adjustment amount is greater than an HFP adjustment maximum value, modifying the HFP adjustment amount to a preset HFP adjustment maximum value; when the HFP adjustment amount is greater than 1 and less than or equal to the HFP adjustment maximum value, decreasing the HFP adjustment amount by 1; and setting the HFP size to a value obtained by adding the HFP adjustment amount to an original HFP value or subtracting the HFP adjustment amount from the original HFP value.

[0016] According to an embodiment of the present disclosure, setting the HFP size to a value obtained by adding the HFP adjustment amount to an original HFP value or subtracting the HFP adjustment amount from the original HFP value may include: when a first sampling value is selected as the sampling value, setting the HFP size to a value obtained by adding the HFP adjustment amount to the original HFP value; and when a second sampling value is selected as the sampling value, setting the HFP size to a value obtained by subtracting the HFP adjustment amount from the original HFP value.

[0017] According to an embodiment of the present disclosure, the fine-tuning control operation may include: when a first sampling value is selected as the sampling value, increasing the horizontal part end point value by 1; and when a second sampling value is selected as the sampling value, decreasing the horizontal part end point value by 1.

[0018] According to an embodiment of the present disclosure, the method may further include: receiving a command for switching from a video mode to a command mode; and switching from the video mode to the command mode at a time point when the transmission of the current video frame is completed, rather than switching to the command mode immediately once the switching command is generated.

[0019] According to an embodiment of the present disclosure, an apparatus for seamless switching between a command mode and a video mode may include: a Display Serial Interface (DSI) block configured to receive video data and a control signal including an external synchronization signal; a buffer block configured to delay the video data and the control signal received through the DSI block; a command mode timing controller configured to generate an internal synchronization signal and load data from a frame memory based on the internal synchronization signal; a sampling count block configured to generate a sampling value by measuring a time interval between a time point of the external synchronization signal and a time point of the internal synchronization signal; an arithmetic block configured to generate a parameter for shifting the internal synchronization signal based on the sampling value; a synchronization control block configured to identify whether the internal synchronization signal and the external synchronization signal are synchronized based on the parameter, control the internal synchronization signal to be shifted when it is identified that the internal synchronization signal and the external synchronization signal are not synchronized, and switch between the video mode and the command mode when it is identified that the internal synchronization signal and the external synchronization signal are synchronized; and a data path selection block configured to output the video data and the command mode control signal received from the command mode timing controller or output the video data and the video mode control signal received from the buffer block based on a mode selection signal received from the synchronization control block.

[0020] According to an embodiment of the present disclosure, the apparatus may further include a Clock Domain Crossing (CDC) block configured to synchronize with an internal clock domain by latching the external synchronization signal with an internal oscillator clock.

[0021] According to an embodiment of the present disclosure, the sampling count block may include: a first counter block configured to measure a first sampling value indicating a number of clocks from a time point of the internal synchronization signal to a time point of the external synchronization signal; a second counter block configured to measure a second sampling value indicating a number of clocks from a time point of the external synchronization signal to a time point of the internal synchronization signal; a first sampling point register configured to store the first sampling value; and a second sampling point register configured to store the second sampling value, wherein a smaller value between the first sampling value and the second sampling value is selected as the sampling value.

[0022] According to an embodiment of the present disclosure, the arithmetic block may be configured to: obtain a quotient and a remainder obtained by dividing the sampling value output from the sampling count block by a bus number of a display panel; set the quotient as a Horizontal Front Porch (HFP) adjustment amount; generate a Fine Tuning (FT) adjustment amount by multiplying the remainder by an adjustment parameter and dividing a product of the multiplication by the bus number; and output the HFP adjustment amount, the remainder, and the FT adjustment amount as parameters.

[0023] According to an embodiment of the present disclosure, the synchronization control block may include: an HFP control block configured to control the internal synchronization signal to shift by modifying the size of the HFP (the waiting time after the valid data of the output horizontal section) for all horizontal sections in a frame based on the HFP adjustment amount; a fine-tuning control block configured to control the internal synchronization signal to shift by adjusting the horizontal section end point value (H end point value) for the horizontal section in which an overflow occurs, the overflow occurring when the cumulative value obtained by accumulating the FT adjustment amount in each horizontal section is greater than the adjustment parameter; and a synchronization control block configured to identify whether the internal synchronization signal and the external synchronization signal are synchronized, switch between the command mode and the video mode when it is identified that the internal synchronization signal and the external synchronization signal are synchronized, and control the HFP control block and the fine-tuning control block to operate when the internal synchronization signal and the external synchronization signal are not synchronized.

[0024] According to an embodiment of the present disclosure, the HFP control block may be configured to: when the HFP adjustment amount is greater than the maximum HFP adjustment value, modify the HFP adjustment amount to a preset maximum HFP adjustment value; when the HFP adjustment amount is greater than 1 and less than or equal to the maximum HFP adjustment value, reduce the HFP adjustment amount by 1; set the HFP size by adding the HFP adjustment amount to the original HFP value or subtracting the HFP adjustment amount from the original HFP value; and transmit the set HFP size to the command mode timing controller, and the command mode timing controller is configured to generate an internal synchronization signal based on the HFP size.

[0025] According to an embodiment of the present disclosure, the HFP control block may be configured to: when the first sampled value is less than the second sampled value, set the HFP size by adding the HFP adjustment amount to the original HFP value to control the time point of generating the internal synchronization signal to be delayed; and when the second sampled value is less than the first sampled value, set the HFP size by subtracting the HFP adjustment amount from the original HFP value to control the time point of generating the internal synchronization signal to be advanced.

[0026] According to an embodiment of the present disclosure, the fine-tuning control block may be configured to: when the first sampled value is less than the second sampled value, increase the horizontal section end point value by 1 for the horizontal section in which an overflow occurs; when the second sampled value is less than the first sampled value, reduce the horizontal section end point value by 1 for the horizontal section in which an overflow occurs; and transmit the horizontal section end point value to the command mode timing controller, and the command mode timing controller may be configured to set the length of the corresponding horizontal section based on the horizontal section end point value.

[0027] According to an embodiment of the present disclosure, the synchronization control block may be configured to: when the remainder is zero, control the fine-tuning control block not to operate; and when the HFP adjustment amount is zero, control the HFP control block not to operate.

[0028] According to an embodiment of the present disclosure, the synchronization control block may be configured to, when receiving a switching command, switch from the video mode to the command mode after receiving a signal indicating the completion of the transmission of the current video frame, rather than immediately switching to the command mode once a command for switching from the video mode to the command mode is received.

[0029] According to an embodiment of the present disclosure, a display device includes: a display panel configured to output a video; a Display Serial Interface (DSI) block configured to receive video data and a control signal including an external synchronization signal; a buffer block configured to delay the video data and the control signal received through the DSI block; a command mode timing controller configured to generate an internal synchronization signal and load data from a frame memory based on the internal synchronization signal; a sampling count block configured to generate a sampling value by measuring a time interval between a time point of the external synchronization signal and a time point of the internal synchronization signal; an arithmetic block configured to generate a parameter for shifting the internal synchronization signal based on the sampling value; a synchronization control block configured to identify whether the internal synchronization signal and the external synchronization signal are synchronized based on the parameter, control the internal synchronization signal to be shifted when it is identified that the internal synchronization signal and the external synchronization signal are not synchronized, and switch between the video mode and the command mode when it is identified that the internal synchronization signal and the external synchronization signal are synchronized; a data path selection block configured to output the video data and a command mode control signal received from the command mode timing controller or output the video data and a video mode control signal received from the buffer block based on a mode selection signal received from the synchronization control block; a timing controller configured to obtain video data and a control signal from a frame memory and an external device, and generate input data, a source control signal, and a gate control signal; a source driver circuit configured to generate a video signal to be displayed on the display panel based on the input data and the source control signal; and a gate driver circuit configured to sequentially output a plurality of gate signals based on the gate control signal to control the display panel.

[0030] According to the present disclosure, when driving a display, seamless mode conversion is feasible without a flickering phenomenon during mode conversion between a command mode using internal synchronization and a video mode driven by an external synchronization signal.

[0031] According to the present disclosure, due to limitations on the host processor or device, even when there is a delay or latency in the transition timing between the command mode and the video mode, a flicker phenomenon is prevented.

[0032] The effects to be achieved in the present disclosure are not limited to the foregoing effects, and those of ordinary skill in the art to which the present disclosure pertains will clearly understand other effects not mentioned above based on the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings - which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification - illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0034] In the drawings:

[0035] Figure 1 A display device according to the present disclosure is shown;

[0036] Figure 2 Display timing parameters when the display panel is driven are shown;

[0037] Figure 3 Examples of data paths in the command mode and the video mode are shown;

[0038] Figure 4 is a flowchart showing a method of synchronizing an internal synchronization signal and an external synchronization signal when transitioning from the video mode to the command mode according to the present disclosure;

[0039] Figure 5 is a diagram showing operations when transitioning from the video mode to the command mode according to the present disclosure;

[0040] Figure 6 is a flowchart showing a method of synchronizing an internal synchronization signal and an external synchronization signal when transitioning from the command mode to the video mode according to the present disclosure;

[0041] Figure 7 is a diagram showing operations performed when the interval from the internal synchronization signal to the external synchronization signal is less than the interval from the external synchronization signal to the internal synchronization signal when transitioning from the command mode to the video mode according to the present disclosure;

[0042] Figure 8 is a diagram showing operations performed when the interval from the external synchronization signal to the internal synchronization signal is less than the interval from the internal synchronization signal to the external synchronization signal when transitioning from the command mode to the video mode according to the present disclosure;

[0043] Figure 9is a flowchart showing a method of generating a sampling value by counting a time interval between an internal synchronization signal and an external synchronization signal according to the present disclosure;

[0044] Figure 10 and Figure 11 is a diagram showing an example of an operation of identifying a sampling value for description based on Figure 9 of the flowchart;

[0045] Figure 12 is a flowchart showing a method by which a mode conversion device generates a parameter to be used for shifting an internal synchronization signal;

[0046] Figure 13 is a flowchart showing a method of shifting an internal synchronization signal based on a parameter;

[0047] Figure 14 is a diagram showing an example of a horizontal front porch (HFP) control operation;

[0048] Figure 15 is a diagram showing an example of a fine tuning control operation;

[0049] Figure 16 is a diagram showing an overall configuration of a mode conversion device for seamless conversion between a video mode and a command mode according to the present disclosure;

[0050] Figure 17 is a diagram showing a detailed configuration of a sampling count block 200 according to the present disclosure;

[0051] Figure 18 is a diagram showing a configuration of a synchronization control block 400 according to the present disclosure; and

[0052] Figure 19 is a state transition diagram of a finite state machine of a synchronization control block 440 according to the present disclosure.

[0053] Throughout the drawings, the same or similar numbers may refer to the same or similar elements. Detailed Description of the Invention

[0054] The description of the present disclosure is merely for aspects of structure-to-function description, and thus the scope of the present disclosure should not be construed as being limited to the present disclosure set forth herein. In other words, the present disclosure can be modified in various ways and has various forms, and thus the scope of the present disclosure should be understood to include equivalents for implementing the technical idea.

[0055] Meanwhile, the meanings of the terms described in the present disclosure should be understood as follows.

[0056] The terms "first", "second", etc. are used herein to distinguish one element from other elements, and these elements should not be limited by these terms. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0057] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. On the other hand, other expressions used to describe the relationship between elements, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", etc. should be interpreted in the same way.

[0058] Unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. It will also be understood that the terms "comprising" or "including" when used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0059] In the steps, reference signs (e.g., a, b, c, etc.) are for convenience of description and do not imply the order of the steps. Unless the context clearly indicates otherwise, it may occur differently from the stated order. In other words, the steps may occur in the same order as stated, may be executed substantially simultaneously, or may be executed in the reverse order.

[0060] The present disclosure may be embodied in computer-readable code in a computer-readable recording medium, and the computer-readable recording medium includes all kinds of recording media on which data readable by a computer system is stored. Examples of computer-readable recording media include read-only memory (ROM), random access memory (RAM), compact disc (CD)-ROM, magnetic tape, floppy disk, optical data storage devices, etc., and also include implementations in the form of carrier waves (e.g., transmission via the Internet). Additionally, the computer-readable recording medium may be distributed on computer systems connected by a network, such that the computer-readable code can be stored and executed in a distributed manner.

[0061] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure pertains. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0062] First, terms used in the present disclosure will be briefly described.

[0063] The present disclosure provides the following dynamic synchronization method: the time point of an internal synchronization signal generated by an internal oscillator (OSC) of a display driver integrated circuit (DDI) is gradually shifted to synchronize with the time point of an external synchronization signal received from a host through a horizontal front porch (HFP) control method and a fine tuning control method, and the time points of two asynchronous synchronization signals are synchronized with each other through this dynamic synchronization method.

[0064] Here, the HFP control method refers to a method of shifting the time point of the internal synchronization signal by changing the HFP value to be applied to the entire horizontal section H, where the HFP value represents the waiting time after the effective video data of the output horizontal section.

[0065] In addition, the fine tuning control method refers to a method of shifting the time point of the internal synchronization signal by adjusting only the horizontal section end point H_endpoint for a specific horizontal section H.

[0066] An HFP limit setting register can be provided to limit the adjustable range of HFP, so that the sampling operation and the adjustment operation can overlap or be separated according to parts.

[0067] Clock gating is a technology for minimizing power waste by controlling the clock supply gate. Specifically, the internal blocks of a central processing unit (CPU) are grouped according to functions, and the clock is not supplied to unused blocks. Since the power waste generated by unused CPU blocks is eliminated, the power consumption is reduced.

[0068] Hereinafter, the present disclosure will be described in detail in the order of the accompanying drawings.

[0069] Figure 1 A display device according to the present disclosure is shown.

[0070] Referring to Figure 1 , the display device 1000 may include a device capable of displaying an image or video. For example, the display device 1000 may include, but is not limited to, a television (TV), a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a computer, a camera device, or a wearable device, etc.

[0071] The display device 1000 may include a display panel 10, a timing controller 20, a source driver circuit 30, a gate driver circuit 40, and a frame memory 50. According to the present disclosure, the gate driver circuit 40 and the display panel 10 may be provided as a single unit, and the timing controller 20 and the source driver circuit 30 may be referred to as a panel control circuit. However, the present disclosure is not limited thereto.

[0072] The display panel 10 can be configured to output video. For example, the display panel 10 can be embodied by one of a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), an actuated mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), and a vacuum fluorescent display (VFD), but is not limited thereto.

[0073] The display panel 10 can include a plurality of sub-pixels PX for emitting light. The plurality of sub-pixels PX can be arranged in rows and columns. For example, the plurality of sub-pixels PX can be arranged in a dot matrix structure including n rows and m columns (where n and m are natural numbers). In this case, the row in which the sub-pixels PX are arranged will be referred to as a sub-pixel row SPR, and the column in which the sub-pixels PX are arranged will be referred to as a sub-pixel column SPC. For example, regarding Figure 1 the first sub-pixel column, the second sub-pixel column, ……, the m-th sub-pixel column can be arranged from left to right.

[0074] The sub-pixel PX can be a basic unit from which light is emitted. The sub-pixels PX can each include a driving element. According to various aspects, each of the sub-pixels PX can emit one of red light, green light, and blue light, but is not limited thereto. For example, the sub-pixel PX can emit white light.

[0075] According to various aspects, the sub-pixel PX can include a light emitting element configured to emit light and a pixel circuit configured to drive the light emitting element. The pixel circuit can include a plurality of switching devices, and the plurality of switching devices can control the flow of a video signal and a driving voltage applied to the light emitting element. For example, the light emitting element can include a light emitting diode (LED), an organic LED (OLED), a quantum dot LED (QLED), or a micro LED, but there is no limitation on the type of the light emitting element according to various aspects of the present disclosure.

[0076] The sub-pixels PX of the display panel 10 can be driven in units of gate lines (hereinafter referred to as “lines”). In other words, the sub-pixels PX can be driven in units of sub-pixel rows. For example, the sub-pixels arranged in one gate line can be driven during a first portion, and the sub-pixels arranged in another gate line can be driven during a second portion after the first portion. In this case, the unit time portion during which the sub-pixels PX are driven can be referred to as one horizontal portion (1H time or line).

[0077] The display panel 10 can include an active display area in which the aforementioned pixels for displaying video are present and a non-active area in which video cannot be displayed.

[0078] Figure 2 Shows the timing parameters of a frame when the display panel 10 is driven.

[0079] Referring to Figure 2 , PX and PY can vary according to the resolution of the display. For example, a display with a resolution of 1920x1080 can have a PX of 1920 and a PY of 1080.

[0080] Meanwhile, inactive (blank) portions of the horizontal front porch (HFP) and horizontal back porch (HBP) may exist in the front and rear of the lines in a frame. Therefore, clocks may be consumed as much as the HFP and HBP before and after displaying video data for a line. In addition, inactive (blank) portions of the vertical front porch (VFP) and vertical back porch (VBP) may exist at the start and end of a frame. Therefore, lines may be consumed as much as the VFP and VBP before and after actually displaying video data.

[0081] Since a frame includes both an active portion and an inactive portion, one horizontal portion can be HBP + PX + HFP, and the number of lines can be VBP + PY + VFP. In the inactive portion, the video data can be dummy data.

[0082] To display one frame of data, a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync can be used. The vertical synchronization signal can be generated along with the start of the frame data, and the horizontal synchronization signal can be generated along with the start of the data in a line. The horizontal synchronization signal and the vertical synchronization signal can be used as control signals for displaying the frame data on the display panel 10.

[0083] Returning to referring Figure 1 , the frame memory 50 can be configured to temporarily store the video data of a frame to be displayed on the display panel 10 and transmit the video data to the timing controller 20 based on the control signals of the timing controller 20. The frame memory can employ a volatile memory such as a static random access memory (SRAM), but is not limited thereto. Alternatively, the frame memory can use various types of memories.

[0084] The timing controller 20 can be configured to obtain the video data from the frame memory 50 and appropriately process or transform the video data to generate the input data IN. The timing controller 20 can transmit the input data IN to the source driver circuit 30.

[0085] The timing controller 20 can be configured to receive an external control signal OCS from an external device. The external control signal OCS can include but is not limited to the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the clock signal OCLK.

[0086] The timing controller 20 may control the operations of the source driver circuit 30 and the gate driver circuit 40 based on an external control signal. According to various aspects, the timing controller 20 may be configured to receive an external control signal OCS and generate a source control signal SCS for controlling the source driver circuit 30 and a gate control signal GCS for controlling the gate driver circuit 40.

[0087] The source driver circuit 30 may be configured to generate video signals VS1 to VSm corresponding to a video displayed in the display panel 10 based on input data IN and the source control signal SCS, output the generated video signals VS1 to VSm to the display panel 10, and output the generated video signals. According to various aspects, the source driver circuit 30 may generate video signals VS1 to VSm having voltage levels corresponding to the input data IN.

[0088] The source driver circuit 30 may be configured to output the video signals VS1 to VSm to be output in the order of sub-pixel rows of the display panel 10. According to various aspects, the source driver circuit 30 may be configured to provide the video signals VS1 to VSm to be displayed in the 1H portion during the 1H portion to the sub-pixels PX driven in the 1H portion. The video signals VS1 to VSm output from the source driver circuit 30 may be transmitted to the sub-pixels PX through the data lines DL1 to DLm of the display panel 10.

[0089] The gate driver circuit 40 may be configured to sequentially output a plurality of gate signals GS1 to GSn in response to the gate control signal GCS.

[0090] The gate signals GS1 to GSn are signals for respectively turning on the sub-pixels PX connected to the gate lines GL1 to GLn and may be applied to the gate terminals of the transistors respectively included in the sub-pixels PX. According to various aspects, each of the gate signals GS1 to GSn may include at least one of a scan signal, a light emission signal, and an initialization signal.

[0091] According to various aspects, the frame memory 50, the timing controller 20, the source driver circuit 30, and the gate driver circuit 40 may be embodied as a single integrated circuit (IC) because they are all included in a driver IC for the command mode. According to another aspect, the three circuits other than the frame memory 50 may be embodied as a single IC because they are included in a driver IC for only the video mode. According to still another aspect, the timing controller 20, the source driver circuit 30, and the gate driver circuit 40 may be embodied as being mounted on the display panel 10.

[0092] Figure 3 An example of the data path in the command mode and the video mode is shown.

[0093] Referring to Figure 3 , in command mode, video data received from an external device or host can be stored in frame memory 50 via a Display Serial Interface (DSI) 800, and a command mode timing controller 700 can obtain the video data from frame memory 50 and transfer the video data to a data path selection block 500 while generating a control signal including internal synchronization signals such as a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync, so as to display the video on a display panel 10.

[0094] In video mode, video and a control signal including external synchronization signals such as a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync can be received from an external device or host via DSI 800, and the video and the control signal are transferred to the data path selection block 500. Based on a control signal regarding whether to select video mode or command mode, the data path selection block 500 can output the control signal and video data along path 3000 according to video mode, or output the control signal and video data along path 2000 according to command mode.

[0095] In this case, since the internal synchronization signal generated in command mode is not synchronized with the external synchronization signal used in video mode, flickering may occur during mode transition.

[0096] According to the present disclosure, for seamless transition, that is, to prevent flickering during mode transition, it is proposed to add a synchronization controller 4000 for controlling the external synchronization signal and the internal synchronization signal to be synchronized with each other. In this case, a buffer block 600 can also be added on path 3000 for video mode to buffer the signal received via DSI 800 while the synchronization controller 4000 synchronizes the external synchronization signal and the internal synchronization signal with each other. In addition, the synchronization controller 4000 at least includes, for example, a Clock Domain Crossing (CDC) block 100, a sampling count block 200, an arithmetic block 300, and a synchronization control block 400 as Figure 16 shown.

[0097] The device shown for switching between video mode and command mode without flickering Figure 3 shown can be used to replace Figure 1 the timing controller 20 of the display device shown, or can be placed between the frame memory 50 and the timing controller 20 and provide the control signal and video data to the timing controller 20.

[0098] First, the operation of the device shown for switching between video mode and command mode without flickering Figure 3 shown will be described.

[0099] Figure 4It is a flowchart showing a method of synchronizing an internal synchronization signal and an external synchronization signal when switching from a video mode to a command mode according to the present disclosure.

[0100] Referring to Figure 4 , at operation S400, the display device 1000 or the mode conversion device may receive a command for switching from a video mode driven by an external synchronization signal to a command mode using an internal synchronization signal.

[0101] At operation S410, once the command for the conversion is received, the mode conversion device may not immediately switch to the command mode but identify whether the transmission of the video frame currently transmitted to the display panel 10 is completed.

[0102] At operation S411, when it is identified that the transmission of the video frame has not been completed, the video mode may be maintained.

[0103] At operation S420, after the transmission of the video frame is completed, the mode conversion device switches from the video mode to the command mode and generates an internal synchronization signal.

[0104] When the transmission of one video frame is completed and the transmission of the next video frame starts, an external synchronization signal may be input. Therefore, when the internal synchronization signal is generated through the foregoing operation after the transmission of one video frame is completed, the internal synchronization signal may be synchronized with the external synchronization signal. Thus, flickering can be prevented.

[0105] Figure 5 Shows the operations when switching from a video mode to a command mode according to the present disclosure.

[0106] Referring to Figure 5 , a command for switching from a video mode to a command mode (VID_ON = 0) may be received at a point 500 in the middle of transmitting one frame. Then, as Figure 5 shown, the mode conversion device waits for a transmission completion signal without immediately switching to the command mode and generating an internal synchronization signal. The mode conversion device may perform a mode conversion from the video mode to the command mode for the display device at a point 510 where the transmission completion signal is identified. In addition, an internal synchronization signal may be generated.

[0107] According to one aspect, as Figure 5 shown, the internal clock signal may not be applied to the internal logic device by gating control in the video mode to reduce power consumption, but may be applied to the internal logic device by releasing the gating after switching to the command mode. Similarly, even if the gating is released in the video mode, the external clock signal may not be applied to the internal logic device by gating in the command mode.

[0108] Figure 6It is a flowchart showing a method of synchronizing an internal synchronization signal and an external synchronization signal when switching from a command mode to a video mode according to the present disclosure.

[0109] Referring to Figure 6 , at operation S610, the display device 1000 or the mode conversion device may receive a command (VID_ON = 1) for switching from a command mode driven by an internal synchronization signal to a video mode using an external synchronization signal.

[0110] At operation S620, the mode conversion device may count the time interval between the internal synchronization signal and the external synchronization signal. Here, the time interval may be counted as the number of clocks from an internal oscillator, and a sampling value may be generated based on the counted number of clocks.

[0111] At operation S630, the mode conversion device may generate a parameter for shifting the internal synchronization signal based on the sampling value.

[0112] At operation S640, the mode conversion device may shift the internal synchronization signal based on the generated parameter. In this case, the internal synchronization signal may be shifted by an HFP control method and a fine tuning control method (to be described later).

[0113] At operation S650, when the synchronization between the internal synchronization signal and the external synchronization signal is completed, the mode conversion device may switch the display device 1000 from a command mode using the internal synchronization signal to a video mode driven by the external synchronization signal.

[0114] Figure 7 Shows operations performed when switching from a command mode to a video mode according to the present disclosure when the interval from the internal synchronization signal to the external synchronization signal is less than the interval from the external synchronization signal to the internal synchronization signal.

[0115] Referring to Figure 7 , when the interval from the internal synchronization signal to the external synchronization signal is less than the interval from the external synchronization signal to the internal synchronization signal, the mode conversion device may shift the time point of the internal synchronization signal in the direction to be gradually delayed (710, 720, 730) by an HFP control method or a fine tuning control method.

[0116] Here, when the time point at which the internal synchronization signal is shifted falls within a preset target range, the synchronization is completed, and thus the command mode may be switched to the video mode.

[0117] Figure 8 Shows operations performed when switching from a command mode to a video mode according to the present disclosure when the interval from the external synchronization signal to the internal synchronization signal is less than the interval from the internal synchronization signal to the external synchronization signal.

[0118] Reference Figure 8 When the interval from the external synchronization signal to the internal synchronization signal is less than the interval from the internal synchronization signal to the external synchronization signal, the mode conversion device can shift the time point of the internal synchronization signal in the direction (810, 820, 830) to be gradually advanced by the HFP control method or the fine tuning control method.

[0119] Here, when the time point at which the internal synchronization signal is shifted falls within a preset target range, the mode can be switched from the command mode to the video mode.

[0120] Figure 9 is a flowchart showing a method of generating a sampling value by counting the time interval between an internal synchronization signal and an external synchronization signal according to the present disclosure. Figure 9 can show Figure 6 Aspects of operation S620 in

[0121] Reference Figure 9 In operation S910, the mode conversion device can obtain a first sampling value indicating the time interval from the time point of the internal synchronization signal to the time point of the external synchronization signal.

[0122] In addition, in operation S920, the mode conversion device can obtain a second sampling value indicating the time interval from the time point of the external synchronization signal to the time point of the internal synchronization signal.

[0123] In operation S930, the mode conversion device can select the smaller value between the first sampling value and the second sampling value and identify the selected value as the final sampling value.

[0124] In operations S910 and S920, the sampling value indicating the time interval between the time points of the two synchronization signals can be based on the number of clocks of the internal oscillator during the corresponding time interval.

[0125] Figure 10 and Figure 11 shows an example of an operation for identifying a sampling value based on Figure 9 a flowchart.

[0126] Reference Figure 10 The mode conversion device can start counting from the internal synchronization signal point 1031, end counting at the external synchronization signal point 1041, and store the first sampling value SAMPLE_POINT1, which is the count value up to that time.

[0127] In addition, the mode conversion device can start counting from the external synchronization signal point 1041, end counting at the internal synchronization signal point 1033, and store the second sampling value SAMPLE_POINT2, which is the count value up to that time.

[0128] Referring to Figure 11 , the mode conversion device can start counting from the internal synchronization signal point 1151, end counting at the external synchronization signal point 1161, and store the first sampling value SAMPLE_POINT1, which is the count value up to that time.

[0129] In addition, the mode conversion device can start counting from the external synchronization signal point 1161, end counting at the internal synchronization signal point 1153, and store the second sampling value SAMPLE_POINT2, which is the count value up to that time.

[0130] The foregoing operations can be repeatedly executed as shown in Figure 10 and Figure 11 .

[0131] Figure 10 The difference between Figure 11 is based on the difference between the first sampling value and the second sampling value. Figure 10 shows the case where the second sampling value is small, and Figure 11 shows the case where the first sampling value is small. To reduce the time spent in performing synchronization, the smaller sampling value can be used in synchronizing the external synchronization signal and the internal synchronization signal. Therefore, in the operation S930 of Figure 9 , the mode conversion device can select the second sampling value as the sampling value in the case of Figure 10 , and select the first sampling value as the sampling value in the case of Figure 11 .

[0132] Figure 12 is a flowchart showing a method for the mode conversion device to generate parameters for shifting the internal synchronization signal. Figure 12 The aspects of the operation S630 in Figure 6 can be shown.

[0133] The parameters for the mode conversion device to shift the internal synchronization signal may include the HFP adjustment amount used in the HFP control method, the FT adjustment amount used in the fine-tuning control method, and the remainder.

[0134] In the HFP control method, the HFP value applied to all horizontal portions H included in one frame, that is, included between two adjacent vertical synchronization signals Vsync, is changed so as to shift the internal synchronization signal point. In this case, the HFP value is changed in all lines, and thus the point for generating the next vertical synchronization signal may be very different from the original point.

[0135] In the fine-tuning control method, only the endpoints of the horizontal portion H are adjusted for a specific horizontal portion, thereby shifting the internal synchronization signal point.

[0136] Reference Figure 12 At operation S1210, the mode conversion device may obtain an HFP adjustment amount based on the quotient obtained by dividing the sampling value by the horizontal portion, i.e., the number of lines in a frame, as shown in Equation 1 below.

[0137] HFP adjustment amount = sampling value / number of lines - [Equation 1]

[0138] Here, as Figure 2 shown, the number of lines may involve VBP (vertical back porch), PY, and VFP (vertical front porch).

[0139] In addition, the fine tuning control is for as many adjustments as the number of sampling counts not adjusted by the HFP control. For this purpose, at operation S1220, the mode conversion device may calculate the remainder that cannot be adjusted by the HFP control, i.e., the sampling count, as shown in Equation 2 below.

[0140] Remainder = sampling value % number of lines - [Equation 2]

[0141] In addition, at operation S1230, another parameter for the fine tuning control, i.e., the FT adjustment amount, may be obtained by multiplying the adjustment parameter by the remainder and dividing it by the number of lines, as shown in Equation 3 below. In Equation 3, the adjustment parameter may be 1 greater than the maximum value of the FT adjustment amount. For example, when the FT adjustment amount is represented by 16 bits, the maximum value that the FT adjustment amount can have is "FFFFh", and thus the adjustment parameter may be "10000h", i.e., 2^16.

[0142] FT adjustment amount = adjustment parameter * remainder / number of lines - [Equation 3]

[0143] Figure 13 is a flowchart showing a method of shifting an internal synchronization signal based on parameters. Figure 13 may show Figure 6 aspects of operation S640 in

[0144] Reference Figure 13 At operation S1310, the mode conversion device may obtain the parameters HFP adjustment amount, remainder, and FT adjustment amount generated in operation S630.

[0145] At operation S1315, the mode conversion device may identify whether the internal synchronization signal and the external synchronization signal are synchronized. According to one aspect, the mode conversion device may identify whether the internal synchronization signal and the external synchronization signal are synchronized by identifying whether the internal synchronization signal falls within the target range of the external synchronization signal based on the HFP adjustment amount and / or the remainder. When it is identified that the internal synchronization signal and the external synchronization signal are synchronized, the mode conversion device no longer needs to perform the control for shifting the internal synchronization signal and may terminate the control.

[0146] When it is recognized that the internal synchronization signal and the external synchronization signal are not synchronized and the internal synchronization signal needs to be shifted, the mode conversion device may perform the HFP control operation of operation S1320 and the fine-tuning control operation of operation S1330 based on the received parameters.

[0147] The fine-tuning control operation may be performed only when the remainder is not zero.

[0148] In addition, according to one aspect, when both the HFP control operation and the fine-tuning control operation are required, the HFP control operation may be performed first, and then the fine-tuning control operation may be performed; the fine-tuning control operation may be performed first, and then the HFP control operation may be performed; or the HFP control operation and the fine-tuning control operation may be performed simultaneously.

[0149] At operation S1320, the HFP control operation may be performed to first change the HFP adjustment amount.

[0150] 1) When the HFP adjustment amount is greater than the preset HFP adjustment maximum value HFP_LIMIT, the HFP adjustment amount may be changed to the HFP adjustment maximum value. Thus, problems such as some insufficient driving time and excessive frame rate drop that may occur when driving the display can be eliminated. When the HFP adjustment amount is greater than the HFP adjustment maximum value, the adjustment operation may be continuously performed by sequentially reflecting the sampled values generated in operation S620. Thus, it is possible to quickly reach near the target external synchronization signal. However, when the sampling operation in operation S620 and the adjustment operation in operation S640 are performed simultaneously, the sampling result may be relatively inaccurate.

[0151] 2) When the HFP adjustment amount is greater than 1 and less than or equal to the HFP adjustment maximum value, it may be changed to, for example, HFP adjustment amount = HFP adjustment amount - 1. Thus, the adjustment operation when the HFP adjustment amount becomes 1 can always be performed. In addition, in this case, the sampled values in operation S620 obtained while the adjustment operation in operation S640 is being performed are not used. In other words, the sampling operation in operation S620 and the adjustment operation in operation S640 are performed separately, so that relatively accurate sampled values can be obtained, thereby achieving precise adjustment. However, the adjustment may take more time.

[0152] 3) When the HFP adjustment amount is less than or equal to 1, the HFP adjustment amount can remain as it is. Therefore, when the calculated HFP adjustment amount is 1, an adjustment operation with a minimum HFP adjustment amount of 1 can be performed. Even in this case, the sampled values in operation S620 obtained while the adjustment operation in operation S640 is being executed are not used. In other words, the sampling operation in operation S620 and the adjustment operation in operation S640 are executed separately, so that relatively accurate sampled values can be obtained, thereby achieving precise adjustment. However, the adjustment may take more time.

[0153] Next, the HFP control operation can be modified to use the finally adjusted HFP adjustment amount when setting the HFP size.

[0154] The HFP size can be decreased or increased based on the adjustment direction information of the internal synchronization signal. When Figure 9 the selected small value is the first sampled value, the internal synchronization signal needs to be delayed to synchronize with the external synchronization signal. When the selected small value is the second sampled value, the internal synchronization signal needs to be advanced to synchronize with the external synchronization signal. Therefore, when the sampled value is the first sampled value, the HFP adjustment amount can be added to the original HFP value to increase the HFP size, and when the sampled value is the second sampled value, the HFP adjustment amount can be subtracted from the original HFP value to decrease the HFP size.

[0155] The final HFP size value can be transmitted to the command mode timing controller set in the mode conversion device, which generates an internal synchronization signal, and each horizontal synchronization signal of the command mode timing controller can be synchronously generated at the time interval of "HBP + PX + HFP". Since the same number of horizontal synchronization signals, i.e., the same number of lines, are provided between vertical synchronization signals, the internal synchronization signal may shift relative to the external synchronization signal while generating the next vertical synchronization signal later or earlier than the original vertical synchronization signal.

[0156] The operations shown in Figure 13 can be repeated until it is recognized that the internal synchronization signal and the external synchronization signal are synchronized with each other.

[0157] Figure 14 An example of the HFP control operation is shown.

[0158] Referring to Figure 14 , when a predetermined period of time has elapsed after each of the internal vertical synchronization signals 1410 to 1417, calculation completion signals 1420 to 1427 can be generated to notify that the parameters have been completely calculated in operation S630. Figure 14 The HFP adjustment amounts 1430 to 1435 calculated in operation S630 are shown.

[0159] Through the HFP control operation, the HFP adjustment amount is modified based on the calculated HFP adjustment amount so as to obtain a modified HFP adjustment amount 1440 to 1446, and the modified HFP adjustment amount 1440 to 1446 is added to the original HFP value (e.g., 48) so as to obtain a final HFP size 1450 to 1456.

[0160] When the calculated HFP adjustment amount 1430 is 30 in the example of Figure 14 it is greater than the HFP adjustment maximum value (e.g., 8) and thus the modified HFP adjustment amount 1440 can become 8. Accordingly, as the modified HFP adjustment amount is added to the original HFP value, the HFP size 1450 can become 56 (frame rate decrease) or 40 (frame rate increase). When such an adjustment is made, the internal vertical synchronization signal is shifted toward the external vertical synchronization signal, so that the HFP adjustment amount 1431 becomes 22. Since this HFP adjustment amount is also greater than the HFP adjustment maximum value, the modified HFP adjustment amount 1441 becomes 8, and the HFP size 1451 becomes 56 (frame rate decrease) or 40 (frame rate increase). Through this adjustment, the internal vertical synchronization signal is further shifted toward the external vertical synchronization signal, and thus the HFP adjustment amount 1432 becomes 14. Since this HFP adjustment amount is also greater than the HFP adjustment maximum value, the modified HFP adjustment amount 1442 becomes 8, and the HFP size 1452 becomes 56 (frame rate decrease) or 40 (frame rate increase). Through this adjustment, the internal vertical synchronization signal is further shifted toward the external vertical synchronization signal, and thus the HFP adjustment amount 1433 becomes 6. Since this HFP adjustment amount is greater than 1 and less than or equal to the HFP adjustment maximum value, the modified HFP adjustment amount 1443 is decreased by 1 to become 5, and the HFP size 1453 becomes 53 (frame rate decrease) or 43 (frame rate increase).

[0161] In a part where the HFP adjustment amount is less than or equal to the HFP adjustment maximum value, the adjustment operation in operation S640 and the sampling operation in operation S620 can be respectively performed. Accordingly, in a part of the internal vertical synchronization signal 1413, as the HFP size 1453 is applied in operation S640, the internal vertical synchronization signal is shifted. In a part of the next internal vertical synchronization signal 1414, sampling can be performed without performing the adjustment operation. Accordingly, the parameter calculation in operation S630 may not be performed in this part, and thus the same HFP adjustment amount 1433 of 6 can be maintained. In addition, the modified HFP adjustment amount can be 0 so as not to perform the HFP control operation in this part, and thus the HFP size 1454 can be equal to the original HFP value. This can relatively accurately measure the time interval between the external synchronization signal and the internal synchronization signal.

[0162] When generating the internal vertical synchronization signal 1415, sampling is completed without the HFP control operation, the parameters are calculated again, and the calculation completion signal 1425 is generated. The HFP adjustment amount 1434 in this case can be modified to 1 because, as a result of the previous adjustment, the internal vertical synchronization signal has shifted further towards the external vertical synchronization signal. Since this HFP adjustment amount is equal to 1, the modified HFP adjustment amount 1445 of 1 can remain as it is, and the HFP size 1455 can become 49 (frame rate decrease) or 47 (frame rate increase).

[0163] In the portion of the internal vertical synchronization signal 1416, for accurate sampling, the HFP control operation is not performed, the HFP adjustment amount 1434 remains as it is, the modified HFP adjustment amount 1446 becomes 0, and the HFP size 1456 has the original HFP value.

[0164] When generating the internal vertical synchronization signal 1417, sampling can be completed without the HFP control operation, the parameters can be calculated again, and calculation completion 1427 can be generated. The HFP adjustment amount 1435 in this case becomes 0, such that the HFP control operation can no longer be performed, and the HFP size 1456 can remain at the original HFP value of 48.

[0165] In operation S1330, a fine-tuning control operation can be performed to increase or decrease a specific horizontal portion by 1. As Figure 2 shown, one horizontal portion can be identified as HBP + PX + HFP, and such an added value can be referred to as the horizontal portion endpoint value H endpoint value. The specific horizontal portion can be increased or decreased by 1 based on the adjustment direction information of the internal synchronization signal. When Figure 9 the selected small value is the first sampling value, the internal synchronization signal needs to be delayed to synchronize with the external synchronization signal. When the selected small value is the second sampling value, the internal synchronization signal needs to be advanced to synchronize with the external synchronization signal. Therefore, when the sampling value is the first sampling value, the horizontal portion endpoint value can be increased by 1. When the sampling value is the second sampling value, the horizontal portion endpoint value can be decreased by 1. Increasing or decreasing the horizontal portion endpoint value by 1 may mean increasing or decreasing the HFP value by 1 in the corresponding horizontal portion. Therefore, HFP control is to modify the HFP across the entire horizontal portion, while fine-tuning control is to increase or decrease the HFP by 1 in a specific horizontal portion.

[0166] The fine-tuning control operation can use the FT adjustment amount to identify the horizontal portion whose horizontal portion endpoint value is to be modified. In Equation 3, it is assumed that the FT adjustment amount is represented by 16 bits, but the FT adjustment amount can be represented by other bits. As the number of bits representing the FT adjustment amount increases, finer adjustment is possible.

[0167] The fine control operation can accumulate the FT adjustment amount in each horizontal section. In addition, the horizontal section endpoint value of the horizontal section where the accumulated FT adjustment amount overflows can be modified.

[0168] Figure 15 An example of the fine control operation is shown.

[0169] Referring to Figure 15 , a plurality of internal horizontal synchronization signals 1520 to 1529 indicating the start of the horizontal section can be generated after the internal vertical synchronization signal 1510 indicating the start of the frame.

[0170] When the internal vertical synchronization signal 1510 is generated, sampling in a section can be completed, and thus the generation of the parameters in operation S630 can be completed. The completion of the parameter generation can be indicated by the calculation completion signal 1530. Referring to Figure 15 , the FT adjustment amount in the parameters generated by operation S630 can be 8000h. Here, "h" can indicate a hexadecimal number.

[0171] The accumulated value can be obtained by accumulating the FT adjustment amount value on the previously accumulated value in each horizontal section 1540 to 1549. As a result of the accumulation, there may be horizontal sections 1541, 1543, 1545, 1547, and 1549 where overflow occurs. Overflow may occur when the number of bits used to represent the FT adjustment amount is 16 but the value cannot be represented by 16 bits. For example, the 17th bit is required to represent 8000h + 8000h = 10000h. Therefore, when the FT adjustment amount is represented by 16 bits, the accumulated value is represented by 17 bits, and when the 17th bit becomes 1, it can be recognized that overflow has occurred. When overflow occurs, the 17th bit can be reset to 0 again. As another method of identifying overflow, overflow is recognized when a carry is generated when the 16-bit FT adjustment amount is added to the 16-bit accumulated value. In other words, when the value exceeds the expression range of the 16-bit accumulative adder, which means the accumulated value is greater than or equal to 2^16, overflow occurs. In the horizontal section where overflow occurs, in the case of a frame rate decrease where the internal synchronization signal needs to be delayed, the horizontal section endpoint value increases by 1, but in the case of a frame rate increase where the internal synchronization signal needs to be advanced, the horizontal section endpoint value decreases by 1. In Figure 15 the example shown, for the horizontal sections 1541, 1543, 1545, 1547, and 1549 where overflow occurs, the horizontal section endpoint value becomes 401 in the case of a frame rate decrease, and the horizontal section endpoint value becomes 399 in the case of a frame rate increase.

[0172] Through the foregoing operations, the mode conversion device synchronizes the internal synchronization signal used in the command mode with the external synchronization signal used in the video mode within a preset target range (e.g., the target difference in the number of internal clocks). Then, in operation S650, when the difference in the number of clocks between the internal synchronization signal and the external synchronization signal is within the preset target range, the mode conversion device can switch from the command mode to the video mode.

[0173] As described above, the internal synchronization signal and the external synchronization signal are synchronized when converting from the command mode to the video mode or when converting from the video mode to the command mode, thereby preventing flickering that may occur during mode conversion.

[0174] Figure 16 Shows the overall configuration of a mode conversion device for seamless conversion between video mode and command mode according to the present disclosure.

[0175] Refer to Figure 16 , the mode conversion device may include a clock domain crossing (CDC) block 100, a sampling count block 200, an arithmetic block 300, a synchronization control block 400, a data path selection block 500, a buffer block 600, a command mode timing controller 700, and a display serial interface (DSI) block 800.

[0176] For ease of understanding, in addition to the mode conversion device, Figure 16 a frame memory 50 is also shown.

[0177] DSI refers to a standard defined by the Mobile Industry Processor Interface (MIPI) Alliance, which defines a serial bus and communication protocol between a host that provides video data and a destination device for the video data.

[0178] The DSI block 800 can be connected to the host through DSI and is configured to receive video data to be displayed on the pixels of the display panel 10 and control signals from the host. In Figure 16 the example shown, DSI is used to access the host, but it is not limited thereto. Alternatively, other communication protocols and interfaces can be used to access the host.

[0179] The buffer block 600 can perform CDC processing and sampling operations on the external synchronization signal received from the host in video mode, and an operation for delaying the signal received through the DSI block 800 by as much time as required to convert from the command mode to the video mode. According to one aspect, the buffer block 600 may include a first-in first-out (FIFO) or a shift register.

[0180] The CDC block 100 can be configured to latch an external synchronization signal received from a host to an internal oscillator, so as to synchronize the external synchronization signal with the internal clock domain. Therefore, the synchronization controller 4000 can be configured to operate in synchronization with an internal clock and prevent failures caused by asynchrony.

[0181] The data path selection block 500 can be configured to output data and synchronization signals generated by the command mode timing controller 700 or received from the buffer block 600 according to a set mode. The data path selection block 500 can select a path based on a signal (video enable) received from the synchronization control block 400 (to be described later).

[0182] The sampling count block 200 can measure the time interval between the time point of an external synchronization signal (hereinafter referred to as "external synchronization signal") subjected to CDC processing and the time point of an internal synchronization signal based on the number of clocks in the internal oscillator 900.

[0183] Figure 17 A detailed configuration of the sampling count block 200 according to the present disclosure is shown.

[0184] Refer to Figure 17 , the sampling count block 200 can include a first counter block 210, a second counter block 220, a first sampling point register 215, and a second sampling point register 225.

[0185] The first counter block 210 counts the number of clocks in the internal oscillator from the time point of an internal synchronization signal (e.g., internal vertical synchronization signal) to the time point of an external synchronization signal (e.g., external vertical synchronization signal latched by the CDC block 100). Then, the counted number of clocks can be stored in the first sampling point register 215.

[0186] The second counter block 220 counts the number of clocks in the internal oscillator from the time point of an external synchronization signal (e.g., external vertical synchronization signal latched by the CDC block 100) to the time point of an internal synchronization signal (e.g., internal vertical synchronization signal). Then, the counted number of clocks can be stored in the second sampling point register 225.

[0187] The operation of the sampling count block 200 will be described with reference to Figure 10 and Figure 11 the foregoing examples shown.

[0188] Refer to Figure 10, the first counter block 210 can start counting from the internal synchronization signal point 1031, end counting at the external synchronization signal point 1041, and store the first sampled value SAMPLE_POINT1 in the first sample point register 215, which is the count value up to that time.

[0189] The second counter block 220 can start counting from the external synchronization signal point 1041, end counting at the internal synchronization signal point 1033, and store the second sampled value SAMPLE_POINT2 in the second sample point register 225, which is the count value up to that time.

[0190] Referring to Figure 11 , the first counter block 210 can start counting from the internal synchronization signal point 1151, end counting at the external synchronization signal point 1161, and store the first sampled value SAMPLE_POINT1 in the first sample point register 215, which is the count value up to that time.

[0191] The second counter block 220 can start counting from the external synchronization signal point 1161, end counting at the internal synchronization signal point 1153, and store the second sampled value SAMPLE_POINT2 in the second sample point register 225, which is the count value up to that time.

[0192] The foregoing operations of the sampling count block 200 can be repeated as Figure 10 and Figure 11 shown.

[0193] Figure 10 The difference between Figure 11 is based on the difference between the first sampled value and the second sampled value. Figure 10 shows the case where the second sampled value is small, and Figure 11 shows the case where the first sampled value is small. To reduce the time spent in performing the entire operation, a smaller sampled value can be used in synchronizing the external synchronization signal and the internal synchronization signal. Therefore, the sampling count block 200 can select the second sampled value to be transmitted to the arithmetic block 300 in the case of Figure 10 , and can select the first sampled value to be transmitted to the arithmetic block 300 in the case of Figure 11 .

[0194] The sampled value calculated in the sampling count block 200 can be the number of internal oscillator clocks required to shift the time point of the internal synchronization signal to the time point of the external synchronization signal in order to synchronize the internal synchronization signal with the external synchronization signal.

[0195] The arithmetic block 300 may be configured to calculate and output information regarding sampling values, quotients, etc., which are used to identify control methods in the synchronization control block 400 (to be described later), and the quotient is obtained by dividing the sampling value by the number of buses.

[0196] The arithmetic block 300 may be configured to receive a sampling value from the sampling count block 200 and obtain an HFP adjustment amount and an FT adjustment amount to be used in the HFP control method and / or the fine tuning control method based on the received sampling value.

[0197] As described above, the HFP control method is to change the HFP value to be applied to all horizontal portions H included in one frame, i.e., between two adjacent vertical synchronization signals Vsync, so as to shift the internal synchronization signal point, and the HFP value indicates the standby time after the output of the horizontal portion.

[0198] The fine tuning control method refers to a method of shifting the internal synchronization signal point by fine tuning the horizontal portion endpoints H endpoints only for specific horizontal portions.

[0199] The arithmetic block 300 is configured to obtain the HFP adjustment amount required for HFP control for one horizontal portion 1H by dividing the selected sampling value by the total number of horizontal portions, as in the foregoing equation 1.

[0200] In addition, the remainder used as the basis for performing the fine tuning control and the FT adjustment amount required for performing the fine tuning control can be calculated based on the foregoing equations 2 and 3. In this calculation, it is assumed that the FT adjustment amount has a bit width of 16 bits.

[0201] The synchronization control block 400 may be configured to control the synchronization between the internal synchronization signal and the external synchronization signal based on the output value of the arithmetic block 300.

[0202] Figure 18 The configuration of the synchronization control block 400 according to the present disclosure is shown.

[0203] Refer to Figure 18 , the synchronization control block 400 may include a fine tuning control block 410, an HFP control block 420, a clock gating control block 430, and a synchronization control block 440.

[0204] The HFP control block 420 may be configured to perform HFP control based on Figure 13 operation S1320 of. As Figure 14 shown, in order to shift the internal synchronization signal, the HFP control block 420 may be configured to identify the HFP size to be applied to all horizontal portions in each frame portion and provide the identified HFP size to the command mode timing controller 700.

[0205] The fine-tuning control block 410 may be configured to perform fine-tuning control based on Figure 13 the operation S1330. As Figure 15 shown, in order to finely shift the internal synchronization signal, the fine-tuning control block 410 may be configured to control the internal synchronization signal to be finely shifted by increasing or decreasing the endpoint value in a specific horizontal portion by 1, and provide the increased or decreased endpoint value to the command mode timing controller 700.

[0206] The clock gating control block 430 may be configured to reduce power consumption by gating the clocks related to the video mode and the clocks related to the command mode based on the control of the synchronization control block 440.

[0207] The synchronization control block 440 may be configured to provide signals for operating the HFP control block 420 and the fine-tuning control block 410. The HFP control block 420 and the fine-tuning control block 410 may start and end operations based on the operation control signals and parameters received from the synchronization control block 440.

[0208] The synchronization control block 440 may be configured to control the transition from the command mode to the video mode when the internal synchronization signal is shifted to fall within a target range in which the internal synchronization signal can be recognized as synchronized with the external synchronization signal.

[0209] To identify whether the internal synchronization signal falls within the target range, the synchronization control block 440 may use the sampled value or the HFP adjustment amount and the remainder value, which indicate the time interval between the external synchronization signal and the internal synchronization signal.

[0210] The synchronization control block 440 may be configured to control the current operation mode of the display device. The synchronization control block 440 may identify whether the display device is operating in the command mode or the video mode.

[0211] In addition, the synchronization control block 440 may be configured to provide control information to the data path selection block 500 and the clock gating control block 430 based on the current mode in which the display device operates.

[0212] According to one aspect, the synchronization control block 440 may be configured to provide a control signal for allowing the data path selection block 500 to output the signal received from the command mode timing controller 700 and a control signal for allowing the clock gating control block 430 to gate the clocks related to the video mode when the current mode of the display device is the command mode.

[0213] According to another aspect, the synchronization control block 440 may be configured to provide a control signal for allowing the data path selection block 500 to output a signal received from the buffer block 600 and a control signal for allowing the clock gating control block 430 to gate a clock related to the command mode when the current mode of the display device is the video mode. Accordingly, power consumption can be reduced by gating the internal oscillator clock input to the frame memory 50, the command mode timing controller 700, the CDC block 100, the sampling count block 200, the arithmetic block 300, the fine tuning control block 410, and the HFP control block 420.

[0214] To perform the foregoing operations, the synchronization control block 440 may operate a finite state machine. The finite state machine operated by the synchronization control block 440 may have states as shown in Table 1 below.

[0215] [Table 1]

[0216]

[0217]

[0218] Figure 19 is a state transition diagram of the finite state machine of the synchronization control block 440 according to the present disclosure.

[0219] Referring to Figure 19 ,"Done" may indicate a state in which the display device operates in the video mode. In "Done", the synchronization control block 440 may provide a control signal for allowing the data path selection block 500 to output a signal received from the buffer block 600, and a control signal for allowing the clock gating control block 430 to gate a clock related to the command mode.

[0220] When a signal for switching to the command mode is received in "Done" (VID_ON = 0), the synchronization control block 440 may enter the "idle state". In this case, when the parameter is set to synchronize the external synchronization signal with the internal synchronization signal (SYNC_ENABLE = 1), the synchronization control block 440 enters the "idle state" after performing synchronization as shown in Figure 4 , or directly enters the "idle state" when synchronization is not required (SYNC_ENABLE = 0).

[0221] "Idle state" may indicate a state in which the display device operates in the command mode. In the "idle state", the synchronization control block 440 may provide a control signal for allowing the data path selection block 500 to output a signal received from the command mode timing controller 700, and a control signal for allowing the clock gating control block 430 to gate a clock related to the video mode.

[0222] When a signal for switching to the video mode is received in the "idle state" (VID_ON = 1) but synchronization is not required (SYNC_ENABLE = 0), the synchronization control block 440 can directly enter the "completed" state. When the parameter is set to synchronize the external synchronization signal with the internal synchronization signal (SYNC_ENABLE = 1), the synchronization control block 440 can enter the "sampling initialization", and then enter the "completed" state after synchronizing the internal synchronization signal with the external synchronization signal, as Figure 6 shown.

[0223] When a signal for switching to the video mode is received in the "idle state" (VID_ON = 1) and the parameter is set to perform synchronization (SYNC_ENABLE = 1), the synchronization control block 440 can enter the "sampling initialization".

[0224] "Sampling initialization" indicates the sampling standby state, and in this state, the sampling count block 200 can be ready to start sampling in response to the internal synchronization signal. When an internal synchronization signal (int_vsync = 0) is generated during "sampling initialization", the synchronization control block 440 can enter the "sampling point 1".

[0225] In "sampling point 1", the sampling count block 200 can perform sampling to obtain a first sampling value, obtain the first sampling value that undergoes sampling when the external synchronization signal is received, and perform sampling to obtain a second sampling value. Therefore, when an external synchronization signal (cdc_vid_vsync = 0) is received in "sampling point 1", the synchronization control block 440 can cause the finite state machine to enter the "sampling point 2".

[0226] "Sampling point 2" can indicate the state where the sampling count block 200 performs sampling on the second sampling value. When an internal synchronization signal (int_vsync = 0) is received in "sampling point 2", the synchronization control block 440 can recognize that the sampling of the second sampling value is completed in the sampling count block 200, and cause the finite state machine to enter the "adjustment calculation".

[0227] In the "adjustment calculation", the synchronization control block 440 can recognize whether the internal synchronization signal falls within the target range to synchronize with the external synchronization signal. When it is recognized that the internal synchronization signal is synchronized with the external synchronization signal (target_in), the synchronization control block 440 can cause the finite state machine to enter the "completed" state, which indicates the state where the display device operates in the video mode.

[0228] When the internal synchronization signal is not synchronized with the external synchronization signal in "adjustment calculation", the synchronization control block 440 can enter "fine tuning" to perform fine tuning control, enter "HFP control" to perform HFP control, or enter "both controls" to perform both fine tuning control and HFP control based on parameters such as the parameter (BOTH_ENABLE = 1) indicating whether to perform both HFP control and fine tuning control after the parameters required for HFP control and fine tuning control are fully calculated (cal_done = 1).

[0229] In the corresponding state, the synchronization control block 440 can enter "sampling initialization" or "sampling point 1" based on the calculation parameters of the HFP adjustment amount value. According to one aspect, when the calculated HFP adjustment amount is greater than the HFP adjustment maximum value HFP_LIMIT, the synchronization control block 440 can enter "sampling point 1". In this case, for fast synchronization, sampling can be performed while shifting the internal synchronization signal. According to another aspect, when the calculated HFP adjustment amount is less than or equal to the HFP adjustment maximum value HFP_LIMIT, the synchronization control block 440 can enter "sampling initialization". In this case, for accurate sampling, the internal synchronization signal can be shifted separately from the sampling.

[0230] When switching from the command mode to the video mode, the states other than "idle" and "complete" can be repeated until synchronization is recognized in "adjustment calculation".

[0231] Although the exemplary aspects of the present disclosure have been described above, those skilled in the art will understand that various modifications and changes can be made without departing from the spirit and scope of the present disclosure as claimed in the appended claims.

[0232] Based on the foregoing method, while driving the display, seamless switching between the modes can be performed without flicker during the mode conversion between the command mode using the internal synchronization signal and the video mode driven by the external synchronization signal.

Claims

1. A method for seamless switching between a command mode and a video mode when driving a display, the method comprising: Receiving a command for switching from the command mode to the video mode; Generating a sampling value by measuring a time interval between a time point of an internal synchronization signal used in the command mode and a time point of an external synchronization signal received in the video mode; Generating a parameter for shifting the internal synchronization signal based on the sampling value; Shifting the internal synchronization signal based on the parameter to synchronize with the external synchronization signal; And When the internal synchronization signal of the command mode is synchronized with the external synchronization signal, switching from the command mode to the video mode.

2. The method according to claim 1, wherein Generating the sampling value includes: Obtaining a first sampling value that indicates the number of clocks from the time point of the internal synchronization signal to the time point of the external synchronization signal; Obtaining a second sampling value that indicates the number of clocks from the time point of the external synchronization signal to the time point of the internal synchronization signal; and Selecting a smaller value between the first sampling value and the second sampling value as the sampling value.

3. The method according to claim 2, wherein Generating a parameter for shifting the internal synchronization signal based on the sampling value includes: Generating a quotient and a remainder obtained by dividing the sampling value by the number of buses of the display panel; Setting the quotient as the horizontal front porch (HFP) adjustment amount; and Generating a fine tuning (FT) adjustment amount by multiplying the remainder by an adjustment parameter and dividing the product of the multiplication by the number of buses.

4. The method according to claim 3, wherein Shifting the internal synchronization signal based on the parameter to synchronize with the external synchronization signal includes: Identifying whether the internal synchronization signal and the external synchronization signal are synchronized; and When it is identified that the internal synchronization signal and the external synchronization signal are not synchronized, performing at least one of an HFP control operation and a fine tuning control operation. In the HFP control operation, the internal synchronization signal is shifted by modifying the HFP size for all horizontal portions in a frame based on the HFP adjustment amount, where the HFP represents the waiting time after the valid data of the output horizontal portion, and in the fine tuning control operation, the internal synchronization signal is shifted by adjusting the horizontal portion endpoint value for the horizontal portion where an overflow occurs, the overflow occurs when a cumulative value obtained by accumulating the FT adjustment amount in each horizontal portion is greater than the adjustment parameter, and the horizontal portion endpoint value is referred to as the H endpoint value.

5. The method according to claim 4, wherein Performing the fine tuning control operation when the remainder is not zero, and Wherein, when the HFP adjustment amount is not zero, performing the HFP control operation.

6. The method according to claim 4, wherein The HFP control operation includes: When the HFP adjustment amount is greater than the maximum HFP adjustment value, modifying the HFP adjustment amount to a preset maximum HFP adjustment value; When the HFP adjustment amount is greater than 1 and less than or equal to the maximum HFP adjustment value, reducing the HFP adjustment amount by 1; and Setting the HFP size to a value obtained by adding the HFP adjustment amount to the original HFP value or subtracting the HFP adjustment amount from the original HFP value.

7. The method according to claim 6, wherein Setting the HFP size to a value obtained by adding the HFP adjustment amount to the original HFP value or subtracting the HFP adjustment amount from the original HFP value includes: When the first sampled value is selected as the sampled value, setting the HFP size to a value obtained by adding the HFP adjustment amount to the original HFP value; and When the second sampled value is selected as the sampled value, setting the HFP size to a value obtained by subtracting the HFP adjustment amount from the original HFP value.

8. The method according to claim 4, wherein The fine tuning control operation includes: When the first sampled value is selected as the sampled value, increasing the horizontal part endpoint value by 1; and When the second sampled value is selected as the sampled value, decreasing the horizontal part endpoint value by 1.

9. The method according to claim 1, further comprising: Receiving a command for switching from the video mode to the command mode; And Switching from the video mode to the command mode at a time point when the transmission of the current video frame is completed, rather than immediately switching to the command mode as soon as the command for switching is generated.

10. An apparatus for seamless switching between a command mode and a video mode, the apparatus comprising: A display serial interface DSI block configured to receive video data and a control signal including an external synchronization signal; A buffer block configured to delay the video data and the control signal received through the DSI block; A command mode timing controller configured to generate an internal synchronization signal and load data from a frame memory based on the internal synchronization signal; A sampling count block configured to generate a sampled value by measuring a time interval between a time point of the external synchronization signal and a time point of the internal synchronization signal; An arithmetic block configured to generate a parameter for shifting the internal synchronization signal based on the sampled value; A synchronization control block configured to identify whether the internal synchronization signal and the external synchronization signal are synchronized based on the parameter, control the internal synchronization signal to shift when it is identified that the internal synchronization signal and the external synchronization signal are not synchronized, and switch between the video mode and the command mode when it is identified that the internal synchronization signal and the external synchronization signal are synchronized; And A data path selection block configured to output video data and a command mode control signal received from the command mode timing controller or output video data and a video mode control signal received from the buffer block based on a mode selection signal received from the synchronization control block.

11. The apparatus according to claim 10, further comprising a clock domain crossing CDC block configured to synchronize with an internal clock domain by latching the external synchronization signal with an internal oscillator clock.

12. The apparatus according to claim 10, wherein, The sampling count block includes: A first counter block configured to measure a first sampled value, the first sampled value indicating the number of clocks from the time point of the internal synchronization signal to the time point of the external synchronization signal; A second counter block configured to measure a second sampled value, the second sampled value indicating the number of clocks from the time point of the external synchronization signal to the time point of the internal synchronization signal; A first sampled point register configured to store the first sampled value; and A second sampled point register configured to store the second sampled value, wherein the smaller value between the first sampled value and the second sampled value is selected as the sampled value.

13. The device according to claim 12, wherein, The arithmetic block is configured to: Obtain a quotient and a remainder obtained by dividing the sampled value output from the sampling count block by the number of buses of the display panel; Set the quotient as the horizontal front porch (HFP) adjustment amount; Generate a fine tuning (FT) adjustment amount by multiplying the remainder by an adjustment parameter and dividing the product of the multiplication by the number of buses; And Output the HFP adjustment amount, the remainder, and the FT adjustment amount as parameters.

14. The apparatus according to claim 13, wherein, The synchronization control block includes: An HFP control block configured to control the internal synchronization signal to shift by modifying the HFP size for all horizontal portions in a frame based on the HFP adjustment amount, and output the waiting time after the valid data of the horizontal portion; A fine tuning control block configured to control the internal synchronization signal to shift by adjusting the horizontal portion end point value for the horizontal portion where an overflow occurs, the overflow occurring when the cumulative value obtained by accumulating the FT adjustment amount in each horizontal portion is greater than the adjustment parameter, and the horizontal portion end point value is referred to as the H end point value, and A synchronization control block configured to identify whether the internal synchronization signal and the external synchronization signal are synchronized, switch between the command mode and the video mode when it is identified that the internal synchronization signal and the external synchronization signal are synchronized, and control the HFP control block and the fine tuning control block to operate when the internal synchronization signal and the external synchronization signal are not synchronized.

15. The apparatus according to claim 14, wherein, The HFP control block is configured to: When the HFP adjustment amount is greater than the maximum HFP adjustment value, modify the HFP adjustment amount to a preset maximum HFP adjustment value; When the HFP adjustment amount is greater than 1 and less than or equal to the maximum HFP adjustment value, reduce the HFP adjustment amount by 1; Set the HFP size by adding the HFP adjustment amount to the original HFP value or subtracting the HFP adjustment amount from the original HFP value; And Transmit the set HFP size to the command mode timing controller, and The command mode timing controller is configured to generate the internal synchronization signal based on the HFP size.

16. The device according to claim 15, wherein, The HFP control block is configured to: When the first sampled value is less than the second sampled value, set the HFP size by adding the HFP adjustment amount to the original HFP value to control the time point of generating the internal synchronization signal to be delayed; and When the second sampled value is less than the first sampled value, set the HFP size by subtracting the HFP adjustment amount from the original HFP value to control the time point of generating the internal synchronization signal to be advanced.

17. The apparatus according to claim 14, wherein, The fine-tuning control block is configured to: When the first sampled value is less than the second sampled value, for the horizontal portion where the overflow occurs, increase the endpoint value of the horizontal portion by 1; When the second sampled value is less than the first sampled value, for the horizontal portion where the overflow occurs, decrease the endpoint value of the horizontal portion by 1; And Transmit the endpoint value of the horizontal portion to the command-mode timing controller, Wherein, the command-mode timing controller is configured to set the length of the corresponding horizontal portion based on the endpoint value of the horizontal portion.

18. The device according to claim 14, wherein, The synchronization control block is configured to: When the remainder is zero, control the fine-tuning control block not to operate; and When the HFP adjustment amount is zero, control the HFP control block not to operate.

19. The device according to claim 14, wherein, The synchronization control block is configured to, when receiving a command for switching from the video mode to the command mode, switch from the video mode to the command mode after receiving a signal indicating the completion of the transmission of the current video frame, rather than immediately switching to the command mode upon receiving the switching command.

20. A display device, comprising: A display panel configured to output video; A display serial interface DSI block configured to receive video data and control signals including an external synchronization signal; a buffer block configured to delay the video data and the control signals received through the DSI block; A command-mode timing controller configured to generate an internal synchronization signal and load data from a frame memory based on the internal synchronization signal; A sampling count block configured to generate a sampled value by measuring the time interval between the time points of the external synchronization signal and the internal synchronization signal; An arithmetic block configured to generate a parameter for shifting the internal synchronization signal based on the sampled value; A synchronization control block configured to identify whether the internal synchronization signal and the external synchronization signal are synchronized based on the parameter, control the internal synchronization signal to shift when it is identified that the internal synchronization signal and the external synchronization signal are not synchronized, and switch between the video mode and the command mode when it is identified that the internal synchronization signal and the external synchronization signal are synchronized; A data path selection block configured to output the video data and command-mode control signals received from the command-mode timing controller or output the video data and video-mode control signals received from the buffer block based on a mode selection signal received from the synchronization control block; A timing controller configured to obtain the video data and the control signals from the frame memory and an external device, and generate input data, a source control signal, and a gate control signal; A source driver circuit configured to generate a video signal to be displayed on the display panel based on the input data and the source control signal; And A gate driver circuit configured to sequentially output a plurality of gate signals based on the gate control signal to control the display panel.

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