Display panel and display device

Abstract

The present application discloses a display panel and a display device. By arranging at least part of the thin-film transistors in the pixel circuit on an inclined plane having an angle greater than 0° with the plane where the substrate is located, the external impact force applied to the display panel is decomposed into a radial force perpendicular to the inclined plane and a tangential force parallel to the inclined plane. The radial force is the main factor causing damage such as cracks on the display panel, thereby reducing the impact force applied in the radial direction of the inclined plane, protecting at least part of the thin-film transistors from the influence of the external impact force, and improving the strength of the display panel. In addition, since the driving transistor in the pixel circuit is relatively sensitive and is subject to the requirements of the process, the angle between the surface where the driving transistor is located and the plane where the substrate is located is set to be smaller than the angle between the surface where the at least one switching transistor is located and the plane where the substrate is located, so that the angle between the surface where the driving transistor is located and the plane where the substrate is located is smaller, or directly parallel to the plane where the substrate is located, thereby ensuring the stability of the driving transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Thinning is an important development trend of display devices at present. However, as display devices gradually become thinner, the display panel, upper protective member and lower protective member in the display device all need to be thinner, which will inevitably weaken the strength of the display panel, making the display panel prone to damage such as cracks. Once the display panel has cracks and other damage, it is easy to cause the thin film transistors of the pixel circuit in the display panel to fail, causing display abnormalities of the display panel. Summary of the Invention

[0003] To solve the above technical problems, embodiments of the present application provide a display panel and a display device to improve the strength of the display panel.

[0004] To achieve the above objectives, the present invention provides the following technical solutions:

[0005] A display panel, comprising:

[0006] substrate;

[0007] Multiple pixel circuits are located on a first side of a substrate, the pixel circuits include multiple thin film transistors, the multiple thin film transistors include a driving transistor and a multiple switching transistors, the surface where the driving transistor is located is a first surface, the angle between the first surface and the plane where the substrate is located is a first angle, the surface where at least one of the multiple switching transistors is located is a second surface, the angle between the second surface and the plane where the substrate is located is a second angle, the first angle is smaller than the second angle, the first angle is not less than 0°, and the second angle is less than 90°.

[0008] A display device comprises the above-mentioned display panel.

[0009] Compared with the existing technology, the above technical solution has the following advantages:

[0010] The display panel provided in the embodiment of the present application arranges at least part of the thin-film transistors in the pixel circuit on an inclined plane having an angle greater than 0° with the plane where the substrate is located. When the display panel is subjected to external impact force, the external impact force can be decomposed into a radial force perpendicular to the inclined plane and a tangential force parallel to the inclined plane based on the inclined plane. The radial force is the main factor causing damage such as cracks on the display panel. The external impact force is thus distributed to the tangential direction of the inclined plane, reducing the impact force on the radial direction of the inclined plane, protecting at least part of the thin-film transistors in the pixel circuit from the influence of the external impact force, and improving the strength of the display panel.

[0011] Furthermore, since the driving transistor in the pixel circuit is relatively sensitive and is subject to process requirements, the angle between the surface where the driving transistor is located and the plane where the substrate is located is set to be smaller than the angle between the surface where at least one switching transistor among the multiple switching transistors is located and the plane where the substrate is located, so that the angle between the surface where the driving transistor is located and the plane where the substrate is located is smaller, or directly parallel to the plane where the substrate is located, thereby ensuring the stability of the driving transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A schematic top view of a display panel provided in one embodiment of the present application;

[0014] Figure 2 A schematic diagram of a circuit structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0015] Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application, in which a driving transistor is located on a first surface;

[0016] Figure 4 A schematic diagram of a display panel provided in an embodiment of the present application, in which a switch transistor is located on the second surface;

[0017] Figure 5 A schematic cross-sectional view of a display panel according to an embodiment of the present application;

[0018] Figure 6 A schematic diagram showing that, in the display panel provided in an embodiment of the present application, the surface of the insulating layer facing away from the substrate includes a first surface and a second surface;

[0019] Figure 7 Another schematic diagram of a display panel provided in an embodiment of the present application, wherein the surface of the insulating layer facing away from the substrate includes a first surface and a second surface;

[0020] Figure 8 A schematic diagram of a display panel provided in an embodiment of the present application, wherein the surface of the first side of the substrate comprises the first surface, and the surface of the insulating layer facing away from the substrate comprises the second surface;

[0021] Figure 9A schematic diagram of a display panel provided in an embodiment of the present application, in which, when the first angle is 0°, a driving transistor in a pixel circuit is located on the first surface, and at least one switching transistor in the pixel circuit is located on the second surface;

[0022] Figure 10 Schematic diagram of the process steps of sequentially forming an insulating layer, a thin film transistor, and a planarization layer on the first side of the substrate, taking the first angle of 0° as an example;

[0023] Figure 11 A schematic diagram of the distribution of thin film transistors on the first surface and the second surface in a pixel circuit of the display panel provided by an embodiment of the present application;

[0024] Figure 12 A schematic diagram of another distribution of thin film transistors on the first surface and the second surface in a pixel circuit of the display panel provided by an embodiment of the present application;

[0025] Figure 13 A schematic diagram of a display panel provided by an embodiment of the present application, in which a gate reset transistor is located on the third surface;

[0026] Figure 14 A schematic diagram of a display panel provided in an embodiment of the present application, wherein a surface of the insulating layer facing away from the substrate further includes a connection plane;

[0027] Figure 15 A schematic diagram of a first electrical connection line in a pixel circuit extending from a first surface to a second surface in a display panel provided by an embodiment of the present application;

[0028] Figure 16 A schematic diagram of a second electrical connection line in a pixel circuit extending from a connection plane to a second surface in a display panel provided by an embodiment of the present application;

[0029] Figure 17-Figure 19 Schematic diagrams of the display panel provided in an embodiment of the present application, in which the angles between the transition region between the first surface and the second surface and the plane where the substrate is located are respectively a right angle, an acute angle, and an obtuse angle;

[0030] Figure 20 A schematic diagram of a display panel provided in an embodiment of the present application, wherein the transition region between the first surface and the second surface is a curved surface;

[0031] Figure 21 A schematic structural diagram of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0034] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0035] As described in the background technology section, as display devices gradually become thinner, the display panel, upper protective member and lower protective member in the display device all need to be thinned, which will inevitably weaken the strength of the display panel, making the display panel prone to damage such as cracks. Once the display panel has cracks and other damage, it is easy to cause the thin film transistors of the pixel circuit in the display panel to fail, causing abnormal display of the display panel.

[0036] In view of this, an embodiment of the present application provides a display panel, Figure 1 A schematic top view of a display panel provided in an embodiment of the present application is given. Figure 1 As shown, the display panel includes:

[0037] substrate 100;

[0038] A plurality of pixel circuits 10 are located on the first side of the substrate 100, such as Figure 2 As shown, the pixel circuit 10 includes a plurality of thin film transistors (such as Figure 2 T1-T7), multiple thin film transistors including driving transistors (such as Figure 2 T3) and multiple switching transistors (such as Figure 2 T1-T2, T4-T7), such as Figure 3 As shown, the surface where the driving transistor T3 is located is the first surface 11, and the angle between the first surface 11 and the plane where the substrate is located is the first angle θ1, as shown in FIG. Figure 4 As shown, at least one switching transistor Tx (Tx represents Figure 2The surface where any one of T1-T2, T4-T7 is located is the second surface 12, the angle between the second surface 12 and the plane where the substrate is located is the second angle θ2, the first angle θ1 is smaller than the second angle θ2, and the first angle is not less than 0°, and the second angle is less than 90°.

[0039] It should be noted that in Figure 1 In the display panel shown, a plurality of pixel circuits 10 may be arranged in an array, and the display panel further includes a power signal line PVDD, a data signal line Vdata, a first reference signal line Vref1, a second reference signal line Vref2, scan signals S(n-1), S(n), S(n+1), and a light emitting control signal line Emit, etc., to control each pixel circuit 10 to drive the display pixel ( Figure 1 (not shown) work.

[0040] Figure 2 The following is a schematic diagram of a pixel circuit structure, in which a pixel circuit 10 includes a storage capacitor Cst and seven thin film transistors T1-T7 as an example, wherein T1 is a power write transistor, T2 is a data write transistor, T3 is a drive transistor, T4 is a compensation transistor, T5 is a gate reset transistor, T6 is a light emitting control transistor, T7 is an anode initialization transistor, D is a light emitting element, PVEE is a common power signal terminal, PVDD is a power signal line, S(n-1) is a first scanning signal line, Sn is a second scanning signal line, N1 and N2 represent connection nodes, and the connection method of each thin film transistor and signal line is as follows: Figure 2 This application does not limit the specific circuit structure of the pixel circuit, that is, the pixel circuit 10 may also include Figure 2 Other circuit structures other than the driving transistor may be used depending on the specific situation. In the following, T3 represents the driving transistor, and Tx represents any switching transistor other than the driving transistor in the pixel circuit.

[0041] In the embodiment of the present application, the surface where the thin film transistor is located refers to the surface where the entire thin film transistor is located. Therefore, the surface where the driving transistor T3 is located (i.e., the first surface 11) is the surface where the driving transistor is located, and the surface where the switching transistor Tx is located (i.e., the second surface 12) is the surface where the switching transistor is located. Then, among the multiple thin film transistors in the pixel circuit, the angle between the surface where at least one switching transistor Tx is located (i.e., the second surface 12) and the plane where the substrate is located (i.e., the second angle θ2) is greater than 0°. That is, at least one switching transistor Tx is entirely located on an inclined plane having an angle greater than 0° with the surface where the substrate is located, while the angle between the surface where the driving transistor T3 is located (i.e., the first surface 11) and the plane where the substrate is located (i.e., the first angle θ1) is not less than 0°. In other words, the driving transistor can be located on a surface parallel to the plane where the substrate is located, or on an inclined plane having an angle greater than 0° with the plane where the substrate is located. That is, in the display panel provided in the embodiment of the present application, at least some of the thin film transistors in the pixel circuit 10 are located on an inclined plane having an angle greater than 0° with the plane where the substrate is located.

[0042] In order to more clearly show that the thin film transistor is located on the slope as a whole, Figure 5 A schematic cross-sectional structure diagram of a display panel provided in an embodiment of the present application is given, as shown in FIG. Figure 5 As shown, the display panel includes a substrate 100 and a driving circuit layer 200 located on the first side of the substrate 100. The pixel circuit 10 is located in the driving circuit layer 200. The driving circuit layer 200 includes an insulating layer 110, a semiconductor layer b, a gate insulating layer GI, a gate metal layer M1, a capacitor insulating layer IMD, a capacitor metal layer MC, an interlayer dielectric layer ILD and a source-drain metal layer M2 stacked in a direction away from the substrate 100. Among them, the semiconductor layer b is the semiconductor layer where the active layer of the thin film transistors T3 and Tx in the pixel circuit 10 is located, the gate metal layer M1 is the metal conductive layer where the gates of the thin film transistors T3 and Tx in the pixel circuit 10 are located, the source-drain metal layer M2 is the metal conductive layer where the source and drain of the thin film transistors T3 and Tx in the pixel circuit 10 are located, and the gate metal layer M1 and the capacitor metal layer MC are the metal conductive layers where the two plates of the capacitor Cst in the pixel circuit 10 are located. Figure 5 It can be clearly seen that in the embodiment of the present application, the surface where the thin film transistor is located is the surface where the entire thin film transistor is located. When at least part of the thin film transistors in the pixel circuit 10 are located on an inclined plane having an angle greater than 0° with the plane where the substrate 100 is located, the source and drain metal layer M2 and the film layers thereunder of at least part of the thin film transistor are all located on an inclined plane having an angle greater than 0° with the plane where the substrate 100 is located.

[0043] exist Figure 5It can also be seen that the thin film transistors T3 and Tx in the pixel circuit 10 are connected to the anode RE of the display pixel 20 (including the anode RE, the organic light-emitting layer OM and the cathode SE) to drive the display pixel 20 to operate, and a planarization layer PLN is provided on the side of the thin film transistors T3 and Tx in the driving circuit layer 200 facing away from the substrate 100, so that the surface of the driving circuit layer 200 facing away from the substrate 100 is parallel to the plane where the substrate is located, so that other film layers such as the display pixel 20 are provided on the surface of the driving circuit layer 200 facing away from the substrate 100.

[0044] Combine Figure 3-Figure 5 It can be seen that the first surface 11 having a first angle with the plane where the substrate is located, and the second surface 12 having a second angle with the plane where the substrate is located can be achieved by forming an insulating layer 110 on the first side of the substrate 100, so that the insulating layer 110 has multiple slopes or flat layers, but the present application is not limited to this. In other embodiments of the present application, the first surface and the second surface can also be formed by the substrate itself or by other film layers that can form a slope or a plane on the first side of the substrate, depending on the specific circumstances.

[0045] Figure 3 and Figure 4 It also gives a schematic diagram of the force on the thin film transistors on the inclined surface when the display panel is subjected to external impact. Figure 3 and Figure 4 It can be seen that by arranging at least part of the thin film transistors in the pixel circuit on an inclined plane with an angle greater than 0° with the plane where the substrate is located, when the display panel is subjected to an external impact force F, the external impact force F can be decomposed into a radial force F1 perpendicular to the inclined plane and a tangential force F2 parallel to the inclined plane with the inclined plane as a reference. The radial force F1 is the main factor causing damage such as cracks on the display panel. Therefore, the external impact force F is distributed to the tangential direction of the inclined plane, reducing the impact force F1 in the radial direction of the inclined plane, protecting at least part of the thin film transistors in the pixel circuit from the influence of the external impact force, and improving the strength of the display panel.

[0046] It can be seen from this that in order to better protect the thin film transistors in the pixel circuit when the display panel is subjected to external impact, the angle between the surface where the thin film transistors are located and the plane where the substrate is located can be increased.

[0047] However, the inventors have discovered that the driving transistor T3 in the pixel circuit 10 is relatively sensitive, especially when a laser annealing process is required to prepare the driving transistor T3. If the angle between the surface where the driving transistor T3 is located (i.e., the first surface 11) and the surface where the substrate is located (i.e., the first angle θ1) is too large, the energy density of the laser irradiation on the inclined surface will be different during the laser annealing process, resulting in uneven heating of the driving transistor, affecting the crystallization state of the film layer in the driving transistor, and causing poor performance of the driving transistor.

[0048] Based on this, in the display panel provided in the embodiment of the present application, a first angle θ1 between the surface where the driving transistor T3 in the pixel circuit 10 is located (i.e., the first surface 11) and the plane where the substrate is located is set to be smaller than a second angle θ2 between the surface where at least one switching transistor Tx among the multiple switching transistors is located (i.e., the second surface 12) and the plane where the substrate is located, so that the angle between the surface where the driving transistor is located and the plane where the substrate is located is smaller, or directly parallel to the plane where the substrate is located, thereby ensuring the stability of the driving transistor.

[0049] In summary, the display panel provided in the embodiment of the present application arranges at least part of the thin film transistors in the pixel circuit on an inclined plane having an angle greater than 0° with the plane where the substrate is located, and utilizes the inclined plane to alleviate the external impact force on the display panel, thereby reducing the impact of the external impact force on at least part of the thin film transistors in the pixel circuit when the display panel is subjected to the external impact force, thereby improving the strength of the display panel. At the same time, the angle between the surface where the driving transistor is located and the plane where the substrate is located is set to be smaller than the angle between the surface where at least one switching transistor among the multiple switching transistors is located and the plane where the substrate is located, so that the angle between the surface where the driving transistor is located and the plane where the substrate is located is smaller, or directly parallel to the plane where the substrate is located, thereby ensuring the stability of the driving transistor.

[0050] Optionally, in one embodiment of the present application, at least one switching transistor Tx of one pixel circuit 10 is disposed on one second surface 12 , that is, in this embodiment, one second surface 12 corresponds to one pixel circuit 10 .

[0051] In another embodiment of the present application, at least one switching transistor Tx of a plurality of pixel circuits 10 is disposed on one second surface 12 , that is, in this embodiment, one second surface 12 corresponds to a plurality of pixel circuits.

[0052] Optionally, in one embodiment of the present application, Figure 6-Figure 7 As shown, the display panel also includes:

[0053] The insulating layer 110 is located on the first side of the substrate 100 , and the surface of the insulating layer 110 facing away from the substrate 100 includes a first surface 11 and a second surface 12 .

[0054] In this embodiment, reference Figure 6-Figure 7 As shown, in order to form a first surface 11 having an angle of not less than 0° with the plane where the substrate is located and a second surface 12 having an angle greater than 0° with the plane where the substrate is located on the first side of the substrate 100, an insulating layer 110 is formed on the first side of the substrate 100, so that the surface of the insulating layer 110 facing away from the substrate 100 includes both the first surface 11 and the second surface 12.

[0055] Specifically, refer to Figure 6 As shown, when the angles between the first surface 11 and the second surface 12 and the plane of the substrate are greater than 0°, the insulating layer 110 may include multiple first slopes 111 and multiple second slopes 112, so that the surface of the first slope 111 facing away from the substrate 100 is used as the first surface 11, and the surface of the second slope 112 facing away from the substrate 100 is used as the second surface 12.

[0056] refer to Figure 7 As shown, when the first surface 11 is parallel to the plane of the substrate, that is, the first angle θ1 is equal to 0°, the insulating layer 110 may include a flat layer 113 parallel to the plane of the substrate and a plurality of second slopes 112, so that the surface of the flat layer 113 facing away from the substrate 100 is used as the first surface 11, and the surface of the second slopes 112 facing away from the substrate 100 is used as the second surface 12.

[0057] Optionally, in another embodiment of the present application, as Figure 8 As shown, the surface of the first side of the substrate 100 includes a first surface 11;

[0058] The display panel also includes:

[0059] The insulating layer 110 is located on the first side of the substrate 100 , and the surface of the insulating layer 110 facing away from the substrate 100 includes a second surface 12 .

[0060] In this embodiment, reference Figure 8 As shown, when the first surface 11 is parallel to the plane where the substrate 100 is located, that is, the first angle θ1 is equal to 0°, the area of ​​the surface of the first side of the substrate 100 that is parallel to the plane where the substrate is located can be used as the first surface 11. At the same time, in order to form a second surface 12 having an angle greater than 0° with the plane where the substrate 100 is located on the first side of the substrate 100, an insulating layer 110 is formed on the first side of the substrate 100. The insulating layer 110 may include a plurality of second slopes 112 so that the second slopes 112 are facing away from the surface of the substrate 100 as the second surface 12.

[0061] It can be understood that when the first angle θ1 between the first surface 11 and the plane where the substrate 100 is located is greater than 0°, the area on the surface of the first side of the substrate 100 that has an angle θ1 with the plane where the substrate is located (i.e., the inclined plane area) can be used as the first surface 11. At this time, the first surface 11 can be realized by forming a certain slope through the substrate 100, depending on the specific situation.

[0062] Based on any of the above embodiments, optionally, in one embodiment of the present application, Figure 7-Figure 9As shown, the first angle is equal to 0°, that is, the first surface 11 is parallel to the plane where the substrate 100 is located. At this time, the driving transistor T3 in the pixel circuit 10 is located on the first surface 11 parallel to the plane where the substrate 100 is located, so as to further ensure the stability of the driving transistor. At least one switching transistor Tx in the pixel circuit 10 is located on the second surface 12 to reduce the external impact force on the at least one switching transistor Tx.

[0063] The following takes the case where the first angle is equal to 0° as an example to describe how to form the second surface 12 by forming the insulating layer 110 on the first side of the substrate 100 in an actual process.

[0064] Specifically, such as Figure 10 As shown, first, a substrate 100 is provided; then, a film is formed on the entire first side of the substrate 100 to form an insulating layer 110; secondly, a photoresist PR is set on the side of the insulating layer 110 away from the substrate 100, and the photoresist PR has an inclined surface, so that when the photoresist PR is etched (such as HT process), the etching rate of the area with thinner photoresist PR is fast, and the etching rate of the area with thicker photoresist PR is slow, thereby forming an insulating layer 110 with an inclined surface; subsequently, a switching transistor Tx is set on the insulating layer 110 with the inclined surface, and a driving transistor T3 is formed on the flat insulating layer 110 or on the surface of the first side of the substrate 100, and a planarization layer PLN and a film layer thereon are set.

[0065] Optionally, in one embodiment of the present application, the insulating layer 110 is an inorganic layer, and the thickness of the insulating layer 110 in a direction perpendicular to the plane of the substrate is not greater than 2 μm, depending on the specific situation.

[0066] Since multiple thin-film transistors in a pixel circuit need to be arranged close to each other, and the above embodiments only limit the driving transistor to be located on the first surface and at least one switching transistor to be located on the second surface, then there are many situations for the distribution of multiple thin-film transistors in a pixel circuit, which are specifically described in the following embodiments.

[0067] Optionally, in one embodiment of the present application, Figure 9 and Figure 11 As shown, the first surface 11 includes a first side L1 and a second side L2 arranged opposite to each other in a first direction, the first side L1 of the first surface 11 is connected to one second surface 12, the second side L2 of the first surface 11 is connected to another second surface 12, and the first direction is parallel to the first surface 11.

[0068] In this embodiment, the first surface 11 includes a first side L1 and a second side L2 arranged opposite to each other in the first direction. The first side L1 of the first surface 11 is connected to one second surface 12, and the second side L2 of the first surface 11 is connected to another second surface 12. Then, the first surface 11 is located in the recess of two adjacent second surfaces 12. At this time, for multiple thin film transistors in a pixel circuit 10, the driving transistor T3 is located on the first surface 11, and in a direction perpendicular to the first direction, the switching transistor (for example, Figure 11 The switching transistor M5 in FIG1 is also located on the first surface 11. In the first direction, the switching transistors on both sides of the driving transistor T3 are located on the second surface.

[0069] It is understandable that the present application does not limit the first direction, as long as the first direction is parallel to the first surface, that is, the first direction can be Figure 11 The horizontal direction in Figure 11 The vertical direction in can also be Figure 11 If the oblique angle direction is different in the first direction, then the switch transistor located on the first surface and the driving transistor in a pixel circuit are different, and the switch transistor located on the second surface is also different accordingly.

[0070] Optionally, in another embodiment of the present application, combined with Figure 9 and Figure 12 As shown, the first surface 11 includes a plurality of side edges, and each side edge of the first surface 11 is connected to a second surface 12 .

[0071] Specifically, in one embodiment of the present application, the first surface 11 includes four side edges, and each side edge of the first surface 11 is connected to a second surface 12 .

[0072] In this embodiment, the first surface 11 includes a plurality of side edges, and each side edge of the first surface 11 is connected to a second surface 12, that is, the first surface 11 is surrounded by the second surface 12, and the first surface 11 is located in the recess of the second surface 12. In this case, for the plurality of thin film transistors in a pixel circuit 10, the driving transistor T3 is located on the first surface 11, and the switching transistors (such as Figure 12 The switching transistors M1 - M2 , M4 - M7 in the embodiment are all located on the second surface 12 .

[0073] It is understood that the present application does not limit the number of sides of the first surface, such as Figure 12 In the embodiment, the first surface 11 may have four sides. Of course, the first surface 11 may also have three sides, five sides, etc., depending on the specific situation.

[0074] It should be noted that in Figure 11 and Figure 12 In the embodiment, the first surface 11 may be a surface parallel to the plane where the substrate is located. Of course, the first surface 11 may also be a surface having a first angle θ1 with the plane where the substrate is located, depending on the specific situation.

[0075] It should also be noted that in Figure 11 and Figure 12 In the layout structure of the pixel circuit shown in the figure, M1-M2, M4-M7 are six switch transistors, which can be connected to Figure 2 The pixel circuits shown in FIG1 have one-to-one correspondence between T1 and T2, and T4 and T7, or may not have one-to-one correspondence. Figure 11 Can be with Figure 2 The layout structure of other pixel circuits is different from the pixel circuit shown.

[0076] It should be noted that Figure 11 and Figure 12 The layout structure of the pixel circuit shown is based on Figure 5 The gate metal layer M1 is used to make the scanning signal lines S(n-1) and Sn, the capacitor metal layer MC is used to make the reference signal line Vref, and the source and drain metal layer M2 is used to make the power signal line PVDD and the data signal line Vdata. This is for illustrative purposes only and does not limit the present application.

[0077] Based on any of the above embodiments, optionally, in one embodiment of the present application, the plurality of switch transistors are all located on the second surface 12 .

[0078] For example, Figure 12 As shown, the first surface 11 includes a plurality of side edges, and each side edge of the first surface 11 is connected to a second surface 12 , so that a plurality of switching transistors are respectively arranged on each second surface 12 connected to each side edge of the first surface 11 .

[0079] It should be noted that this embodiment is not limited to Figure 11 In the case shown, for example, the second surface 12 located on the first side of the substrate 100 can be arranged periodically, that is, the insulating layer 110 located on the first side of the substrate 100 can be designed to be periodically tilted, so that multiple switching transistors in the pixel circuit are all arranged on the second surface 12.

[0080] It should also be noted that, in this embodiment, since the plurality of switch transistors in the pixel circuit are all located on the second surface 12 , the surfaces where the switch transistors are located have the same inclination angle relative to the plane where the substrate is located.

[0081] As is known from the above, in order to better protect the thin film transistors in the pixel circuit from damage when the display panel is subjected to external impact, the angle between the surface where the thin film transistors are located and the plane where the substrate is located can be increased. Figure 2 It can be seen that the multiple switching transistors in the pixel circuit 10 include a gate reset transistor T5. Specifically, the first scanning signal line S(n-1) controls the on / off state of the gate reset transistor T5 in the pixel circuit 10 and resets the gate potential of the driving transistor T3 when the gate reset transistor T5 is turned on. Considering that the gate reset transistor T5 is a dual-gate transistor, which is more sensitive than other switching transistors (mostly single-gate transistors), the angle between the surface on which the gate reset transistor T5 is located and the plane on which the substrate is located can be set to be larger, so that the surface on which the gate reset transistor T5 is located is more inclined relative to the plane on which the substrate is located, thereby reducing stress damage to the gate reset transistor T5 and improving protection.

[0082] Specifically, in one embodiment of the present application, Figure 2 As shown, the plurality of switching transistors include a gate reset transistor T5, as shown in FIG. Figure 13 As shown, the surface where the gate reset transistor T5 is located is the third surface 13, and the angle between the third surface 13 and the plane where the substrate is located is a third angle θ3, as shown in FIG. Figure 4 As shown, at least one switching transistor Tx other than the gate reset transistor T5 among the multiple switching transistors is located on the second surface 12, the third angle θ3 is greater than the second angle θ2, and the third angle is less than 90°, that is, in this embodiment, the gate reset transistor T5 is arranged on a slope that is more inclined than the slope where the other at least one switching transistor Tx is located, so that the gate reset transistor T5 is less subject to stress damage and is better protected.

[0083] It should be noted that, in this embodiment, the two transistors serving as the gate reset transistors T5 need to be located on the same slope.

[0084] It should also be noted that Figure 2Only one 7T1C pixel circuit structure is listed. It is conceivable that in order to improve the performance of the display panel, the circuit structure of the pixel circuit is diverse. Therefore, among the multiple switching transistors, except for the gate reset transistor which is a dual-gate transistor, the other switching transistors may also be dual-gate transistors. The dual-gate transistor may be a low-temperature polysilicon thin film transistor (LTPS TFT) or an indium gallium zinc oxide thin film transistor (IGZO TFT). Therefore, for the other switching transistors that are dual-gate transistors, since the dual-gate transistor is more sensitive, the other switching transistors that are dual-gate transistors may also be located on the third surface 13 to better protect the dual-gate transistor by using the inclined surface with a larger inclination angle.

[0085] As can be seen from the foregoing, on the first side of the substrate 100, the insulating layer 110 can be formed so that the surface of the insulating layer 110 facing away from the substrate 100 includes at least the second surface 12. The first surface 11 can be the surface of the first side of the substrate 100, or it can be a portion of the surface of the insulating layer 110 facing away from the substrate 100. On this basis, optionally, in one embodiment of the present application, as Figure 14 As shown, the surface of the insulating layer 110 facing away from the substrate further includes a connection plane 14, and the connection plane 14 is parallel to the plane where the substrate is located;

[0086] The second surface 12 includes a third side L3 and a fourth side L4 disposed opposite to each other in the second direction. The third side L3 of the second surface 12 is connected to the first surface 11, and the fourth side L4 of the second surface 12 is connected to the connecting plane 14. The second direction is parallel to the second surface 12.

[0087] The connection plane 14 is not provided with a driving transistor T3 or any switching transistor Tx.

[0088] In this embodiment, the insulating layer 110 includes a second slope 112, the surface of the second slope 112 facing away from the substrate 100 is the second surface 12, the end of the second slope 112 close to the substrate 100 is the third side L3 of the second surface 12, the end of the second slope 112 away from the substrate 100 is the fourth side L4 of the second surface 12, and the third side L3 of the second surface 12 is connected to the first surface 11, that is, the end of the second slope 112 close to the substrate 100 is connected to the first surface 11, and the first surface 11 can be the surface of the first side of the substrate 100 (such as Figure 6-Figure 7 As shown), the first slope 111 in the insulating layer 110 may be away from the surface of the substrate 100 (as shown Figure 8As shown in FIG, the fourth side L4 of the second surface 12 is connected to the connection plane 14, that is, the end of the second slope 112 facing away from the substrate 100 is connected to the connection plane 14, that is, the end of the second slope 112 away from the substrate 100 has a connection plane 14 parallel to the plane where the substrate is located, and the connection plane 14 may be connected to another second surface 12 or not, depending on the specific situation.

[0089] In this embodiment, since the connection plane 14 is parallel to the plane of the substrate and is located closer to the display surface in the display panel, if the thin film transistor in the pixel circuit is set on the connection plane 14, when the display panel is subjected to external impact, the thin film transistor will suffer greater stress damage. Therefore, the driving transistor T3 or any switching transistor Tx is not set on the connection plane 14, but wiring can be set on the connection plane 14.

[0090] Optionally, in one embodiment of the present application, Figure 15 As shown, the pixel circuit 10 further includes at least one first electrical connection line X. The first electrical connection line X includes a first portion X1 and a second portion X2. The first portion X1 is located on the first surface 11, and the second portion X2 spans the first and second surfaces 11 and 12. The line width w2 of the second portion X2 is smaller than the line width w1 of the first portion X1. This is because the second angle θ2 between the second surface 12 and the plane of the substrate is greater than the first angle θ1 between the first surface 11 and the plane of the substrate, i.e., the second surface 12 is more inclined relative to the first surface 11. Therefore, when the first electrical connection line X passes from the first surface 11 to the second surface 12, it is equivalent to extending from a lower surface to a higher surface. In actual manufacturing processes, this situation is prone to the risk of under-etching, i.e., etching residue. Therefore, the line width w2 of the second portion X2 of the first electrical connection line X spanning the first and second surfaces 11 and 12 is set to be smaller than the line width w1 of the first portion X1 of the first electrical connection line X located on the first surface 11, thereby reducing the risk of etching residue.

[0091] Optionally, in another embodiment of the present application, as Figure 16As shown, the pixel circuit 10 further includes at least one second electrical connection line Y. The second electrical connection line Y includes a third portion Y1 and a fourth portion Y2. The third portion Y1 is located on the connection plane 14, and the fourth portion Y2 spans the connection plane 14 and the second surface 12. The line width w4 of the fourth portion Y2 is greater than the line width w3 of the third portion Y1. This is because the connection plane 14 is connected to the side of the second surface 12 away from the substrate 100, and the connection plane 14 is parallel to the plane of the substrate. Therefore, when the second electrical connection line Y enters the second surface 12 from the connection plane 14, it is equivalent to extending from a higher surface to a lower surface. In this case, in the actual manufacturing process, there is a risk of over-etching. Therefore, the line width w4 of the fourth portion Y2 of the second electrical connection line Y spanning the connection plane 14 and the second surface 12 is set to be greater than the line width w3 of the third portion Y1 of the second electrical connection line Y located on the second surface 12, thereby reducing the risk of over-etching.

[0092] The connection method of the first surface 11 and the second surface 12 on the first side of the substrate 100 is described below. Specifically, Figure 14 As shown, the first surface 11 and the second surface 12 can be directly connected, that is, connected at a natural angle;

[0093] or as Figure 17-19 As shown, there is a transition area 15 between the first surface 11 and the second surface 12. Figure 15-17 As shown in the solid circle, the transition region 15 may form a fourth angle θ4 with the plane where the substrate is located, and the fourth angle θ4 is greater than 0° and less than 180°. Figure 17 As shown, the transition region 15 is perpendicular to the plane where the substrate is located, that is, the fourth angle θ4 is 90°; Figure 18 As shown, the transition region 15 forms an acute angle transition with the plane where the substrate is located, that is, the fourth angle θ4 is an acute angle; Figure 19 As shown, the transition region 15 forms an obtuse angle transition with the plane where the substrate is located, that is, the fourth angle θ4 is an obtuse angle.

[0094] or as Figure 20 As shown, there is a transition area 15 between the first surface 11 and the second surface 12, and the transition area 15 is an arc-shaped surface.

[0095] It should be noted that when the first surface 11 and the second surface 12 are connected via the arc-shaped transition region 15 , the wiring can smoothly transition between the first surface 11 and the second surface 12 .

[0096] It should also be noted that the specific connection method between the first surface 11 and the second surface 12 on the first side of the substrate 100 is related to the etching process of the insulating layer located on the first side of the substrate.

[0097] Optionally, in one embodiment of the present application, Figure 5 As shown, the display panel further includes: a plurality of display pixels 20 located on a side of the plurality of pixel circuits 10 away from the substrate 100, the display pixels 20 corresponding one-to-one to the pixel circuits 10, the plurality of display pixels 20 including display pixels of multiple colors, and the angles between the second surface where at least one switching transistor in the pixel circuit corresponding to display pixels of different colors and the plane where the substrate is located are different. However, the present application is not limited to this. In other embodiments of the present application, the angles between the second surface where at least one switching transistor in the pixel circuit corresponding to display pixels of different colors and the plane where the substrate is located may also be the same. Alternatively, the angles between the second surface where at least one switching transistor in the pixel circuit corresponding to display pixels of different colors and the plane where the substrate is located may be different, while the angles between the second surface where at least one switching transistor in the pixel circuit corresponding to display pixels of different colors and the plane where the substrate is located may be the same, depending on the specific circumstances.

[0098] The present application also provides a display device, such as Figure 21 As shown, the display device 300 includes the display panel 400 provided by any of the above embodiments. Since the display panel 400 has been described in detail in the above embodiments, it will not be repeated here.

[0099] The display device 300 can be any electronic device with a display function, such as a touch screen display, a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television.

[0100] In summary, the display panel provided by the embodiment of the present application, by arranging at least part of the thin film transistors in the pixel circuit on an inclined plane having an angle greater than 0° with the plane where the substrate is located, the external impact force applied to the display panel is decomposed into a radial force perpendicular to the inclined plane and a tangential force parallel to the inclined plane. The radial force is the main factor causing damage such as cracks on the display panel, thereby reducing the impact force applied in the radial direction of the inclined plane, protecting at least part of the thin film transistors from the influence of external impact force, and improving the strength of the display panel. In addition, since the driving transistor in the pixel circuit is more sensitive and is subject to the requirements of the process, the angle between the surface where the driving transistor is located and the plane where the substrate is located is set to be smaller than the angle between the surface where the at least one switching transistor is located and the plane where the substrate is located, so that the angle between the surface where the driving transistor is located and the plane where the substrate is located is smaller, or directly parallel to the plane where the substrate is located, thereby ensuring the stability of the driving transistor.

[0101] The various parts in this manual are described in a combination of parallel and progressive manners. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0102] With respect to the above description of the disclosed embodiments, the features described in the various embodiments in this specification may be interchanged or combined with one another to enable those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: substrate; a plurality of pixel circuits located on a first side of the substrate, the pixel circuits comprising a plurality of thin film transistors, the plurality of thin film transistors comprising a driving transistor and a plurality of switching transistors, the driving transistor being located on a first surface, the first surface having a first angle between the first surface and the plane of the substrate, at least one of the plurality of switching transistors being located on a second surface, the second surface having a second angle between the second surface and the plane of the substrate, the first angle being smaller than the second angle, the first angle being no smaller than 0°, and the second angle being smaller than 90°; The multiple switching transistors include a gate reset transistor, the surface where the gate reset transistor is located is a third surface, the angle between the third surface and the plane where the substrate is located is a third angle, and at least one switching transistor other than the gate reset transistor among the multiple switching transistors is located on the second surface, the third angle is greater than the second angle, and the third angle is less than 90°.

2. The display panel according to claim 1, wherein: At least one switching transistor of the pixel circuit is disposed on one of the second surfaces.

3. The display panel according to claim 1, wherein: At least one switching transistor of a plurality of the pixel circuits is disposed on one of the second surfaces.

4. The display panel according to claim 1, wherein: Also includes: An insulating layer is located on the first side of the substrate, and a surface of the insulating layer facing away from the substrate includes the first surface and the second surface.

5. The display panel according to claim 1, wherein: The surface of the first side of the substrate includes the first surface; The display panel further includes: An insulating layer is located on the first side of the substrate, and a surface of the insulating layer facing away from the substrate includes the second surface.

6. The display panel according to claim 1, 4 or 5, characterized in that: The first angle is equal to 0°.

7. The display panel according to claim 1, wherein: The first surface includes a first side and a second side oppositely arranged in a first direction, the first side of the first surface is connected to one of the second surfaces, the second side of the first surface is connected to another of the second surfaces, and the first direction is parallel to the first surface.

8. The display panel according to claim 1, wherein: The first surface includes a plurality of side edges, and each side edge of the first surface is connected to one of the second surfaces.

9. The display panel according to claim 1, wherein: The plurality of switch transistors are all located on the second surface.

10. The display panel according to claim 4 or 5, characterized in that: The surface of the insulating layer facing away from the substrate further includes a connection plane, and the connection plane is parallel to the plane where the substrate is located; The second surface includes a third side and a fourth side arranged opposite to each other in a second direction, the third side of the second surface is connected to the first surface, the fourth side of the second surface is connected to the connecting plane, and the second direction is parallel to the second surface; The driving transistor or any of the switching transistors is not arranged on the connection plane.

11. The display panel according to claim 10, wherein: The pixel circuit also includes at least one first electrical connection line, which includes a first part and a second part. The first part is located on the first surface, the second part spans the first surface and the second surface, and the line width of the second part is smaller than the line width of the first part.

12. The display panel according to claim 10, wherein: The pixel circuit also includes at least one second electrical connection line, the second electrical connection line includes a third part and a fourth part, the third part is located on the connection plane, the fourth part spans the connection plane and the second surface, and the line width of the fourth part is greater than the line width of the third part.

13. The display panel according to claim 4 or 5, characterized in that: The first surface is directly connected to the second surface; or, There is a transition area between the first surface and the second surface, and a fourth angle is formed between the transition area and the plane where the substrate is located. The fourth angle is greater than 0° and less than 180°, or the transition area is an arc surface.

14. The display panel according to claim 1, wherein The display panel also includes: a plurality of display pixels located on a side of the plurality of pixel circuits away from the substrate, the display pixels corresponding one-to-one to the pixel circuits, the plurality of display pixels including display pixels of multiple colors, and the angles between the second surface where at least one switching transistor in the pixel circuits corresponding to display pixels of different colors is located and the plane where the substrate is located are different.

15. The display panel according to claim 4 or 5, characterized in that: The insulating layer is an inorganic layer, and the thickness of the insulating layer in a direction perpendicular to the plane where the substrate is located is not greater than 2 μm.

16. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 15.

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