Display panel and manufacturing method thereof, and display device

Abstract

The embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device, which belong to the field of display technology. The display panel includes an interlayer dielectric layer located on one side of a substrate, a cutting path, and a first flat layer. The cutting path includes a plurality of vias penetrating the interlayer dielectric layer, and the first flat layer is located on the side of the interlayer dielectric layer away from the substrate. Because the side of the first flat layer close to the display area is inclined in a direction away from the substrate, and there is a gap between the side of the cutting path away from the display area, the size of the gap can be flexibly set so that when the anode layer is formed by a patterning process, the exposure light is reflected in different directions on the inclined side of the first flat layer and the side of the interlayer dielectric layer away from the substrate, so that the exposure amount at the via hole is better, avoiding the residual anode layer at the via hole. That is, the anode layer formed on the second insulating side away from the substrate is only located in the display area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Currently, in the manufacturing process of display panels, a display motherboard including a plurality of display panels is usually formed first, and then the display motherboard is cut to obtain individual display panels.

[0003] Each display panel in a display motherboard typically includes a substrate, multiple layers of insulation, planarization, and anode layers stacked sequentially away from the substrate, and a dicing path along one side of the substrate for cutting. In related art, residual anode layer residue within the dicing path affects the yield of the display panel. Summary of the Invention

[0004] The embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device, which can solve the problem of residual anode layer at the cutting line position in the related art.

[0005] The technical solution is as follows:

[0006] In one aspect, a display panel is provided, comprising:

[0007] a substrate having a display area and a non-display area at least partially surrounding the display area;

[0008] an interlayer dielectric layer, the interlayer dielectric layer being located on one side of the substrate and being located in the display area and the non-display area;

[0009] a cutting path, the cutting path being located on one side of the substrate and in the non-display area, the cutting path comprising a plurality of via holes penetrating the interlayer dielectric layer and sequentially arranged along a first direction;

[0010] a first planar layer, the first planar layer being located on a side of the interlayer dielectric layer away from the substrate and located in the non-display area, the first planar layer being away from the display area relative to the cutting street, a side of the first planar layer close to the display area being spaced apart from a side of the cutting street away from the display area, and the first planar layer being inclined in a direction away from the substrate toward a direction away from the cutting street;

[0011] An anode layer is located on a side of the first planar layer away from the substrate and is located in the display area.

[0012] Optionally, the non-display area has a connection area and a fan-out area sequentially arranged in a direction close to the display area; the first planar layer is located in the connection area; and the display panel further includes:

[0013] a first metal line extending along a second direction, the first metal line being located on a side of the interlayer dielectric layer away from the substrate and being located in the connection area and the fan-out area, the second direction intersecting the first direction;

[0014] The orthographic projection of the first flat layer on the substrate partially overlaps with the orthographic projection of the first metal line on the substrate, and except for the overlapping portion, there is a gap between the side of the remaining portion of the first flat layer close to the display area and the side of the cutting path away from the display area.

[0015] Optionally, in the second direction, the first flat layer has a groove recessed in a direction away from the cutting street;

[0016] The distance between a side of the remaining portion of the first planar layer close to the display area and a side of the cutting street away from the display area is equal to the maximum width of the trench in the second direction.

[0017] Optionally, the orthographic projection of the groove on the substrate is rectangular, circular, elliptical or trapezoidal.

[0018] Optionally, the display panel further includes:

[0019] A pin portion, the pin portion is located on a side of the interlayer dielectric layer away from the substrate and located in the fan-out area, the pin portion comprising a plurality of routing pins spaced apart along the first direction;

[0020] Wherein, in the first direction, the length of the groove is greater than or equal to the length of the pin portion, and the pin portion is located within a range defined by extension lines on both sides of the groove.

[0021] Optionally, the first metal line includes a first power line and a second power line arranged at intervals along the first direction, and the potential of a first power signal provided by the first power line is greater than the potential of a second power signal provided by the second power line;

[0022] Wherein, the groove and the pin portion are located between the first power line and the second power line.

[0023] Optionally, the display panel further includes:

[0024] a second metal line extending along the first direction, the second metal line being located on a side of the interlayer dielectric layer close to the substrate and located in the connection region;

[0025] The orthographic projection of the first planar layer on the substrate covers the orthographic projection of the second metal line on the substrate.

[0026] Optionally, the cutting street is located in the connection area, and the cutting street is close to the fan-out area relative to the first planar layer.

[0027] Optionally, the first direction and the second direction are both parallel to the display surface of the display panel, and the first direction is perpendicular to the second direction.

[0028] Optionally, the display panel further includes:

[0029] a buffer layer, the buffer layer being located between the interlayer dielectric layer and the substrate and being located in the display area and the non-display area;

[0030] a transistor located in the display area, the transistor comprising: an active layer and a gate insulating layer located between the buffer layer and the interlayer dielectric layer and stacked in sequence in a direction away from the substrate; a gate metal layer located between the gate insulating layer and the interlayer dielectric layer; and a source / drain metal layer located between the interlayer dielectric layer and the second planarization layer;

[0031] Wherein, the via hole penetrates the interlayer dielectric layer and the gate insulating layer and exposes the buffer layer;

[0032] Furthermore, in a display panel having a first metal line, a second metal line and a pin portion, the first metal line and the pin portion are both located in the same layer as the source / drain metal layer, and the second metal line is located in the same layer as the gate metal layer.

[0033] Optionally, the display panel further includes:

[0034] The second planar layer is located on a side of the interlayer dielectric layer away from the substrate and is located in the display area. The second planar layer and the first planar layer are located in the same layer.

[0035] Optionally, the thickness of the first planar layer is smaller than the thickness of the second planar layer.

[0036] Optionally, a distance between a side of the first planar layer close to the display area and a side of the cutting street away from the display area is greater than 10 micrometers.

[0037] In another aspect, a method for manufacturing a display panel is provided, for manufacturing the display panel according to the above aspect, the method comprising:

[0038] providing a substrate having a display area and a non-display area at least partially surrounding the display area;

[0039] forming an interlayer dielectric layer on one side of the substrate, wherein the interlayer dielectric layer is located in the display area and the non-display area;

[0040] forming a cutting path penetrating the interlayer dielectric layer on one side of the substrate, the cutting path being located in the non-display area, and the cutting path comprising a plurality of via holes sequentially arranged along a first direction;

[0041] A first flat layer is formed on a side of the interlayer dielectric layer away from the substrate, the first flat layer is located in the non-display area, and the first flat layer is away from the display area relative to the cutting street. A side of the first flat layer close to the display area is spaced apart from a side of the cutting street away from the display area, and the first flat layer is inclined in a direction away from the substrate toward a direction away from the cutting street.

[0042] An anode layer is formed on a side of the first planar layer away from the substrate, and the anode layer is located in the display area.

[0043] On the other hand, a display device is provided, comprising: the display panel as described in the above aspect.

[0044] In summary, the beneficial effects brought about by the technical solutions provided by the embodiments of the present disclosure may include at least:

[0045] Provided are a display panel, a manufacturing method thereof, and a display device. The display panel includes an interlayer dielectric layer located on one side of a substrate, a cutting path, and a first flat layer. The cutting path includes a plurality of vias penetrating the interlayer dielectric layer, and the first flat layer is located on the side of the interlayer dielectric layer away from the substrate. Because the side of the first flat layer close to the display area is inclined in a direction away from the substrate, and there is a gap between the side of the cutting path away from the display area, the gap size can be flexibly set so that when the anode layer is formed using a patterning process, the exposure light is reflected in different directions on the inclined side of the first flat layer and the side of the interlayer dielectric layer away from the substrate, so that the exposure amount at the via hole is better, avoiding the anode layer from remaining at the via hole. That is, the anode layer formed on the side of the second insulation away from the substrate is only located in the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 is a schematic diagram of a substrate in a display panel provided by an embodiment of the present disclosure;

[0048] Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0049] Figure 3is a cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0050] Figure 4 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure;

[0051] Figure 5 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure;

[0052] Figure 6 is a schematic diagram of another substrate in a display panel provided by an embodiment of the present disclosure;

[0053] Figure 7 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0054] Figure 8 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure;

[0055] Figure 9 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure;

[0056] Figure 10 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0057] Figure 11 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure;

[0058] Figure 12 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0059] Figure 13 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0061] Figure 1 Schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 1 As shown, the display panel includes:

[0062] The substrate 01 has a display area A1 and a non-display area B1 at least partially surrounding the display area A1. Figure 1 In the substrate 01 shown, the non-display area B1 is located on the left side of the display area A1, and is adjacent to (ie, adjacent to and in contact with) the display area A1, so as to partially surround the display area A1. Of course, it is not limited to the left side. Figure 1The non-display area B1 may be located at the lower side and / or the upper side of the display area A1. Alternatively, the non-display area B1 may be located on each side of the display area A1 to surround the display area A1.

[0063] In addition, it should be noted that the area of ​​the display area A1 is generally much larger than the area of ​​the non-display area B1. The accompanying drawings are only for schematic illustration and do not limit the areas of the display area A1 and the non-display area B1.

[0064] exist Figure 1 Based on the structure shown, Figure 2 A top view of a display panel provided by an embodiment of the present disclosure is shown. Figure 3 yes Figure 2 The cross-sectional view of the structure shown in the MM' direction. And, Figure 2 Only the non-display area B1 is shown. Figure 3 Showing the display area A1 and the non-display area B1. Figure 2 and Figure 3 It can be seen that the display panel described in the embodiment of the present disclosure further includes:

[0065] Interlayer dielectric (ILD) layer 02 is located on one side of substrate 01 and is located in display area A1 and non-display area B1. Specifically, a portion of interlayer dielectric layer 02 is located in display area A1, while another portion is located in non-display area B1. The entire layer covers one side of substrate 01.

[0066] The cutting line 03 is located on one side of the substrate 01 and in the non-display area B1. The cutting line 03 includes a plurality of via holes K1 penetrating the interlayer dielectric layer 02 and arranged in sequence along the first direction X1.

[0067] in, Figure 3 The cross-sectional view schematically illustrates only one via K1. When manufacturing a display panel, the display motherboard can be cut along the cutting path 03, i.e., at the via K1, to obtain a single display panel. Optionally, the sidewalls of the via K1 can be perpendicular to the substrate 01 to facilitate cutting.

[0068] A first planarization (PLN) layer 04 is located on the side of the interlayer dielectric layer 02 away from the substrate 01 and in the non-display area B1. Furthermore, the first planarization layer 04 is located away from the display area A1 relative to the scribe line 03. That is, the first planarization layer 04 is located on the side of the scribe line 03 away from the display area A1.

[0069] The side of the first flat layer 04 close to the display area A1 (i.e., side f indicated in the figure) is inclined in a direction away from the substrate 01 and in a direction away from the cutting path 03. In other words, the angle α between the side of the first flat layer 04 close to the display area A1 and the upper surface of the interlayer dielectric layer 02 away from the substrate 01 is an obtuse angle, which is greater than 90 degrees. In addition, there is a spacing d1 between the side of the first flat layer 04 close to the display area A1 and the side of the cutting path 03 away from the display area A1. That is, the orthographic projection of side f on the substrate 01 does not overlap with the orthographic projection of the sidewall of the via K1 included in the cutting path 03 away from the display area A1 on the substrate 01. Based on the position of the first flat layer 04, it can be seen that the side of the first flat layer 04 close to the display area A1 can be considered as a boundary of the first flat layer 04, which is referred to as an inclined boundary in the following embodiment.

[0070] Furthermore, it includes an anode layer 05. The anode layer 05 is located on a side of the first planar layer 04 away from the substrate 01 and is located in the display area A1.

[0071] It should be noted that the anode layer 05 can be formed by a single patterning process using a mask. The single patterning process includes the following steps: photoresist coating, exposure, development, etching, and photoresist stripping. Figure 4 As shown, an anode film 05 m may be formed on the side of the first planar layer 04 away from the substrate 01 , and then a mask M1 is used to perform a patterning process on the anode film 05 m to form the anode layer 05 .

[0072] Since the depth of the via K1 in the cutting lane 03 is generally deep, Figure 4 It can also be seen that the photoresist (PR) coated at the via K1 is generally thicker. On this basis, if the inclined boundary of the first flat layer 04 is set to contact the side of the cutting path 03 away from the display area A1, when the light L00 is used for exposure processing, the light will be all obliquely reflected in the same direction at the inclined boundary of the first flat layer 04, thereby resulting in insufficient exposure at the via K1 and residual anode layer 05 at the via K1 (see Figure 5 As shown in the accompanying drawings, the anode layer 05 formed is not only located in the display area A1, but also partially located at the via K1 in the non-display area B1, resulting in poor product yield. Furthermore, because the anode layer 05 is a highly reflective film, it is more likely to leave residue at the via than when forming other film layers.

[0073] In the embodiment of the present disclosure, a gap d1 is set between the side of the first flat layer 04 close to the display area A1 and the side of the cutting street 03 away from the display area A1, so that the inclined boundary of the first flat layer 04 does not contact the side of the cutting street 03 away from the display area A1. The gap d1 can be flexibly set. For example, the gap d1 is set to be large, so that the side of the interlayer dielectric layer 02 away from the substrate (i.e., Figure 3 The upper surface shown in FIG. 1 is mostly not covered by the first flat layer 04 near the via hole K1. During exposure, the light L00 is reflected in different directions at the inclined boundary and the portion of the interlayer dielectric layer 02 on the side away from the substrate that is not covered by the first flat layer 04, rather than being completely reflected obliquely in the same direction. On this basis, sufficient exposure can be ensured to prevent the anode layer 05 from remaining at the via hole K1, that is, the anode layer 05 formed is only located in the display area A1 (see FIG. 1 ). Figure 4 As shown in the accompanying drawings). In this way, a good yield of the display product is ensured.

[0074] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes an interlayer dielectric layer located on one side of a substrate, a cutting path, and a first flat layer. The cutting path includes a plurality of vias penetrating the interlayer dielectric layer, and the first flat layer is located on the side of the interlayer dielectric layer away from the substrate. Because the side of the first flat layer close to the display area is inclined in a direction away from the substrate, and there is a gap between the side of the cutting path away from the display area, the size of the gap can be flexibly set so that when the anode layer is formed by a patterning process, the exposure light is reflected in different directions on the inclined side of the first flat layer and the side of the interlayer dielectric layer away from the substrate, so that the exposure amount at the via hole is better, avoiding the residual anode layer at the via hole. That is, the anode layer formed on the side of the second insulation away from the substrate is only located in the display area.

[0075] Optionally, the distance d1 between the side of the first planar layer 04 close to the display area A1 and the side of the cutting street 03 away from the display area A1 can be greater than 10 micrometers (μm). Figure 2 and Figure 3 , the distance d1 between the first planar layer 04 and the via hole K1 can be set to be greater than 10 μm. For example, d1 can be set to be 12 μm.

[0076] Optional, Figure 6 FIG. 1 is a schematic diagram of another display panel structure provided by an embodiment of the present disclosure. Figure 6As shown, the non-display area B1 may have a connection area B11 and a fan-out area B12 arranged in sequence along the direction close to the display area A1. Among them, as the name implies, the connection area B11 may refer to the area where the signal line is connected to the circuit that provides the signal to the signal line. The fan-out area B12 may refer to the area where the signal line fan-out (also called lead-out) belongs. Optionally, the signal line included in the connection area B11 may be a signal line for lighting test before leaving the factory, such as a switch signal line and a data line lead. When cutting through the cutting path 03, the connection area B11 can be cut off, and the display panel leaving the factory does not include the connection area B11. The lighting signal can be input to the display area A1 through the fan-out area B12 to light up the pixels in the display panel located in the display area A1.

[0077] exist Figure 6 Based on the regional division shown, Figure 7 A top view of another display panel provided by an embodiment of the present disclosure is shown. Figure 8 Shown Figure 7 Cross-sectional view of the structure shown in the MM' direction. Figure 9 Shown Figure 7 The cross-section of the structure shown in the NN' direction. Figures 7 to 9 It can be seen that the first flat layer 04 described in the embodiment of the present disclosure can be located only in the connection area B11. In addition, the display panel may further include:

[0078] The first metal lines L1 extending along the second direction Y1 generally include multiple lines. These first metal lines L1 can be located on the side of the interlayer dielectric layer O2 away from the substrate O1 and can be located in the connection area B11 and the fan-out area B12. That is, a portion of each first metal line L1 can be located in the connection area B11, and another portion can be located in the fan-out area B12. In some embodiments, the first metal lines L1 can also fan out to the display area A1 via the fan-out area B12. That is, the first metal lines L1 can also be located in the display area A1.

[0079] For example, still refer to Figure 7 As can be seen, the first metal line L1 may include a first power line VDD and a second power line VSS spaced apart along the first direction X1. The potential of the first power signal provided by the first power line VDD may be greater than the potential of the second power signal provided by the second power line VSS. The first power line VDD and the second power line VSS may fan out to the display area A1 via the fan-out area B12 and connect to the pixels in the display area A1 to drive the pixels to emit light.

[0080] Optionally, the first direction X1 and the second direction Y1 may both be parallel to the display surface of the display panel, and the second direction Y1 may intersect with the first direction X1. For example, the first direction X1 is perpendicular to the second direction Y1. Figure 7 The MM' direction is the second direction Y1. Figure 8 The NN' direction is the first direction X1.

[0081] Optional, continue to refer to Figure 7 It can be seen that the orthographic projection of the first flat layer 04 on the substrate 01 and the orthographic projection of the first metal line L1 on the substrate 01 can partially overlap. And except for the overlapping part, there is a spacing d1 between the side of the remaining part of the first flat layer 04 close to the display area A1 and the side of the cutting road 03 away from the display area A1. That is, in the embodiment of the present disclosure, it is possible to set only the part of the inclined boundary of the first flat layer 04 that does not overlap with the first metal line L1 and the side of the cutting road 03 away from the display area A1 to have a spacing d1. And as described in the above embodiment, this d1 can be set larger, such as greater than 10μm. In this way, not only can the anode layer 05 be prevented from remaining at the via K1, but also the metal wire can be protected to prevent external water and oxygen from corroding the metal wire, further ensuring a good product yield.

[0082] That is, in the embodiment of the present disclosure, it can be as follows Figure 2 As shown, there is a large gap between the entire inclined boundary of the first flat layer 04 and the side of the cutting road 03 away from the display area A1. Figure 7 As shown, only the inclined boundary of the first flat layer 04 is provided with a large distance from the side of the cutting street 03 away from the display area A1. The premise is that the distance d1 is set to ensure that no anode layer 05 remains at the via hole K1.

[0083] Optionally, based on the larger distance d1 between the inclined boundary of the first flat layer 04 and the side of the cutting road 03 away from the display area A1, Figure 7 and Figure 9 As can be seen, in the second direction Y1, the first planar layer 04 can have a recessed groove C1 extending away from the scribe line 03. In other words, a groove design can be implemented in the first planar layer 04 to alleviate the problem of residual anode layer 05. Furthermore, since this configuration does not require additional film layers, it does not increase costs, resulting in a simple process and low cost, making it suitable for mass production.

[0084] Thus, the distance d1 between the remaining portion of the first planar layer 04 near the display area A1 and the dicing street 03 away from the display area A1 can be equal to the maximum width w1 of the trench C1 in the second direction Y1. In other words, the embodiment of the present disclosure can set the width w1 of the trench C1 to be greater than 10 μm.

[0085] Example, combined Figure 7 and Figure 9It can also be seen that the orthographic projection of the trench C1 on the substrate 01 can be rectangular, circular, elliptical, or trapezoidal. Of course, in some embodiments, the orthographic projection of the trench C1 on the substrate 01 can also be other shapes, such as irregular shapes, and the embodiments of the present disclosure do not limit the shape.

[0086] Optional, still reference Figure 7 As can be seen, the display panel described in the embodiments of the present disclosure may further include a pin portion 06. This pin portion 06 may be located on a side of the interlayer dielectric layer 02 away from the substrate 01 and may be located only in the fan-out region B12. This pin portion 06 may include a plurality of routing pins (also referred to as pin feet) arranged at intervals along the first direction X1. These pin feet may be connected to signal lines or external circuits. Figure 7 Only 5 pins are shown schematically.

[0087] In the first direction X1 , the length l1 of the groove C1 may be greater than or equal to the length l2 of the pin portion 06 , that is, the length l1 of the groove C1 may be flexibly adjusted according to the width of the pin foot.

[0088] Furthermore, the pin portion 06 may be located within the range defined by the extension lines on both sides of the groove C1. Here, the extension line may refer to the extension line extending toward the pin portion 06. Figure 7 As can be seen, the pin portion 06 is surrounded by the groove C1 on both sides in the first direction X1. This effectively protects the pins and prevents the connection between different pins and signal crosstalk caused by the groove, further ensuring a good product yield.

[0089] Optional, still reference Figure 7 It can be seen that, based on the first metal line L1 including the first power line VDD and the second power line VSS, the groove C1 and the pin portion 06 can be located between the first power line VDD and the second power line VSS, which can facilitate the narrow frame design of the display panel.

[0090] Optional, still reference Figure 7 As can be seen, the display panel described in the embodiments of the present disclosure may further include: second metal lines L2 extending along the first direction X1, generally including multiple lines. The second metal lines L2 may be located on the side of the interlayer dielectric layer O2 close to the substrate O1 and only in the connection area B11. In conjunction with the above embodiments, it can be seen that the second metal lines L2 may be signal lines for lighting testing, such as the switch line Switch.

[0091] The orthographic projection of the first flat layer 04 on the substrate 01 can cover the orthographic projection of the second metal line L2 on the substrate 01. Figures 7 to 9The second metal line L2 can be covered by the first planar layer O4. The trench design extends only to the side of the second metal line L2 closest to the display area A1, but does not contact the side of the second metal line L2 closer to the display area A1. This reduces the residual anode layer O5 while ensuring reliable protection of the second metal line L2, further ensuring a high product yield.

[0092] Optional, combined Figure 7 and Figure 10 From the schematic diagram of another area division shown, it can be seen that the cutting road 03 recorded in the embodiment of the present disclosure can be located in the connection area B11, and is close to the fan-out area B12 relative to the first flat layer 04. That is, the cutting road 03 is located on the side of the first flat layer 04 close to the fan-out area B12. Of course, in some other embodiments, the cutting road 03 can also be located in the fan-out area B12, and is closer to the connection area B11 relative to the pin portion 06. In other words, the cutting road 03 can be located on the side adjacent to the connection area B11 and the fan-out area B12, and is located in the connection area B11 or the fan-out area B12. Alternatively, the cutting road 03 can be partially located in the connection area B11 and partially located in the fan-out area B12. In addition, Figure 10 The trench design locations are also schematically indicated.

[0093] Optionally, based on the above drawings, Figure 11 FIG. 1 shows a cross-sectional view of another display panel provided by an embodiment of the present disclosure, including a display area A1 and a non-display area B1. Figure 11 As shown, the display panel may further include:

[0094] Buffer layer 07. The buffer layer 07 may be located between the interlayer dielectric layer 02 and the substrate 01, and located in the display area A1 and the non-display area B1. That is, a portion of the buffer layer 07 may be located in the display area A1, and another portion may be located in the non-display area B1.

[0095] The second planar layer 08 may be located on a side of the interlayer dielectric layer 02 away from the substrate 01 and located in the display area A1 .

[0096] Transistor T1, which may be located in display area A1. Furthermore, transistor T1 may include: an active layer P1 and a gate insulator (GI) layer GI located between a buffer layer 07 and an interlayer dielectric layer 02, stacked sequentially in a direction away from substrate 01; a gate metal layer GT located between the gate insulator layer GI and the interlayer dielectric layer 02; and a source / drain metal layer SD located between the interlayer dielectric layer 02 and the second planar layer 08. That is, Figure 11 The transistor T1 shown may be a top-gate transistor. Of course, in some other embodiments, the transistor T1 may also be a bottom-gate transistor.

[0097] The via K1 included in the cutting path 03 can penetrate the interlayer dielectric layer 02 and the gate insulating layer GI and expose the buffer layer 07. The via K1 formed in this way can be deep, so it is easy to cut. The second flat layer 08 and the first flat layer 04 can be located in the same layer. And, combined with Figure 7 and Figure 11 It can be seen that the first metal line L1 and the lead portion 06 may be located in the same layer as the source / drain metal layer SD, and the second metal line L2 may be located in the same layer as the gate metal layer GT.

[0098] It should be noted that being located in the same layer may refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and are formed through the same patterning process. In this way, the manufacturing process and manufacturing costs can be saved, and the manufacturing efficiency can be accelerated.

[0099] That is, in the disclosed embodiment, the second planar layer 08 in the display area A1 and the first planar layer 04 in the non-display area B1 can be made of the same material and formed through a single patterning process. The first metal line L1 and lead portion 06 in the non-display area B1, as well as the source and drain metal layer SD included in the transistor T1 in the display area A1, can be made of the same material and formed through a single patterning process. The second metal line L2 in the non-display area B1 and the gate metal layer GT included in the transistor T1 in the display area A1 can be made of the same material and formed through a single patterning process.

[0100] Optional, continue to refer to Figure 11 It can be seen that in the display panel described in the embodiment of the present disclosure, the thickness of the first planar layer 04 can be less than that of the second planar layer 08, and the thickness direction can be perpendicular to the substrate 01. On this basis, the slope of the inclined boundary of the first planar layer 04 can be made gentle, further ensuring sufficient exposure when forming the anode layer 05 and preventing the anode layer 05 from remaining in the via K1.

[0101] For example, since the first flat layer 04 and the second flat layer 08 are located in the same layer, a semi-transmissive and semi-reflective mask plate can be used when the first flat layer 04 and the second flat layer 08 are formed simultaneously, which has a wider range of applications.

[0102] It should be noted that, in addition to the deep hole positions of the cutting path 03, which can adopt the design of the embodiment of the present disclosure (such as the groove design for the first flat layer 04), the deep hole positions at other positions that are prone to cause residual anode layer can also be designed in the same way, thereby effectively ensuring a good product yield.

[0103] In addition, combined with Figure 11 , the connection relationship and materials between the layers in the display panel are described as follows:

[0104] On the one hand, the display panel may further include: a light emitting layer, a pixel definition layer (PDL), a cathode layer, and a support layer PS, which are located on a side of the anode layer 05 away from the substrate 01 and are stacked in sequence. Figure 11 The pixel defining layer PDL and the support layer PS are only schematically shown.

[0105] On the other hand, the source / drain metal layer SD may include: a source metal layer S1 and a drain metal layer D1 located in the same layer and spaced apart from each other. The source metal layer S1 and the drain metal layer D1 may overlap the active layer P1 through a overlapping hole that penetrates the interlayer dielectric layer 02 and the gate insulating layer GI and exposes the active layer P1. In addition, the active layer P1 may have a semiconductor region (also called a channel region) and a conductive region (referred to as a source region and a drain region, respectively) located on both sides of the channel region. The semiconductor region may not be doped, or the doping type may be different from that of the source and drain regions, and thus have semiconductor properties. The conductive region may be doped and thus have conductivity. The doped impurities may vary depending on the type of transistor (i.e., N-type or P-type). The source / drain metal layer SD may overlap the conductive region. The anode layer 05 may overlap the drain metal layer D1 through a overlapping hole that penetrates the second planar layer 08 and exposes the drain metal layer D1. In this way, the transistor T1 can transmit a driving voltage to the anode layer 05 through the drain metal layer D1. The driving voltage and the driving voltage applied to the cathode layer can form a voltage difference, thereby driving the light-emitting layer to emit light.

[0106] It should be noted that a pixel generally includes a pixel circuit and a light-emitting element, and the light-emitting element includes the anode layer 05, the light-emitting layer, and the cathode layer described in the above embodiment. The pixel circuit includes multiple transistors such as a data writing transistor, a reset transistor, and a driving transistor, wherein the driving transistor can be electrically connected to the anode layer 05 included in the light-emitting element to provide a driving signal to the light-emitting element, thereby driving the light-emitting element to emit light. In this way, Figure 11 The transistor T1 shown may be referred to as a driving transistor.

[0107] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes an interlayer dielectric layer located on one side of a substrate, a cutting path, and a first flat layer. The cutting path includes a plurality of vias penetrating the interlayer dielectric layer, and the first flat layer is located on the side of the interlayer dielectric layer away from the substrate. Because the side of the first flat layer close to the display area is inclined in a direction away from the substrate, and there is a gap between the side of the cutting path away from the display area, the size of the gap can be flexibly set so that when the anode layer is formed by a patterning process, the exposure light is reflected in different directions on the inclined side of the first flat layer and the side of the interlayer dielectric layer away from the substrate, so that the exposure amount at the via hole is better, avoiding the residual anode layer at the via hole. That is, the anode layer formed on the side of the second insulation away from the substrate is only located in the display area.

[0108] Figure 12 FIG. 1 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure. The method can be used to manufacture the display panel shown in the above figures. Figure 12 As shown, the method includes:

[0109] Step 1201: Provide a substrate.

[0110] like Figure 1 As shown, the provided substrate 01 may include a display area A1 and a non-display area B1 at least partially surrounding the display area A1. Optionally, the provided substrate 01 may include: a glass substrate or a flexible substrate.

[0111] Step 1202: Form an interlayer dielectric layer on one side of the substrate.

[0112] Optionally, a one-time patterning process can be used to form an interlayer dielectric layer on the substrate. Figure 3 and Figure 11 It can be seen that the formed interlayer dielectric layer 02 can be located in the display area A1 and the non-display area B1.

[0113] Step 1203: forming a cutting path penetrating the interlayer dielectric layer on one side of the substrate.

[0114] Optionally, a single patterning process may be used to form a cutting path on the substrate that penetrates the interlayer dielectric layer. Figure 3 and Figure 11 It can be seen that the formed cutting street 03 may be located in the non-display area B1 and includes a plurality of via holes K1 sequentially arranged along the first direction X1.

[0115] Step 1203: forming a first planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0116] Optionally, a single patterning process may be used to form a first flat layer on the side of the interlayer dielectric layer away from the substrate. Figure 3It can be seen that the formed first planar layer 04 can be located only in the non-display area B1. The first planar layer 04 is away from the display area A1 relative to the scribe line 03. A distance d1 can exist between the side of the first planar layer 04 close to the display area A1 and the side of the scribe line 03 away from the display area A1. The distance d1 is inclined from the direction away from the substrate 01 toward the direction away from the scribe line 03. For example, the distance d1 can be greater than 10 μm.

[0117] Step 1204: forming an anode layer on a side of the first planar layer away from the substrate.

[0118] Alternatively, a single patterning process can be used to form the anode layer on the side of the first planar layer away from the substrate. Furthermore, as can be seen from the above embodiments, by setting the spacing d1 relatively large, sufficient exposure can be ensured during the patterning process to form the anode layer, ensuring that no anode layer 05 remains at the location of via K1. This means that the formed anode layer 05 is located only in the display area A1. This ensures a high product yield.

[0119] Optional, reference Figure 6 and Figure 7 As can be seen, the non-display area B1 can include a connection area B11 and a fan-out area B12 arranged sequentially in a direction approaching the display area A1. Based on this, the first planarization layer 04 can be formed only in the connection area B11. Furthermore, a patterning process can be further employed to form first metal lines L1 extending along the second direction Y1 on the side of the interlayer dielectric layer 02 away from the substrate 01. Furthermore, the formed first metal lines L1 can be located in both the connection area B11 and the fan-out area B12.

[0120] The second direction Y1 may intersect the first direction X1. For example, the first direction X1 may be perpendicular to the second direction Y1. Furthermore, the first direction X1 and the second direction Y1 may both be parallel to the supporting surface of the substrate 01.

[0121] In the embodiment of the present disclosure, Figure 7 It can also be seen that the orthographic projection of the formed first flat layer 04 on the substrate 01 can partially overlap with the orthographic projection of the first metal line L1 on the substrate 01, and except for the overlapping portion, there is a distance d1 between the side of the remaining part of the first flat layer 04 close to the display area A1 and the side of the cutting road 03 away from the display area A1.

[0122] For example, the first planar layer 04 can have a recessed groove C1 in the second direction Y1, extending away from the scribe line 03. This groove design can be used to improve the residual anode layer 05. As described in the above embodiment, the spacing d1 can be equal to the maximum width w1 of the groove C1 in the second direction Y1. Alternatively, the first planar layer 04 can be etched to form the groove C1.

[0123] Optional, continue to refer to Figure 7 It can be seen that the orthographic projection of the formed trench C1 on the substrate 01 may be rectangular.

[0124] Optional, continue to refer to Figure 7 It can be seen that a patterning process can be further used to form a pin portion 06 on the side of the interlayer dielectric layer 02 away from the substrate 01. The formed pin portion 06 can be located only in the fan-out area B12. The pin portion 06 can include a plurality of routing pins, i.e., pins, arranged at intervals along the first direction X1.

[0125] Furthermore, in the first direction X1 , the length L1 of the formed groove C1 may be greater than or equal to the length L2 of the pin portion 06 , and the pin portion 06 is located within a range defined by extension lines on both sides of the groove C1 .

[0126] Optional, continue to refer to Figure 7 It can be seen that the formed first metal line L1 may include a first power line VDD and a second power line VSS arranged at intervals along the first direction X1, and the potential of the first power signal provided by the first power line VDD is greater than the potential of the second power signal provided by the second power line VSS.

[0127] On this basis, the formed groove C1 and the lead portion 06 can be located between the first power line VDD and the second power line VSS. In other words, the groove C1 and the lead portion 06 can be formed between the first power line VDD and the second power line VSS.

[0128] Optional, continue to refer to Figures 7 to 9 As can be seen, a further patterning process can be used to form a second metal line L2 extending along the first direction X1 on the side of the interlayer dielectric layer 02 close to the substrate 01. Furthermore, the formed second metal line L2 can be located only in the connection area B11. Furthermore, the orthographic projection of the formed first planar layer 04 on the substrate 01 covers the orthographic projection of the formed second metal line L2 on the substrate 01.

[0129] Optional, continue to refer to Figures 7 to 9 It can be seen that the formed scribe line 03 may be located only in the connection area B11 and is closer to the fan-out area B12 relative to the first planar layer 04 .

[0130] Optional, continue to refer to Figure 11As can be seen, a buffer layer 07 can be further formed between the interlayer dielectric layer 02 and the substrate 01 using a patterning process, and the formed buffer layer 07 can be located in the display area A1 and the non-display area B1. A second flat layer 08 is formed on the side of the interlayer dielectric layer 02 away from the substrate 01 using a patterning process, and the formed second flat layer 08 is only located in the display area A1. Furthermore, a transistor T1 is formed in the display area A1 using a patterning process. Furthermore, the formed transistor T1 includes an active layer P1 and a gate insulating layer GI located between the buffer layer 07 and the interlayer dielectric layer 02 and stacked in sequence in a direction away from the substrate 01, a gate metal layer GT located between the gate insulating layer GI and the interlayer dielectric layer 02, and a source / drain metal layer SD located between the interlayer dielectric layer 02 and the second flat layer 08.

[0131] On this basis, the formed via K1 can optionally penetrate the interlayer dielectric layer 02 and the gate insulating layer GI and expose the buffer layer 07. That is, the via K1 can be obtained by processing the interlayer dielectric layer 02 and the gate insulating layer GI, thereby forming the cutting path 03. The formed second flat layer 08 and the first flat layer 04 can be located on the same layer. That is, the second flat layer 08 and the first flat layer 04 can be formed using the same material through a single patterning process. Furthermore, the formed first metal line L1 and the pin portion 06 can both be located on the same layer as the source / drain metal layer SD, and the second metal line L2 and the gate metal layer GT can be located on the same layer. That is, the first metal line L1, the pin portion 06, and the source / drain metal layer SD included in the transistor T1 can be formed using the same material through a single patterning process. The second metal line L2 and the gate metal layer GT can also be formed using the same material through a single patterning process.

[0132] Optionally, in the embodiment of the present disclosure, the thickness of the first planar layer 04 may be smaller than the thickness of the second planar layer 08. In this way, a semi-transmissive and semi-reflective mask may be used to simultaneously form insulating layers in the same layer but with different thicknesses.

[0133] In summary, the embodiments of the present disclosure provide a method for manufacturing a display panel. The display panel formed by this method includes an interlayer dielectric layer located on one side of the substrate, a cutting path and a first flat layer. The cutting path includes a plurality of vias penetrating the interlayer dielectric layer, and the first flat layer is located on the side of the interlayer dielectric layer away from the substrate. Because the side of the formed first flat layer close to the display area is inclined in a direction away from the substrate, and there is a gap between the side of the cutting path away from the display area, the size of the gap can be flexibly set so that when the anode layer is formed by a patterning process, the exposure light is reflected in different directions on the inclined side of the first flat layer and the side of the interlayer dielectric layer away from the substrate, so that the exposure amount at the via is better, avoiding the residual anode layer at the via. That is, the anode layer formed on the side of the second insulation away from the substrate is only located in the display area.

[0134] Figure 13 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 13 As shown, the display device includes: the display panel 00 as shown in the above figures. In addition, the display device may further include a power supply component J1, which can be connected to the display panel 00 to supply power to the display panel 00.

[0135] Optionally, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigation system, or transparent display product. Transparent display products can be used for in-vehicle displays in cars and subways, as well as in window displays in hotels and clothing stores, offering advantages such as clear image quality and realistic display effects.

[0136] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0137] Furthermore, the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0138] For example, in the embodiments of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0139] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0140] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0141] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection.

[0142] "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0143] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel includes: a substrate having a display area and a non-display area at least partially surrounding the display area; an interlayer dielectric layer, the interlayer dielectric layer being located on one side of the substrate and being located in the display area and the non-display area; a cutting path, the cutting path being located on one side of the substrate and in the non-display area, the cutting path comprising a plurality of via holes penetrating the interlayer dielectric layer and sequentially arranged along a first direction; a first planar layer, the first planar layer being located on a side of the interlayer dielectric layer away from the substrate and located in the non-display area, the first planar layer being away from the display area relative to the cutting street, a side of the first planar layer close to the display area being spaced apart from a side of the cutting street away from the display area, and the first planar layer being inclined in a direction away from the substrate toward a direction away from the cutting street; an anode layer, the anode layer being located on a side of the first planar layer away from the substrate and located in the display area; The orthographic projection of the anode layer on the substrate does not overlap with the orthographic projection of the multiple vias on the substrate, and also does not overlap with the orthographic projection of a portion of the interlayer dielectric layer on the side of the cutting path away from the display area that is not covered by the first flat layer on the substrate.

2. The display panel according to claim 1, wherein: The non-display area includes a connection area and a fan-out area sequentially arranged in a direction close to the display area; the first planar layer is located in the connection area; and the display panel further includes: a first metal line extending along a second direction, the first metal line being located on a side of the interlayer dielectric layer away from the substrate and being located in the connection area and the fan-out area, the second direction intersecting the first direction; The orthographic projection of the first flat layer on the substrate partially overlaps with the orthographic projection of the first metal line on the substrate, and except for the overlapping portion, there is a gap between the side of the remaining portion of the first flat layer close to the display area and the side of the cutting path away from the display area.

3. The display panel according to claim 2, wherein: In the second direction, the first flat layer has a groove recessed in a direction away from the cutting street; The distance between a side of the remaining portion of the first planar layer close to the display area and a side of the cutting street away from the display area is equal to the maximum width of the trench in the second direction.

4. The display panel according to claim 3, wherein: The orthographic projection of the trench on the substrate is rectangular, circular, elliptical or trapezoidal.

5. The display panel according to claim 3, wherein: The display panel further includes: A pin portion, the pin portion is located on a side of the interlayer dielectric layer away from the substrate and located in the fan-out area, the pin portion comprising a plurality of routing pins spaced apart along the first direction; Wherein, in the first direction, the length of the groove is greater than or equal to the length of the pin portion, and the pin portion is located within a range defined by extension lines on both sides of the groove.

6. The display panel according to claim 5, wherein: The first metal line includes a first power line and a second power line arranged at intervals along the first direction, the potential of a first power signal provided by the first power line is greater than the potential of a second power signal provided by the second power line; Wherein, the groove and the pin portion are located between the first power line and the second power line.

7. The display panel according to any one of claims 2 to 6, characterized in that: The display panel further includes: a second metal line extending along the first direction, the second metal line being located on a side of the interlayer dielectric layer close to the substrate and located in the connection region; The orthographic projection of the first planar layer on the substrate covers the orthographic projection of the second metal line on the substrate.

8. The display panel according to any one of claims 2 to 6, characterized in that: The dicing street is located in the connection area, and the dicing street is close to the fan-out area relative to the first planar layer.

9. The display panel according to any one of claims 2 to 6, characterized in that: The first direction and the second direction are both parallel to the display surface of the display panel, and the first direction is perpendicular to the second direction.

10. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: a buffer layer, the buffer layer being located between the interlayer dielectric layer and the substrate and being located in the display area and the non-display area; a transistor located in the display area, the transistor comprising: an active layer and a gate insulating layer located between the buffer layer and the interlayer dielectric layer and stacked in sequence in a direction away from the substrate; a gate metal layer located between the gate insulating layer and the interlayer dielectric layer; and a source / drain metal layer located between the interlayer dielectric layer and a second planarization layer; Wherein, the via hole penetrates the interlayer dielectric layer and the gate insulating layer and exposes the buffer layer; Furthermore, in a display panel having a first metal line, a second metal line and a pin portion, the first metal line and the pin portion are both located in the same layer as the source / drain metal layer, and the second metal line is located in the same layer as the gate metal layer.

11. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: The second planar layer is located on a side of the interlayer dielectric layer away from the substrate and is located in the display area. The second planar layer and the first planar layer are located in the same layer.

12. The display panel according to claim 11, wherein: It is characterized by: The thickness of the first planar layer is smaller than the thickness of the second planar layer.

13. The display panel according to any one of claims 1 to 6, characterized in that: A distance between a side of the first planar layer close to the display area and a side of the cutting street away from the display area is greater than 10 micrometers.

14. A method for manufacturing a display panel, characterized in that: For manufacturing the display panel according to any one of claims 1 to 13, the method comprises: providing a substrate having a display area and a non-display area at least partially surrounding the display area; forming an interlayer dielectric layer on one side of the substrate, wherein the interlayer dielectric layer is located in the display area and the non-display area; forming a cutting path penetrating the interlayer dielectric layer on one side of the substrate, the cutting path being located in the non-display area, and the cutting path comprising a plurality of via holes sequentially arranged along a first direction; A first flat layer is formed on a side of the interlayer dielectric layer away from the substrate, the first flat layer is located in the non-display area, and the first flat layer is away from the display area relative to the cutting street. A side of the first flat layer close to the display area is spaced apart from a side of the cutting street away from the display area, and the first flat layer is inclined in a direction away from the substrate toward a direction away from the cutting street. An anode layer is formed on a side of the first planar layer away from the substrate, and the anode layer is located in the display area.

15. A display device, characterized in that: The display device comprises: the display panel according to any one of claims 1 to 13.

Images