Chip protection circuit wiring test system and method

Abstract

The present invention discloses a wiring test system and method for a chip protection circuit, comprising: a data acquisition module, the data acquisition module acquires the model of a chip to be tested and the position of wiring nodes in a corresponding protection circuit; a wiring node relationship analysis module, the wiring node relationship analysis module acquires the position of wiring nodes in the corresponding protection circuit of the chip to be tested obtained in the data acquisition module, and analyzes the interference value of each wiring node in different wirings and the influence value between different wirings; a historical data processing module, the historical data processing module acquires the analysis result obtained by the wiring node relationship analysis module, combines the historical data of a chip with the same model as the chip to be tested, and acquires the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a wiring test system and method for a chip protection circuit. Background Art

[0002] With the rapid development of integrated circuits, people are using them more and more widely. Through small chips, people can quickly process big data, which brings great convenience to people's production and life. However, due to the high integration of chips, the connection between various components in the chip is achieved through wiring. When the wiring fails, the function of the chip will also be affected. Therefore, the detection of wiring in the chip is particularly important.

[0003] In the existing wiring test system for chip protection circuits, the overall function of the chip is only confirmed by chip function detection software to determine whether the chip itself has a fault. However, this fault judgment method has a major defect and does not take into account the influence relationship between wiring nodes and wiring in the chip protection circuit. As a result, during the chip detection process, only the probability of a fault in the chip can be obtained, but the specific location of the fault in the chip cannot be locked.

[0004] In view of the above situation, we need a wiring test system and method for chip protection circuits. Summary of the invention

[0005] The object of the present invention is to provide a wiring test system and method for a chip protection circuit to solve the problems raised in the above background technology.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: a wiring test system for a chip protection circuit, comprising:

[0007] A data acquisition module, wherein the data acquisition module obtains the model of the chip to be tested and the location of the wiring nodes in the corresponding protection circuit;

[0008] A wiring node relationship analysis module, which obtains the positions of wiring nodes in the protection circuit corresponding to the chip under test obtained in the data acquisition module, and analyzes the interference values ​​of each wiring node in different wirings and the influence values ​​between different wirings;

[0009] A historical data processing module, wherein the historical data processing module obtains the analysis results obtained by the wiring node relationship analysis module, combines the historical data of the chip with the same model as the chip to be tested, and obtains the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested;

[0010] A wiring failure rate prediction module is used to obtain the processing result obtained by the historical data processing module and predict the wiring failure rate of the protection circuit in the chip to be tested.

[0011] The present invention collects the model of the chip to be tested and the position of the wiring nodes in the corresponding protection circuit, and analyzes the interference of different wiring nodes during wiring, thereby predicting the influence value between different wirings in the chip to be tested; at the same time, combined with the relationship between the wiring influence value and the chip failure rate in historical data, the failure rate of the protection circuit of the chip to be tested is predicted; this method is different from the test method for chip protection circuit in the prior art. This method predicts the wiring failure rate in the chip by analyzing the relationship between each wiring and wiring node in the chip. In the prediction result, according to the failure rate corresponding to different wirings, the wiring position where the fault has occurred can be quickly locked, and the area where the fault occurs can be locked. In the prior art, only the overall function of the chip is simply judged to have a fault, and the specific location of the fault cannot be locked.

[0012] Furthermore, after obtaining the model of the chip to be tested, the data acquisition module will obtain the size of the chip to be tested through the database and establish a geometric model.

[0013] At the same time, a plane rectangular coordinate system is established with the center point of the geometric model as the origin, a straight line passing through the origin and parallel to the longest side of the chip to be tested as the x-axis, and a straight line passing through the origin and parallel to the plane to which the chip to be tested belongs and perpendicular to the x-axis as the y-axis;

[0014] The positions of the wiring nodes in the corresponding protection circuit of the chip to be tested are obtained through the database, the obtained wiring nodes are numbered, and the wiring nodes corresponding to the numbers are marked at the corresponding coordinate points in the plane rectangular coordinate system.

[0015] The data acquisition module of the present invention obtains the size resume proportional model of the chip to be tested in order to coordinate and concretize the position of the wiring nodes on the chip to be tested, so as to facilitate the subsequent calculation of the distance between different wiring nodes, and then calculate the interference value of each wiring node in different wirings; the wiring nodes are numbered to avoid confusion in the subsequent calculation of the interference values ​​of different wiring nodes.

[0016] Furthermore, the method for the wiring node relationship analysis module to analyze the interference value of each wiring node in different wirings includes the following steps:

[0017] S1.1, obtaining the corresponding coordinate points of the wiring nodes corresponding to each number in the plane rectangular coordinate system;

[0018] S1.2, select the wiring node corresponding to number i, obtain the wiring nodes corresponding to the other numbers within the first unit distance L0 with i as the center, and record the distances between the wiring node corresponding to number i and the wiring nodes corresponding to the other numbers respectively,

[0019] The distance between the wiring node corresponding to number i and the wiring node corresponding to number i1 is recorded as L i-i1 ;

[0020] S1.3, in order of the acquired distances from small to large, enter the distances between the wiring node corresponding to number i recorded in S1.2 and the wiring nodes corresponding to the remaining numbers into a blank set, to obtain the first set Ai corresponding to the wiring node corresponding to number i,

[0021] The value corresponding to the i2th element in Ai is recorded as Ai i2 ;

[0022] S1.4, obtain the interference value Bi of the wiring node corresponding to number i,

[0023] Said

[0024] Among them, Ai i3 Indicates the total number of elements in the set corresponding to Ai,

[0025] f(Ai i2 ) means Ai i2 The interference value generated by the wiring node with the corresponding number to the wiring node with the number i.

[0026] In the process of analyzing the interference value of each wiring node in different wirings by the wiring node relationship analysis module of the present invention, the distance between different wiring nodes is obtained. This is because in the wiring process, the wirings corresponding to the wiring nodes with closer distances may intersect, which may cause the chip to malfunction. The closer the distance between two wiring nodes, the greater the probability of the wiring intersection, and one wiring node may interfere with the wiring of another wiring node. Since there may be multiple other wiring nodes around each wiring node in the chip, and each wiring node will have an impact on it, the interference value of each wiring node is calculated to be equal to the sum of the interference values ​​of the surrounding wiring nodes, that is,

[0027] Further, get Ai i2 The interference value f(Ai) generated by the wiring node with the corresponding number to the wiring node with the number i i2 ) method comprises the following steps:

[0028] S1.4.1. Get the values ​​corresponding to the i2th element in Ai;

[0029] S1.4.2, determine the value corresponding to i2,

[0030] When i2=1, then it is determined that Ai i2 The interference value generated by the wiring node with the corresponding number to the wiring node with number i

[0031] When i2>1, the values ​​corresponding to the first i2-1 elements in Ai are further obtained;

[0032] S1.4.3. Connect the wiring nodes corresponding to the first i2 elements in Ai to the wiring nodes corresponding to number i.

[0033] Take any one of the wiring nodes corresponding to the first i2-1 elements in Ai and the line segment formed by the wiring node corresponding to number i as the first edge, and take the line segment formed by the wiring node corresponding to the i2th element in Ai and the wiring node corresponding to number i as the second edge, and obtain the minimum value of the angle formed by different first edges and second edges, recorded as θ,

[0034] Among the three wiring nodes corresponding to θ, except for the wiring node corresponding to the i2th element in Ai and the wiring node corresponding to the number i, the wiring node is denoted as c, and the number of the element corresponding to c in Ai is denoted as c1;

[0035] S1.4.4, compare θ with the first fault tolerance threshold θ1,

[0036] When θ≤θ1, it is determined that the wiring node corresponding to the i2th element in Ai is within the fault tolerance range corresponding to the wiring node c.

[0037] When θ>θ1, it is determined that the wiring node corresponding to the i2th element in Ai is not within the fault tolerance range corresponding to the wiring node c.

[0038] The present invention obtains Ai i2 The interference value f(Ai) generated by the wiring node with the corresponding number to the wiring node with the number i i2 ), the value corresponding to i2 is determined by considering the effect of the elements before i2 in Ai on Ai. i2 The influence of the wiring nodes with corresponding numbers. When i2 is equal to 1, θ cannot be obtained (the angle cannot be formed), and then it is impossible to determine the influence of the wiring node corresponding to θ on Ai i2 The influence of the corresponding numbered wiring nodes; setting Is to Ai i2The interference degree of the wiring node with the corresponding number on the wiring node with the number i is quantified, so as to facilitate the subsequent calculation of the influence value of different wirings in the chip on the rest of the wirings; comparing θ with the first fault tolerance threshold θ1 is to determine the relationship between the wiring node corresponding to the i2th element in Ai and the wiring node c. When the wiring node corresponding to the i2th element in Ai is within the fault tolerance range corresponding to the wiring node c, it means that the wiring node corresponding to the i2th element in Ai is relative to the wiring node corresponding to the number i, in the direction of the wiring node c, and thus the wiring node c is located between the wiring node corresponding to the number i and the wiring node corresponding to the i2th element in Ai, and thus Ai i2 When the wiring node with the corresponding number interferes with the wiring node with number i, it is further interfered by the wiring node c. From the content of S1.3, we can know that the distance between the wiring node corresponding to the element closer to the front in Ai and the wiring node corresponding to number i is closer, and the function In the above example, y and x are negatively correlated. The larger the x, the smaller the corresponding y. When it is determined that the wiring node corresponding to the i2th element in Ai is within the fault tolerance range corresponding to the wiring node c,

[0039] Furthermore, the method for the wiring node relationship analysis module to analyze the influence values ​​between different wirings includes the following steps:

[0040] S2.1, obtain two wiring nodes corresponding to the two ends of each wiring, and record them as the first wiring node and the second wiring node;

[0041] S2.2, obtaining the interference value of the first node of each wiring, obtaining the interference value of the second node of each wiring,

[0042] The interference value of the first node in the jth wiring is recorded as The interference value of the second node in the jth wiring is recorded as

[0043] S2.3, obtain the influence value Rj of the j-th wiring on the rest of the wiring,

[0044] In the process of analyzing the influence values ​​between different wirings by the wiring node relationship analysis module of the present invention, since the two ends of each wiring correspond to a wiring node respectively, and the interference value corresponding to each wiring node respectively reflects the situation around the wiring node, the interference value corresponding to each wiring node can be directly calculated. This can directly reflect the influence of the j-th wiring as a whole on the surrounding wiring nodes, and the influence of the j-th wiring as a whole on the surrounding wirings.

[0045] Furthermore, the historical data processing module obtains the error rates corresponding to the wirings corresponding to different impact values ​​in the historical data, and obtains a variation curve between the chip wiring error rate and the impact value.

[0046] The method for obtaining the change curve between the chip wiring error rate and the impact value by the historical data processing module comprises the following steps:

[0047] S3.1. Obtain the impact values ​​corresponding to the wiring errors in all chips in the historical data;

[0048] S3.2, respectively counting the ratios of the number of wiring errors corresponding to different impact values ​​to the total number of wirings corresponding to the corresponding impact values, and recording them in the form of an array [r, d], where r represents the impact value, and d represents the ratio of the number of wiring errors corresponding to the impact value r to the total number of wirings corresponding to the corresponding impact value;

[0049] S3.3, establish a first plane rectangular coordinate system, wherein the horizontal axis H of the first plane rectangular coordinate system represents the influence value corresponding to the wiring, and the vertical axis Z of the first plane rectangular coordinate system represents the ratio of the number of wiring errors corresponding to the influence value to the total number of wiring errors corresponding to the corresponding influence value;

[0050] S3.4. In the first plane rectangular coordinate system, mark the points corresponding to each array obtained in S3.2 respectively, and fit the points marked in the first plane rectangular coordinate system through the standard linear regression equation model prefabricated in the database to obtain the change curve Z=G(H) between the chip wiring error rate and the influence value.

[0051] In the process of obtaining the variation curve between the chip wiring error rate and the influence value by the historical data processing module of the present invention, the wiring conditions in all chips in the historical data are statistically analyzed, and the arrays composed of the influence values ​​and error rates corresponding to different wirings are quantified, and then each array is fitted through a linear regression equation model to obtain the variation curve between the influence value and the error rate corresponding to the chip wiring in the historical data, thereby providing a data basis for predicting the second error rate corresponding to the corresponding wiring in the chip to be tested according to the influence value corresponding to each wiring in the chip to be tested in the subsequent process, and because the sample corresponds to all chips, the sample data is larger, and the fitting curve is more consistent with the actual error rate of each wiring of the chip, thereby making the accuracy of the second error rate corresponding to each wiring obtained in the subsequent process higher.

[0052] Furthermore, the method for the historical data processing module to obtain the influence value of each wiring in the chip under test on the wiring failure rate of the protection circuit of the chip under test includes the following steps:

[0053] S4.1. Obtain the impact values ​​corresponding to different wirings in the chip to be tested;

[0054] S4.2, obtaining the actual error rate of wiring in the chip corresponding to different impact values ​​in different batches of chips with the same model as the chip to be tested within the first unit time in the historical data,

[0055] The average of the actual error rates of the wiring corresponding to the same impact value in different batches of chips is used as the first error rate of the wiring corresponding to the corresponding impact value in the chip to be tested.

[0056] The first error rate corresponding to the wiring with an impact value of r1 in the chip under test is recorded as

[0057] S4.3, according to the change curve Z=G(H) between the chip wiring error rate and the impact value, predict the second error rate d2 corresponding to the wiring with the impact value r1 in the chip to be tested, wherein d2=G(r1);

[0058] S4.4, obtain the influence value Qr1 of the wiring of the chip under test with an influence value r1 on the wiring failure rate of the protection circuit of the chip under test,

[0059] in, is the first bias coefficient, Represents the second bias coefficient.

[0060] In the process of obtaining the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested by the historical data processing module of the present invention, the second error rate d2 corresponding to the wiring with an influence value of r1 in the chip to be tested is a prediction result obtained based on the change curve Z=G(H) between the chip wiring error rate and the influence value. However, since in the process of obtaining Z=G(H), the samples are selected for all chips of all models in the historical data, and then when predicting the chip corresponding to a specific model, there may be a certain degree of deviation, which needs to be corrected. Then, the historical data processing module obtains the first error rate corresponding to the wiring with an influence value of r1 in the chip to be tested according to the chip data of the same model as the chip to be tested in the historical data, and is recorded as Then through the first error rate To calibrate the second error rate d2 in the prediction result, and then predict the final error rate result corresponding to the wiring with an impact value of r1 in the chip to be tested, that is, the impact value Qr1 of the wiring with an impact value of r1 in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested; set In order to use the form of partial weight coefficient With G(r1) to determine the value, the first bias coefficient The second bias coefficient The sum of is equal to 1, which will make The larger the value of G(r1), the larger the bias coefficient, making the final calibration result closer to The larger value of G(r1) is used to obtain the influence of the wiring with the worst impact value of r1 on the wiring failure rate of the protection circuit of the chip under test.

[0061] Furthermore, the method for predicting the wiring failure rate of the protection circuit in the chip to be tested by the wiring failure rate prediction module includes the following steps:

[0062] S5.1. Obtain the number of each wiring in the protection circuit of the chip to be tested and the influence value of the corresponding wiring on the wiring failure rate of the protection circuit of the chip to be tested.

[0063] The influence of the wiring numbered k on the wiring failure rate of the protection circuit of the chip under test is recorded as Q k ;

[0064] S5.2, predicting the wiring failure rate E of the protection circuit in the chip to be tested,

[0065] Wherein, k1 represents the total number of wirings in the protection circuit of the chip to be tested.

[0066] A wiring test method for a chip protection circuit, the method comprising the following steps:

[0067] S1. Obtain the model of the chip to be tested and the location of the wiring nodes in the corresponding protection circuit through the data acquisition module;

[0068] S2. Obtain the positions of the wiring nodes in the corresponding protection circuit of the chip under test obtained in the data acquisition module through the wiring node relationship analysis module, and analyze the interference values ​​of each wiring node in different wirings and the influence values ​​between different wirings;

[0069] S3, obtaining the analysis results obtained by the wiring node relationship analysis module through the historical data processing module, combining the historical data of the chip with the same model as the chip to be tested, and obtaining the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested;

[0070] S4. Obtain the processing result obtained by the historical data processing module through the wiring failure rate prediction module to predict the wiring failure rate of the protection circuit in the chip to be tested.

[0071] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: the present invention collects the model of the chip to be tested and the position of the wiring nodes in the corresponding protection circuit, analyzes the interference received by different wiring nodes during wiring, and then predicts the influence value between different wirings in the chip to be tested; and combines the relationship between the wiring influence value and the chip failure rate in the historical data to predict the failure rate of the protection circuit of the chip to be tested; different from the testing method of the chip protection circuit in the prior art, this method predicts the wiring failure rate in the chip by analyzing the relationship between each wiring and wiring node in the chip, and according to the failure rates corresponding to different wirings, it can quickly lock the wiring position where the fault has occurred and lock the area where the fault occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0073] Figure 1 It is a structural schematic diagram of a wiring test system for a chip protection circuit of the present invention;

[0074] Figure 2 It is a flow chart of a method for analyzing interference values ​​received by each wiring node in different wirings by a wiring node relationship analysis module in a wiring test system of a chip protection circuit of the present invention;

[0075] Figure 3 It is a flow chart of a method for a historical data processing module in a wiring test system of a chip protection circuit of the present invention to obtain an influence value of each wiring in a chip to be tested on a wiring failure rate of a chip protection circuit to be tested;

[0076] Figure 4 It is a flow chart of the wiring test method of the chip protection circuit of the present invention. DETAILED DESCRIPTION

[0077] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0078] See also Figure 1-Figure 4 The present invention provides a technical solution: a wiring test system for a chip protection circuit, comprising:

[0079] A data acquisition module, wherein the data acquisition module obtains the model of the chip to be tested and the location of the wiring nodes in the corresponding protection circuit;

[0080] A wiring node relationship analysis module, which obtains the positions of wiring nodes in the protection circuit corresponding to the chip under test obtained in the data acquisition module, and analyzes the interference values ​​of each wiring node in different wirings and the influence values ​​between different wirings;

[0081] A historical data processing module, wherein the historical data processing module obtains the analysis results obtained by the wiring node relationship analysis module, combines the historical data of the chip with the same model as the chip to be tested, and obtains the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested;

[0082] A wiring failure rate prediction module is used to obtain the processing result obtained by the historical data processing module and predict the wiring failure rate of the protection circuit in the chip to be tested.

[0083] After obtaining the model of the chip to be tested, the data acquisition module will obtain the size of the chip to be tested through the database and establish a proportional model.

[0084] At the same time, a plane rectangular coordinate system is established with the center point of the geometric model as the origin, a straight line passing through the origin and parallel to the longest side of the chip to be tested as the x-axis, and a straight line passing through the origin and parallel to the plane to which the chip to be tested belongs and perpendicular to the x-axis as the y-axis;

[0085] The positions of the wiring nodes in the corresponding protection circuit of the chip to be tested are obtained through the database, the obtained wiring nodes are numbered, and the wiring nodes corresponding to the numbers are marked at the corresponding coordinate points in the plane rectangular coordinate system.

[0086] The method for analyzing the interference value of each wiring node in different wirings by the wiring node relationship analysis module comprises the following steps:

[0087] S1.1, obtaining the corresponding coordinate points of the wiring nodes corresponding to each number in the plane rectangular coordinate system;

[0088] S1.2, select the wiring node corresponding to number i, obtain the wiring nodes corresponding to the other numbers within the first unit distance L0 with i as the center, and record the distances between the wiring node corresponding to number i and the wiring nodes corresponding to the other numbers respectively,

[0089] The distance between the wiring node corresponding to number i and the wiring node corresponding to number i1 is recorded as L i-i1 ;

[0090] S1.3, in order of the acquired distances from small to large, enter the distances between the wiring node corresponding to number i recorded in S1.2 and the wiring nodes corresponding to the remaining numbers into a blank set, to obtain the first set Ai corresponding to the wiring node corresponding to number i,

[0091] The value corresponding to the i2th element in Ai is recorded as Ai i2 ;

[0092] S1.4, obtain the interference value Bi of the wiring node corresponding to number i,

[0093] Said

[0094] Among them, Ai i3 Indicates the total number of elements in the set corresponding to Ai,

[0095] f(Ai i2 ) means Ai i2 The interference value generated by the wiring node with the corresponding number to the wiring node with the number i.

[0096] Get Ai i2 The interference value f(Ai) generated by the wiring node with the corresponding number to the wiring node with the number i i2 ) method comprises the following steps:

[0097] S1.4.1. Get the values ​​corresponding to the i2th element in Ai;

[0098] S1.4.2, determine the value corresponding to i2,

[0099] When i2=1, then it is determined that Ai i2 The interference value generated by the wiring node with the corresponding number to the wiring node with number i

[0100] When i2>1, the values ​​corresponding to the first i2-1 elements in Ai are further obtained;

[0101] S1.4.3. Connect the wiring nodes corresponding to the first i2 elements in Ai to the wiring nodes corresponding to number i.

[0102] Take any one of the wiring nodes corresponding to the first i2-1 elements in Ai and the line segment formed by the wiring node corresponding to number i as the first edge, and take the line segment formed by the wiring node corresponding to the i2th element in Ai and the wiring node corresponding to number i as the second edge, and obtain the minimum value of the angle formed by different first edges and second edges, recorded as θ,

[0103] Among the three wiring nodes corresponding to θ, except for the wiring node corresponding to the i2th element in Ai and the wiring node corresponding to the number i, the wiring node is denoted as c, and the number of the element corresponding to c in Ai is denoted as c1;

[0104] S1.4.4, compare θ with the first fault tolerance threshold θ1,

[0105] When θ≤θ1, it is determined that the wiring node corresponding to the i2th element in Ai is within the fault tolerance range corresponding to the wiring node c.

[0106] When θ>θ1, it is determined that the wiring node corresponding to the i2th element in Ai is not within the fault tolerance range corresponding to the wiring node c.

[0107] In this embodiment, if the first set A2 corresponding to the wiring node numbered 2 is equal to {0.1, 0.2},

[0108] The angle between the wiring node corresponding to 0.1 and the wiring node numbered 2 and the wiring node corresponding to 0.2 is 0 degrees, and the first fault tolerance threshold θ1 is equal to 5 degrees.

[0109] Because 0.1 corresponds to element number 1 in A2,

[0110] Then the interference value generated by the wiring node corresponding to number 0.1 to the wiring node corresponding to number 2 is

[0111] Because 0.2 corresponds to element number 2 in A2,

[0112] Therefore, we need to further obtain the value corresponding to the first 2-1=1 element in A2, which is 0.1.

[0113] The line segment formed by the wiring node corresponding to the first element in A2 and the wiring node corresponding to number 2 is used as the first edge, and the line segment formed by the wiring node corresponding to the second element in A2 and the wiring node corresponding to number 2 is used as the second edge, and the angles formed by different first edges and second edges are obtained.

[0114] That is, the angle between the wiring node corresponding to 0.1 and the wiring node numbered 2 and the wiring node corresponding to 0.2 is 0 degrees.

[0115] Because 0<5,

[0116] Therefore, the wiring node corresponding to the second element in A2 is within the fault tolerance range of the wiring node corresponding to the first element in A2.

[0117] Then f(0.2)=f(0.1)≈3.16.

[0118] The method for analyzing the influence values ​​between different wirings by the wiring node relationship analysis module comprises the following steps:

[0119] S2.1, obtain two wiring nodes corresponding to the two ends of each wiring, and record them as the first wiring node and the second wiring node;

[0120] S2.2, obtaining the interference value of the first node of each wiring, obtaining the interference value of the second node of each wiring,

[0121] The interference value of the first node in the jth wiring is recorded as The interference value of the second node in the jth wiring is recorded as

[0122] S2.3, obtain the influence value Rj of the j-th wiring on the rest of the wiring,

[0123] The historical data processing module obtains the error rates corresponding to the wirings corresponding to different impact values ​​in the historical data, and obtains a variation curve between the chip wiring error rate and the impact value.

[0124] The method for obtaining the change curve between the chip wiring error rate and the impact value by the historical data processing module comprises the following steps:

[0125] S3.1. Obtain the impact values ​​corresponding to the wiring errors in all chips in the historical data;

[0126] S3.2, respectively counting the ratios of the number of wiring errors corresponding to different impact values ​​to the total number of wirings corresponding to the corresponding impact values, and recording them in the form of an array [r, d], where r represents the impact value, and d represents the ratio of the number of wiring errors corresponding to the impact value r to the total number of wirings corresponding to the corresponding impact value;

[0127] S3.3, establish a first plane rectangular coordinate system, wherein the horizontal axis H of the first plane rectangular coordinate system represents the influence value corresponding to the wiring, and the vertical axis Z of the first plane rectangular coordinate system represents the ratio of the number of wiring errors corresponding to the influence value to the total number of wiring errors corresponding to the corresponding influence value;

[0128] S3.4. In the first plane rectangular coordinate system, mark the points corresponding to each array obtained in S3.2 respectively, and fit the points marked in the first plane rectangular coordinate system through the standard linear regression equation model prefabricated in the database to obtain the change curve Z=G(H) between the chip wiring error rate and the influence value.

[0129] The method for the historical data processing module to obtain the influence value of each wiring in the chip under test on the wiring failure rate of the protection circuit of the chip under test includes the following steps:

[0130] S4.1. Obtain the impact values ​​corresponding to different wirings in the chip to be tested;

[0131] S4.2, obtaining the actual error rate of wiring in the chip corresponding to different impact values ​​in different batches of chips with the same model as the chip to be tested within the first unit time in the historical data,

[0132] The average of the actual error rates of the wiring corresponding to the same impact value in different batches of chips is used as the first error rate of the wiring corresponding to the corresponding impact value in the chip to be tested.

[0133] The first error rate corresponding to the wiring with an impact value of r1 in the chip under test is recorded as

[0134] S4.3, according to the change curve Z=G(H) between the chip wiring error rate and the impact value, predict the second error rate d2 corresponding to the wiring with the impact value r1 in the chip to be tested, wherein d2=G(r1);

[0135] S4.4, obtain the influence value Qr1 of the wiring of the chip under test with an influence value r1 on the wiring failure rate of the protection circuit of the chip under test,

[0136] in, is the first bias coefficient, Represents the second bias coefficient.

[0137] In this embodiment, if the first error rate corresponding to the wiring with an impact value of 10 in the protection circuit of the chip to be tested is 0.02,

[0138] According to the variation curve Z=G(H) between the chip wiring error rate and the impact value, the predicted second error rate corresponding to the wiring with an impact value of 10 is 0.03.

[0139] Then the first bias coefficient is equal to

[0140] The second bias coefficient is equal to

[0141] Then, the influence value Q10 of the wiring with an influence value of 10 in the chip under test on the wiring failure rate of the protection circuit of the chip under test is obtained, Q10=0.4*0.02+0.6*0.03=0.026.

[0142] The method for predicting the wiring failure rate of the protection circuit in the chip to be tested by the wiring failure rate prediction module comprises the following steps:

[0143] S5.1. Obtain the number of each wiring in the protection circuit of the chip to be tested and the influence value of the corresponding wiring on the wiring failure rate of the protection circuit of the chip to be tested.

[0144] The influence of the wiring numbered k on the wiring failure rate of the protection circuit of the chip under test is recorded as Q k ;

[0145] S5.2, predicting the wiring failure rate E of the protection circuit in the chip to be tested,

[0146] Wherein, k1 represents the total number of wirings in the protection circuit of the chip to be tested.

[0147] A wiring test method for a chip protection circuit, the method comprising the following steps:

[0148] S1. Obtain the model of the chip to be tested and the location of the wiring nodes in the corresponding protection circuit through the data acquisition module;

[0149] S2. Obtain the positions of the wiring nodes in the corresponding protection circuit of the chip under test obtained in the data acquisition module through the wiring node relationship analysis module, and analyze the interference values ​​of each wiring node in different wirings and the influence values ​​between different wirings;

[0150] S3, obtaining the analysis results obtained by the wiring node relationship analysis module through the historical data processing module, combining the historical data of the chip with the same model as the chip to be tested, and obtaining the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested;

[0151] S4. Obtain the processing result obtained by the historical data processing module through the wiring failure rate prediction module to predict the wiring failure rate of the protection circuit in the chip to be tested.

[0152] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0153] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A wiring test system for a chip protection circuit, characterized in that: include: A data acquisition module, wherein the data acquisition module obtains the model of the chip to be tested and the location of the wiring nodes in the corresponding protection circuit; A wiring node relationship analysis module, which obtains the positions of wiring nodes in the protection circuit corresponding to the chip under test obtained in the data acquisition module, and analyzes the interference values ​​of each wiring node in different wirings and the influence values ​​between different wirings; A historical data processing module, wherein the historical data processing module obtains the analysis results obtained by the wiring node relationship analysis module, combines the historical data of the chip with the same model as the chip to be tested, and obtains the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested; A wiring failure rate prediction module, wherein the wiring failure rate prediction module obtains the processing result obtained by the historical data processing module and predicts the wiring failure rate of the protection circuit in the chip to be tested; After obtaining the model of the chip to be tested, the data acquisition module will obtain the size of the chip to be tested through the database and establish a proportional model. At the same time, a plane rectangular coordinate system is established with the center point of the geometric model as the origin, a straight line passing through the origin and parallel to the longest side of the chip to be tested as the x-axis, and a straight line passing through the origin and parallel to the plane to which the chip to be tested belongs and perpendicular to the x-axis as the y-axis; The positions of the wiring nodes in the corresponding protection circuit of the chip to be tested are obtained through the database, the obtained wiring nodes are numbered, and the wiring nodes corresponding to the numbers are marked at the corresponding coordinate points in the plane rectangular coordinate system; The method for analyzing the interference value of each wiring node in different wirings by the wiring node relationship analysis module comprises the following steps: S1.1, obtaining the corresponding coordinate points of the wiring nodes corresponding to each number in the plane rectangular coordinate system; S1.2, select the wiring node corresponding to number i, obtain the wiring nodes corresponding to the other numbers within the first unit distance L0 with i as the center, and record the distances between the wiring node corresponding to number i and the wiring nodes corresponding to the other numbers respectively, The distance between the wiring node corresponding to number i and the wiring node corresponding to number i1 is recorded as L i-i1 ; S1.3, in order of the acquired distances from the smallest to the largest, the distances between the wiring node corresponding to number i recorded in S1.2 and the wiring nodes corresponding to the remaining numbers are entered into a blank set, to obtain the first set Ai corresponding to the wiring node corresponding to number i, The value corresponding to the i2th element in Ai is recorded as Ai i2 ; S1.4, obtain the interference value Bi of the wiring node corresponding to number i, Said Among them, Ai i3 Indicates the total number of elements in the set corresponding to Ai, f(Ai i2 ) means Ai i2 The interference value generated by the wiring node with the corresponding number to the wiring node with the number i.

2. The wiring test system for chip protection circuit according to claim 1, characterized in that: Get Ai i2 The interference value f(Ai) generated by the wiring node with the corresponding number to the wiring node with the number i i2 ) method comprises the following steps: S1.4.

1. Get the values ​​corresponding to the i2th element in Ai; S1.4.2, determine the value corresponding to i2, When i2=1, then it is determined that Ai i2 The interference value generated by the wiring node with the corresponding number to the wiring node with number i When i2>1, the values ​​corresponding to the first i2-1 elements in Ai are further obtained; S1.4.

3. Connect the wiring nodes corresponding to the first i2 elements in Ai to the wiring nodes corresponding to number i. Take any one of the wiring nodes corresponding to the first i2-1 elements in Ai and the line segment formed by the wiring node corresponding to number i as the first edge, and take the line segment formed by the wiring node corresponding to the i2th element in Ai and the wiring node corresponding to number i as the second edge, and obtain the minimum value of the angle formed by different first edges and second edges, recorded as θ, Among the three wiring nodes corresponding to θ, except for the wiring node corresponding to the i2th element in Ai and the wiring node corresponding to the number i, the wiring node is denoted as c, and the number of the element corresponding to c in Ai is denoted as c1; S1.4.4, compare θ with the first fault tolerance threshold θ1, When θ≤θ1, it is determined that the wiring node corresponding to the i2th element in Ai is within the fault tolerance range corresponding to the wiring node c. When θ>θ1, it is determined that the wiring node corresponding to the i2th element in Ai is not within the fault tolerance range corresponding to the wiring node c.

3. The wiring test system for chip protection circuit according to claim 2, characterized in that: The method for analyzing the influence values ​​between different wirings by the wiring node relationship analysis module comprises the following steps: S2.1, obtain two wiring nodes corresponding to the two ends of each wiring, and record them as the first wiring node and the second wiring node; S2.2, obtaining the interference value of the first node of each wiring, obtaining the interference value of the second node of each wiring, The interference value of the first node in the jth wiring is recorded as The interference value of the second node in the jth wiring is recorded as S2.3, obtain the influence value Rj of the j-th wiring on the rest of the wiring, 4. The wiring test system for chip protection circuit according to claim 3, characterized in that: The historical data processing module obtains the error rates corresponding to the wirings corresponding to different impact values ​​in the historical data, and obtains a variation curve between the chip wiring error rate and the impact value. The method for obtaining the change curve between the chip wiring error rate and the impact value by the historical data processing module comprises the following steps: S3.

1. Obtain the impact values ​​corresponding to the wiring errors in all chips in the historical data; S3.2, respectively counting the ratios of the number of wiring errors corresponding to different impact values ​​to the total number of wirings corresponding to the corresponding impact values, and recording them in the form of an array [r, d], where r represents the impact value, and d represents the ratio of the number of wiring errors corresponding to the impact value r to the total number of wirings corresponding to the corresponding impact value; S3.3, establish a first plane rectangular coordinate system, wherein the horizontal axis H of the first plane rectangular coordinate system represents the influence value corresponding to the wiring, and the vertical axis Z of the first plane rectangular coordinate system represents the ratio of the number of wiring errors corresponding to the influence value to the total number of wiring errors corresponding to the corresponding influence value; S3.

4. In the first plane rectangular coordinate system, mark the points corresponding to each array obtained in S3.2 respectively, and fit the points marked in the first plane rectangular coordinate system through the standard linear regression equation model prefabricated in the database to obtain the change curve Z=G(H) between the chip wiring error rate and the influence value.

5. The wiring test system for chip protection circuit according to claim 4, characterized in that: The method for the historical data processing module to obtain the influence value of each wiring in the chip under test on the wiring failure rate of the protection circuit of the chip under test includes the following steps: S4.

1. Obtain the impact values ​​corresponding to different wirings in the chip to be tested; S4.2, obtaining the actual error rate of wiring in the chip corresponding to different impact values ​​in different batches of chips with the same model as the chip to be tested within the first unit time in the historical data, The average of the actual error rates of the wiring corresponding to the same impact value in different batches of chips is used as the first error rate of the wiring corresponding to the corresponding impact value in the chip to be tested. The first error rate corresponding to the wiring with an impact value of r1 in the chip under test is recorded as S4.3, according to the change curve Z=G(H) between the chip wiring error rate and the impact value, predict the second error rate d2 corresponding to the wiring with the impact value r1 in the chip to be tested, wherein d2=G(r1); S4.4, obtain the influence value Qr1 of the wiring of the chip under test with an influence value r1 on the wiring failure rate of the protection circuit of the chip under test, in, is the first bias coefficient, Represents the second bias coefficient.

6. The wiring test system for chip protection circuit according to claim 5, characterized in that: The method for predicting the wiring failure rate of the protection circuit in the chip to be tested by the wiring failure rate prediction module comprises the following steps: S5.

1. Obtain the number of each wiring in the protection circuit of the chip to be tested and the influence value of the corresponding wiring on the wiring failure rate of the protection circuit of the chip to be tested. The influence of the wiring numbered k on the wiring failure rate of the protection circuit of the chip under test is recorded as Q k ; S5.2, predicting the wiring failure rate E of the protection circuit in the chip to be tested, Wherein, k1 represents the total number of wirings in the protection circuit of the chip to be tested.

7. A wiring test method for a chip protection circuit using the wiring test system for a chip protection circuit according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: S1. Obtain the model of the chip to be tested and the location of the wiring nodes in the corresponding protection circuit through the data acquisition module; S2. Obtain the positions of the wiring nodes in the corresponding protection circuit of the chip under test obtained in the data acquisition module through the wiring node relationship analysis module, and analyze the interference values ​​of each wiring node in different wirings and the influence values ​​between different wirings; S3, obtaining the analysis results obtained by the wiring node relationship analysis module through the historical data processing module, combining the historical data of the chip with the same model as the chip to be tested, and obtaining the influence value of each wiring in the chip to be tested on the wiring failure rate of the protection circuit of the chip to be tested; S4. Obtain the processing result obtained by the historical data processing module through the wiring failure rate prediction module to predict the wiring failure rate of the protection circuit in the chip to be tested.

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