Frequency calibration system and method for frequency synthesizer

Abstract

This invention discloses a frequency calibration system and method for a frequency synthesizer, which can reduce frequency calibration time and avoid reducing calibration resolution, thereby ensuring the accuracy of frequency calibration results. The frequency calibration system includes a counting circuit, a sampling circuit, and a current mirror control module. The input of the counting circuit is connected to a crystal oscillator for counting the reference clock generated by the crystal oscillator. The first output of the counting circuit is connected to one end of the sampling circuit, which is a frequency divider sampling circuit used to divide and sample the frequency output by the voltage-controlled oscillator. The other end of the sampling circuit is connected to the second output of the counting circuit. The current mirror control module is used to adjust the control word for controlling the current mirror. The output of the current mirror control module is connected to the current mirror circuit, and the output of the current mirror circuit is connected to the voltage-controlled oscillator. The output of the voltage-controlled oscillator outputs the calibrated frequency. The frequency calibration method applies the above-mentioned frequency calibration system.

Description

Technical Field

[0001] This invention relates to the field of frequency synthesizer technology, specifically to a frequency calibration system and method for a frequency synthesizer. Background Technology

[0002] In wireless communication systems, frequency synthesizers are commonly used to provide wireless transceivers with high-resolution, low-phase-noise, and fast-stabilized local oscillator signals. A frequency synthesizer, also known as a phase-locked loop (PLL) synthesizer, is primarily based on a PLL architecture. This architecture achieves frequency calibration mainly through a combination of coarse and fine adjustments. Coarse adjustment refers to the VCO (voltage-controlled oscillator) frequency calibration process, while fine adjustment refers to the sub-band adjustment process before the closed-loop locking process. However, this adjustment method requires a relatively long time for frequency acquisition and locking. As the loop bandwidth of the frequency synthesizer increases and the closed-loop locking time decreases, the proportion of frequency calibration time in the overall locking time of the frequency synthesizer becomes increasingly larger, failing to meet the rapid calibration requirements of the frequency synthesizer.

[0003] Two other frequency calibration methods are provided in the prior art: the period comparison method and the count comparison method. The period comparison method refers to using a time-voltage converter to convert the signal period after VCO frequency division and the reference clock period TREF into voltage values, and then using a voltage comparator to compare the magnitude of these two voltage values. The frequency sub-band of the VCO is adjusted based on the comparison result. This calibration method has a short calibration time, which can solve the problem of the frequency calibration time occupying a long lock time of the frequency synthesizer. However, its minimum calibration resolution is limited by the reference frequency and has only been verified in integer frequency phase-locked loops. In addition, the main modules such as the time-voltage converter and voltage comparator in this structure are based on analog circuit design, which is susceptible to the influence of circuit mismatch, power supply and ground noise interference, resulting in the problem of reduced calibration resolution of the frequency synthesizer. The reduction in calibration resolution seriously affects the accuracy of the frequency calibration results.

[0004] The counting comparison method involves counting the VCO-divided signal and the reference clock signal within a fixed time interval, then comparing the count results to determine how to adjust the frequency sub-band. This adjustment primarily utilizes a binary search algorithm, where the number of sub-band searches is equal to the bit width of the current mirror array control word. During adjustment, the counting time for each search step is reduced by increasing the operating frequency of the counter in the calibration circuit, thus accelerating the overall calibration process. However, the number of searches in this method is determined by the bit width of the current mirror. With a larger bit width, the calibration time is longer. Furthermore, during calibration, even when the VCO frequency is very close to the frequency error threshold, the binary search algorithm must continue to be executed, resulting in a still lengthy calibration time. Summary of the Invention

[0005] To address the problem that existing frequency synthesizers have long frequency calibration times, failing to meet the requirements for rapid calibration while avoiding reduced calibration frequency resolution, this invention provides a frequency calibration system and method for a frequency synthesizer. This system can reduce frequency calibration time and avoid reducing calibration resolution, thereby ensuring the accuracy of frequency calibration results.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A frequency calibration system for a frequency synthesizer includes a counting circuit, a sampling circuit, and a current mirror control module. The counting circuit's input is connected to a crystal oscillator for counting a reference clock generated by the crystal oscillator; the counting circuit's first output is connected to the first input of the sampling circuit.

[0008] The sampling circuit is a frequency divider sampling circuit, which is used to divide and sample the frequency output by the voltage-controlled oscillator. The other input terminal of the sampling circuit is connected to the second output terminal of the counting circuit. The reference frequency count output by the second output terminal is obtained by logically inverting the reference frequency count output by the first output terminal.

[0009] The current mirror control module is used to adjust the control word for controlling the current mirror. The output terminal of the current mirror control module is connected to the current mirror circuit. The output terminal of the current mirror circuit is connected to the voltage-controlled oscillator. The output terminal of the voltage-controlled oscillator outputs the calibrated frequency fvco.

[0010] Its further feature is that,

[0011] The counting circuit includes a reference clock counter and a logic NOT gate. The input terminal of the reference clock counter is connected to one end of the crystal oscillator, and the other end of the crystal oscillator is grounded. The output terminal of the reference clock counter is connected to the input terminal of the logic NOT gate. The output terminal of the logic NOT gate is connected to the first input terminal of the second logic AND gate to the (n+1)th logic AND gate in the sampling circuit. The output terminal of the reference clock controller is connected to the second input terminal of the first logic AND gate in the sampling circuit.

[0012] The sampling circuit includes a first AND gate, n flip-flops, n parallel second AND gates up to the (n+1)th AND gate, a filter, and a subtractor, where n is an integer. The outputs of the first AND gates are connected to the inputs of the flip-flops, and the outputs of the flip-flops are connected one-to-one with the second inputs of the second AND gates. The outputs of the second AND gates are connected to one end of the filter, and the other end of the filter is connected to the first input of the subtractor. The second input of the subtractor receives the division ratio N.ps, and the output of the subtractor is connected to the second input of the first comparator in the current mirror control module.

[0013] The current mirror control module includes a first comparator, a sign determination unit, a minimum error detection algorithm unit, a binary search algorithm unit, a second comparator, a first switch unit, an ICO current mirror control bit adjuster, and a second switch unit. The second input terminal of the first comparator is connected to the output terminal of the subtractor. The first input terminal of the first comparator receives a critical value Δth. The output terminals of the first comparator and the sign determination unit are connected to one end of the first switch unit. The other end of the first switch unit is connected to the binary search algorithm unit, the minimum error detection algorithm unit, and the second comparator, respectively. The output terminals of the binary search algorithm unit, the minimum error detection algorithm unit, and the second comparator are all connected to one end of the ICO current mirror control bit adjuster. The other end of the ICO current mirror control bit adjuster is connected to the control terminal of the second switch unit. One end of the second switch unit is connected to the current mirror circuit, and the other end of the second switch unit is connected to the second input terminal of the first logic AND gate.

[0014] The first switching unit is a 2-to-1 selector;

[0015] The second switching unit includes m MOSFETs or relays, where m is a positive integer;

[0016] The current mirror circuit includes m MOS transistors M1 to Mm. The sources of each MOS transistor M1 to Mm are connected to a voltage source VDD. The gates of each MOS transistor M1 to Mm are connected together. The drains of each MOS transistor M1 to Mm are connected one-to-one with one end of each of the m MOS transistors or relays. The other ends of each of the m MOS transistors or relays are respectively connected to the input of the voltage-controlled oscillator. The output of the voltage-controlled oscillator is the second input of the first logic AND gate and outputs the calibrated frequency fvco.

[0017] A frequency calibration method for a frequency synthesizer, characterized in that the algorithm includes: S1, counting the reference clock signal generated by the crystal oscillator through a counting circuit and outputting a reference frequency count Q.2^k, inverting the reference frequency count Q.2^k output by the first output terminal to obtain a reference frequency count QN.2^k, and when the counting period of the counting circuit reaches a preset value k, the reference frequency count Q.2^k output by the first output terminal is 0;

[0018] S2. During the counting period of the counting circuit, the calibrated frequency fvco is sampled by the frequency divider sampling circuit. The sampled data is represented by the array D<15:1>, where the value of the sampled data D<15:1> is the number of cycles of the frequency fvco. The sampled data D<15:1> forms a digital control word.

[0019] S3. Based on the sampled data D<15:1> and the frequency division ratio N.ps, calculate the offset between the center frequency of the current frequency sub-band and the frequency error threshold;

[0020] S4. In the current mirror control module, firstly, the offset is compared with the preset critical value Δth. Then, based on the comparison result, it is determined whether the frequency error is close to the frequency error threshold. If so, the digital control word is adjusted according to the minimum error detection method to obtain the smallest bit control word in the digital control word. If not, the binary search algorithm is switched to adjust the digital control word.

[0021] S5. Control the current mirror circuit using the digital control word output by the current mirror control module.

[0022] Its further feature is that,

[0023] In step S1, the reference clock signal generated by the crystal oscillator is counted by the reference clock counter in the counting circuit. The reference frequency count Q.2^k is 1 by default. When the count value output by the counting circuit reaches the preset 2^k, the reference frequency count Q.2^k output by the first output terminal of the counting circuit is 0. When the next reference clock signal arrives, the output reference frequency count Q.2^k is reset to 1. Then, the reference frequency count Q.2^k is logically inverted by a logic NOT gate to obtain the reference frequency count QN.2^k. The reference frequency count QN.2^k is sent from the second output terminal of the counting circuit to the other input terminal of the sampling circuit.

[0024] In step S2, the reference frequency count Q.2^k is passed through the first logic AND gate A1 to obtain the reference frequency count QN.2^k. During the counting period, the reference frequency count Q.2^k output by the first output terminal is 1, and it is divided by 2^1, 2^2, 2^3 to 2^15 by the frequency divider. At the same time, the reference frequency count QN.2^k output by the second output terminal is 0, and the sampled data D<15:1> is 0. After the counting period is reached, the reference frequency count Q.2^k output by the first output terminal is 0, the frequency divider stops working, and the reference frequency count QN.2^k output by the second output terminal is 1. The corresponding second logic AND gate to the Nth logic AND gate... The AND gate is used to sample and obtain the sampled data D<15:1>. In step S3, according to the counting period, the corresponding sampled data D<15:k> is subtracted from the frequency division ratio N.ps by a subtractor. Specifically, when the counting period is 1, i.e., k=1, the sampled data D<15:1> is subtracted from the frequency division ratio N.ps; when the counting period is 4, i.e., k=2, the sampled data D<15:2> is subtracted from the frequency division ratio N.ps, and so on. When the counting period is 2^k, i.e., the counting period of the reference clock is 2^k, the sampled data D<15:k> is subtracted from the frequency division ratio N.ps to obtain the remainder Δd. The remainder Δd represents the target frequency offset.

[0025] In step S4, the residual value Δd is compared with the critical value Δth by the first comparator. Based on the comparison result, it is determined whether the frequency error is close to the frequency error threshold. The specific determination steps include: S41. If Δd>Δth, it means that the current frequency sub-band is significantly different from the target frequency. The two-to-one selector in the switching unit is used to switch to the binary search algorithm unit.

[0026] S42. The digital control word is calibrated using the binary search algorithm in the binary search algorithm unit. The specific calibration method is as follows: the highest bit to the lowest bit of the sampling data output by the sampling unit is traversed by binary search to realize the sequential calibration of the digital control word; at the same time, the value of the control bit that has been calibrated by binary search is saved until all calibrations are completed, which is the value of the optimal sub-band. If the binary search method is terminated early and the minimum error detection is entered, the remaining control words except for the smallest control word will retain the value of the current sub-band.

[0027] S43. If Δd < Δth, it indicates that the current sub-band frequency is close to the target frequency and the current sub-band frequency is close to the frequency error threshold. The minimum error detection algorithm unit is connected to the system through the two-to-one selector in the switching unit. The remaining value Δd at this time is stored in the database Δd1. At the same time, the first comparator and the reference clock counter are cleared and reset to prepare for the next comparison.

[0028] S44. The digital control word is calibrated using the minimum error detection algorithm;

[0029] S45. The current mirror control bit adjuster adjusts the control bit of the digital control word according to the calibration result to obtain the minimum control word bit, and sets k to 0 at the same time.

[0030] S46. Then, the current mirror circuit is controlled using the smallest control word.

[0031] S47. The current mirror control position adjuster adjusts the control position of the digital control word according to the calibration result;

[0032] S48. The current mirror circuit is controlled by the adjusted digital control word.

[0033] In step S43, after obtaining the smallest bit of the digital control word, a final frequency sampling calibration is required. The final residual value Δd is stored in the database Δd2. The data stored in Δd2 is compared with the data in Δd1, and the minimum value in the comparison result is obtained. This minimum value is the most suitable current frequency sub-band.

[0034] The above-described structure of the present invention can achieve the following beneficial effects: The present application uses a counting circuit to count the reference clock signal output by the crystal oscillator, and then uses a frequency divider sampling circuit to perform frequency divider sampling on the frequency QN.2^k. The sampling data of the frequency divider sampling is used to calculate the offset between the center frequency of the current frequency sub-band and the frequency error threshold, so that the subsequent current mirror control module can adjust the digital control word according to the offset, thereby realizing frequency calibration.

[0035] The current mirror control module of this application mainly selects the specific mode of digital control word control by comparing the aforementioned offset with a preset critical value. When the offset differs significantly from the critical value Δth, a binary search algorithm is used to adjust the digital control word. When the calibration frequency is very close to the target frequency (i.e., the difference between the residual value Δd and the critical value Δth is small), the minimum error detection method is used to adjust and obtain the smallest control word for controlling the current mirror circuit. It can be seen that this comparison and selection method is beneficial to end the binary search algorithm early and enter the minimum error detection algorithm to adjust the digital control word. The minimum error detection algorithm can directly obtain the smallest control word in the digital control word to control the current mirror circuit, that is, directly enter the final precise calibration stage, thereby greatly saving calibration time.

[0036] Furthermore, to avoid reducing the calibration frequency resolution, a larger threshold value Δth is set, which is more conducive to entering the minimum error detection stage earlier. At this time, it is only necessary to adjust the minimum error detection method from controlling only the smallest bit control word to controlling the smallest two bits control words. That is, increase the number of times the minimum error detection method calibrates the frequency. At the same time, compare the residual values ​​Δd1 and Δd2 of the two minimum control word calibrations, and obtain the minimum value in the comparison results. This minimum value is the most suitable current frequency sub-band. The determination of the most suitable current frequency sub-band ensures the accuracy of the calibration results. Attached Figure Description

[0037] Figure 1 This is a circuit diagram of the counting circuit of the present invention;

[0038] Figure 2 This is a circuit diagram of the sampling circuit, current mirror control module, and current mirror circuit of the present invention.

[0039] Figure 3 This is a circuit diagram of the symbol determination unit of the present invention;

[0040] Figure 4 This is a flowchart of the calibration algorithm of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and the above-mentioned drawings of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products or devices.

[0042] To address the issue of long frequency calibration times in existing frequency synthesizers, which fail to meet the requirements for rapid calibration while simultaneously reducing calibration resolution, this application provides a frequency calibration system for a frequency synthesizer in one specific embodiment. The system includes a counting circuit 1, a sampling circuit 2, and a current mirror control module 3. The input of the counting circuit 1 is connected to a crystal oscillator 4 for counting the reference clock generated by the crystal oscillator 4. The first output of the counting circuit 1 is connected to one input of the sampling circuit 2, and the second output of the counting circuit 1 is connected to the other input of the sampling circuit 2. The specific circuit structure of the counting circuit 1 includes a reference clock counter 11 and a NOT gate 12. The input of the reference clock counter 11 is connected to one end of the crystal oscillator 4, and the other end of the crystal oscillator 4 is grounded. The output of the reference clock counter 11 is connected to the input of the NOT gate 12 and the first inputs of the first AND gates A2 to A16 (k+1) in the sampling circuit 2. The output of the NOT gate 12 is connected to the first input of the second AND gate 21 in the sampling circuit.

[0043] Sampling circuit 2 is a frequency divider sampling circuit used to perform multiple frequency divider samplings on the VCO output frequency. The other end of sampling circuit 2 is connected to the input terminal of current mirror control module 3. The specific circuit structure of the sampling circuit is as follows: the sampling circuit includes a first logic AND gate A1, n flip-flops T1~Tn, a second logic AND gate A2~the (n+1)th logic AND gate A16, a filter 23, and a subtractor 24, where n is an integer. In this embodiment, the value of n is 15. The output terminal of the first logic AND gate A1 is connected to the input terminals of flip-flops T1~Tk respectively. The output terminals of flip-flops T1~Tn are connected one-to-one with the second input terminals of the second logic AND gates A2~the (n+1)th logic AND gate A16. The output terminal of the second logic AND gate is connected to one end of the filter, and the other end of the filter is connected to the first input terminal of the subtractor. The second input terminal of the subtractor inputs the frequency division ratio N.ps. The output terminal of the subtractor is connected to the second input terminal of the first comparator and the input terminal of the sign judgment unit in the current mirror control module respectively.

[0044] The current mirror control module 3 is used to generate control words to control the current mirror. The output terminal of the current mirror control module 3 is connected to the current mirror circuit 5, and the output terminal of the current mirror circuit 5 is connected to the voltage-controlled oscillator and outputs the calibrated frequency fvco. In this embodiment, the specific circuit structure of the current mirror control module is as follows: the current mirror control module 3 includes a first comparator 31, a sign determination unit 32, a minimum error detection algorithm unit 33, a binary search algorithm unit 34, a second comparator 35, a first switching unit 36, an ICO current mirror control bit adjuster 37, and a second switching unit 38. The positive input terminal of the first comparator 31 is connected to the output terminal of the subtractor 23, and the inverting input terminal of the first comparator 31 receives the critical value Δth. The output terminals of the first comparator 31 and the sign determination unit 32 are connected to one end of the first switching unit 36, and the other end of the first switching unit 36 ​​is connected to the other end of the first switching unit 38. One end is connected to the binary search algorithm unit 34, the minimum error detection algorithm unit 33, and the second comparator 35 respectively. The outputs of the binary search algorithm unit 34, the minimum error detection algorithm unit 33, and the second comparator 35 are all connected to one end of the ICO current mirror control bit adjuster 37. The other end of the ICO current mirror control bit adjuster 37 is connected to the control terminal of the second switching unit 38. One end of the second switching unit 38 is connected to the current mirror circuit 5, and the other end of the second switching unit 38 is connected to the input terminal of the voltage-controlled oscillator 6. The output terminal of the voltage-controlled oscillator 6 is connected to the second input terminal of the first logic AND gate A1 and outputs the calibrated frequency fvco. In this embodiment, the first switching unit is a 2-to-1 selector, and the second switching unit is m parallel MOS transistors.

[0045] In this embodiment, the sign determination unit 32 includes a NAND gate 321, two AND gates 322, and a NOR gate 323. The input terminal of the NAND gate 321 is connected to the output terminal of the filter, the frequency division ratio, and the first input terminal of the two AND gates 322, respectively. That is, the input terminal of the NAND gate 321 is respectively input to A=D.<n+k> B=N <n> ，N <n>The most significant bit of the division ratio N.ps is the binary representation of the division ratio, where N represents the division ratio and ps indicates that the divider uses a multi-mode divider. The output of NAND gate 321 is connected to the second input of AND gate 322, and the output of AND gate 322 is connected to the input of NOR gate 323, outputting Y1 and Y3 respectively. The output of NOR gate 323 outputs Y2. When A > B, Y1 outputs 1 (Y1=1); when A = B, Y2 outputs 1 (Y2=1); and when A < B, Y3 outputs 1 (Y3=1). In this application, a larger k indicates a longer sampling period. Considering that when the calibration circuit is first started, the current frequency sub-band may differ significantly from the frequency error threshold, a longer sampling period is used and the difference is ignored... <k:1>The sampled data, through a sign determination circuit, compares D<15:k+1> with the frequency division ratio N.ps, thus avoiding the problem of incorrect control word direction in the binary division method. The comparison circuit is as follows: Figure 3 As shown, first, the highest bit is processed. If the (n+k)th bit sampled by the VCO (i.e., D)<n+k> The highest score N <n>If the value is greater, Y1 outputs 1, and the sign is positive; otherwise, Y3 outputs 1, and the sign is negative. If the two bits are equal, the next higher bit is compared.

[0046] The current mirror circuit includes m MOSFETs M1 to Mm, where m is a positive integer. The sources of MOSFETs M1 to Mm are all connected to the voltage source VDD. The gates of MOSFETs M1 to Mm are connected together. The drains of MOSFETs M1 to Mn are connected one-to-one with one end of each of the m MOSFETs or relays. The other ends of the m MOSFETs or relays are respectively connected to the second input of the first logic AND gate and output the calibrated frequency fvco.

[0047] Traditional accumulation counting methods require multiple full adders and flip-flops, involving a large number of gate circuits. Furthermore, the flip-flops are synchronously clock-triggered, resulting in high power consumption. The multiple frequency divider sampling method used in this invention only requires flip-flops connected in a frequency divider structure and is asynchronously clock-triggered. Therefore, the sampling circuit of this application reduces the investment in components, has a simpler structure, and greatly reduces power consumption and cost.

[0048] The frequency of the frequency synthesizer is calibrated using the aforementioned frequency calibration system. The specific calibration steps include: S1. The reference clock signal generated by the crystal oscillator 4 is counted using the reference clock counter 11 in the counting circuit 1. The output of the reference clock counter 11 (i.e., the first output of the counting circuit) outputs a reference frequency count Q.2^k, which is defaulted to 1 (2^k represents 2k, and Q.2^k indicates that the counting period output by the first output is 2 to the power of k of the crystal oscillator period). When the count value of the counting circuit reaches the preset 2^k, the output reference frequency count Q.2^k is 0, where Q represents the counter output, 2^k represents the number of counting cycles of the reference clock, and QN represents the inverted counter output. When the next reference clock signal arrives, the output reference frequency count Q.2^k is reset to 1; then, the reference frequency count Q.2^k is logically inverted using a NOT gate to obtain the reference frequency count QN.2^k.

[0049] S2. When the counting period of the counting circuit reaches the preset value k, the reference frequency count Q.2^k outputs 0. The reference frequency count QN.2^k is sampled by a frequency divider sampling circuit. The sampled value is represented by the array D<15:1>, where D<15:1> refers to the number of cycles of the current frequency fvco within the sampling period, represented in binary. The sampled data D<15:1> is the number of cycles of frequency fvco. The array D<15:1> represents arrays D15~D1. Specifically, in step S2, after the reference frequency count Q.2^k passes through the first logic AND gate A1, it is divided by 2^1, 2^2, 2^3 to 2^15 by flip-flops within the counting period. When the counting period is reached, the output reference frequency count Q.2^k is 0, and all flip-flops stop working. At the same time, the reference frequency count QN.2^k is 1, and the corresponding second AND gate to the Nth logic AND gate are sampled to obtain the sampled data D<15:1>.

[0050] S3. Based on the sampled data and the division ratio N.ps, calculate the offset between the center frequency of the current frequency sub-band and the frequency error threshold. In this step S3, according to the counting period, the corresponding sampled data D<15:1>~D<15:k> are subtracted from the division ratio N.ps by a subtractor. Specifically, when the counting period is 1, i.e., k=1, the sampled data D<15:1> is subtracted from the division ratio N.ps; when the counting period is 4, i.e., k=2, the sampled data D<15:2> is subtracted from the division ratio N.ps, and so on. When the counting period is 2^k, i.e., the counting period of the reference clock is 2^k, the sampled data D<15:k> is subtracted from the division ratio N.ps to obtain the remainder Δd, which represents the offset.

[0051] S4. The residual Δd is compared with the critical value Δth by the first comparator. Based on the comparison result, it is determined whether the frequency error is close to the frequency error threshold. The specific judgment steps include: S41. If Δd>Δth, it means that the current frequency sub-band is significantly different from the target frequency. The two-to-one selector in the switching unit is used to switch to the binary search algorithm unit.

[0052] S42. The digital control word is calibrated using the binary search algorithm in the binary search algorithm unit. The specific calibration method is as follows: the highest bit to the lowest bit of the sampling data output by the sampling unit is traversed by binary search to realize the sequential calibration of the digital control word; the value of the control bit that has been calibrated by binary search is saved until all calibrations are completed, which is the value of the optimal sub-band. If the binary search method is terminated early and the minimum error detection is entered, the remaining control words except for the smallest control word will retain the value of the current sub-band.

[0053] S43. If Δd < Δth, it indicates that the current sub-band frequency is close to the target frequency and is nearing the frequency error threshold. The minimum error detection algorithm unit is connected to the system via a two-to-one selector in the switching unit. The remaining value Δd is stored in the database Δd1, and the first comparator and reference clock counter are reset to prepare for the next comparison. After obtaining the smallest control word in the digital control word, a final frequency sampling calibration is performed. The final remaining value Δd is stored in the database Δd2. The data stored in Δd2 is compared with the data in Δd1, and the minimum value in the comparison result is obtained. This minimum value is the most suitable frequency sub-band at present.

[0054] S44. The digital control word is calibrated using the minimum error detection algorithm;

[0055] S45. The current mirror control bit adjuster adjusts the control bit of the digital control word according to the calibration result to obtain the minimum control word bit, and sets k to 0 at the same time.

[0056] S46. Then, the current mirror circuit is controlled using the smallest control word.

[0057] S47. The current mirror control position adjuster adjusts the control position of the digital control word according to the calibration result;

[0058] S48. The current mirror circuit is controlled by the adjusted digital control word.

[0059] In the calibration process, when the calibration frequency is very close to the target frequency, the present invention adds a first comparator for comparison. Based on the comparison result, it determines whether the current calibration frequency is close to the target frequency. If they are close, the remaining unnecessary calibration process can be skipped directly. The error values ​​of the two minimum frequencies are compared to select the most suitable sub-band. That is, the current binary search algorithm is skipped directly and the final accurate calibration stage is entered, which greatly saves calibration time.

[0060] In addition, this application can flexibly adjust the sampling period of the sampling circuit by adjusting the k value. The adjustment of the calibration time and calibration accuracy of the sampling circuit is mainly achieved by adjusting the sampling period. Therefore, the flexible adjustment of the sampling period is conducive to flexibly adjusting the calibration time and sampling accuracy, thereby obtaining a suitable calibration time and higher sampling accuracy.

[0061] The above are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of the invention should be considered to be included within the scope of protection of the invention.< / n> < / n> < / n>

Claims

1. A frequency calibration system for a frequency synthesizer comprising a counting circuit, a sampling circuit, a current mirror control module, characterized in that, The input terminal of the counting circuit is connected to a crystal oscillator for counting the reference clock generated by the crystal oscillator; the first output terminal of the counting circuit is connected to the first input terminal of the sampling circuit. The sampling circuit is a multi-frequency divider sampling circuit, which is used to divide and sample the frequency output by the voltage-controlled oscillator. The other input terminal of the sampling circuit is connected to the second output terminal of the counting circuit. The reference frequency count output by the second output terminal is obtained by logically inverting the reference frequency count output by the first output terminal. The current mirror control module is used to adjust the control word for controlling the current mirror. The output terminal of the current mirror control module is connected to the current mirror circuit. The output terminal of the current mirror circuit is connected to the voltage-controlled oscillator. The output terminal of the voltage-controlled oscillator outputs the calibrated frequency. The counting circuit includes a reference clock counter and a logic NOT gate. The input terminal of the reference clock counter is connected to one end of the crystal oscillator, and the other end of the crystal oscillator is grounded. The output terminal of the reference clock counter is connected to the input terminal of the logic NOT gate. The output terminal of the logic NOT gate is connected to the first input terminal of the second logic AND gate to the (n+1)th logic AND gate in the sampling circuit. The output terminal of the reference clock controller is connected to the second input terminal of the first logic AND gate in the sampling circuit. The sampling circuit includes a first AND gate, n flip-flops, n parallel second AND gates up to the (n+1)th AND gate, a filter, and a subtractor, where n is a positive integer. The outputs of the first AND gates are connected to the inputs of the flip-flops, and the outputs of the flip-flops are connected one-to-one with the second inputs of the second AND gates. The outputs of the second AND gates are connected to one end of the filter, and the other end of the filter is connected to the first input of the subtractor. The second input of the subtractor receives the division ratio N.ps, and the output of the subtractor is connected to the second input of the first comparator in the current mirror control module. The current mirror control module includes a first comparator, a sign determination unit, a minimum error detection algorithm unit, a binary search algorithm unit, a second comparator, a first switch unit, an ICO current mirror control position adjuster, and a second switch unit. The second input terminal of the first comparator is connected to the output terminal of the subtractor. The first input terminal of the first comparator receives a critical value Δth. The output terminals of the first comparator and the sign determination unit are connected to one end of the first switch unit. The other end of the first switch unit is connected to the binary search algorithm unit, the minimum error detection algorithm unit, and the second comparator, respectively. The output terminals of the binary search algorithm unit, the minimum error detection algorithm unit, and the second comparator are all connected to one end of the ICO current mirror control position adjuster. The other end of the ICO current mirror control position adjuster is connected to the control terminal of the second switch unit. One end of the second switch unit is connected to the current mirror circuit, and the other end of the second switch unit is connected to the input terminal of the voltage-controlled oscillator. The first switching unit is a 2-to-1 selector; the second switching unit includes m MOSFETs or relays, where m is a positive integer; The current mirror circuit includes m MOS transistors M1 to Mm, where m is a positive integer. The sources of each MOS transistor M1 to Mm are connected to a voltage source VDD. The gates of each MOS transistor M1 to Mm are connected together. The drains of each MOS transistor M1 to Mm are connected one-to-one with one end of each of the m MOS transistors or relays. The other ends of each of the m MOS transistors or relays are respectively connected to the input terminals of the voltage-controlled oscillator. The output terminals of the voltage-controlled oscillator are respectively connected to the first input terminal of the first logic AND gate and output the calibrated frequency fvco.

2. A frequency calibration method, which applies the frequency calibration system of the frequency synthesizer according to claim 1, characterized in that, The method includes: S1, counting the reference clock signal generated by the crystal oscillator through a counting circuit and outputting a reference frequency count Q.2^k; inverting the output reference frequency count Q.2^k to obtain a reference frequency count QN.2^k; when the counting period of the counting circuit reaches a preset value k, the reference frequency count Q.2^k output by the first output terminal of the counting circuit is 0. S2. During the counting period of the counting circuit, the calibrated frequency fvco is sampled by the frequency divider sampling circuit. The sampled data is represented by the array D<15:1>, where the value of the sampled data D<15:1> is the number of cycles of the frequency fvco. The sampled data D<15:1> forms a digital control word. S3. Based on the sampled data D<15:1> and the frequency division ratio N.ps, calculate the offset between the center frequency of the current frequency sub-band and the frequency error threshold; S4. In the current mirror control module, firstly, the offset is compared with the preset critical value Δth. Then, based on the comparison result, it is determined whether the frequency error is close to the frequency error threshold. If so, the digital control word is adjusted according to the minimum error detection method to obtain the smallest bit control word in the digital control word. If not, the binary search algorithm is switched to adjust the digital control word. S5. Control the current mirror circuit using the digital control word output by the current mirror control module.

3. The frequency calibration method according to claim 2, characterized in that, In step S1, the reference clock signal generated by the crystal oscillator is counted by the reference clock counter in the counting circuit. The reference frequency count Q.2^k is 1 by default. When the count value output by the counting circuit reaches the preset 2^k, the reference frequency count Q.2^k output by the first output terminal of the counting circuit is 0. When the next reference clock signal arrives, the output reference frequency count Q.2^k is reset to 1. Then, the reference frequency count Q.2^k is logically inverted by a logic NOT gate to obtain the reference frequency count QN.2^k. The reference frequency count QN.2^k is sent from the second output terminal of the counting circuit to the other input terminal of the sampling circuit.

4. The frequency calibration method of claim 3, wherein, In step S2, the reference frequency count Q.2^k is passed through the first logic AND gate A1 to obtain the reference frequency count QN.2^k. During the counting period, the reference frequency count Q.2^k output by the first output terminal is 1, and it is divided by 2^1, 2^2, 2^3 to 2^15 by the frequency divider. At the same time, the reference frequency count QN.2^k output by the second output terminal is 0, and the sampled data D<15:1> is 0. After the counting period is reached, the reference frequency count Q.2^k output by the first output terminal is 0, the frequency divider stops working, and the reference frequency count QN.2^k output by the second output terminal is 1. The corresponding second logic AND gate to the Nth logic AND gate... The sampling is performed using an AND gate to obtain the sampled data D<15:1>. In step S3, according to the counting period, the corresponding sampled data D<15:k> is subtracted from the division ratio N.ps using a subtractor. Specifically, when the counting period is 1 (k=1), the sampled data D<15:1> is subtracted from the division ratio N.ps; when the counting period is 4 (k=2), the sampled data D<15:2> is subtracted from the division ratio N.ps, and so on. When the counting period is 2^k (i.e., the counting period of the reference clock is 2^k), the sampled data D<15:k> is subtracted from the division ratio N.ps to obtain the remainder Δd, which represents the frequency offset.

5. The frequency calibration method of claim 4, wherein, In step S4, the residual value Δd is compared with the critical value Δth by the first comparator. Based on the comparison result, it is determined whether the frequency error is close to the frequency error threshold. The specific determination steps include: S41. If Δd>Δth, it means that the current frequency sub-band is significantly different from the target frequency. The two-to-one selector in the switching unit is used to switch to the binary search algorithm unit. S42. The digital control word is calibrated using the binary search algorithm in the binary search algorithm unit. The specific calibration method is as follows: the highest bit to the lowest bit of the sampling data output by the sampling unit is traversed by binary search to realize the sequential calibration of the digital control word; at the same time, the value of the control bit that has been calibrated by binary search is saved until all calibrations are completed, which is the value of the optimal sub-band. If the binary search method is terminated early and the minimum error detection is entered, the remaining control words except for the smallest control word will retain the value of the current sub-band. S43. If Δd < Δth, it indicates that the current sub-band frequency is close to the target frequency and the current sub-band frequency is close to the frequency error threshold. The minimum error detection algorithm unit is connected to the system through the two-to-one selector in the switching unit. The remaining value Δd at this time is stored in the database Δd1. At the same time, the first comparator and the reference clock counter are cleared and reset to prepare for the next comparison. S44. The digital control word is calibrated using the minimum error detection algorithm; S45. The current mirror control bit adjuster adjusts the control bit of the digital control word according to the calibration result to obtain the minimum control word bit, and sets k to 0 at the same time. S46. Then, the current mirror circuit is controlled using the smallest control word. S47. The current mirror control position adjuster adjusts the control position of the digital control word according to the calibration result; S48. The current mirror circuit is controlled by the adjusted digital control word. In step S43, after obtaining the smallest bit of the digital control word, a final frequency sampling calibration is required. The final residual value Δd is stored in the database Δd2. The data stored in Δd2 is compared with the data in Δd1, and the minimum value in the comparison result is obtained. This minimum value is the most suitable current frequency sub-band.

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