A digital signal processor (DSP) assembler transplantation method based on processor architecture description

Abstract

This invention discloses a method for porting a digital signal processor (DSP) assembler based on a processor architecture description, comprising the following steps: S1. Based on the processor architecture description, a lexical analysis and syntax analysis part of the assembler is constructed to realize the parsing of special assembly instructions; S2. Taking the parsed instruction data or instruction binary code as input, dynamic encoding and decoding of instructions are implemented according to the instruction definition, thereby realizing the conversion between the object file and the assembly file. This DSP assembler porting method further improves the performance of the assembler and automates the porting process, adapting it to the digital signal processor architecture. It also provides support for single instruction multiple data, very long instruction words, and instruction validity checks. While ensuring that the program execution result meets expectations, it greatly reduces the number of clock cycles required for execution, possesses universality, and meets the needs of rapid processor architecture updates.

Description

Technical Field

[0001] This invention relates to the field of digital signal porting technology, specifically to a method for porting a digital signal processor (DSP) assembler based on a processor architecture description. Background Technology

[0002] DSPs are primarily used for error detection, as well as filtering and compressing analog signals in transmission. It is a type of signal processing performed by a digital signal processor or similar device. DSPs are characterized by high performance and low power consumption, and can execute DSP-specific processing algorithms. Typically, a DSP first converts an analog signal into a digital signal, and then applies signal processing techniques and algorithms. For example, when processing audio signals, DSPs help reduce noise and distortion. Some applications of DSPs include audio signal processing, digital image processing, speech recognition, and biomedicine.

[0003] Traditional toolchain porting uses a manual porting method, which requires modification of a large number of data structures and functions during the porting process. The development cycle is long and very complex, making it difficult to meet the needs of rapid processor architecture updates while ensuring tool availability. This invention provides a method for porting digital signal processor (DSP) assemblers based on processor architecture description. Summary of the Invention

[0004] The purpose of this invention is to provide a method for porting a digital signal processor (DSP) assembler based on a processor architecture description, in order to solve the problems mentioned in the background art, which are caused by the traditional toolchain porting method using manual porting, which has a long development cycle and complex structure, making it difficult to ensure tool availability and rapid updates of processor architecture.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for porting a digital signal processor (DSP) assembler based on processor architecture description, wherein S1. Based on the processor architecture description, the lexical analysis and syntax analysis parts of the assembler are constructed to realize the parsing of special assembly instructions;

[0007] S2. Taking the parsed instruction data or instruction binary code as input, and implementing dynamic encoding and decoding of instructions according to the instruction definition, thereby realizing the conversion between object files and assembly files;

[0008] S3. Optimizes assembler functionality and performance, providing support for Very Long Instruction Word, Single Instruction Multiple Data, and instruction validity checking;

[0009] In step S1, the construction of the assembler's lexical analysis and syntax analysis parts includes the following steps:

[0010] a. The lexical analysis part of the assembler is constructed using Lex files, which decompose the input assembly instruction stream into different categories of labels through the declaration, conversion rules, and auxiliary functions of the Lex file;

[0011] b. In order to further distinguish between opcodes, registers and symbols, string splitting and priority matching methods are also required to avoid mismatches of regular expressions. In the S assembly instruction format, spaces are used to separate instruction opcodes and operands, and labels always end with a colon.

[0012] In step b, the string splitting and priority matching methods specifically include the following:

[0013] a1. Use the first space of the assembly instruction as the delimiter to split the string. If the first string obtained by splitting contains a colon, then proceed to label matching; otherwise, proceed to opcode matching.

[0014] b1. If the string to be matched is located in the second string obtained by splitting, then proceed to the symbol matching in the operands;

[0015] c1. If the sign of the operand to be entered matches, an exact comparison of names should first be performed in the register set. If a match is found, the sign is the register name; otherwise, the sign is a sign or immediate type.

[0016] In step S2, the instruction definition implements dynamic encoding and decoding of instructions, including dynamic instruction encoding and disassembly.

[0017] Step S3 involves optimizing the assembler's functionality and performance, including the following steps:

[0018] a2. Add corresponding data types and structures to provide vector instructions to support SIMD;

[0019] b2. Add relevant descriptions to the processor architecture file to provide the assembler with support for VLIW;

[0020] C2. Perform a validity check on the data dependencies between instructions.

[0021] Compared with the prior art, the beneficial effects of the present invention are:

[0022] This DSP assembler porting method further improves the assembler's performance and adapts it to the digital signal processor architecture. It also provides support for single instruction multiple data, very long instruction word, and instruction validity checks. While ensuring that the program execution results meet expectations, it greatly reduces the number of clock cycles required for execution. The development cycle is short and it has universality, meeting the needs of rapid processor architecture updates. At the same time, the assembler porting process is automated, avoiding manual operations involving large amounts of data. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating the overall workflow of this invention.

[0024] Figure 2 This is a diagram of the assembler architecture in this invention;

[0025] Figure 3 This is a flowchart of the lexical analysis process in this invention;

[0026] Figure 4 This is a schematic diagram of the vector instruction data composition in this invention;

[0027] Figure 5 This is the instruction-data dependency graph in this invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Example

[0030] Please see Figure 1-5 The present invention provides a technical solution:

[0031] A method for porting a digital signal processor (DSP) assembler based on a processor architecture description includes the following steps:

[0032] S1. See also Figure 2 Based on the processor architecture description, the lexical analysis and syntax analysis parts of the assembler were constructed to realize the parsing of special assembly instructions;

[0033] S2. Taking the parsed instruction data or instruction binary code as input, and implementing dynamic encoding and decoding of instructions according to the instruction definition, thereby realizing the conversion between object files and assembly files;

[0034] S3. Optimizes assembler functionality and performance, providing support for Very Long Instruction Word, Single Instruction Multiple Data, and instruction validity checking;

[0035] For further explanation, in step S1, please refer to... Figure 3 The construction of the assembler's lexical and syntax analysis parts includes the following steps:

[0036] a. The lexical analysis part of the assembler is constructed using Lex files, which decompose the input assembly instruction stream into different categories of labels through the declaration, conversion rules, and auxiliary functions of the Lex file;

[0037] It should be noted that Lex declarations, conversion rules, and auxiliary functions are used to define the opcodes, numbers, registers, and other symbols required for DSP instructions, as well as the corresponding processing functions. When the input matches the regular expression, the corresponding code segment is executed.

[0038] b. In order to further distinguish between opcodes, registers and symbols, string splitting and priority matching methods are also required to avoid mismatches of regular expressions. In the S assembly instruction format, spaces are used to separate instruction opcodes and operands, and labels always end with a colon.

[0039] In step b, the string splitting and priority matching methods are explained as follows:

[0040] 1. Use the first space of the assembly instruction as the delimiter to split the string. If the first string obtained by splitting contains a colon, then proceed to label matching; otherwise, proceed to opcode matching.

[0041] 2. If the string to be matched is located in the second string obtained by splitting, then proceed to the symbol matching in the operand;

[0042] 3. If the sign of the operand is matched, the name should be compared precisely in the register set. If it matches, the sign is the register name; otherwise, the sign is a sign or immediate type.

[0043] Based on the above, the lexical analysis and syntax analysis parts of the assembler were constructed. Specifically, the syntax analysis part of the assembler was constructed using Yacc, thereby specifying the organization method between labels. Yacc declarations, rule segments, and code segments were used to define the format composition of DSP instructions, such as the format of VLIW, single instructions, operands, and opcodes.

[0044] operand:operand''REG{……}

[0045] |operand''NUMBER{……}

[0046] |operand''SYM{……}

[0047] |REG{……}

[0048] |NUMBER{……}

[0049] |SYM{……}

[0050] Match the corresponding grammar based on the non-terminal symbols output by lexical analysis, execute the corresponding code segment, and complete the instruction format check and data filling.

[0051] To further explain, in step S2, the instruction definition implementation of dynamic encoding and decoding includes dynamic instruction encoding and disassembly;

[0052] Dynamic instruction encoding is the process of converting instructions in an assembly file into machine code in an object file; disassembly is the process of parsing machine code in a binary object file into assembly instructions.

[0053] To elaborate further, dynamic instruction encoding determines the instruction type based on the opcode and operands output by lexical and syntactic analysis, searches for a completely matching instruction from the instruction list of that type, further determines the values ​​of the opcode and operands according to the instruction definition, fills the corresponding data structure, and outputs the final encoding of the instruction;

[0054] The disassembler obtains the opcode of an instruction from the object file, traverses the instruction definition list, and if the opcode and operands match, outputs the corresponding assembly code as a string.

[0055] To elaborate further, based on the instruction code length, the opcode of an instruction is obtained from the object file. The instruction definition list is traversed to search for instructions whose opcode and operands both match the binary machine code. Based on the static definition of the instruction, the corresponding assembly code is output in the form of a string.

[0056] To further explain, step S3, which optimizes the assembler's functionality and performance, includes the following steps:

[0057] a2. Add corresponding data types and structures to provide vector instructions to support SIMD;

[0058] Among them, see Figure 4 The total bit width of the DSP vector instruction is 128 bits, of which the sub-bit widths are 8 bits, 16 bits and 32 bits, corresponding to 16 groups, 8 groups and 4 groups of data respectively, which constitute the vector instruction data.

[0059] b2. Add relevant descriptions to the processor architecture file to provide the assembler with support for VLIW;

[0060] c2. Perform legality checks on data dependencies between instructions;

[0061] Based on step b2 above, to support 8-way parallel VLIW, a 3-bit slot code needs to be added to the instruction encoding, such as 000 for slot 0 and 111 for slot 7. Support is also provided for the syntax of separating instructions with "|". In addition, due to the hardware limitations of the processor, each slot can only use a specified type of instruction. For example, slots four and five can only use NOP instructions and load instructions, while slots six and seven can use NOP instructions, store instructions, scalar operation instructions and data transfer instructions. Therefore, the correspondence between instructions and slots also needs to be explained.

[0062] Based on the above c2 step, see Figure 5 Any write operation instruction may result in a data conflict. Since the digital signal processor supports a maximum of 8 transmits and data access will cause a certain clock cycle delay, it is necessary to judge the data dependency of the write-after-read type and handle it accordingly.

[0063] The main method for handling data conflicts is to add delay slots. When the delay slot flag is 1, it means that the instruction needs to add a delay slot. The number of delay slots to be inserted needs to be calculated based on the context and execution cycle of the instruction, so as to avoid data conflicts between instructions.

[0064] Specifically, assuming the execution cycle of instruction N is M, a data dependency graph needs to be established for this instruction and the following M-1 instructions. It is then determined whether they use the write result of instruction N. If other instructions in the VLIW containing the instruction have data conflicts, the VLIW needs to be split and the order of the conflicting instructions needs to be adjusted. If the interval between the instruction and other conflicting instructions is less than M-1 clock cycles, a corresponding empty instruction needs to be inserted. If the interval between the instruction and other potentially conflicting instructions is greater than or equal to M-1 clock cycles, the instruction is valid.

[0065] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for porting a digital signal processor (DSP) assembler based on a processor architecture description, characterized in that, Includes the following steps: S1. Based on the processor architecture description, the lexical analysis and syntax analysis parts of the assembler were constructed to realize the parsing of special assembly instructions; The construction of the assembler's lexical and syntax analysis parts includes the following steps: a. The lexical analysis part of the assembler is constructed using Lex files, which decompose the input assembly instruction stream into different categories of labels through the declaration, conversion rules, and auxiliary functions of the Lex file; b. In order to further distinguish between opcodes, registers and symbols, string splitting and priority matching methods are also required to avoid mismatches of regular expressions. In the S assembly instruction format, spaces are used to separate instruction opcodes and operands, and labels always end with a colon. The specific methods for string splitting and priority matching include the following: a1. Use the first space of the assembly instruction as the delimiter to split the string. If the first string obtained by splitting contains a colon, then proceed to label matching; otherwise, proceed to opcode matching. b1. If the string to be matched is located in the second string obtained by splitting, then proceed to the symbol matching in the operands; c1. If the sign of the operand to be entered matches, an exact comparison of names should first be performed in the register set. If a match is found, the sign is the register name; otherwise, the sign is a sign or immediate type. S2. Taking the parsed instruction data or instruction binary code as input, and implementing dynamic encoding and decoding of instructions according to the instruction definition, thereby realizing the conversion between object files and assembly files; Instruction definition implementation includes dynamic instruction encoding and disassembly; S3. Optimizes assembler functionality and performance, providing support for Very Long Instruction Word, Single Instruction Multiple Data, and instruction validity checking; Optimizing the assembler's functionality and performance includes the following steps: a2. Add corresponding data types and structures to provide vector instructions to support SIMD; b2. Add relevant descriptions to the processor architecture file to provide the assembler with support for VLIW; C2. Perform a validity check on the data dependencies between instructions.

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