Universal polar code multi-bit parallel list decoding method and device

Abstract

The present application proposes a general multi-bit parallel list decoding method for polar codes, comprising: obtaining a polar code to be decoded and dividing it into M bit groups; sequentially placing the M bit groups into a decoder for decoding to obtain a decoding result, including: performing parallel metric calculation on the currently placed M bit group to obtain 2 M L path metrics; construct a master-slave sorting network for the decoder; exchange the path metric values ​​selected from the master-slave sorting network to obtain L path metric values; use the M-bit values ​​corresponding to the obtained L paths as the decoding decision for that path, and then as the decoding result for the current M-bit group; obtain the decoding results for all M-bit groups, and then use the smallest path among the L smallest paths in the decoding results of all M-bit groups as the final decoding path, and the sequence of all M-bit values ​​corresponding to this path as the decoding result of the polar code. The present invention, which adopts the above scheme, solves the technical problems of complexity and performance in list sorting for polar code decoding.

Description

Technical Field

[0001] The present application relates to the field of information processing technology, and in particular to a general polar code multi-bit parallel list decoding method and device. Background Art

[0002] Polar codes are the latest and most advanced channel error correction coding technology. They have been implemented in the 5G mobile communications standard and are a candidate for future 6G mobile communications. Polar codes are increasingly being used.

[0003] For polar code decoding, list-elimination decoding is the optimal method, offering the best performance. During list-elimination decoding, the path metrics calculated for each list must be sorted to select the list with the optimal metric. Conventionally, polar code decoding requires a minimum of 16 candidate lists. To minimize performance loss, larger lists are preferred. However, a large number of lists increases sorting complexity and occupies a long period of time, significantly reducing the decoding rate of polar codes.

[0004] To address the problems of high list complexity and long cycle times, many methods have been proposed. The first method is to reduce the number of lists, such as reducing the number of lists to less than 8, such as single-list, dual-list, or quad-list. This method reduces the number of lists and complexity, but significantly reduces performance. The second method is approximate sorting, which uses the highest two digits of each list to represent the metric value of each list, reducing the precision of the values ​​of each list. This allows the use of a smaller bit-width comparator for sorting and comparison, reducing computational complexity and increasing computational speed. This method can also result in low precision and inaccurate sorting, which can lead to a loss of decoding performance. Summary of the Invention

[0005] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0006] To this end, the first objective of this application is to propose a general multi-bit parallel list decoding method for polar codes, which solves the technical problem that the complexity and performance of list sorting in polar code decoding in existing methods cannot be guaranteed simultaneously, thereby achieving dual guarantees of sorting complexity and performance.

[0007] A second objective of the present application is to provide a universal polar code multi-bit parallel list decoding device.

[0008] The third object of this application is to provide a computer device.

[0009] A fourth object of the present application is to provide a non-transitory computer-readable storage medium.

[0010] To achieve the above-mentioned objectives, the first embodiment of the present application proposes a general multi-bit parallel list decoding method for polar codes, comprising: obtaining a polar code to be decoded, and dividing the polar code into at least one M-bit group; sequentially placing the divided M-bit groups into a decoder for decoding to obtain a decoding result; wherein the list size of the decoder is L, and the divided M-bit groups are sequentially placed into the decoder for decoding to obtain a decoding result, comprising: performing parallel metric calculation on the M-bit group currently placed into the decoder to obtain 2 M L path metrics; construct a master sorting network for the decoder, and select the smallest L path metrics in the master sorting network; construct a slave sorting network for the decoder, and select the smallest N path metrics in the slave sorting network, where N is the list size parameter of the decoder; exchange the path metrics selected from the master and slave sorting networks to obtain the final L path metrics; use the M-bit values ​​corresponding to the final L paths as the decoding decision of the path, and use the decoding decision as the decoding result of the current M-bit group; obtain the decoding results of all M-bit groups, and then use the smallest path among the smallest L paths in the decoding results of all M-bit groups as the final decoding path, and the sequence of all M-bit values ​​corresponding to the path as the decoding result of the polar code.

[0011] The universal multi-bit parallel list decoding method for polar codes in the embodiments of the present application reduces complexity through two-level comparisons, master and slave. Simultaneously, two-level sorting is used. The master sorting ensures accurate sorting with minimal performance loss, while the slave sorting reduces sorting complexity and improves decoding rate.

[0012] Optionally, in one embodiment of the present application, for a decoder with a list size of L, the main sorting network has a total of 2L path metrics, wherein the main sorting network is composed of path metrics constitute,

[0013] The 2L path metric values ​​are sorted, and the L path metric values ​​with the smallest path metric values ​​are extracted as the smallest L path metric values ​​of the main sorting network.

[0014] Optionally, in one embodiment of the present application, constructing a slave sorting network and selecting the smallest N path metrics in the slave sorting network include:

[0015] Decoding and selecting parameter N based on the polar code multi-bit parallel list;

[0016] According to the selected parameter N, a sorting network is constructed, where the sorting network is composed of path metrics. constitute;

[0017] Among the NL path metric values ​​included in the sorted network, find the smallest N path metric values.

[0018] Optionally, in one embodiment of the present application, exchanging N path metric values ​​in the master-slave sorting network to obtain the minimum L path metric values ​​includes:

[0019] Sorting the largest N path metrics among the extracted L minimum path metrics and the selected minimum N path metrics to obtain the reordered minimum N path metrics;

[0020] The unsorted path metric values ​​among the extracted L minimum path metric values ​​are combined with the re-sorted minimum N path metric values ​​to obtain final L path metric values.

[0021] To achieve the above objectives, a second embodiment of the present invention provides a general polar code multi-bit parallel list decoding device, including a data processing module and a decoding module, wherein:

[0022] a data processing module, configured to obtain a polar code to be decoded and divide the polar code into at least one M-bit group;

[0023] A decoding module is used to sequentially input the divided M bit groups into a decoder for decoding to obtain a decoding result;

[0024] Among them, the list size of the decoder is L, and the decoding module is specifically used for:

[0025] Perform parallel metric calculation on the M bit group currently put into the decoder, and get 2 M L path metrics;

[0026] Construct the main sorting network of the decoder and select the smallest L path metrics in the main sorting network;

[0027] Construct a slave sorting network for the decoder and select the N smallest path metrics from the slave sorting network, where N is the list size parameter of the decoder.

[0028] Exchange the path metrics selected from the master-slave sorting network to obtain the final L path metrics;

[0029] The M-bit values ​​corresponding to the final L paths are used as the decoding decisions for the paths, and the decoding decisions are used as the decoding results for the current M-bit group.

[0030] Decoding results of all M-bit groups are obtained. Then, the smallest path among the L smallest paths in the decoding results of all M-bit groups is used as the final decoding path, and the sequence of all M-bit values ​​corresponding to the path is used as the decoding result of the polar code.

[0031] To achieve the above objectives, a third embodiment of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the above-mentioned general multi-bit parallel list decoding method for polar codes is implemented.

[0032] To achieve the above objectives, a fourth aspect of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a processor, the processor can perform the above-mentioned general polar code multi-bit parallel list decoding method.

[0033] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0035] Figure 1 This is a flowchart of a general polar code multi-bit parallel list decoding method provided in Example 1 of the present application;

[0036] Figure 2 This is a diagram of the decoding process of an embodiment of the present application;

[0037] Figure 3 This is a master-slave exchange sorting network diagram of an embodiment of the present application;

[0038] Figure 4 This is a simulation diagram of the decoding performance of the polar code list when M=4 according to an embodiment of the present application;

[0039] Figure 5 A schematic structural diagram of a general polar code multi-bit parallel list decoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0041] The following describes a general polar code multi-bit parallel list decoding method and apparatus according to an embodiment of the present application with reference to the accompanying drawings.

[0042] Figure 1This is a flowchart of a general polar code multi-bit parallel list decoding method provided in Example 1 of the present application.

[0043] like Figure 1 As shown, the general polar code multi-bit parallel list decoding method includes the following steps:

[0044] Step 101: Obtain a polar code to be decoded, and divide the polar code into at least one M-bit group;

[0045] Step 102: The divided M bit groups are sequentially put into a decoder for decoding to obtain a decoding result.

[0046] The universal multi-bit parallel list decoding method for polar codes in the embodiments of this application reduces complexity through two-level comparisons, master and slave. Simultaneously, two-level sorting is employed: master sorting ensures accurate sorting with minimal performance loss, while slave sorting reduces sorting complexity and improves decoding rate. This master-slave sorting method achieves both sorting complexity and performance. This method reduces the complexity of the sorting network used in multi-bit parallel list decoding of polar codes, facilitates engineering implementation, and offers the advantages of low hardware cost and high hardware throughput.

[0047] In this application, the divided M bit groups are sequentially put into the decoder for decoding, and the process of obtaining the decoding result is as follows: Figure 2 Shown, including:

[0048] S1, L paths M bits parallel metric calculation, a total of 2ML path metrics;

[0049] S2, build the main sorting network;

[0050] S3, build a sorting network;

[0051] S4. Exchange the N path metrics in the master-slave sorting network to obtain the minimum L path metrics.

[0052] S5. Use the M-bit value corresponding to the smallest L paths as the decoding decision of the path;

[0053] S6: Determine whether all bits have been decoded; if so, proceed to S7; otherwise, proceed to S1 to decode the next group of M bits;

[0054] S7. The smallest path among the L smallest paths is used as the final decoding path, and the sequence of all M-bit values ​​corresponding to the path is used as the decoding result of the polar code.

[0055] Optionally, in one embodiment of the present application, the sorting structure is as follows Figure 3 As shown, for polar code M-bit parallel list decoding, 2 ML path metrics, using an ordered matrix To indicate that each list selects the two smallest path metrics For a decoder with a list size of L, the main sorting network has a total of 2L path metrics,

[0056] The constructed set of 2L path metric value elements is sorted, and L path metric values ​​with the smallest path metric values ​​are extracted.

[0057] Optionally, in one embodiment of the present application, constructing a slave sorting network and selecting the smallest N path metrics in the slave sorting network include:

[0058] Select an appropriate N parameter to ensure that the performance of multi-bit parallel list decoding of polar codes is not degraded;

[0059] Parameter selection, L = 8, N = 2; L = 32, N = 4; the selected parameters are suitable for M = 2, 4, 8 bit parallel decoding; the decoding performance of M = 4 is as follows Figure 4 As shown;

[0060] According to the selected N parameter, a slave sorting network is constructed and the path metric value is selected for the polar code M-bit parallel list decoding algorithm. To form a sorting network;

[0061] In constructing a set of NL path metric elements, find the smallest N path metric values ​​therein.

[0062] Optionally, in one embodiment of the present application, exchanging N path metric values ​​in the master-slave sorting network to obtain the minimum L path metric values ​​includes:

[0063] The switching network sorts the largest N path metrics among the selected L minimum path metrics and the found minimum N path metrics to find the minimum N path metrics;

[0064] The selected (LN) smallest path metric values ​​are combined with the obtained N path metric values ​​to obtain the final L path metric values.

[0065] In order to implement the above embodiment, the present application also proposes a general polar code multi-bit parallel list decoding device.

[0066] Figure 5 A schematic structural diagram of a general polar code multi-bit parallel list decoding device provided in an embodiment of the present application.

[0067] like Figure 5As shown, the universal polar code multi-bit parallel list decoding device includes a data processing module and a decoding module, wherein:

[0068] a data processing module, configured to obtain a polar code to be decoded and divide the polar code into at least one M-bit group;

[0069] A decoding module is used to sequentially input the divided M bit groups into a decoder for decoding to obtain a decoding result;

[0070] Among them, the list size of the decoder is L, and the decoding module is specifically used for:

[0071] Perform parallel metric calculation on the M bit group currently put into the decoder, and get 2 M L path metrics;

[0072] Construct the main sorting network of the decoder and select the smallest L path metrics in the main sorting network;

[0073] Construct a slave sorting network for the decoder and select the N smallest path metrics from the slave sorting network, where N is the list size parameter of the decoder.

[0074] Exchange the path metrics selected from the master-slave sorting network to obtain the final L path metrics;

[0075] The M-bit values ​​corresponding to the final L paths are used as the decoding decisions for the paths, and the decoding decisions are used as the decoding results for the current M-bit group.

[0076] Decoding results of all M-bit groups are obtained. Then, the smallest path among the L smallest paths in the decoding results of all M-bit groups is used as the final decoding path, and the sequence of all M-bit values ​​corresponding to the path is used as the decoding result of the polar code.

[0077] It should be noted that the aforementioned explanation of the embodiment of the general polar code-oriented multi-bit parallel list decoding method also applies to the general polar code-oriented multi-bit parallel list decoding device of this embodiment, and will not be repeated here.

[0078] To implement the above embodiments, the present invention further proposes a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method described in the above embodiments is implemented.

[0079] In order to implement the above embodiments, the present invention further proposes a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method of the above embodiments is implemented.

[0080] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0081] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0082] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0083] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0084] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0085] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0086] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0087] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A general multi-bit parallel list decoding method for polar codes, characterized in that: The following steps are involved: Obtaining a polar code to be decoded, and dividing the polar code into at least one M-bit group; The divided M bit groups are sequentially put into the decoder for decoding to obtain the decoding results; The list size of the decoder is L, and the divided M bit groups are sequentially placed into the decoder for decoding to obtain a decoding result, including: Perform parallel metric calculation on the M bit group currently put into the decoder, and get 2 M L path metrics; Constructing a main sorting network of the decoder, and selecting the smallest L path metrics in the main sorting network; Constructing a slave sorting network of the decoder, and selecting the smallest N path metrics in the slave sorting network, where N is a list size parameter of the decoder; Exchange the path metrics selected from the master-slave sorting network to obtain the final L path metrics; Using the M-bit values ​​corresponding to the final L paths as decoding decisions for the paths, and using the decoding decisions as decoding results for the current M-bit group; Decoding results of all M-bit groups are obtained, and then a minimum path among the minimum L paths in the decoding results of all M-bit groups is used as a final decoding path, and a sequence of all M-bit values ​​corresponding to the path is used as a decoding result of the polar code.

2. The method according to claim 1, wherein For a decoder with a list size of L, the main sorting network has a total of 2L path metrics, where the main sorting network consists of path metrics constitute, The 2L path metric values ​​are sorted, and L path metric values ​​with the smallest path metric values ​​are extracted as the smallest L path metric values ​​of the main sorting network.

3. The method according to claim 1, wherein The construction of the sorting network and the selection of the smallest N path metrics in the sorting network include: Decoding selection parameter N based on the polar code multi-bit parallel list; According to the selected parameter N, a slave sorting network is constructed, wherein the slave sorting network is composed of path metrics. constitute; Among the NL path metric values ​​included in the sorting network, find the smallest N path metric values.

4. The method according to claim 1, wherein The exchanging N path metric values ​​in the master-slave sorting network to obtain the minimum L path metric values ​​includes: Sorting the largest N path metrics among the extracted L minimum path metrics and the selected minimum N path metrics to obtain the reordered minimum N path metrics; The unsorted path metric values ​​among the extracted L minimum path metric values ​​are combined with the re-sorted minimum N path metric values ​​to obtain the final L path metric values.

5. A general polar code multi-bit parallel list decoding device, characterized in that: It includes a data processing module and a decoding module, wherein: The data processing module is configured to obtain a polar code to be decoded and divide the polar code into at least one M-bit group; The decoding module is used to sequentially place the divided M bit groups into a decoder for decoding to obtain a decoding result; The list size of the decoder is L, and the decoding module is specifically used to: Perform parallel metric calculation on the M bit group currently put into the decoder, and get 2 M L path metrics; Constructing a main sorting network of the decoder, and selecting the smallest L path metrics in the main sorting network; Constructing a slave sorting network of the decoder, and selecting the smallest N path metrics in the slave sorting network, where N is a list size parameter of the decoder; Exchange the path metrics selected from the master-slave sorting network to obtain the final L path metrics; Using the M-bit values ​​corresponding to the final L paths as decoding decisions for the paths, and using the decoding decisions as decoding results for the current M-bit group; Decoding results of all M-bit groups are obtained, and then a minimum path among the minimum L paths in the decoding results of all M-bit groups is used as a final decoding path, and a sequence of all M-bit values ​​corresponding to the path is used as a decoding result of the polar code.

6. The device according to claim 5, characterized in that For a decoder with a list size of L, the main sorting network has a total of 2L path metrics, where the main sorting network consists of path metrics constitute, The 2L path metric values ​​are sorted, and L path metric values ​​with the smallest path metric values ​​are extracted as the smallest L path metric values ​​of the main sorting network.

7. The device according to claim 5, characterized in that The second extraction module is specifically used to: Select parameter N based on the performance of polar code multi-bit parallel list decoding; According to the selected parameter N, a slave sorting network is constructed, wherein the slave sorting network is composed of the path metric m3 1: : L N constitute; Among the NL path metric values ​​included in the sorting network, find the smallest N path metric values.

8. The device according to claim 5, wherein Switch modules are specifically used for: Sorting the largest N path metrics among the extracted L minimum path metrics and the selected minimum N path metrics to obtain the reordered minimum N path metrics; The unsorted path metric values ​​among the extracted L minimum path metric values ​​are combined with the re-sorted minimum N path metric values ​​to obtain the final L path metric values.

9. A computer device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method according to any one of claims 1 to 4 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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