Integrated circuit and method of forming the same

Abstract

Embodiments of the present invention provide integrated circuits and methods for forming the same. The integrated circuit includes a first nanostructure transistor, the first nanostructure transistor comprising: a plurality of first semiconductor nanostructures located above a substrate; and a source / drain region contacting each of the first semiconductor nanostructures. The integrated circuit also includes a second nanostructure transistor, the second nanostructure transistor comprising: a plurality of second semiconductor nanostructures; and a second source / drain region contacting one or more of the second semiconductor nanostructures, but not contacting one or more other second semiconductor nanostructures.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods for forming the same. Background Technology

[0002] There has always been a need to enhance computing power in electronic devices, including smartphones, tablets, desktop computers, laptops, and many other types of electronic devices. Integrated circuits provide this computing power to these devices. One way to enhance computing power in integrated circuits is to increase the number of transistors and other integrated circuit components that can be contained within a given area of ​​a semiconductor substrate.

[0003] Nanostructured transistors can help improve computing power because they can be very small and have improved functionality compared to traditional transistors. A nanostructured transistor can comprise multiple semiconductor nanostructures (such as nanowires, nanosheets, etc.) that serve as the channel region of the transistor. Summary of the Invention

[0004] According to one aspect of an embodiment of the present invention, an integrated circuit is provided, comprising: a substrate; a first transistor located above the substrate, the first transistor including: a plurality of stacked first semiconductor nanostructures corresponding to a channel region of the first transistor; and a first source / drain region contacting each of the first semiconductor nanostructures; and a second transistor located above the substrate, the second transistor including: a plurality of stacked second semiconductor nanostructures; and a second source / drain region contacting the highest second semiconductor nanostructure of the second semiconductor nanostructures and having a bottom surface higher than the lowest second semiconductor nanostructure of the second semiconductor nanostructures.

[0005] According to another aspect of the present invention, an integrated circuit is provided, comprising: a substrate; a first transistor located above the substrate, and including: a plurality of stacked first semiconductor nanostructures; a first gate metal surrounding each first semiconductor nanostructure; and a first source / drain region contacting the highest first semiconductor nanostructure of the first semiconductor nanostructure and electrically isolated from the lowest first semiconductor nanostructure of the first semiconductor nanostructure.

[0006] According to another aspect of the present invention, a method for forming an integrated circuit is provided, comprising: forming a plurality of first semiconductor nanostructures of a first transistor over a substrate; forming a plurality of second semiconductor nanostructures of a second transistor over a substrate; growing an epitaxial semiconductor layer over the substrate, wherein the epitaxial semiconductor layer contacts a bottom first semiconductor nanostructure of the plurality of first semiconductor nanostructures; forming a first source / drain region of the first transistor over the epitaxial semiconductor layer, wherein the first source / drain region contacts a top first semiconductor nanostructure of the plurality of first semiconductor nanostructures, wherein the first source / drain region has a bottom surface higher than the bottom first semiconductor nanostructure of the first semiconductor nanostructure; and forming a second source / drain region of the second transistor in contact with all the second semiconductor nanostructures, wherein the second source / drain region has a bottom surface lower than the bottom surface of the first source / drain region. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figures 1A-1D This is a view of an integrated circuit according to some embodiments;

[0009] Figures 2A-2L These are cross-sectional views of integrated circuits at different stages of process according to some embodiments;

[0010] Figure 3 This is a flowchart of a process for forming an integrated circuit according to some embodiments. Detailed Implementation

[0011] In the following description, numerous thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given by way of example for various embodiments. Those skilled in the art will recognize that, according to the invention, other dimensions and materials can be used in many cases without departing from the scope of the invention.

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] In the following description, certain specific details are set forth to provide a thorough understanding of various embodiments of the invention. However, those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known structures related to electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of embodiments of the invention.

[0015] Unless the context otherwise requires, throughout the specification and the following claims, the word “comprising” and its variations, such as “including” and “comprise”, shall be interpreted in an open, inclusive sense, meaning “including but not limited to”.

[0016] The use of ordinal numbers such as first, second, and third does not necessarily imply a sense of order in the sequence, but may simply be a distinction between multiple instances of an action or structure.

[0017] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment," "in an embodiment," or "in some embodiments" appearing in various places throughout the specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in one or more embodiments in any suitable manner.

[0018] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural indicators unless otherwise expressly provided. It should also be noted that the term “or” is generally used to include the meaning of “and / or” unless otherwise expressly provided.

[0019] Embodiments of the present invention provide an integrated circuit with nanostructured transistors having different effective channel widths while having substantially the same area consumption. Each transistor has multiple stacked nanostructures corresponding to a transistor channel region. The effective channel width of each transistor corresponds to the combined width of the stacked nanostructures. Each transistor initially has the same number of stacked nanostructures. The effective channel width of the transistor is adjusted by forming source / drain regions to connect only to a selected number of stacked nanostructures. The depth of the source / drain regions is controlled by selectively performing an epitaxial growth that effectively extends the substrate height in the region connecting fewer channels to the source / drain regions. The greater the number of nanostructures connected to the transistor source / drain regions, the larger the effective channel width of the transistor.

[0020] As described above, selectively controlling the effective channel width enables the formation of transistors or transistor groups with specific characteristics. For example, low-power devices can be formed by reducing the number of channels connected to the source / drain regions. Higher-speed devices can be formed by connecting more channels to the source / drain regions. Furthermore, transistors with different effective channel widths can occupy substantially the same amount of substrate area. The result is an integrated circuit with dedicated high-speed and low-power devices without increasing design complexity or area loss. Device performance and wafer yield are improved.

[0021] Figure 1A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 includes a substrate 102. The integrated circuit also includes four transistors 104a, 104b, 104c, and 104d. As will be described in more detail below, transistors 104a-104d include different effective channel widths but do not consume substantially different amounts of integrated circuit area.

[0022] Transistors 104a-104d may correspond to full-to-the-loop gate transistors. The full-to-the-loop gate transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches compared to those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the full-to-the-loop gate structure. Additionally, each of the full-to-the-loop gate transistors 104a-104d may include multiple semiconductor nanostructures corresponding to the channel region of transistor 104a-104d. The nanostructures may include nanosheets, nanowires, or other types of nanostructures.

[0023] In some embodiments, substrate 102 includes a single-crystal semiconductor layer located on at least a surface portion. Substrate 102 may include a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In the exemplary process described herein, substrate 102 includes Si, but other semiconductor materials may be used without departing from the scope of the invention.

[0024] Transistor 104a comprises multiple nanostructures 106a. The nanostructures 106a are stacked along either the vertical or Z-axis. Figure 1A In the example, there are three stacked nanostructures 106a. However, in practice, there may be only two stacked nanostructures 106a, or there may be more than three stacked nanostructures 106a, without departing from the scope of the invention. The nanostructure 106a corresponds to the channel region of the transistor 104a.

[0025] Nanostructure 106a may comprise one or more layers of Si, SiGe, or other semiconductor materials. Other semiconductor materials may be used in nanostructure 106a without departing from the scope of the invention. In the non-limiting example described herein, nanostructure 106a is silicon. The vertical thickness of nanostructure 106a may be between 3 nm and 10 nm. Semiconductor nanostructures 106a may be spaced apart from each other by 3 nm to 15 nm. Other thicknesses and materials may be used in nanostructure 106a without departing from the scope of the invention.

[0026] Transistor 104a includes gate metal 108a. Gate metal 108a surrounds nanostructure 106a. Gate metal 108a corresponds to a gate electrode, or they correspond to one of the metals constituting the gate electrode of substrate 102. Gate metal 108a may include one or more of titanium nitride, tungsten, tantalum, tantalum nitride, aluminum tantalum nitride, ruthenium, cobalt, aluminum, titanium, or other suitable conductive materials. Gate metal 108a may have a length between 5 nm and 150 nm along the X direction. Other materials and thicknesses may be used for gate metal 108a without departing from the scope of the invention.

[0027] Transistor 104a includes source / drain regions 110a. Each source / drain region 110a is in contact with a nanostructure 106a. Each nanostructure 106a extends along the X-direction between source / drain regions 110a. Source / drain regions 110a comprise semiconductor material. In the case of an N-type transistor, source / drain regions 110a may be doped with N-type dopant. N-type dopant types may include P, As, or other N-type dopant types. In the case of a P-type transistor, source / drain regions 110a may be doped with P-type dopant types. P-type dopant types may include B or other P-type dopant types. Doping can be performed in situ during epitaxial growth. Source / drain regions 110a may comprise other materials and structures without departing from the scope of the invention. In the case of an N-type transistor, source / drain regions 110a may comprise Si, SiC, or other semiconductor materials. In the case of a P-type transistor, the source / drain region 110a may include Si, SiC, or other semiconductor materials.

[0028] Transistor 104a includes a gate dielectric (not shown). The gate dielectric is located between gate metal 108a and nanostructure 106a. The gate dielectric surrounds nanostructure 106a. Gate metal 108a surrounds the gate dielectric.

[0029] In some embodiments, the gate dielectric includes a high-k gate dielectric layer and an interface gate dielectric layer. The interface gate dielectric layer is a low-k gate dielectric layer. The interface gate dielectric layer is in contact with the nanostructure 106a. The high-k gate dielectric layer is in contact with the low-k gate dielectric layer and the gate metal 108a. The interface gate dielectric layer is located between the nanostructure 106a and the high-k gate dielectric layer. The low-k gate dielectric layer may be referred to as the interface gate dielectric layer.

[0030] The interface gate dielectric layer may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric material. The interface dielectric layer may include a relatively low-k dielectric relative to a high-k dielectric such as hafnium oxide or other high-k dielectric materials that can be used in the gate dielectric of a transistor.

[0031] The high-k gate dielectric layer comprises one or more dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The thickness of the high-k dielectric is in the range of about 1 nm to about 3 nm. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer without departing from the scope of the invention. The high-k gate dielectric layer may include a first layer and a second layer, the first layer comprising HfO2 having dipole doping including La and Mg, and the second layer comprising a higher K ZrO layer having crystalline structure.

[0032] Transistor 104a includes an internal spacer 114. The internal spacer 114 may comprise silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, or other dielectric materials not departing from the scope of the invention. The internal spacer 114 physically separates the gate metal 108a from the source / drain region 110a. This prevents short circuits between the gate metal 108a and the source / drain region 110a. The internal spacer 114 may have a thickness between 2 nm and 10 nm. Other materials, dimensions, and structures may be used for the internal spacer 114 without departing from the scope of the invention. The internal spacer may have a thickness between 2 nm and 10 nm.

[0033] Transistor 104a includes source / drain contacts 111a. Each source / drain contact 111a is located above and electrically connected to a corresponding source / drain region 110a. Electrical signals can be applied to the source / drain region 110a through the source / drain contacts 111a. The source / drain contacts 111a may include conductive materials such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. The source / drain contacts may have a width between 5 nm and 50 nm along the X-direction.

[0034] Transistor 104a may include a silicide (not shown). The silicide is formed on top of the source / drain region 110a. Source / drain contacts 111a are positioned to contact the silicide. The silicide facilitates a good electrical connection between the source / drain contacts 111a and the source / drain region 110a. The silicide may include titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicides. The source / drain contacts 111a may have a width between 5 nm and 50 nm.

[0035] Transistor 104a includes an epitaxial semiconductor layer 118a. The epitaxial semiconductor layer 118a may include an intrinsic semiconductor material. The epitaxial semiconductor layer 118a may be formed from the substrate 102 using an epitaxial growth process after an etching process has been used to form a recess in the substrate 102. The epitaxial layer 118a has a top surface that is lower than the bottom surface of the bottom semiconductor nanostructure 106a. The epitaxial semiconductor layer 118a may include the same semiconductor material as the substrate 102, or it may include a different semiconductor material. The epitaxial semiconductor layer 118a may include silicon, silicon germanium, or other suitable semiconductor materials.

[0036] Transistor 104a also includes a dielectric isolation structure 120a located below the source / drain regions 110a. Specifically, the respective dielectric isolation structure 120a is positioned between the semiconductor substrate 102 and each source / drain region 110a. The dielectric isolation structure 120a may be positioned to contact the top surface of the semiconductor substrate 102 and the bottom surface 126a of the source / drain regions 110a.

[0037] The dielectric isolation structure 120a is positioned in direct contact with the epitaxial semiconductor region 118a. The source / drain region 110a is in direct contact with the dielectric isolation structure 120a. The dielectric isolation structure 120a may comprise SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials. The dielectric isolation structure 120a may have a thickness between 1 nm and 15 nm. This thickness can be sufficient to ensure substantially no leakage current, but not so thick as to adversely affect the potential thickness of the source / drain region to be formed thereon. Other thicknesses and materials may be used for the dielectric isolation structure 120a without departing from the invention.

[0038] The presence of the dielectric isolation structure 120a ensures that leakage current does not flow from the source / drain region 110a into the semiconductor substrate 102. This significantly improves the efficiency of the first transistor 104a by essentially eliminating leakage current. This reduces power consumption and heat generation.

[0039] Transistor 104a includes a pair of dielectric layers 124 and 125. Dielectric layers 124 and 125 can together serve as a gate spacer layer positioned between gate electrode 108a and source / drain contact 111a. Dielectric layer 124 can be positioned to contact gate metal 108a and can include SiN, SiON, SiOCN, SiCN, or other suitable dielectric materials. Dielectric layer 125 can include silicon oxide or other suitable dielectric materials. Dielectric layer 124 can include fewer or more dielectric layers than two.

[0040] Transistor 104a can be operated by applying a voltage to the source / drain region 110a and the gate metal 108a. The voltage can be applied to the source / drain region 110a via the source / drain contact 111a. Figure 1A A gate contact (not shown) is applied to the gate metal 108a. The voltage can be selected to turn on or off transistor 104a. When transistor 104a is on, current can flow through each nanostructure 106a between the source / drain regions 110a. When transistor 104a is off, current does not flow through the nanostructures 106a.

[0041] In transistor 104a, each semiconductor nanostructure 106a is in contact with the source / drain region 110a. Therefore, when transistor 104a is turned on, each semiconductor nanostructure 106a conducts current between the source / drain regions 110a. The bottom surface 126a of the source / drain regions 110a is lower than the bottom surface of the lowest semiconductor nanostructure 106a.

[0042] Transistor 104a has a channel length corresponding to the distance between source / drain regions 108a along the X direction. Transistor 104a has an effective channel width corresponding to the sum of the widths of each semiconductor nanostructure 106a. The width of a single semiconductor nanostructure 106a corresponds to the dimension of the semiconductor nanostructure 106a along the Y direction. Therefore, due to the presence of three semiconductor nanostructures 106a in contact with the source / drain region 110a, the total effective channel width of transistor 104a is three times the width of a single semiconductor nanostructure 106a.

[0043] The amount of current flowing through a transistor is partly based on its channel width. If the same voltage is applied to the terminals of two transistors that are identical except for their channel width, the transistor with a wider channel will carry a larger current than the transistor with a narrower channel. A transistor with a narrower channel will consume less power than a transistor with a wider channel. A transistor with a wider channel will be able to turn on and off more quickly.

[0044] Including transistors with different channel widths to provide some transistors that consume less power and others that have faster performance can be beneficial for integrated circuits. As mentioned above, this can be achieved by having a number of transistors with different widths. One solution to achieve this is to form some transistors that occupy a larger substrate area than others. However, this has the disadvantage of potentially consuming a larger area to provide transistors with wide channels.

[0045] The transistors provided by integrated circuit 100 have different effective channel widths while consuming substantially the same amount of area. This is achieved by connecting different numbers of stacked semiconductor nanostructures to the source / drain regions of the transistors. Although each transistor may include the same number of stacked semiconductor nanostructures, transistors with smaller channel widths can be formed by selectively connecting only a subset of the total available number of semiconductor nanostructures to the source / drain regions of the transistors.

[0046] exist Figure 1A In the figures, transistors 104b-104d have many of the same types of components and structures as transistor 104a. Structures in transistors 104b-104d that have similar structures to those in transistor 104a are labeled with the same reference numerals, but with different suffix letters. For example, transistor 104b includes a semiconductor nanostructure 106b, transistor 104c includes a semiconductor nanostructure 106c, and transistor 104d includes a semiconductor nanostructure 106d. When describing transistors 104b-104d, the differences between transistors 104b-104d and transistor 104a will be emphasized, without describing structures that may be substantially similar to those associated with transistor 104a.

[0047] In one embodiment, transistors 104a and 104d have the same first conductivity type. Transistors 104b and 104c have the same second conductivity type. The second conductivity type is the opposite of the first conductivity type. In one example, the first conductivity type is N-type, and the second conductivity type is P-type. Therefore, the source / drain regions 110a and 110d of transistors 104a and 104d can be doped with N-type dopant, while the source / drain regions 110b and 110c of transistors 104b and 104c can be doped with P-type dopant. Other doping differences may exist between transistors 104a and 104d and transistors 104b and 104c.

[0048] exist Figure 1AIn the transistors 104a and 104b, the effective channel widths are substantially the same. This is because both transistors 104a and 104b have the same number (three) of semiconductor nanostructures 106a and 106b connected between the source / drain regions 110a and 110b. Transistor 104b may differ from transistor 104a in that transistor 104a includes a dielectric isolation structure 120a located between the source / drain region 110a and the epitaxial semiconductor region 118a, while transistor 104b does not include a similar dielectric isolation structure between the source / drain region 110b and the epitaxial semiconductor region 118b. One reason for this is that the source / drain region 110b may exhibit a crystal mismatch with the epitaxial semiconductor region 118b, which imparts beneficial strain to the source / drain region 110b. Strain can improve the conductivity of the source / drain region 110b. Therefore, in some cases, the P-type transistor 104b may not include a dielectric isolation structure that isolates the source / drain region 110b from the epitaxial semiconductor region 118b. In other cases, the P-type transistor 104b may also include a dielectric isolation structure similar to the dielectric isolation structure 120a of transistor 104a.

[0049] Transistors 104c and 104d have smaller effective channel widths than transistors 104a and 104b. This is because the lowest semiconductor nanostructures 106c and 106d of transistors 104c and 104d are not connected to the source / drain regions 110c and 110d. The epitaxial semiconductor regions 118c and 118d of transistors 104c and 104d have greater heights than the epitaxial semiconductor regions 118a and 118b of transistors 104a and 104b. In particular, the epitaxial semiconductor regions 118c and 118d are in contact with the lowest semiconductor nanostructures 106c and 106d.

[0050] Dielectric isolation structures 120c and 120d are positioned on epitaxial semiconductor regions 118c and 118d. The top surfaces of dielectric isolation structures 120c and 120d are higher than the top surfaces 128c and 128d of the lowest semiconductor nanostructures 106c and 106d of transistors 104c and 104d. Further details regarding the materials and processes used to form the dielectric isolation structures 120a-120d and the epitaxial semiconductor regions 118a-118d are provided in the section on... Figures 2C-2E Provided by China.

[0051] Source / drain regions 110c and 110d are formed on top of dielectric isolation structures 120c and 120d. Since the top surfaces of dielectric isolation structures 120c and 120d are higher than the top surfaces 128c and 128d of the lowest semiconductor nanostructures 106c and 106d, the source / drain regions 110c and 110d do not contact the lowest semiconductor nanostructures 106c and 106d. In other words, the bottom surfaces 126c and 126d of source / drain regions 110c and 110d are higher than the top surfaces 128c and 128d of the lowest semiconductor nanostructures 106c and 104d. As a result, the lowest semiconductor nanostructures 106c and 106d of transistors 104c and 104d are not used as channel regions for transistors 104c and 104d. Therefore, the total effective channel width of transistors 104c and 104d is twice the width of a single semiconductor nanostructure 106c or 106d. Figure 1A In the example, the effective channel width of transistors 104c and 104d is two-thirds that of transistors 104a and 104b.

[0052] In some embodiments, transistors 104c and 104d may be configured such that, depending on the total number of available semiconductor nanostructures and design selection, two or more of the minimum semiconductor nanostructures 106c and 106d are not connected to the source / drain regions 110c and 110d.

[0053] Figure 1B This is a simplified top view of an integrated circuit 100 according to some embodiments. Figure 1B The top view illustrates according to Figure 1A The transistor of the principle shown has two units. Specifically, the first unit 130 is designed for speed. Therefore, the first unit 130 includes, as described above... Figure 1A Transistors 104a and 104b are described as having relatively wide effective channel widths. The second unit 132 is designed to reduce power consumption. Therefore, the second unit 132 includes, as described above... Figure 1A The transistors 104c and 104d are described as having relatively small effective channel widths.

[0054] exist Figure 1B In the diagram, gate metals 108a-108d are shown as a single connected gate metal for all four transistors. In practice, gate metals 108a-108d may be connected to each other or electrically isolated from each other. Figure 1B The source / drain regions 110a-110d on both sides of the gate metals 108a-108d are also shown. In practice, transistors 104a-104d can be arranged differently. Figure 1B As shown, and including those not shown for simplicity. Figure 1B Other components in it.

[0055] Figure 1C It is cut along the cutting line C according to some embodiments. Figure 1A A cross-sectional view of integrated circuit 100. Figure 1C A hybrid fin structure 136 is shown that separates the source / drain regions 110a-110d from each other. Figure 1C In the diagram, the hybrid fin structure 136 is shown as a single layer. However, in practice, the hybrid fin structure 136 may comprise multiple layers. The dielectric material of the hybrid fin structure 136 may include one or more of SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials. The width of the hybrid fin structure 136 may be smaller than the width of the shallow trench isolation region 134.

[0056] In one embodiment, the hybrid fin structure 136 includes a first dielectric layer, a second dielectric layer, and a high-k dielectric layer. In some embodiments, the first dielectric layer comprises silicon nitride. In some embodiments, the second dielectric layer comprises silicon oxide. The high-k dielectric layer may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k dielectric layer may be referred to as the helmet layer for the hybrid fin structure 136. Other materials and structures may be used for the dielectric layer without departing from the scope of the invention.

[0057] Figure 1C A shallow trench isolation region 134 in the substrate 102 beneath the hybrid fin structure 136 is also shown. The dielectric material used for the shallow trench isolation region 134 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material. Other materials and structures may be used for the shallow trench isolation region 134 without departing from the scope of the invention.

[0058] Figure 1C The source / drain contact regions 111a-111d, which are electrically connected to the source / drain regions 110a-110d, are also shown. Although Figure 1C The source / drain contact regions 111a-111d are shown as a single phase connection structure, but in practice, the source / drain contact regions 111a-111d may include a single phase connection structure or an electrically isolated structure. Figure 1C It is also shown that source / drain regions 110a and 110b have larger dimensions along the vertical direction Z compared to source / drain regions 110c and 110d.

[0059] Figure 1D It is cut along the cutting line D according to some embodiments. Figure 1A A cross-sectional view of integrated circuit 100. Figure 1D The view shows gate electrodes 108a-108d surrounding semiconductor nanostructures 106a-106d. (As previously discussed...) Figure 1B As described, the gate metals 108a-108d can be a single gate metal connected together or can be electrically isolated from each other.

[0060] Figure 1D The width W of the semiconductor nanostructures 106a-106d along the Y direction is also shown. In some embodiments, the width W is between 5 nm and 20 nm. However, other dimensions can be used for the width W of the semiconductor nanostructures 106a-106d without departing from the scope of the invention. The effective width Weff of the transistor can be given by the following relationship:

[0061] Weff = n * W,

[0062] Where n is the number of semiconductor nanostructures electrically connected to the source / drain regions of the transistor. Figure 1A In the example, n = 3 for transistors 104a and 104b, and n = 2 for transistors 104c and 104d. In another formula, the effective width of the transistor can be given by the following relationship:

[0063] Weff = n*(W+H),

[0064] Where H is the vertical height or thickness of a single semiconductor nanostructure. In some embodiments, H can be between 3 nm and 10 nm, although other values ​​of H can be used without departing from the scope of the invention.

[0065] Figure 1D This illustrates the benefits of the principles of the present invention. Transistors 104a and 104b have different effective channel widths compared to transistors 104c and 104d, but each of transistors 104a-104d has substantially the same dimensions and Y-direction. This can greatly simplify the layout and process design for forming integrated circuit 100.

[0066] Figures 2A-2L This is a cross-sectional view of an integrated circuit 100 at an intermediate stage of the process according to some embodiments. Figure 2A The locations of four different transistors 104a-104d on substrate 102 are shown. Substrate 102 may include, as shown in the diagram... Figure 1A The materials and structure described.

[0067] For each transistor 104a-104d, the integrated circuit 100 includes a semiconductor stack. For each transistor 104a-104d, the semiconductor stack includes a plurality of semiconductor nanostructures 106a-106d. For each transistor 104a-104d, the semiconductor stack includes a plurality of sacrificial semiconductor nanostructures 142. The semiconductor nanostructures 106a-106d may have the following characteristics: Figure 1A The materials, composition, and dimensions are described. The sacrificial semiconductor nanostructures fall between 106a and 106d. Further details regarding sacrificial semiconductor nanostructure 142 are provided below.

[0068] Integrated circuit 100 includes a plurality of dummy gate structures 140, each dummy gate structure 140 being located above a corresponding semiconductor stack. The dummy gate structures 140 are positioned at the locations where the gate electrodes of transistors 104a-104d will be placed. The dummy gate structures 140 are located above the channel regions of transistors 104a-104d, as will be described in more detail below.

[0069] Each dummy gate structure 140 includes a polysilicon layer 144. The polysilicon layer 144 may have a thickness between 20 nm and 100 nm. The polysilicon layer 144 may be deposited by epitaxial growth, CVD process, physical vapor deposition (PVD) process, or ALD process. Other thicknesses and deposition processes may be used to deposit the polysilicon layer 144 without departing from the scope of the invention.

[0070] Each dummy gate structure 140 includes a dielectric layer 146 on a polysilicon layer 144 and a dielectric layer 148 on the dielectric layer 146. In one example, dielectric layer 146 includes silicon nitride. In one example, dielectric layer 148 includes silicon oxide. Dielectric layers 146 and 148 can be deposited by CVD. Dielectric layer 146 can have a thickness between 5 nm and 15 nm. Dielectric layer 148 can have a thickness between 15 nm and 50 nm. Other thicknesses, materials, and deposition processes can be used for dielectric layers 146 and 148 without departing from the scope of the invention.

[0071] Spacer layer 124 has been deposited on polysilicon layer 144 and dielectric layers 146 and 148. The spacer layer may include silicon nitride, SiOCN, or other suitable dielectric layers. Spacer layer 124 may be deposited using CVD, PVD, ALD, or other suitable processes. Spacer layer 124 may have a thickness between 2 nm and 10 nm. Spacer layer 124 may have other materials, deposition processes, and thicknesses without departing from the scope of the invention.

[0072] A dielectric layer 125 has been deposited on the spacer layer 124. The dielectric layer 125 may include silicon nitride, SiOCN, or other suitable dielectric layers. The dielectric layer 125 may be deposited using CVD, PVD, ALD, or other suitable processes. The dielectric layer 125 may have a thickness between 2 nm and 10 nm. The dielectric layer 125 may be made of the same material as or a different material from the spacer layer 124. Alternatively, the spacer layer 124 and the dielectric layer 125 may be considered together as a spacer layer for the dummy gate 140. The dielectric layer 125 may have other materials, deposition processes, and thicknesses without departing from the scope of the invention. The total thickness of the dielectric layers 124 and 125 along the X direction may be between 3 nm and 10 nm.

[0073] The integrated circuit 100 includes a trench 150 located between semiconductor stacks. More specifically, the process of forming or defining the semiconductor stacks may include forming the trench 150. The trench 150 also extends into the substrate 102.

[0074] The sacrificial semiconductor nanostructure 142 comprises a semiconductor material different from that of the semiconductor nanostructures 106a-106d. In an example where the semiconductor nanostructures 106a-106d comprise silicon, the sacrificial semiconductor nanostructure 142 may comprise SiGe. In some embodiments, the semiconductor nanostructures 106a-106d and the sacrificial semiconductor nanostructure 142 are formed by an alternating epitaxial growth process from the semiconductor substrate 102. The alternating epitaxial growth process is performed until a selected number of semiconductor nanostructures 106a-106d and the sacrificial semiconductor nanostructure 142 have been formed.

[0075] exist Figure 2B In the process, a recessing step has been performed to recess the sacrificial semiconductor nanostructure 142. The recessing process removes the exterior of the sacrificial semiconductor nanostructure 142 without completely removing it. The recessing process can be implemented using anisotropic etching, which selectively etches the material of the sacrificial semiconductor nanostructure 142 relative to the materials of the semiconductor nanostructures 106a-106d and the substrate 102. The anisotropic etching process may include a timed etching process. The duration of the etching process is selected such that only a portion of the sacrificial semiconductor nanostructure 142 is removed, without completely removing it.

[0076] exist Figure 2BIn this process, dielectric spacers 114 have been deposited between the exposed portions of semiconductor nanostructures 106a-106d. Specifically, dielectric spacers 114 are formed at locations where the sacrificial semiconductor nanostructures 142 have been recessed. Dielectric spacers 114 can be deposited using ALD, CVD, or other suitable processes. In one example, dielectric spacers 114 comprise silicon nitride. Other materials and deposition processes can be used for dielectric spacers 114 without departing from the scope of the invention.

[0077] exist Figure 2C In this process, epitaxial semiconductor regions 118a-118d have been formed at the bottom of trench 150. When forming trench 150 for the source / drain regions, an etching process can etch the bottom of the trench to a depth below the lowest sacrificial semiconductor nanostructure 142 and into the substrate 102. The epitaxial growth process used to form the epitaxial regions 118a-118d provides semiconductor material in the recessed portions of the substrate 102.

[0078] Epitaxial semiconductor regions 118a-118d may include intrinsic semiconductor material. Epitaxial semiconductor regions 118a-118d are epitaxially grown from substrate 102. Epitaxial semiconductor regions 118a-118d may include the same material as semiconductor substrate 102. In an example where substrate 102 is Si, epitaxial regions 118a-118d may include intrinsic Si. In some embodiments, while semiconductor substrate 102 may be doped, epitaxial semiconductor regions 118a-118d are not doped. Epitaxial semiconductor regions 118a-118d can be considered as part of semiconductor substrate 102. Epitaxial semiconductor regions 118a-118d correspond to a regrowth portion of semiconductor substrate 102 etched during trench 150 formation. Other processes and materials may be used for epitaxial semiconductor regions 118a-118d without departing from the scope of the invention.

[0079] exist Figure 2D In this process, mask 152 has been formed and patterned on integrated circuit 100. After patterning, mask 152 covers the regions of transistors 104a and 104b. Mask 152 may include conductive materials, such as titanium, aluminum, tungsten, or other conductive materials. Mask 152 may include dielectric materials, such as silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, or other suitable dielectric materials. Mask 152 can be deposited using ALD, PVD, CVD, or other processes. Mask 152 can be patterned using photolithography. Although in Figure 2D It is not shown in the view, but mask 152 may also be formed on the exposed portion of trench isolation area 134.

[0080] exist Figure 2DIn this process, a second epitaxial growth process is performed. This second epitaxial growth process increases the thickness of the epitaxial semiconductor regions 118c and 118d because these regions are not covered by mask 152. Since the presence of mask 152 blocks epitaxial growth, the epitaxial semiconductor regions 118a and 118b do not increase in thickness or height. The second epitaxial growth process also allows intrinsic semiconductor material to be added to the epitaxial semiconductor regions 118c and 118d.

[0081] In some embodiments, the epitaxial semiconductor regions 118c and 118d have top surfaces that are substantially flush with the top surfaces of the lowest semiconductor nanostructures 106c and 106d. Therefore, the epitaxial semiconductor regions 118c and 118d are in direct contact with the lowest semiconductor nanostructures 106c and 106d. Alternatively, the extension of the epitaxial semiconductor regions 118c and 118d may correspond to the formation of new epitaxial semiconductor regions on top of the epitaxial semiconductor regions 118c and 118d.

[0082] exist Figure 2E In this process, mask 152 has been further patterned to cover only the area of ​​transistor 104b, thereby exposing the previously covered area of ​​transistor 104a. Figure 2E In the process, after further patterning of mask 152, dielectric isolation structure 120a has been formed on the top surface of epitaxial semiconductor region 118a. Dielectric isolation structure 120c has been formed on the top surface of epitaxial semiconductor region 118c. Dielectric isolation structure 120d has been formed on the top surface of epitaxial semiconductor region 118d. Dielectric isolation structures 120a, 120c, and 120d can have the following characteristics: Figure 1A The composition and thickness are described. Due to the presence of mask 152, a dielectric isolation region is not formed at transistor 118b.

[0083] The dielectric isolation structures 120a, 120c, and 120d can be formed using various processes. In one example, the dielectric layer can be deposited overlay over the regions of transistors 104a, 104c, and 104d. The dielectric layer can include silicon nitride, Al2O3, or other suitable dielectric materials. The dielectric layer can have a thickness between 3 nm and 5 nm. The dielectric layer can be deposited using CVD, ALD, PVD, or other processes. Other materials, thicknesses, and deposition processes can be used for the dielectric layer without departing from the scope of the invention.

[0084] After the dielectric layer is deposited, a dopant implantation process can be performed. Dopant atoms bombard integrated circuit 100. The dopant atoms travel essentially in a straight line downwards, allowing them to reach the dielectric layer portion at the bottom of trench 150. The dopant atoms embed themselves into the dielectric layer located at the bottom of trench 150. Because the dopant atoms travel downwards, the dielectric layer portion on the sidewalls of the dummy gate structure 140 does not receive dopant atoms. (The remaining text appears to be unrelated and likely refers to a different process.) Figure 2E As described in further detail, dopant atoms can alter the properties of the dielectric layer located at the bottom of trench 150. Dopant atoms can include ions.

[0085] In some embodiments, the dopant atoms are carbon ions. Therefore, in an example where the dielectric layer is silicon nitride, portions of the dielectric layer and the bottom of trench 150 become SiCN. In another example, the dopant atoms are oxygen ions, causing the dielectric layer portion at the bottom of the trench to become SiON. Other suitable types of ions or particles can be used to make the transformed portion of the dielectric layer relative to the bottom of trench 150 selectively etchable. Therefore, various other materials can be used for the dielectric layer and for the dopant atoms without departing from the scope of the invention. Although Figure 2E The description explains the injection of dopant atoms, but dopant types such as compounds or molecules can be used.

[0086] exist Figure 2E In the trench 150, dielectric isolation structures 120a, 120c, and 120d have been formed from the dielectric layer located at the bottom of the trench 150. The dielectric isolation structures 120a, 120c, and 120d are related to... Figure 2E The dielectric isolation structures 120a, 120c, and 120d are formed during the described ion bombardment process. The formation of the dielectric isolation structures 120a, 120c, and 120d may also include performing a thermal annealing process after ion implantation. The dielectric isolation structures 120a, 120c, and 120d are positioned in direct contact with the epitaxial semiconductor regions 118a, 118c, and 118d located at the bottom of the trench 150.

[0087] The dielectric isolation structures 120a, 120c, and 120d can have a thickness between 1 nm and 15 nm. This thickness can be sufficient to ensure virtually no leakage current, but not so thick as to adversely affect the potential thickness of the source / drain regions to be formed thereon. Other thicknesses can be used without departing from the invention. Other processes and materials can be used to form the dielectric isolation structures 120a, 120c, and 120d.

[0088] exist Figure 2FIn this structure, source / drain regions 110a-110d are formed on dielectric isolation structures 120a, 120c, and 120d and on epitaxial semiconductor region 118b. Source / drain regions 110a-110d can be epitaxially grown from semiconductor nanostructures 106a-106d. Source / drain regions 110a and 110d can be in-situ doped with N-type dopant atoms. The source / drain regions 110a and 110d of N-type transistors 104a and 104d can comprise the same materials as semiconductor nanostructures 106a and 106d. Source / drain regions 110b and 110c can be in-situ doped with P-type dopant atoms. The source / drain regions 110b and 110c of P-type transistors 104b and 104c can comprise the same materials as semiconductor nanostructures 106b and 106c. Alternatively, the source / drain regions 110a-110d may comprise materials different from those of the semiconductor nanostructures 106a-106d. N-type source / drain regions 110a and 110d can be formed in the first epitaxial growth step. P-type source / drain regions 110b and 110c can be formed in the second epitaxial growth step. Although in Figure 2F It is not shown in the diagram, but since the epitaxial region 118d is higher than the epitaxial region 118a, it is possible for the source / drain region 110d to be higher than the source / drain region 110a. Although in Figure 2F It is not shown in the figure, but since the epitaxial region 118c is higher than the epitaxial region 118b, the source / drain region 110c can be higher than the source / drain region 110b.

[0089] Source / drain regions 110a, 110c, and 110d are located directly above the top of dielectric isolation structures 120a, 120c, and 120d. Source / drain region 110b is formed directly above epitaxial semiconductor region 118b.

[0090] exist Figure 2G In the process, the processing of transistors 104a-104d is completed. Figure 2G The transistors 104a-104d correspond to Figure 1A Transistors 104a-104d. The polysilicon layer 144 and dielectric layers 146 and 148 of the dummy gate structure 140 have been removed. After the removal of the polysilicon layer 144, the sacrificial semiconductor nanostructure 142 is removed using an etching process that selectively removes the sacrificial semiconductor nanostructure 142 relative to the semiconductor nanostructures 106a-106d.

[0091] After the sacrificial semiconductor nanostructure 142 is removed, the gap remains at the location where the sacrificial semiconductor nanostructure 142 was. Semiconductor nanostructures 106a-106d are exposed. A gate dielectric layer (not shown) is deposited around the semiconductor nanostructures 106a-106d. The gate dielectric layer may include an interface dielectric layer and a high-k dielectric layer. The interface dielectric layer may include a thickness of... and Silicon oxide is sandwiched between the layers. A high-k dielectric layer is deposited on the interface dielectric layer and may include hafnium oxide. The high-k dielectric layer may have... and The thickness between [the specified values]. The material of the gate dielectric layer can be deposited by ALD, CVD, or PVD. Other structures, materials, thicknesses, and deposition processes can be used for the gate dielectric layer without departing from the scope of this invention.

[0092] After depositing a gate dielectric layer around the semiconductor nanostructures 106a-106d, gate electrodes 108a-108d are formed. The gate metals 108a-108d may include one or more metal layers, including tungsten, copper, aluminum, titanium, gold, tantalum, titanium nitride, tantalum nitride, or other suitable materials. The gate metals 108a-108d can be deposited by ALD, PVD, or CVD. The gate metals 108a-108d fill all remaining space around the semiconductor nanostructures 106a-106d and fill the remaining space vacated by removing the polysilicon layer 144. Other materials, thicknesses, deposition processes, and structures may be used for the gate electrodes 108a-108d without departing from the scope of the invention. In practice, gate metals 108a and 108d may have different compositions than gate metals 108b and 108c. In particular, different numbers of layers and metals can be used for the gate electrodes 108a-108d to achieve the desired threshold voltage for the transistors used in the N-type transistors 104a and 104d and the P-type transistors 104b and 104c.

[0093] Figures 2H-2J According to some embodiments Figure 2G An enlarged view of a portion of transistor 104c. Figures 2H-2J Some potential differences in the relative positions of the source / drain region 110c, the semiconductor nanostructure 106c, the dielectric isolation structure 120c, and the dielectric spacer structure 114 are shown. Transistor 104d can have... Figures 2H-2J The relative positions are similar to those shown in transistor 104c.

[0094] exist Figure 2HIn this configuration, the bottom surface 126c of the source / drain region 110c is substantially flush with the top surface 128c of the lowest semiconductor nanostructure 106c. Correspondingly, the top surface of the dielectric isolation structure 120c is substantially flush with the top surface 128c of the lowest semiconductor nanostructure 106c. This configuration may be undesirable due to the potential risk of current paths between the lowest semiconductor nanostructure 106c and the source / drain region 110c. In practice, the top surface of the dielectric isolation structure 120c may be higher or lower than the top of the lowest semiconductor nanostructure 106c. Additionally, as... Figure 2H As shown, the top of the dielectric isolation structure 120c may or may not be substantially flat.

[0095] exist Figure 2I In the middle, the bottom surface 126c of the source / drain region 110c is lower than the bottom surface 160c of the second lowest semiconductor nanostructure 106c, and higher than the top surface 128c of the lowest semiconductor nanostructure 106c.

[0096] exist Figure 2J In the middle, the bottom surface 126c of the source / drain region 110c is substantially flush with the bottom surface 160c of the second lowest semiconductor nanostructure 106c. In this case, the bottom surface 126c of the source / drain region 110c is substantially flush with the top surface of the dielectric spacer 114.

[0097] In some embodiments, only N-type transistors have a greater number of active semiconductor nanostructures. In other embodiments, only P-type transistors have a greater number of active semiconductor nanostructures. In some embodiments, P-type transistors with a smaller number of active semiconductor nanostructures do not include dielectric isolation structures. In some embodiments, only N-type transistors have a reduced number of active semiconductor nanostructures. In some embodiments, only P-type transistors have a reduced number of active semiconductor nanostructures.

[0098] Figure 2K It is basically similar to Figure 1C The view shown is a cross-sectional view of the integrated circuit 100. Figure 2K In this configuration, a dielectric structure 162 has been formed on one of the hybrid fin structures 136. The dielectric structure 162 electrically isolates the source / drain contact 111d from the source / drain contact 111c. Other dielectric structures 162 may be formed to isolate other source / drain contacts from each other. The dielectric structure 162 may include SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials.

[0099] Figure 2L It is basically similar to Figure 1D The view shown is a cross-sectional view of the integrated circuit 100. Figure 2LIn this configuration, a dielectric structure 164 has been formed on one of the hybrid fin structures 136. The dielectric structure 164 electrically isolates the gate metal 108d from the gate metal 108c. Other dielectric structures 164 may be formed to isolate other gate metals from each other. The dielectric structure 164 may include SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials.

[0100] Figure 3 This is a flowchart of a method 300 for forming an integrated circuit according to some embodiments. Method 300 can utilize... Figure 1A-Figure 2L The described processes, structures, and components. In 302, method 300 includes forming a plurality of first semiconductor nanostructures over a substrate to form a first transistor. An example of the first transistor is... Figure 1A The transistor is 104d. An example of a substrate is... Figure 1A Substrate 102. An example of a first semiconductor nanostructure is Figure 1A The semiconductor nanostructure 106d. In method 300, method 304 includes forming a plurality of second semiconductor nanostructures over a substrate to form a second transistor. An example of a second transistor is... Figure 1A The transistor 104a. An example of a second semiconductor nanostructure is... Figure 1A The semiconductor nanostructure 106a. In 306, method 300 includes growing an epitaxial semiconductor layer over a substrate and contacting the bottom first semiconductor nanostructure of a plurality of first semiconductor nanostructures. An example of the epitaxial semiconductor layer is... Figure 1A The epitaxial semiconductor layer 118d. At 308, method 300 includes forming a first source / drain region of a first transistor above the epitaxial semiconductor layer and contacting the highest first semiconductor nanostructure of a plurality of first semiconductor nanostructures, wherein the first source / drain region has a bottom surface higher than the lowest first semiconductor nanostructure of the first semiconductor nanostructure. An example of the first source / drain region is... Figure 1A The source / drain region is 110d. An example of the bottom surface is... Figure 1A The bottom surface is 126d. In 310, method 300 includes forming a second source / drain region of the second transistor, which contacts all the second semiconductor nanostructures and has a bottom surface lower than the bottom surface of the first source / drain region. An example of the second source / drain region is... Figure 1A The source / drain region is 110a. An example of the bottom surface is... Figure 1A The bottom surface 126a.

[0101] Embodiments of the present invention provide integrated circuits with nanostructured transistors having different effective channel widths while having substantially the same area consumption. Each transistor has multiple stacked nanostructures corresponding to a channel region of the transistor. The effective channel width of each transistor corresponds to the combined width of the stacked nanostructures. Each transistor initially has the same number of stacked nanostructures. The effective channel width of the transistor is adjusted by forming source / drain regions to connect only to a selected number of stacked nanostructures. The depth of the source / drain regions is controlled by selectively performing an epitaxial growth that effectively extends the substrate height in the region connecting fewer channels to the source / drain regions. The greater the number of nanostructures connected to the transistor's source / drain regions, the larger the effective channel width of the transistor.

[0102] As described above, selectively controlling the effective channel width enables the formation of transistors or transistor groups with specific characteristics. For example, low-power devices can be formed by reducing the number of channels connected to the source / drain regions. Higher-speed devices can be formed by connecting more channels to the source / drain regions. Furthermore, transistors with different effective channel widths can occupy substantially the same amount of substrate area. The result is an integrated circuit with dedicated high-speed and low-power devices without increasing design complexity or area loss. Device performance and wafer yield are improved.

[0103] In some embodiments, an integrated circuit includes a substrate and a first transistor located above the substrate. The first transistor includes: a plurality of stacked first semiconductor nanostructures corresponding to a channel region of the first transistor; and a first source / drain region contacting each of the first semiconductor nanostructures. The integrated circuit includes a second transistor located above the substrate. The second transistor includes: a plurality of stacked second semiconductor nanostructures; and a second source / drain region contacting the highest second semiconductor nanostructure of the second semiconductor nanostructures and having a bottom surface higher than the lowest second semiconductor nanostructure of the second semiconductor nanostructures.

[0104] In some embodiments, the first transistor includes: a first epitaxial semiconductor layer extending from a substrate below a first source / drain region and having a top surface of a lowest first semiconductor nanostructure below the first semiconductor nanostructure; and a first dielectric isolation structure located between the first epitaxial semiconductor layer and the second source / drain region; and the second transistor includes: a second epitaxial semiconductor layer located on a substrate below the second source / drain region and in contact with the lowest second semiconductor nanostructure; and a second dielectric isolation structure located between the second epitaxial semiconductor layer and the second source / drain region.

[0105] In some embodiments, the first transistor and the second transistor are N-type transistors.

[0106] In some embodiments, the first transistor includes: a first epitaxial semiconductor layer extending from a substrate below a first source / drain region and having a top surface of a lowest first semiconductor nanostructure below the first semiconductor nanostructure and in contact with the first source / drain region; and the second transistor includes: a second epitaxial semiconductor layer extending upward from a substrate below a second source / drain region and in contact with a lowest second semiconductor nanostructure; and a dielectric isolation structure located between the second epitaxial semiconductor layer and the second source / drain region.

[0107] In some embodiments, the first transistor and the second transistor are P-type transistors.

[0108] In some embodiments, the highest second semiconductor nanostructure is the channel region of the second transistor, wherein the lowest second semiconductor nanostructure is not used as the channel region of the second transistor.

[0109] In some embodiments, the first transistor includes a first gate metal surrounding each first semiconductor nanostructure; and the second transistor includes a second gate metal surrounding each second semiconductor nanostructure.

[0110] In some embodiments, the same number of first semiconductor nanostructures and second semiconductor nanostructures are present.

[0111] In some embodiments, the second transistor includes: a gate metal surrounding each second semiconductor nanostructure; a plurality of dielectric internal spacer structures, each positioned adjacent to the gate metal located between a respective pair of second semiconductor nanostructures; an epitaxial semiconductor layer extending from a substrate below the second source / drain region and contacting the lowest second semiconductor nanostructure; and a dielectric isolation structure located between the epitaxial semiconductor layer and the second source / drain region and contacting at least one dielectric internal spacer structure.

[0112] In some embodiments, the bottom surface of the second source / drain region is higher than the top surface of at least one dielectric isolation structure.

[0113] In some embodiments, a method includes: forming a plurality of first semiconductor nanostructures of a first transistor over a substrate; and forming a plurality of second semiconductor nanostructures of a second transistor over the substrate. The method includes growing an epitaxial semiconductor layer over the substrate and contacting a bottom first semiconductor nanostructure of the plurality of first semiconductor nanostructures; and forming a first source / drain region of the first transistor over the epitaxial semiconductor layer and contacting a top first semiconductor nanostructure of the plurality of first semiconductor nanostructures. The first source / drain region has a bottom surface higher than the bottom surface of the lowest first semiconductor nanostructure of the first semiconductor nanostructures. The method includes forming a second source / drain region of the second transistor, which contacts all the second semiconductor nanostructures and has a bottom surface lower than the bottom surface of the first source / drain region.

[0114] In some embodiments, the above method includes: forming a first gate metal around each first semiconductor nanostructure; and forming a second gate metal around each second semiconductor nanostructure.

[0115] In some embodiments, the method further includes: forming a mask over a substrate; patterning the mask to expose a substrate adjacent to a first transistor and cover a substrate adjacent to a second transistor; and forming an epitaxial semiconductor layer while the mask covers the substrate adjacent to the second transistor.

[0116] In some embodiments, the method further includes: forming a dielectric isolation structure on an epitaxial semiconductor layer by performing a doping implantation process; and forming a first source / drain region on the dielectric isolation structure.

[0117] In some embodiments, an integrated circuit includes a substrate and a first transistor located above the substrate. The first transistor includes: a plurality of stacked first semiconductor nanostructures; a first gate metal surrounding each first semiconductor nanostructure; and a first source / drain region contacting the highest first semiconductor nanostructure and electrically isolated from the lowest first semiconductor nanostructure.

[0118] In some embodiments, the first transistor includes an epitaxial semiconductor layer located between a substrate and a first source / drain region and in contact with a lowest first semiconductor nanostructure.

[0119] In some embodiments, the first transistor includes a dielectric isolation structure located between an epitaxial semiconductor layer and a first source / drain region.

[0120] In some embodiments, the integrated circuit further includes a second transistor located above the substrate, and the second transistor includes: a plurality of stacked second semiconductor nanostructures corresponding to the channel region of the second transistor; and a second source / drain region in contact with each second semiconductor nanostructure.

[0121] In some embodiments, the bottom surface of the second source / drain region is lower than the bottom surface of the first source / drain region.

[0122] In some embodiments, the vertical dimension of the second source / drain region is greater than the vertical dimension of the first source / drain region.

[0123] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, comprising: Substrate; A first transistor, located above the substrate, includes: a plurality of stacked first semiconductor nanostructures corresponding to a channel region of the first transistor; and a first source / drain region in contact with each of the first semiconductor nanostructures; a first epitaxial semiconductor layer embedded in the substrate and located below the first source / drain regions, the first epitaxial semiconductor layer having a top surface below the lowest first semiconductor nanostructure and comprising a first intrinsic semiconductor material; and A second transistor, located above the substrate, includes: a plurality of stacked second semiconductor nanostructures; a second source / drain region in contact with the highest second semiconductor nanostructure of the second semiconductor nanostructures and having a bottom surface higher than the lowest second semiconductor nanostructure of the second semiconductor nanostructures; a second epitaxial semiconductor layer on the substrate below the second source / drain region, the second epitaxial semiconductor layer comprising a second intrinsic semiconductor material; and a second dielectric isolation structure located above the second epitaxial semiconductor layer and separating the second epitaxial semiconductor layer from the second source / drain region.

2. The integrated circuit according to claim 1, wherein: The first transistor further includes a first dielectric isolation structure located above the first epitaxial semiconductor layer and separating the first epitaxial semiconductor layer from the second source / drain.

3. The integrated circuit of claim 2, wherein, The first transistor and the second transistor are N-type transistors.

4. The integrated circuit of claim 1, wherein, The first epitaxial semiconductor layer is in contact with the first source / drain region.

5. The integrated circuit of claim 4, wherein, The first transistor and the second transistor are P-type transistors.

6. The integrated circuit of claim 1, wherein, The highest second semiconductor nanostructure is the channel region of the second transistor, wherein the lowest second semiconductor nanostructure is not used as the channel region of the second transistor.

7. The integrated circuit according to claim 1, wherein: The first transistor includes a first gate metal surrounding each of the first semiconductor nanostructures; and The second transistor includes a second gate metal surrounding each of the second semiconductor nanostructures.

8. The integrated circuit of claim 1, wherein, There are equal numbers of the first semiconductor nanostructure and the second semiconductor nanostructure.

9. The integrated circuit of claim 1, wherein, The second transistor includes: Gate metal surrounds each of the second semiconductor nanostructures; Multiple dielectric internal spacer structures are each positioned adjacent to the gate metal located between a corresponding pair of second semiconductor nanostructures; Wherein, the second epitaxial semiconductor layer is in contact with the lowest second semiconductor nanostructure; and The second dielectric isolation structure is in contact with at least one of the dielectric internal spacer structures.

10. The integrated circuit of claim 9, wherein, The bottom surface of the second source / drain region is higher than the top surface of the at least one dielectric isolation structure.

11. An integrated circuit, comprising: Substrate; as well as A first transistor, located above the substrate, includes: a plurality of stacked first semiconductor nanostructures; a first gate metal surrounding each of the first semiconductor nanostructures; and a first source / drain region contacting the highest first semiconductor nanostructure of the first semiconductor nanostructures and electrically isolated from the lowest first semiconductor nanostructure of the first semiconductor nanostructures, the first source / drain region comprising a doped semiconductor material; and an epitaxial semiconductor layer located between the substrate and the first source / drain regions, the epitaxial semiconductor layer comprising an intrinsic semiconductor material.

12. The integrated circuit according to claim 11, wherein, The epitaxial semiconductor layer and the substrate comprise the same semiconductor material.

13. The integrated circuit according to claim 11, wherein, The first transistor includes a dielectric isolation structure located between the epitaxial semiconductor layer and the first source / drain region.

14. The integrated circuit of claim 11, comprising a second transistor located above the substrate, and the second transistor comprising: Multiple stacked second semiconductor nanostructures correspond to the channel region of the second transistor; as well as The second source / drain region is in contact with each of the second semiconductor nanostructures.

15. The integrated circuit according to claim 14, wherein, The bottom surface of the second source / drain region is lower than the bottom surface of the first source / drain region.

16. The integrated circuit of claim 15, wherein the vertical dimension of the second source / drain region is greater than the vertical dimension of the first source / drain region.

17. A method for forming an integrated circuit, comprising: Multiple first semiconductor nanostructures are formed above the substrate to form the first transistor; Multiple second semiconductor nanostructures of a second transistor are formed above the substrate; An epitaxial semiconductor layer is grown over the substrate, and the epitaxial semiconductor layer is in contact with the bottom first semiconductor nanostructure of the plurality of first semiconductor nanostructures; A first source / drain region of the first transistor is formed above the epitaxial semiconductor layer, and the first source / drain region is in contact with the highest first semiconductor nanostructure of the plurality of first semiconductor nanostructures, wherein the first source / drain region has a bottom surface higher than the lowest first semiconductor nanostructure of the first semiconductor nanostructure; and A second source / drain region is formed in contact with all the second semiconductor nanostructures, and the second source / drain region has a bottom surface that is lower than the bottom surface of the first source / drain region. The epitaxial semiconductor layer is located between the substrate and the first source / drain region, and the epitaxial semiconductor layer comprises an intrinsic semiconductor material.

18. The method of claim 17, comprising: A first gate metal is formed around each of the first semiconductor nanostructures; as well as A second gate metal is formed around each of the second semiconductor nanostructures.

19. The method of claim 18, further comprising: A mask is formed over the substrate; The mask is patterned to expose the substrate adjacent to the first transistor and cover the substrate adjacent to the second transistor; as well as The epitaxial semiconductor layer is formed while the mask covers the substrate adjacent to the second transistor.

20. The method of claim 19, further comprising: A dielectric isolation structure is formed on the epitaxial semiconductor layer by implementing a doping implantation process; as well as The first source / drain region is formed on the dielectric isolation structure.

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