Semiconductor device, method of manufacturing the same, and sensing method using the same

Abstract

A semiconductor device, a method of manufacturing the same, and a sensing method using the same includes a semiconductor fin, an isolation structure, a gate structure, a source / drain structure, a sensing contact, a sensing pad structure, and a read contact. The semiconductor fin includes a channel region and source / drain regions on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is over the channel region of the semiconductor fin. The source / drain structure is over the source / drain regions of the semiconductor fin, respectively. The sensing contact is directly over the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The read contact is directly over the isolation structure and adjacent to the gate structure.

Description

Technical Field

[0001] Some embodiments disclosed herein relate to a semiconductor device including a floating gate, a method of manufacturing the semiconductor device, and a sensing method using the semiconductor device. Background Technology

[0002] The semiconductor integrated circuit industry has experienced rapid growth over the past few decades. Technological advancements in semiconductor materials and design have led to increasingly smaller and more complex circuits. These advancements in materials and design have become possible because of advancements in the technologies associated with processing and manufacturing. Throughout the development of semiconductors, the number of interconnect devices per unit area has increased as the minimum reliably achievable component size has shrunk.

[0003] As dimensions shrink, maintaining the reliability and yield of patterning processes becomes increasingly challenging. In some cases, optical proximity correction and adjustments to lithography parameters (such as process duration, wavelength, focus, and light intensity) can mitigate some defects. However, the currents and systems used to pattern material layers in semiconductor wafers are not entirely satisfactory. Summary of the Invention

[0004] According to some embodiments, a semiconductor device includes a semiconductor fin, an isolation structure, a gate structure, a source / drain structure, a sensing contact, a sensing pad structure, and a read contact. The semiconductor fin includes a channel region and source / drain regions located on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is located above the channel region of the semiconductor fin. The source / drain structures are respectively located above the source / drain regions of the semiconductor fin. The sensing contact is located directly above the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The read contact is located directly above the isolation structure and adjacent to the gate structure.

[0005] According to some embodiments, a method of manufacturing a semiconductor device includes: forming an isolation structure over a substrate to define an active region in the substrate; forming a gate structure over the active region; forming source / drain structures on opposite sides of the active region and the gate structure; depositing an interlayer dielectric (ILD) layer over the substrate and surrounding the gate structure; forming a first opening, a second opening, and a third opening in the ILD layer, such that the first opening exposes the active region, while the second and third openings expose the isolation structure; forming source / drain contacts in the first opening, a read contact in the second opening, and a sense contact in the third opening; and forming an interconnect structure over the gate structure and the sense contacts. The interconnect structure includes a sense pad connected to the sense contacts.

[0006] According to some embodiments, a sensing method for a semiconductor device includes: initializing the potential of a gate structure of a semiconductor detector. The semiconductor detector includes a gate structure, an isolation structure, a readout contact, a sensing contact, and a sensing pad. The gate structure is located above a semiconductor fin. The isolation structure surrounds the semiconductor fin. The readout contact is located on the isolation structure and adjacent to the gate structure. The sensing contact is located on the isolation structure and adjacent to the gate structure. The sensing pad is located on the sensing contact and connected to the sensing contact. A pre-exposure readout operation is performed on the semiconductor detector. After initializing the potential of the gate structure of the semiconductor detector, an electron beam is projected onto the sensing pad of the semiconductor detector. A post-exposure readout operation is performed on the semiconductor detector. Data from the pre-exposure readout operation and the post-exposure readout operation are compared. The intensity of the electron beam is adjusted based on the comparison data from the pre-exposure readout operation and the post-exposure readout operation. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of a semiconductor detector according to some embodiments;

[0009] Figure 2 To illustrate some embodiments according to this disclosure Figure 1 A schematic circuit diagram of a semiconductor detector;

[0010] Figure 3 To illustrate some embodiments according to this disclosure Figure 2 A schematic circuit diagram of a semiconductor detector during programming operations;

[0011] Figure 4 To illustrate some embodiments according to this disclosure Figure 2 A schematic circuit diagram of a semiconductor detector in an erasure operation;

[0012] Figure 5 To illustrate some embodiments according to this disclosure Figure 2 A schematic circuit diagram of a semiconductor detector during a read operation;

[0013] Figure 6 This is an example of the IV characteristics of bit lines in a detector cell before and after electron beam sensing operation.

[0014] Figure 7 A perspective view of a semiconductor detector according to some embodiments;

[0015] Figure 8 To illustrate some embodiments according to this disclosure Figure 7 A schematic circuit diagram of a semiconductor detector;

[0016] Figure 9 A perspective view of a semiconductor detector according to some embodiments;

[0017] Figures 10 to 17C Methods for manufacturing a semiconductor detector at various stages according to some embodiments of this disclosure are shown;

[0018] Figure 18A A perspective view of a semiconductor detector according to some embodiments;

[0019] Figure 18B For along Figure 18A A cross-sectional view taken from line II;

[0020] Figure 18C For along Figure 18A A cross-sectional view taken from line II-II;

[0021] Figure 19 A schematic diagram of an electron beam system for implementing one or more embodiments of the present disclosure;

[0022] Figure 20 This is a flowchart of a method for detecting the optical uniformity of an electron beam, according to various embodiments of the present disclosure.

[0023] [Symbol Explanation]

[0024] 12, 14, 16, 18: Lines

[0025] 100, 100a~100h: Unit cell

[0026] 110:Substrate

[0027] 120: Semiconductor Fin

[0028] 130: Isolation Structure

[0029] 140: Gate structure

[0030] 150: First source / drain structure

[0031] 155: Second source / drain structure

[0032] 160: Read contact

[0033] 161, 171: Inner surface

[0034] 170, 170a~170h: Sensing contacts

[0035] 180: Sensing pad structure

[0036] 182, 182a~182h: Sensing pads

[0037] 184, 184a~184h: Sensing through-holes

[0038] 190, 195: Source / Drain Contacts

[0039] 200, 300: Semiconductor detectors

[0040] 402: Trench

[0041] 410:Substrate

[0042] 412: P-trap

[0043] 413:M-well

[0044] 414, 416: Source / Drain Regions

[0045] 420: Semiconductor Fin

[0046] 430: Isolation Structure

[0047] 440: Gate structure

[0048] 442: Gate dielectric layer

[0049] 444: Work function metal layer

[0050] 446: Filler metal

[0051] 450, 455: Source / drain epitaxial structure

[0052] 460: Read Contacts

[0053] 462, 472, 492: Top surface

[0054] 470: Sensing Contact

[0055] 480: Sensing pad structure

[0056] 482: Sensing pad

[0057] 484: Sensing via

[0058] 486: Conductive via

[0059] 490, 495: Source / Drain Contacts

[0060] 492, 497: Metal alloy layer

[0061] 540: Pseudo-gate structure

[0062] 542: Pseudo-gate dielectric layer

[0063] 544: Pseudo-gate electrode

[0064] 546: Oxide Shielding Layer

[0065] 548: Nitride shroud layer

[0066] 550: Gate spacer

[0067] 552: First Spacing Layer

[0068] 554: Second spacer layer

[0069] 560: Contact Etching Termination Layer

[0070] 565: Interlayer dielectric layer

[0071] 570: Multilayer interconnect structure

[0072] 572: Metallization layer

[0073] 573: Intermetallic Dielectric Layer

[0074] 574: Etching stop layer

[0075] 700: Electron Beam System

[0076] 710: Chamber

[0077] 720: Electronic Source

[0078] 722: Electron Beam

[0079] 730: Electro-optical Module

[0080] 732: Electromagnetic port

[0081] 734: Electrostatic Lens

[0082] 740: Wafer Stage

[0083] 750: Pump Unit

[0084] 760: Modulator

[0085] BL, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8: Bit lines

[0086] D1, D2: Distance

[0087] GND: Grounding

[0088] II, II-II: line

[0089] M10: Method

[0090] O1~O4: Contact openings

[0091] S / D: Source / Drain

[0092] S12, S14, S16, S18, S20, S22, S24: Operations

[0093] +V1~+V3: Positive voltage

[0094] -V1, -V2: Negative voltage

[0095] W: Width

[0096] WL, WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8: Character lines X, Y, Z: Direction Detailed Implementation

[0097] The following disclosure provides many different implementations or examples for achieving various features of the provided object. Specific examples of elements and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include implementations in which the first and second features are in direct contact, and may also include implementations in which an additional feature is formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various implementations or configurations discussed.

[0098] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0099] As used herein, “around,” “approximately,” “close to,” or “substantially” should generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “around,” “approximately,” “close to,” or “substantially” can be inferred. Those skilled in the art will understand that dimensions can vary depending on different technological nodes. They will recognize that dimensions depend on the specific type of device, technological advancements, minimum feature size, etc. Therefore, the terminology is intended to be interpreted in relation to the technology being evaluated.

[0100] The advanced lithography processes, methods, and materials described in this disclosure can be used in many applications, including fin-type field-effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacing between features, and the above disclosure is well-suited for this purpose. Furthermore, the spacers used to form the fins of a FinFET can be processed according to the above disclosure.

[0101] This disclosure relates to semiconductor detectors, methods of forming semiconductor detectors, and methods of using semiconductor detectors. More specifically, some embodiments of this disclosure relate to high-density and zero-power semiconductor detectors for detecting electron beam light. In some embodiments, the semiconductor detector may be implemented on a device comprising a planar device, a multi-gate device, a FinFET, a nanosheet gate FET, and an all-around gate FET.

[0102] Figure 1 This is a perspective view of a semiconductor detector according to some embodiments, and Figure 2 To illustrate some embodiments according to this disclosure Figure 1 A schematic circuit diagram of a semiconductor detector. Figure 1 China and Figure 2 The semiconductor detector may include a single unit cell 100. The unit cell 100 of the semiconductor detector includes a substrate 110, at least one active region, an isolation structure 130, a gate structure 140, a first source / drain structure 150, a second source / drain structure 155, at least one read contact 160, at least one sensing contact 170, and a sensing pad structure 180. The active region may be a semiconductor fin 120 protruding from the substrate 110. It should be noted that although... Figure 1 There are four semiconductor fins 120, but the scope of this disclosure is not limited to this. In other embodiments, those skilled in the art can manufacture a suitable number of semiconductor fins 120 for the semiconductor detector as needed.

[0103] The isolation structure 130 is located above the substrate 110 and laterally surrounds the semiconductor fin 120. That is, the bottom portion of the semiconductor fin 120 is embedded in the isolation structure 130. The isolation structure 130 may be a shallow trench isolation (STI) region.

[0104] The gate structure 140 is located above the isolation structure 130 and intersects with the semiconductor fin 120. The portion of the semiconductor fin 120 covered by the gate structure 140 is referred to as the channel portion of the semiconductor fin 120. In some embodiments, there are no physically connected conductive elements to the gate structure 140, such that the gate structure 140 may be referred to as a floating gate.

[0105] The first source / drain structure 150 and the second source / drain structure 155 are located above the semiconductor fin 120 and on opposite sides of the gate structure 140. Therefore, one of the first source / drain structure 150 and the second source / drain structure 155 serves as the source terminal, and the other of the first source / drain structure 150 and the second source / drain structure 155 serves as the drain terminal. The portion of the semiconductor fin 120 located below the first source / drain structure 150 and the portion of the semiconductor fin 120 located below the second source / drain structure 155 are referred to as the source / drain portions of the semiconductor fin 120.

[0106] Two read contacts 160 are adjacent to the gate structure 140 and located directly above the isolation structure 130, such that the two read contacts 160 are spaced apart from the semiconductor fin 120. The read contacts 160 are located on opposite sides of the gate structure 140 and further spaced apart from the first source / drain structure 150 and the second source / drain structure 155. The read contacts 160 are connected by a dielectric material (e.g., Figure 15A The gate spacer 550, CESL 560, and / or ILD layer 565 are spaced apart from the gate structure 140. Therefore, the gate structure 140, the read contacts 160, and the dielectric material therebetween form a capacitor. A distance D1 is formed between the read contacts 160 and the gate structure 140, and each read contact 160 has an inner surface 161 facing the gate structure 140. The coupling ratio between the gate structure 140 and the read contacts 160 is determined at least by the distance D1 and the area of ​​the inner surface 161 of the read contacts 160. In some embodiments, the coupling ratio between the gate structure 140 and the read contacts 160 is in the range of about 10% to about 50%. Furthermore, the distance D1 may be less than the width W of the first source / drain structure 150. In some embodiments, the semiconductor detector (cell unit 100) includes a single read contact 160 located on one side of the gate structure 140.

[0107] Two sensing contacts 170 are adjacent to the gate structure 140 and located directly above the isolation structure 130, such that the two sensing contacts 170 are spaced apart from the semiconductor fin 120. The sensing contacts 170 are located on opposite sides of the gate structure 140 and further spaced apart from the first source / drain structure 150 and the second source / drain structure 155. In some embodiments, the sensing contacts 170 and the read contacts 160 are located on opposite sides of the first source / drain structure 150 (or the second source / drain structure 155), such that the first source / drain structure 150 is located between the sensing contacts 170 and the read contacts 160. The sensing contacts 170 are connected by a dielectric material (e.g., Figure 15AThe gate spacer 550, CESL 560, and / or ILD layer 565 are spaced apart from the gate structure 140. Therefore, the gate structure 140, the sensing contact 170, and the dielectric material therebetween form a capacitor. A distance D2 is formed between the sensing contact 170 and the gate structure 140, and each sensing contact 170 has an inner surface 171 facing the gate structure 140. The coupling ratio between the gate structure 140 and the sensing contact 170 is determined at least by the distance D2 and the area of ​​the inner surface 171 of the sensing contact 170. In some embodiments, the coupling ratio between the gate structure 140 and the sensing contact 170 is in the range of about 10% to about 50%. Furthermore, the distance D2 may be less than the width W of the first source / drain structure 150. In some embodiments, the semiconductor detector (cell unit 100) includes a single sensing contact 170 located on one side of the gate structure 140. In addition, the isolation structure 130 is in contact with the reading contact 160, the sensing contact 170 and the semiconductor fin 120.

[0108] Sensing pad structure 180 is electrically connected to sensing contact 170. In some embodiments, sensing pad structure 180 is disposed above sensing contact 170 and gate structure 140. In some embodiments, sensing pad structure 180 includes a plurality of sensing pads 182 and sensing vias 184 between adjacent sensing pads 182. Some sensing vias 184 interconnect adjacent sensing pads 182, and some sensing vias 184 interconnect the bottommost sensing pad 182 and sensing contact 170. Sensing pads 182 and sensing vias 184 are made of conductive material, allowing electrons to flow from sensing pads 182 to sensing contact 170. Furthermore, if the bottommost sensing pad 182 is sufficiently close to gate structure 140, a capacitance can be formed between the bottommost sensing pad 182 and gate structure 140.

[0109] In some embodiments, the sensing pad structure 180 includes a single sensing pad 182 connected to the sensing contact 170 via a sensing via 184. The single sensing pad 182 may be located in the lowest layer (e.g., layer M0) of the sensing pad structure 180. In some other embodiments, depending on various requirements, the single sensing pad 182 may be located in an intermediate layer (e.g., layers M1, M2...) or the top layer (e.g., layer Mn) of the sensing pad structure 180.

[0110] The semiconductor detector (cell 100) also includes a word line WL and a bit line BL. The word line WL is electrically connected to a read contact 160, and the bit line BL is electrically connected to a second source / drain structure 155 (i.e., the drain of cell 100). For example, the bit line BL is connected to the second source / drain structure 155 via a source / drain contact 195. Furthermore, the word line WL is electrically isolated from the gate structure 140. In some embodiments, a first source / drain structure 150 is electrically connected to ground (line) GND, which provides a reference potential (e.g., approximately 0V) to the semiconductor detector via the source / drain contact 190 during programming, erasing, and / or reading processes.

[0111] The semiconductor detector (cell unit 100) has four different states: programming, erasing, sensing, and reading. The semiconductor detector performs these four different states (programming, erasing, sensing, and reading) as follows:

[0112] programming: Figure 3 To illustrate some embodiments according to this disclosure Figure 2 A schematic circuit diagram of a semiconductor detector during programming operation. The programming cycle of the semiconductor detector begins by applying a positive voltage +V1 (e.g., about 8V to about 10V) to the word line WL and a negative voltage -V2 (e.g., about 0.6V to about 0.7V) to the bit line BL. Furthermore, a first source / drain structure 150 is connected to ground GND. Therefore, the gate structure 140 is in a floating state, and an electric field is formed in the gate structure 140, thereby driving electrons to flow from the substrate 110 to the gate structure 140 via tunneling effect, and the electrons can be stored in the gate structure 140.

[0113] Remove: Figure 4 To illustrate some embodiments according to this disclosure Figure 2 A schematic circuit diagram of a semiconductor detector during the erasure operation. The erasure cycle of the semiconductor detector is initiated by applying a negative voltage -V1 (e.g., about 8V to about 10V) to the word line WL and a positive voltage +V2 (e.g., about 0.6V to about 0.7V) to the bit line BL. Furthermore, the first source / drain structure 150 is connected to ground GND. Therefore, the gate structure 140 is in a floating state, and an electric field is formed in the gate structure 140, thereby driving electrons to flow from the gate structure 140 to the substrate 110 via tunneling effect, while there are no electrons in the gate structure 140.

[0114] Sensing: During the sensing cycle of the semiconductor detector, no power is applied to the word line WL, bit line BL, and the first source / drain structure 150, such as... Figure 2As shown. In other words, the semiconductor detector is powerless in sensing mode. When the electron beam is incident on the sensing pad structure 180, the electrons of the electron beam enter the sensing pad structure 180 and flow to the sensing contact 170. An electrical coupling is formed between the sensing contact 170 and the gate structure 140, and the voltage in the gate structure 140 is changed.

[0115] Read: Figure 5 To illustrate some embodiments according to this disclosure Figure 2 A schematic circuit diagram of a semiconductor detector during a read operation. The read cycle of the semiconductor detector begins by applying a varying positive voltage +V3 (e.g., from approximately 0V to approximately 6V) to the word line WL and applying ground GND to the first source / drain structure 150, with the gate structure 140 in a floating state, such that the corresponding current under the varying positive voltage +V3 is read from the bit line BL. Experimental results show that this configuration has no read interference under the positive voltage +V3.

[0116] Figure 6 This is an example of the IV characteristics of the bit lines in a detector cell 100 before and after the electron beam sensing operation. Before the sensing operation, the gate structure 140 is substantially free of electrons, and Figure 6 Line 12 shows the IV curve of cell 100 before sensing operation. Lines 14, 16, and 18 show the IV curves of cell 100 after sensing operation at first, second, and third intensities of electron beam light, respectively. The third intensity is higher than the second intensity, which is higher than the first intensity.

[0117] Figure 7 This is a perspective view of a semiconductor detector 200 according to some embodiments, and Figure 8 To illustrate some embodiments according to this disclosure Figure 7 A schematic circuit diagram of a semiconductor detector 200. In some embodiments, the semiconductor detector 200 includes a plurality of unit cells 100. More detailed, Figure 1 The unit cells 100 in the semiconductor detector 200 can be arranged in an array. That is, multiple unit cells 100 can be arranged in the X and / or Y directions. The semiconductor detector 200 also includes multiple word lines (e.g., word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8). Each word line interconnects the read contacts 160 of the unit cells 100 in the same column (i.e., arranged along the X direction). The semiconductor detector 200 also includes multiple bit lines (e.g., bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, and BL8). Each bit line interconnects the second source / drain structure 155 of the unit cells 100 in the same row (i.e., arranged along the Y direction). For clarity, the word lines and bit lines are... Figure 8As shown in and in Figure 7 The text is omitted. With this configuration, the semiconductor detector 200 can simultaneously collect the electron distribution of the electron beam light in the XY directions. In some other embodiments, Figure 7 Each cell unit 100 in the semiconductor detector 200 contains a single sensing pad structure 180 (which may be located at any height of the respective sensing pad structure 180). Other relevant structural details of the cell unit 100 of the semiconductor detector 200 are as follows: Figure 1 The unit cells 100 of the semiconductor detectors in the text are substantially the same or similar, so they will not be described again in the following text.

[0118] Figure 9 This is a perspective view of a semiconductor detector 300 according to some embodiments. The semiconductor detector 300 includes a plurality of unit cells 100a, 100b, 100c, 100d, 100e, 100f, 100g, and 100h. In addition to the sensing pad structure, each unit cell 100a to 100h has a... Figure 1 The configuration is similar to that of unit cell 100 in the diagram. Figure 9 In this configuration, each unit cell 100a-100h has a sensing pad structure comprising a single sensing pad. More specifically, unit cell 100a includes a sensing pad 182a connected to a sensing contact 170a via a sensing via 184a. Unit cell 100b includes a sensing pad 182b connected to a sensing contact 170b via a sensing via 184b. Unit cell 100c includes a sensing pad 182c connected to a sensing contact 170c via a sensing via 184c. Unit cell 100d includes a sensing pad 182d connected to a sensing contact 170d via a sensing via 184d. Unit cells 100a, 100b, 100c, and 100d are arranged in a two-dimensional array such that unit cells 100a, 100b, 100c, and 100d can simultaneously collect the electron distribution of the electron beam light in the XY direction.

[0119] Furthermore, cell 100e includes a sensing pad 182e connected to sensing contact 170e via sensing via 184e. Cell 100f includes a sensing pad 182f connected to sensing contact 170f via sensing via 184f. Cell 100g includes a sensing pad 182g connected to sensing contact 170g via sensing via 184g. Cell 100h includes a sensing pad 182h connected to sensing contact 170h via sensing via 184h. Sensing pad 182e is located directly above and covers sensing pad 182a, but there is no conductive via between sensing pad 182e and sensing pad 182a. That is, sensing pad 182e and sensing pad 182a are electrically isolated. Sensing pad 182f is located directly above and covers sensing pad 182b, but there is no conductive via between sensing pad 182f and sensing pad 182b. That is, sensing pad 182f is electrically isolated from sensing pad 182b. Sensing pad 182g is located directly above and covers sensing pad 182c, but there is no conductive via between sensing pad 182g and sensing pad 182c. That is, sensing pad 182g is electrically isolated from sensing pad 182c. Sensing pad 182h is located directly above and covers sensing pad 182d, but there is no conductive via between sensing pad 182h and sensing pad 182d. That is, sensing pad 182h is electrically isolated from sensing pad 182d. With this configuration, semiconductor detector 300 can simultaneously collect the electron distribution of electron beam light in the XYZ directions. In some embodiments, semiconductor detector 300 includes more unit cells for detecting different X, Y, and / or Z positions. Other related structural details of the unit cells 100a to 100h of semiconductor detector 300 are as follows... Figure 1 The unit cells 100 of the semiconductor detector are substantially the same or similar, so they will not be described again below.

[0120] Figures 10 to 17C Methods for manufacturing a semiconductor detector at various stages according to some embodiments of this disclosure are illustrated. Besides the semiconductor detector, Figures 10 to 15A , Figure 16A and Figure 17A The X, Y, and Z axes are shown. Figures 10 to 15A , Figure 16A and Figure 17A Perspective view of some implementations of a semiconductor detector in the middle stage of manufacturing. Figure 15B , Figure 16B and Figure 17B This is a cross-sectional view of some embodiments of a semiconductor detector in the middle of the manufacturing process along a first cut (e.g., cut II), which is along the longitudinal direction of the read contact 460 (or sense contact 470). Figure 15C , Figure 16C and Figure 17CThis is a cross-sectional view of some embodiments of a semiconductor detector in the middle of the manufacturing process along a second cut (e.g., cut II-II), which is along the longitudinal direction of the channel (i.e., semiconductor fin 420).

[0121] See Figure 10 A substrate 410 is provided. In some embodiments, the substrate 410 is made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as group IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon carbide germanium (SiGeC), GeSn, SiSn, SiGeSn), group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide, indium phosphide, indium antimonide, gallium arsenide, or indium gallium phosphide), etc. Furthermore, the substrate 410 may include an epitaxial layer that can be strained to enhance performance, and / or may include a silicon-on-insulator (SOI) structure.

[0122] One or more semiconductor fins 420 are formed on the substrate 410. The semiconductor fins 420 may be P-type. That is, each semiconductor fin 420 may include a P-well region 412 (see [link to documentation]). Figure 15C Semiconductor fins 420 can be formed using, for example, patterning processes to create trenches, such that trenches are formed between adjacent semiconductor fins 420. As discussed in more detail below, semiconductor fins 420 will be used to form a FinFET. It should be understood that four semiconductor fins 420 are shown for illustrative purposes, but other embodiments may include any number of semiconductor fins. In some embodiments, one or more dummy semiconductor fins are formed adjacent to the semiconductor fins 420.

[0123] Semiconductor fins 420 can be formed by performing an etching process on substrate 410. Specifically, a patterned hard mask structure is formed over substrate 410. In some embodiments, the patterned hard mask structure is formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc. For example, the patterned hard mask structure includes an oxide pad layer and a nitride mask layer located above the oxide pad layer. The patterned hard mask structure covers a portion of substrate 410 but not another portion of substrate 410. The patterned hard mask structure is then used as a mask to pattern substrate 410 to form trenches 402. Thus, semiconductor fins 420 are formed.

[0124] An isolation structure 430, such as shallow trench isolation (STI), is disposed in the trench 402 and above the substrate 410. In some embodiments, the isolation structure 430 may be equivalently referred to as an insulating layer. The isolation structure 430 may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon oxide-doped low-k dielectrics, very low-k dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimide, and combinations thereof. In some embodiments, the isolation structure 430 is formed via processes such as CVD, flowable CVD (FCVD), or spin-coating glass processes, but any acceptable process may be used. Subsequently, portions of the isolation structure 430 extending above the top surface of the semiconductor fin 420 are removed using processes such as etch-back, chemical mechanical polishing (CMP), etc.

[0125] The isolation structure 430 is then recessed to expose the upper portion of the semiconductor fin 420. In some embodiments, the isolation structure 430 is recessed using a single etching process or a multi-etching process. In some embodiments where the isolation structure 430 is made of silicon oxide, the etching process may be, for example, dry etching, chemical etching, or wet cleaning. For example, chemical etching may use fluorinated chemicals, such as dilute hydrofluoric acid (dHF).

[0126] See Figure 11 After forming the semiconductor fin 420 and the isolation structure 430, at least one dummy gate structure 540 is formed above the substrate 410 and at least partially disposed above the semiconductor fin 420. The portion of the semiconductor fin 420 below the dummy gate structure 540 may be referred to as channel region C (see [link to documentation]). Figure 17C and Figure 18C Furthermore, the semiconductor fin 420 can be referred to as the channel layer. The pseudo-gate structure 540 can also define the source / drain region S / D of the semiconductor fin 420 (see [link]). Figure 17C and Figure 18C For example, the region of semiconductor fin 420 adjacent to channel region C and located on opposite sides of channel region C.

[0127] The dummy gate formation operation first forms a dummy gate dielectric layer over the semiconductor fin 420. Subsequently, a dummy gate electrode layer and a hard mask, which may comprise multiple layers (e.g., oxide and nitride layers), are formed over the dummy gate dielectric layer. The hard mask is then patterned into a nitride mask layer 548 and an oxide mask layer 546, and subsequently, the dummy gate electrode layer is patterned into a dummy gate electrode 544 using the nitride mask layer 548 and the oxide mask layer 546 as an etching mask. In some embodiments, after patterning the dummy gate electrode layer, the dummy gate dielectric layer is removed from the S / D region of the semiconductor fin 420 and serves as the dummy gate dielectric layer 542. The etching process may include wet etching, dry etching, and / or combinations thereof. The etching process is selected to selectively etch the dummy gate dielectric layer while substantially not etching the semiconductor fin 420, the dummy gate electrode layer 544, the oxide mask layer 546, and the nitride mask layer 548.

[0128] In some implementations, the lightly-doped-drain (LDD) source / drain regions 414 and 416 (see...) Figure 15C The dopant is formed in the source / drain portions of the semiconductor fin 420. For example, at least one implantation process is performed such that the dopant is implanted in the source / drain portions of the semiconductor fin 420 to form LDD source / drain regions 414 and 416. The pseudo-gate structure 540 serves as a mask for the ion implantation.

[0129] After the formation of the dummy gate structure 540 (or the formation of LDD source / drain regions 414 and 416) is completed, a gate spacer 550 is formed on the sidewalls of the dummy gate structure 540. In some embodiments of the gate spacer formation operation, a spacer material layer is deposited on the substrate 410. The spacer material layer may be a conformal layer, which is subsequently etched back to form the gate spacer 550. In some embodiments, the spacer material layer comprises multiple layers, such as a first spacer layer 552 and a second spacer layer 554 formed above the first spacer layer 552 (see [link to documentation]). Figure 15CBoth the first spacer layer 552 and the second spacer layer 554 are made of suitable materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. By way of example and not limitation, the first spacer layer 552 and the second spacer layer 554 can be formed by sequentially depositing two different dielectric materials over the dummy gate structure 540 using processes such as ALD, plasma-enhanced ALD (PEALD), PECVD, subatmospheric CVD (SACVD), or other suitable processes. An anisotropic etching process is then performed on the first spacer layer 552 and the second spacer layer 554 to expose portions of the semiconductor fin 420 not covered by the dummy gate structure 540 (e.g., in the source / drain regions of the semiconductor fin 420). The portions of the first spacer layer 552 and the second spacer layer 554 located directly above the dummy gate structure 540 can be removed by this anisotropic etching process. For simplicity, portions of the first spacer layer 552 and the second spacer layer 554 on the sidewalls of the dummy gate structure 540 may be retained to form gate sidewall spacers, referred to as gate spacers 550. In some embodiments, the first spacer layer 552 is formed of silicon oxide having a lower dielectric constant than silicon nitride, and the second spacer layer 554 is formed of silicon nitride having higher etch resistance than silicon oxide to subsequent etching processes (e.g., etching source / drain trenches in semiconductor fins 420). In some embodiments, gate spacers 550 may be used to offset subsequently formed doped regions, such as source / drain regions. Gate spacers 550 may be further used to design or modify the source / drain region profiles.

[0130] See Figure 12 After the gate spacer 550 is formed, source / drain epitaxial structures 450 and 455 are formed on the source / drain regions of the semiconductor fin 420 not covered by the pseudo-gate structure 540 and the gate spacer 550. In some embodiments, the formation of the source / drain epitaxial structures 450 and 455 includes recessing the source / drain regions of the semiconductor fin 420 and then epitaxially growing semiconductor material in the recessed source / drain regions of the semiconductor fin 420.

[0131] The source / drain regions of the semiconductor fin 420 can be recessed using a suitable selective etching process. This etching process erodes the semiconductor fin 420 but only erodes the gate spacer 550 and the mask layer 548 of the dummy gate structure 540. For example, the semiconductor fin 420 can be recessed by dry chemical etching with a plasma source and an etchant gas. The plasma source can be inductively coupled plasma (ICP) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), etc., and the etching gas can be fluorine, chlorine, bromine, or combinations thereof. This etching gas etches the semiconductor fin 420 at a faster etch rate than etching the gate spacer 550 and the mask layer 548 of the dummy gate structure 540. In some other embodiments, the semiconductor fin 420 is recessed by wet chemical etching, such as with ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), or combinations thereof, at a faster etching rate than etching the gate spacer 550 and mask layer 548 of the pseudo-gate structure 540. In some other embodiments, the semiconductor fin 420 can be recessed by a combination of dry and wet chemical etching.

[0132] Once a groove is formed in the source / drain region of the semiconductor fin 420, source / drain epitaxial structures 450 and 455 are formed in the source / drain groove of the semiconductor fin 420 by one or more epitaxial techniques or processes that provide one or more epitaxial materials on the semiconductor fin 420. During the epitaxial growth process, gate spacers 550 confine one or more epitaxial materials in the source / drain region of the semiconductor fin 420. In some embodiments, the lattice constants of the source / drain epitaxial structures 450 and 455 are different from the lattice constant of the semiconductor fin 420, such that the channel region in the semiconductor fin 420 and between the source / drain epitaxial structures 450 and 455 can generate strain or stress through the source / drain epitaxial structures 450 and 455 to improve the carrier mobility of the semiconductor device and enhance device performance. Epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes may utilize gaseous and / or liquid precursors that interact with the composition of the semiconductor fin 420.

[0133] In some embodiments, the source / drain epitaxial structures 450 and 455 comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structures 450 and 455 may be in-situ doped during the epitaxial process by introducing dopants comprising: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants comprising combinations thereof. If the source / drain epitaxial structures 450 and 455 are not in-situ doped, a bonding process (i.e., a joint bonding process) is performed to dope the source / drain epitaxial structures 450 and 455. In some exemplary embodiments, the source / drain epitaxial structures 450 and 455 in the n-type transistor comprise SiP.

[0134] Once the source / drain epitaxial structures 450 and 455 are formed, an annealing process can be performed to activate the n-type dopant in the source / drain epitaxial structures 450 and 455. Annealing processes can include, for example, rapid thermal annealing (RTA), laser annealing, and millisecond thermal annealing (MSA).

[0135] See Figure 13An interlayer dielectric (ILD) layer 565 is formed on substrate 410. In some embodiments, a contact etch stop layer (CESL) 560 is also formed prior to the formation of the ILD layer 565. In some embodiments, the CESL 560 comprises a silicon nitride layer, a silicon oxynitride layer, and / or other suitable materials having different etch selectivity than the ILD layer 565. The CESL 560 can be formed by plasma-enhanced chemical vapor deposition (PECVD) and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 565 comprises an oxide such as tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG), and / or other suitable dielectric materials having different etch selectivity than CESL 560. The ILD layer 565 can be deposited using subatmospheric CVD (SACVD), flow-through CVD, or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 565, the wafer is subjected to a high-temperature thermal budget process to anneal the ILD layer 565.

[0136] In some examples, after the formation of the ILD layer 565, a planarization process may be performed to remove excess material from the ILD layer 565. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes portions of the ILD layer 565 (and CESL 560, if present) covering the dummy gate structure 540. In some embodiments, the CMP process also removes the oxide mask layer 546 and the nitride mask layer 548 (e.g., ...). Figure 12 (As shown) and exposes the pseudo-gate electrode 544.

[0137] See Figure 14 Remove the dummy gate electrode 544 and the dummy gate dielectric layer 542 (see [link]). Figure 13This forms a gate trench between the gate spacers 550. The dummy gate electrode 544 and the dummy gate dielectric layer 542 are removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the material in the dummy gate electrode 544 and the dummy gate dielectric layer 542 at a faster etch rate than etching other materials (e.g., gate spacers 550, CESL 560, and / or ILD layer 565).

[0138] Subsequently, a replacement gate structure 440 is formed in the gate trench. The gate structure 440 may be the final gate of a FinFET. The final gate structure may be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, the gate structure 440 forms a gate associated with three sides of the channel region provided by the semiconductor fin 420. In other words, the gate structure 440 surrounds the semiconductor fin 420 on three sides. In various embodiments, the (high-k / metal) gate structure 440 includes a gate dielectric layer 442 lining the gate trench and a gate electrode located above the gate dielectric layer 442. The gate electrode may include a work function metal layer 444 formed on the gate dielectric layer 442 and a fill metal 446 formed above the work function metal layer 444 and filling the remainder of the gate trench. The gate dielectric layer 442 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, the high-k gate dielectric comprises a dielectric material having a high dielectric constant, for example, greater than that of thermally oxidized silicon (~3.9). The work function metal layer 444 and / or fill metal 446 used within the high-k / metal gate structure 440 may comprise metal, metal alloy, or metal silicide. The formation of the high-k / metal gate structure 440 may include multiple deposition processes to form various gate materials, one or more pad layers, and one or more CMP processes to remove excess gate material.

[0139] In some embodiments, the interface layer of the gate dielectric layer 442 may comprise a dielectric material, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 442 may comprise hafnium oxide (HfO2). Alternatively, the gate dielectric layer 442 may comprise other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0140] The work function metal layer 444 may contain a work function metal to provide a suitable work function to the high-k / metal gate structure 440. For an n-type FinFET, the work function metal layer 444 may contain one or more n-type work function metals (N-metals). The n-type work function metals may include, but are not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. The p-type work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the filler metal 446 may exemplary include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0141] Then refer to Figures 15A to 15C ,in Figure 15B For along Figure 15A The cross-sectional view taken from line II, and Figure 15C For along Figure 15AA cross-sectional view taken from line II-II. One or more etching processes are performed to form contact openings O1, O2, O3, and O4 extending through the ILD layer 565 to expose the source / drain epitaxial structures 450, 455, or the isolation structure 430. For example, as... Figure 15B As shown, contact openings O1 and O3 expose the isolation structure 430, and as Figure 15C As shown, contact openings O2 and O4 expose source / drain epitaxial structures 450 and 455, respectively. That is, the depths of contact openings O1 and O3 are greater than the depths of contact openings O2 and O4.

[0142] Then refer to Figures 16A to 16C ,in Figure 16B for Figure 16A The cross-sectional view taken from line II, and Figure 16C for Figure 16A A cross-sectional view taken from line II-II. Read contacts 460 are formed in contact opening O1, sensing contacts 470 are formed in contact opening O3, and source / drain contacts 490 and 495 are formed in contact openings O2 and O4, respectively. As an example, and not a limitation, contact formation includes: depositing one or more conductive materials to overfill contact openings O1, O2, O3, and O4, such that the conductive material contacts the isolation structure 430, and then performing a CMP process to remove excess conductive material outside contact openings O1, O2, O3, and O4. Figure 16B As shown, the top surface 462 of the reading contact 460, the top surface 472 of the sensing contact 470, and the top surface 492 of the source / drain contact 490 are substantially coplanar.

[0143] In some embodiments, metal alloy layers 492 and 497 are formed over source / drain epitaxial structures 450 and 455, respectively, before forming source / drain contacts 490 and 495. Metal alloy layers 492 and 497 may be silicide layers and are formed in contact openings O2 and O4, respectively, via a self-aligned silicide process, and are located over the exposed source / drain epitaxial structures 450 and 455. The silicide process transforms the surface portions of source / drain epitaxial structures 450 and 455 into silicide contacts. The silicide process involves depositing a metal that undergoes a silicide reaction with silicon (Si). To form silicide contacts on source / drain epitaxial structures 450 and 455, a metal blanket is deposited on the source / drain epitaxial structures 450 and 455. After heating the wafer to a temperature at which the metal reacts with the silicon in the source / drain epitaxial structures 450 and 455 to form contacts, the unreacted metal is removed. The silicide contacts remain above the source / drain epitaxial structures 450 and 455, while unreacted metal is removed from other areas. The silicide layer may comprise a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel-platinum silicide, erbium silicide, palladium silicide, and combinations thereof, or other suitable materials. In some embodiments, the metal alloy layers 492 and 497 may comprise germanium.

[0144] Then refer to Figures 17A to 17C ,in Figure 17B For along Figure 17A The cross-sectional view taken from line II, and Figure 17C For along Figure 17A A cross-sectional view taken from line II-II. Figure 16A A multilayer interconnect (MLI) structure 570 is formed on the structure. The MLI structure 570 may contain multiple metallization layers 572. The number of metallization layers 572 can vary according to the design specifications of the semiconductor device. For simplicity, Figure 17B and Figure 17C Eight metallization layers 572 are shown. Each metallization layer 572 includes an inter-metal dielectric (IMD) layer 573 and an etch stop layer 574. For clarity, the IMD layer 573 and the etch stop layer 574 are shown in... Figure 17B and Figure 17C As shown in the figure, while Figure 17A The details are omitted. The metallization layer 572 includes one or more horizontal interconnects, such as word lines WL, bit lines BL, ground lines GND, and sensing pads 482 extending horizontally or laterally in the IMD layer 573, and vertical interconnects, such as sensing vias 484 and conductive vias 486 extending vertically in the IMD layer 573 and passing through the etch stop layer 574. As described above, the sensing pads 482 and sensing vias 484 form a sensing pad structure 480.

[0145] The character line WL, bit line BL, ground line GND, sensing pad 482, sensing via 484, and conductive via 486 can be formed using, for example, a single damascene process, a dual damascene process, or a combination thereof. In some embodiments, the IMD layer 573 may comprise a low-k dielectric material having a k value, for example, less than about 4.0 or even 2.0, disposed between these conductive features. In some embodiments, the IMD layer 573 may be formed from, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or SiO2 formed by any suitable method such as spin coating, chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD). x C y It is made of spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride, and combinations thereof. In some embodiments, the etch stop layer 574 may be made of SiN deposited by CVD or PECVD technology. x SiCN, SiO2, CN, AlO x N y The character line WL, bit line BL, ground line GND, sensing pad 482, sensing via 484, and conductive via 486 may comprise metallic materials such as copper, aluminum, tungsten, and combinations thereof. In some embodiments, the character line WL, bit line BL, ground line GND, sensing pad 482, sensing via 484, and conductive via 486 may further comprise one or more barrier / adhesive layers (not shown) to protect the respective IMD layer 573 from metal diffusion (e.g., copper diffusion) and metal poisoning. The one or more barrier / adhesive layers may comprise titanium, titanium nitride, tantalum, tantalum nitride, etc., and may be formed using physical vapor deposition (PVD), CVD, ALD, etc. Figure 17C As shown, there are no vias for horizontal and / or vertical interconnects between the interconnect MLI structure 570 and the gate structure 440.

[0146] Figure 18A This is a perspective view of a semiconductor detector according to some embodiments. Figure 18B For along Figure 18A The cross-sectional view taken from line II, and Figure 18C For along Figure 18A The cross-sectional view taken from line II-II. Figures 18A to 18C and Figures 17A to 17CThe differences between semiconductor detectors lie in the conductivity type of the semiconductor detector. For example, Figures 17A to 17C The semiconductor detector in the system uses an NMOS configuration, and Figures 18A to 18C The semiconductor detector in the system uses a PMOS configuration. Specifically, in Figure 18C In the substrate 410, a P-well 412 is formed, and an N-well 413 is formed in the P-well 412. The source / drain epitaxial structures 450 and 455 are P-type and are formed in the N-well 413.

[0147] In some embodiments, the source / drain epitaxial structures 450 and 455 comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structures 450 and 455 can be in-situ doped during the epitaxial process by introducing dopants comprising p-type dopants, such as boron or BF2, and / or other suitable dopants comprising combinations thereof. If the source / drain epitaxial structures 450 and 455 are not in-situ doped, a bonding process (i.e., a joint bonding process) is performed to dope the source / drain epitaxial structures 450 and 455. In some exemplary embodiments, the source / drain epitaxial structures 450 and 455 are p-type and comprise GeSnB and / or SiGeSnB.

[0148] The work function metal layer 444 may contain a work function metal to provide a suitable work function to the high-k / metal gate structure 442. For a p-type FinFET, the work function metal layer 444 may contain one or more p-type work function metals (P-metals). P-type work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. Figures 18A to 18C Other relevant structural details of the semiconductor detector in the text are as follows: Figures 17A to 17C The semiconductor detectors used in this study are the same or similar, therefore, this aspect will not be repeated below.

[0149] Figure 19This is a schematic diagram of an electron beam system 700 used to implement one or more embodiments of the present disclosure. According to one or more embodiments of the present disclosure, the electron beam lithography system includes a chamber 710, an electron source 720, an electron optics module 730, a wafer stage 740, a pump unit 750, and a modulator 760. However, the inclusion or omission of other configurations and devices is also possible. In some embodiments, the electron beam system 700 is an electron beam writer or a scanning electron microscope. The electron source 720 is disposed in the chamber 710 and provides electrons emitted from the conductive material (i.e., an electron beam 722) by heating the conductive material to extremely high temperatures, wherein the electrons have sufficient energy to overcome the work function barrier layer and escape from the conductive material (thermal ionization source), or by applying a sufficiently strong electric field to tunnel the barrier layer field (emission source). Electron optics module 730 is disposed in chamber 710 and includes electromagnetic aperture 732, electrostatic (and / or electromagnetic) lens 734, shaping deflector and / or cell selection deflector, and provides multiple Gaussian spot electron beams, variable shape electron beams, and cell projection electron beams. Chamber 710 includes wafer loading and unloading units and provides wafer transport without interrupting system vacuum. Pump unit 750 includes one or more pumps and provides a high vacuum environment for electron beam system 700. Wafer stage 740 is disposed in chamber 710 and includes motor, roller guides, and / or stage, and provides accurate position and movement in the X, Y, and Z directions to the wafer W vacuum-fixed on wafer stage 740 during wafer focusing, leveling, and exposure processes in electron beam system 700. Modulator 760 is used to blank, pulse, or modulate electron beam 722.

[0150] Figure 20 This is a flowchart of a method M10 for detecting the optical uniformity of an electron beam, according to various embodiments of the present disclosure. Method M10 is merely an example and is not intended to limit the present disclosure to the scope expressly described in the claims. Additional operations may be provided before, during, and after method M10, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of the process. Some elements in the drawings have been simplified for clarity and ease of explanation.

[0151] Combination of various operations in method M10 Figures 2 to 5 The discussion will focus on cross-sectional views. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Figure 20 In operation S12, the detector cells of the semiconductor detector are initialized. For example, each gate structure of the detector cell is programmed using a programming process. Figure 3 That is, electrons are injected into the gate structure of the detector unit. Using a programming process, after the initialization process, the electrons in the gate structure of the detector unit can be in a saturated state. Figure 3The description refers to the programming process of the detector cell. Alternatively, each gate structure of the detector cell is programmed using a erase process. Figure 4 That is, electrons are extracted from the gate structure of the detector unit. Using a eraser process, the gate structure of the detector unit can be substantially free of electrons after the initialization (erasure) process. The eraser process for the detector unit is as follows: Figure 4 As shown.

[0152] exist Figure 20 In operation S14, a pre-exposure readout operation is performed. For example, a wafer acceptance test (WAT) is performed on the product wafer to be subjected to an exposure process. The wafer acceptance test includes numerous test items and is part of the IC manufacturing process. The wafer acceptance test is used to determine product quality. During the wafer acceptance test, the semiconductor detector (e.g., ...) is initialized. Figure 1 Semiconductor detector 100 in Figure 7 Semiconductor detector 200 or Figure 9 The semiconductor detector 300 in the middle, and then by executing Figure 5 The process described herein is used to read data from the gate structure of the detector cell of a semiconductor detector. In some implementations, Figure 6 Line 12 in the image represents data obtained from the pre-exposure readout operation.

[0153] exist Figure 20 In operation S16, a sensing operation is performed on the semiconductor detector. In some embodiments, the semiconductor detector is located on the wafer stage of the exposure apparatus (e.g., Figure 19 On the wafer stage 740 of the electron beam system 700 shown. The electron source 720 of the electron beam system 700 is turned on, and the electron beam 722 is incident on, impacted, irradiated, or projected onto the semiconductor detector. The sensing pad structure of the detector cell of the semiconductor detector senses the electron beam and changes the number of electrons in the gate structure. The sensing operation is as follows: Figure 2 As shown.

[0154] exist Figure 20 In operation S18, a post-exposure readout operation is performed. For example, another wafer acceptance test (WAT) is performed on the semiconductor detector. During the wafer acceptance test, by performing... Figure 5 The process described herein reads data from the gate structure of each detector cell of the semiconductor detector again. Figure 6 In the diagram, lines 14, 16, and 18 show the IV curves of the gate structure (at different electron beam intensities) after electron beam sensing operation.

[0155] exist Figure 20In operation S20, the data from the pre-exposure readout operation and the post-exposure readout operation are compared to obtain the intensity. Specifically, by comparing the IV curves of the pre-exposure readout operation and the post-exposure readout operation, the electron change of each gate can be determined, and the corresponding space electron beam intensity can be obtained.

[0156] exist Figure 20 In operation S22, the electron beam distribution of the electron beam system 700 is adjusted based on comparison data. Specifically, the spatial distribution of the electron beam of the semiconductor detector is obtained in operation S20. If a spatial distribution is not desired (e.g., non-uniformity), the parameters of the electron beam system 700 are tuned to form an electron beam with a more uniform spatial distribution. For example, the parameter is the electron beam dose.

[0157] exist Figure 20 In operation S24, the product wafer is processed using a regulated electron beam. For example, the product wafer may be set in... Figure 19 On the wafer stage 740 of the electron beam system 700 shown. Each product wafer contains a photoresist that can be exposed by an adjustable electron beam. The photoresist can then be developed and patterned. The implementation of method M10 improves the patterning quality of the photoresist.

[0158] Based on the above discussion, it is clear that this disclosure offers advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor are specific advantages required for all embodiments. One advantage is that the semiconductor detector is reactive during sensing mode. Another advantage is that the sensing and recording of electron beam intensity are in the same element (i.e., the floating gate), and an additional recorder can be omitted to save layout area. Furthermore, there is only one transistor in the cell, enabling high density and high spatial resolution. Moreover, the semiconductor detector is compatible with semiconductor device (e.g., CMOS) processes. For example, the semiconductor detector can be formed on a semiconductor wafer, allowing it to reflect the intensity distribution of the electron beam on the product wafer. Additionally, the data in the floating gate can be read out using (in-line) wafer acceptance testing, and the data can be fed back in a timely manner to adjust the electron beam intensity.

[0159] According to some embodiments, a semiconductor device includes a semiconductor fin, an isolation structure, a gate structure, a source / drain structure, a sensing contact, a sensing pad structure, and a read contact. The semiconductor fin includes a channel region and source / drain regions located on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is located above the channel region of the semiconductor fin. The source / drain structures are respectively located above the source / drain regions of the semiconductor fin. The sensing contact is located directly above the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The read contact is located directly above the isolation structure and adjacent to the gate structure.

[0160] In some embodiments, one of the source / drain structures is located between the sensing contact and the read contact. In some embodiments, the read contact is spaced apart from the semiconductor fin. In some embodiments, an isolation structure contacts the read contact and the semiconductor fin. In some embodiments, the semiconductor device further includes source / drain contacts connected to one of the source / drain structures, and the top surface of the source / drain contact is substantially coplanar with the top surface of the read contact. In some embodiments, the sensing contact is spaced apart from the semiconductor fin. In some embodiments, an isolation structure contacts the sensing contact and the semiconductor fin. In some embodiments, the semiconductor device further includes source / drain contacts connected to one of the source / drain structures, and the top surface of the source / drain contact is substantially coplanar with the top surface of the sensing contact. In some embodiments, the distance between the gate structure and the read contact is less than the width of one of the source / drain structures. In some embodiments, the semiconductor device further includes word lines connected to the read contact.

[0161] According to some embodiments, a method of manufacturing a semiconductor device includes: forming an isolation structure over a substrate to define an active region in the substrate; forming a gate structure over the active region; forming source / drain structures on opposite sides of the active region and the gate structure; depositing an interlayer dielectric (ILD) layer over the substrate and surrounding the gate structure; forming a first opening, a second opening, and a third opening in the ILD layer, such that the first opening exposes the active region, while the second and third openings expose the isolation structure; forming source / drain contacts in the first opening, a read contact in the second opening, and a sense contact in the third opening; and forming an interconnect structure over the gate structure and the sense contacts. The interconnect structure includes a sense pad connected to the sense contacts.

[0162] In some embodiments, forming source / drain contacts in a first opening, read contacts in a second opening, and sense contacts in a third opening involves filling the first, second, and third openings of the interlayer dielectric layer with a plurality of conductive materials such that the conductive materials contact the isolation structure; removing excess portions of the conductive materials outside the first, second, and third openings of the interlayer dielectric layer to form the source / drain contacts, read contacts, and sense contacts. In some embodiments, an interconnect structure is formed above the gate structure and the sense contacts such that there are no vias in the interconnect structure and the gate structure. In some embodiments, the first, second, and third openings are formed in the interlayer dielectric layer such that the depth of the first opening is greater than the depth of the second opening. In some embodiments, the interconnect structure further includes word lines connected to the read contacts and electrically isolated from the gate structure.

[0163] A sensing method for a semiconductor device includes: initializing the potential of a gate structure of a semiconductor detector. The semiconductor detector includes a gate structure, an isolation structure, a readout contact, a sensing contact, and a sensing pad. The gate structure is located above a semiconductor fin. The isolation structure surrounds the semiconductor fin. The readout contact is located on the isolation structure and adjacent to the gate structure. The sensing contact is located on the isolation structure and adjacent to the gate structure. The sensing pad is located on the sensing contact and connected to the sensing contact. A pre-exposure readout operation is performed on the semiconductor detector. After initializing the potential of the gate structure of the semiconductor detector, an electron beam is projected onto the sensing pad of the semiconductor detector. A post-exposure readout operation is performed on the semiconductor detector. Data from the pre-exposure readout operation and the post-exposure readout operation are compared. The intensity of the electron beam is adjusted based on the comparison data from the pre-exposure readout operation and the post-exposure readout operation.

[0164] In some embodiments, no power is applied to the semiconductor detector during the projection of the electron beam onto the sensing pad of the semiconductor detector. In some embodiments, initializing the potential of the semiconductor detector's gate structure includes applying a positive voltage to the readout contact and applying a negative voltage to the drain of the semiconductor detector. The value of the positive voltage is greater than the value of the negative voltage, and the gate structure is in a floating state during the initialization potential of the semiconductor detector's gate structure. In some embodiments, initializing the potential of the semiconductor detector's gate structure includes applying a negative voltage to the readout contact and applying a positive voltage to the drain of the semiconductor detector. The value of the negative voltage is greater than the value of the positive voltage, and the gate structure is in a floating state during the initialization potential of the semiconductor detector's gate structure. In some embodiments, a post-exposure readout operation of the semiconductor detector includes acquiring a current-voltage profile between the readout contact and the drain of the semiconductor detector.

[0165] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A semiconductor fin includes a channel region and multiple source / drain regions located on opposite sides of the channel region; An isolation structure is laterally surrounding the semiconductor fin; A gate structure is located above the channel region of the semiconductor fin; Multiple source / drain structures are respectively located above the multiple source / drain regions of the semiconductor fin; A sensing contact is located directly above the isolation structure and adjacent to the gate structure; A sensing pad structure is connected to the sensing contact; and A read contact is located directly above the isolation structure and adjacent to the gate structure, wherein a distance between the gate structure and the read contact is less than the width of one of the plurality of source / drain structures.

2. The semiconductor device as claimed in claim 1, characterized in that, One of the plurality of source / drain structures is located between the sensing contact and the reading contact.

3. The semiconductor device as claimed in claim 1, characterized in that, The reading contact is spaced apart from the semiconductor fin.

4. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure contacts the read contact and the semiconductor fin.

5. The semiconductor device as claimed in claim 1, characterized in that, It also includes a source / drain contact connected to one of the plurality of source / drain structures, and a top surface of the source / drain contact is coplanar with a top surface of the read contact.

6. The semiconductor device as claimed in claim 1, characterized in that, The sensing contact is spaced apart from the semiconductor fin.

7. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure is in contact with the sensing contact and the semiconductor fin.

8. The semiconductor device as claimed in claim 1, characterized in that, It also includes a source / drain contact connected to one of the plurality of source / drain structures, and a top surface of the source / drain contact is substantially coplanar with a top surface of the sensing contact.

9. The semiconductor device as claimed in claim 1, characterized in that, The bottom surface of the sensing contact is located below the top surface of the gate structure.

10. The semiconductor device as claimed in claim 1, characterized in that, It also includes a character line that connects to the read contact.

11. A method for manufacturing a semiconductor device, characterized in that, Include: An isolation structure is formed above a substrate to define an active region in the substrate; A gate structure is formed above the active region; Multiple source / drain structures are formed in the active region and on opposite sides of the gate structure; An interphase dielectric layer is deposited on the substrate and around the gate structure; A first opening, a second opening, and a third opening are formed in the interlayer dielectric layer, such that the first opening exposes the active region, the second opening and the third opening expose the isolation structure, and the depth of the first opening is greater than the depth of the second opening. A source / drain contact is formed in the first opening, a read contact is formed in the second opening, and a sensing contact is formed in the third opening; and An interconnect structure is formed above the gate structure and the sensing contact, wherein the interconnect structure includes a sensing pad connected to the sensing contact.

12. The method as described in claim 11, characterized in that, The formation of the source / drain contact in the first opening, the read contact in the second opening, and the sense contact in the third opening includes: The first opening, the second opening, and the third opening of the interlayer dielectric layer are filled with a plurality of conductive materials, such that the plurality of conductive materials are in contact with the isolation structure; and Remove excess portions of the plurality of conductive materials other than the first opening, the second opening and the third opening of the interlayer dielectric layer to form the source / drain contact, the read contact and the sense contact.

13. The method as described in claim 11, characterized in that, The interconnect structure is formed above the gate structure and the sensing contact such that there are no through holes connecting the interconnect structure and the gate structure.

14. The method as described in claim 11, characterized in that, One bottom surface of the sensing contact is located below the top surface of the plurality of source / drain electrodes.

15. The method as described in claim 11, characterized in that, The interconnect structure also includes a word line connected to the read contact and electrically isolated from the gate structure.

16. A sensing method for a semiconductor device, characterized in that, Include: Initialize a potential in a gate structure of a semiconductor detector, wherein the semiconductor detector comprises: The gate structure is located above a semiconductor fin; An isolation structure surrounds the semiconductor fin; A read contact is located on the isolation structure and adjacent to the gate structure; A sensing contact is located on the isolation structure and adjacent to the gate structure; and A sensing pad is located above and connected to the sensing contact; Perform a pre-exposure readout operation on the semiconductor detector; After initializing the potential of the gate structure of the semiconductor detector, an electron beam is projected onto the sensing pad of the semiconductor detector; Perform a post-exposure readout operation on the semiconductor detector, wherein performing the post-exposure readout operation on the semiconductor detector includes acquiring a current-voltage curve between the readout contact and a drain of the semiconductor detector; Compare the data from the pre-exposure read operation and the post-exposure read operation; and The intensity of the electron beam is adjusted based on the comparison data from the pre-exposure readout operation and the post-exposure readout operation.

17. The sensing method as described in claim 16, characterized in that, During the projection of the electron beam onto the sensing pad of the semiconductor detector, no power is applied to the semiconductor detector.

18. The sensing method as described in claim 16, characterized in that, The potential for initializing the gate structure of the semiconductor detector includes: Apply a positive voltage to the read contact; and A negative voltage is applied to a drain of the semiconductor detector, wherein a value of the positive voltage is greater than a value of the negative voltage, and the gate structure is in a floating state during the initialization of the potential of the gate structure of the semiconductor detector.

19. The sensing method as described in claim 16, characterized in that, The potential for initializing the gate structure of the semiconductor detector includes: Apply a negative voltage to the read contact; and A positive voltage is applied to a drain of the semiconductor detector, wherein a value of the negative voltage is greater than a value of the positive voltage, and the gate structure is in a floating state during the initialization of the potential of the gate structure of the semiconductor detector.

20. The sensing method as described in claim 16, characterized in that, The bottom surface of the sensing contact is located below the top surface of the gate structure.

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