Electroluminescent display device and driving method thereof

By introducing a comparison and tracking unit and a digital-to-analog converter into the pixels of the electroluminescent display device, precise tracking and adjustment of the driving current is achieved, the problems of low brightness deviation and compensation performance are solved, and the display performance is significantly improved.

CN115410520BActive Publication Date: 2025-05-06LG DISPLAY CO LTD
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Patent Information

Application Number
CN202210570763.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2021-05-28
Filing Date
2022-05-24
Publication Date
2025-05-06
Estimated Expiration
2042-05-24

AI Technical Summary

Technical Problem

In the conventional electroluminescent display device, the brightness deviation is caused by the difference in driving characteristics between pixels, and the noise problem of the existing compensation technology leads to low compensation performance.

Method used

By introducing a comparison and tracking unit and a digital-to-analog converter in the pixel, the driving current is generated using the sensed data voltage and the reference voltage, and the level of the sensed data voltage is adjusted by the current tracking data until the driving current is within the target current range, thereby improving the sensing performance and compensation performance.

Benefits of technology

The threshold voltage sensing time of the driving element is significantly reduced, the accuracy and efficiency of brightness compensation are improved, and the display performance of the electroluminescent display device is enhanced.

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Abstract

The present disclosure provides an electroluminescent display device and a driving method of the electroluminescent display device. The electroluminescent display device includes: a pixel connected to a data line and a reference voltage line, the pixel including a driving element configured to generate a driving current based on a sensing data voltage provided through the data line and a reference voltage provided through the reference voltage line, and the level of the driving current is proportional to the level of the sensing data voltage; a comparison and tracking circuit configured to predetermine a target current range between a reference low current and a reference high current, and change current tracking data for adjusting the level of the sensing data voltage until the driving current input through the reference voltage line is within the target current range; and a digital-to-analog converter configured to adjust the level of the sensing data voltage to be proportional to the size of the current tracking data and provide the level-adjusted sensing data voltage to the data line.
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Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0069407, filed on May 28, 2021, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to an electroluminescent display device and a driving method thereof. Background Art

[0004] In an electroluminescent display device having an active matrix type, a plurality of pixels each including a light emitting device and a driving element are arranged in a matrix type, and the brightness of an image realized by the pixel is adjusted based on the grayscale of the image data. The driving element controls the pixel current flowing in the light emitting device based on the voltage applied between the gate electrode and the source electrode of the light emitting device (hereinafter referred to as the gate-source voltage). The amount of light emitted by the light emitting device and the brightness of the screen are determined based on the pixel current.

[0005] Since the threshold voltage of the driving element determines the driving characteristics of the pixel, the threshold voltage should be constant in all pixels, but the driving characteristics between pixels may vary due to various reasons such as processing characteristics and degradation characteristics. Such driving characteristic differences lead to brightness deviations, and for this reason, there are limitations in realizing images.

[0006] Compensation techniques for compensating for brightness deviations between pixels have been proposed, but the compensation performance is not high due to noise occurring in a sensing process. Summary of the invention

[0007] In order to overcome the above-mentioned problems of the prior art, the present disclosure may provide an electroluminescent display device and a driving method thereof for improving sensing performance and compensation performance.

[0008] To achieve these objects and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, an electroluminescent display device includes: a pixel connected to a data line and a reference voltage line, the pixel including a driving element configured to generate a driving current based on a sensing data voltage provided through the data line and a reference voltage provided through the reference voltage line, and a level of the driving current is proportional to the level of the sensing data voltage; a comparing and tracking unit configured to predetermine a target current range between a reference low current and a reference high current and change current tracking data for adjusting the level of the sensing data voltage until the driving current input through the reference voltage line is within the target current range; and a digital-to-analog converter configured to adjust the level of the sensing data voltage to be proportional to the size of the current tracking data and provide the level-adjusted sensing data voltage to the data line.

[0009] In another aspect of the present disclosure, a driving method of an electroluminescent display device is provided, the electroluminescent display device including a pixel connected to a data line and a reference voltage line and including a driving element, the driving element being configured to generate a driving current based on a sensing data voltage provided through the data line and a reference voltage provided through the reference voltage line, and wherein a level of the driving current is proportional to a level of the sensing data voltage, the driving method comprising: predetermining a target current range between a reference low current and a reference high current and changing current tracking data for adjusting a level of the sensing data voltage until a driving current input through the reference voltage line is within the target current range; and adjusting a level of the sensing data voltage to be proportional to a size of the current tracking data and providing the level-adjusted sensing data voltage to the data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0011] Figure 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure;

[0012] Figure 2 It is shown that the Figure 1 A diagram of an example of a pixel array in a display panel;

[0013] Figure 3 is a diagram showing a driving system for reducing a threshold voltage sensing time of a driving element in an electroluminescent display device according to an embodiment of the present disclosure;

[0014] Figure 4 Is used to describe Figure 3 A diagram showing a principle of calculating a threshold voltage of a driving element using a specific driving current within a target current range in a driving system;

[0015] Figure 5 It is shown in detail Figure 3 Diagram of the drive system;

[0016] Figure 6 It is shown Figure 5 A diagram of the operating waveform of the drive system;

[0017] Figure 7 It is shown for Figure 5 A diagram of a first source voltage and a second source voltage of a display driver and a sense driver in a driving system of FIG.

[0018] Figure 8 It is shown in Figure 5 A diagram of an example of a current tracking feedback operation performed in a drive system of FIG.

[0019] Fig. 9 It is shown that the Figure 5 A diagram of an example of a current buffer in a drive system of FIG. 1 ; and

[0020] Fig.10 It is shown that by Figure 5 FIG. 1 is a diagram showing the time taken for the threshold voltage of a driving element in a driving system of FIG. 1 to be driven by a driver of FIG. 1 , and a result obtained by comparing the time taken for the threshold voltage of a driving element in a driving system of FIG. 1 with that of the prior art. DETAILED DESCRIPTION

[0021] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be detailed and complete and will fully convey the concepts of the present disclosure to those skilled in the art.

[0022] The advantages and features of the present disclosure and methods for implementing the same will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure detailed and complete, and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0023] The shapes, sizes, ratios, angles, numbers, etc. used to describe the embodiments of the present disclosure disclosed in the accompanying drawings for describing various embodiments of the present disclosure are only exemplary, and the present disclosure is not limited thereto. The same reference numerals represent the same elements throughout. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "comprising", "having", "including", etc. imply that other parts can be added, unless the term "only" is used. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an", and "the" are also intended to include plural forms.

[0024] Even if not explicitly stated, elements of the various embodiments of the present disclosure should be construed as including a range of errors.

[0025] When describing a positional relationship, for example, when the positional relationship between two components is described as "on," "over," "below," and "immediately next to," unless "just" or "directly" is used, one or more other components may be disposed between the two components.

[0026] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0027] Like reference numerals refer to like elements throughout.

[0028] In the present specification, the pixel circuit provided on the substrate of the display panel may be implemented with a thin film transistor (TFT) having an n-type metal oxide semiconductor field effect transistor (MOSFET) structure, but is not limited thereto, and may be implemented with a TFT having a p-type MOSFET structure. The TFT may be a three-electrode element including a gate, a source, and a drain. The source may be an electrode that provides carriers to the transistor. In the TFT, the carriers may start to flow from the source. The drain may be an electrode that enables the carriers to flow out of the TFT. That is, in the MOSFET, the carriers flow from the source to the drain. In an n-type TFT (NMOS), because the carriers are electrons, the source voltage may have a lower voltage than the drain voltage, so that the electrons flow from the source to the drain. In an n-type TFT, because the electrons flow from the source to the drain, the current may flow from the drain to the source. On the other hand, in a p-type TFT (PMOS), because the carriers are holes, the source voltage may be higher than the drain voltage, so that the holes flow from the source to the drain. In a p-type TFT, because holes flow from the source to the drain, current can flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed but switched between them. For example, the source and drain of a MOSFET can be switched between them.

[0029] Furthermore, in the present disclosure, a semiconductor layer of a TFT may be implemented with at least one of an oxide element, an amorphous silicon element, and a polysilicon element.

[0030] In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the gist of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a diagram showing an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 It is shown that the Figure 1 FIG. 1 is a diagram of an example of a pixel array in a display panel.

[0032] Reference Figure 1 and Figure 2 The electroluminescent display device according to an embodiment of the present disclosure may include a timing controller 1, a display panel 10, a driver integrated circuit (IC) 20, a compensation IC 30, a host system 40, a storage device memory 50, and a power supply circuit 60. The gate driving circuit 15 included in the display panel 10 and the data driving circuit 25 embedded in the driver IC 20 may drive the pixels PXL included in the display panel 10.

[0033] The display panel 10 may include a plurality of pixel lines PNL1 to PNL4, and each of the pixel lines PNL1 to PNL4 may include a plurality of pixels PXL and a plurality of signal lines. The "pixel line" described herein may not be a physical signal line, and may represent a group of signal lines and pixels PXL that are adjacent to each other in the extension direction of the gate line. The signal line may include: a plurality of data lines 140 for providing display data voltages and sensing data voltages to the pixels PXL; a plurality of reference voltage lines 150 for providing reference voltages to the pixels PXL; a plurality of gate lines 160 for providing gate signals SCAN to the pixels PXL; and a plurality of first power lines PWL for providing a first source voltage EVDD to the pixels PXL.

[0034] The pixels PXL of the display panel 10 may be arranged in a matrix type to configure a pixel array. Figure 2 Each pixel PXL in the pixel array may be connected to one of the data lines 140, one of the reference voltage lines 150, one of the first power lines PWL, and a first one of the gate lines 160. Figure 2 Each pixel PXL in the pixel array may be connected to a plurality of gate lines 160. Figure 2 Each pixel PXL included in the pixel array may also be supplied with a second source voltage from the power supply circuit 60. The power supply circuit 60 may supply the second source voltage to the pixel PXL through a low-level power supply line or a pad portion.

[0035] The timing controller 1 can generate a gate timing control signal for controlling the operation timing of the gate driving circuit 15 and a data timing control signal for controlling the operation timing of the data driving circuit 25 with reference to the timing signals (e.g., the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE) input from the host system 40.

[0036] The data timing control signal may include a source start pulse, a source sampling clock, and a source output enable signal, but is not limited thereto. The source start pulse may control the data sampling start timing of the drive voltage generating circuit 23. The gate timing control signal may include a gate start pulse and a gate shift clock, but is not limited thereto. The gate start pulse may be applied to the gate stage that generates the first gate output and may activate the operation of the gate stage. The gate shift clock may be commonly input to the gate stage and may be a clock signal for shifting the gate start pulse.

[0037] The timing controller 1 can control the sensing driving timing and the display driving timing of the pixel lines PNL1 to PNL4 of the display panel 10 based on a predetermined sequence, and thus can implement the display driving operation and the sensing driving operation. The display driving operation and the sensing driving operation can be performed differently by the operations of the gate driving circuit 15 and the data driving circuit 25 performed based on the control of the timing controller 1.

[0038] The sensing drive may refer to an operation of applying a sensing data voltage to the pixels PXL including the sensing target pixel line to sense a threshold voltage variation of each of the corresponding pixels PXL and updating a compensation value for compensating for the threshold voltage variation of each of the corresponding pixels PXL based on the sensing result data. In addition, the display drive may refer to an operation of correcting digital image data to be input to the corresponding pixels PXL based on the updated compensation value and applying a display data voltage corresponding to the corrected image data to the corresponding pixels PXL to display the input image on the screen (hereinafter referred to as screen reproduction).

[0039] The display driving operation may be performed in a vertical active period in which the data enable signal is shifted between a logic high level and a logic low level in one frame, and the sensing driving operation may be performed in a vertical blank period other than the vertical active period in one frame. In the vertical blank period, the data enable signal may continuously maintain a logic low level. The sensing driving operation may be performed in a power-on period after a system main power source is applied thereto until before screen reproduction starts, or may be performed in a power-off period after screen reproduction ends until before the system main power source is released.

[0040] The gate driving circuit 15 may be embedded in the display panel 10. The gate driving circuit 15 may be disposed in a non-display area outside a display area where a pixel array is provided. The gate driving circuit 15 may include a plurality of gate stages connected to a gate line 160 of the pixel array. The gate stage may generate a gate signal SCAN for controlling a switching element of the pixel PXL, and may provide the gate signal SCAN to the gate line 160.

[0041] The data driving circuit 25 embedded in the driver IC 20 may include a plurality of comparison and tracking units and a plurality of digital-to-analog converters.

[0042] In display driving, each comparison and tracking unit may provide a reference voltage to the reference voltage line 150, and each digital-to-analog converter may generate a display data voltage and may provide the display data voltage to the data line 140. In display driving, a display driving current may flow in a driving element of the pixel PXL based on the display data voltage and the reference voltage, and a light emitting device of the pixel PXL may emit light using the display driving current, thereby reproducing an image on a screen.

[0043] In the sensing drive, each comparison and tracking unit may provide a reference voltage to the reference voltage line 150, and then, when the driving current input through the reference voltage line 150 is within a predetermined target current range, the gate-source voltage of the driving element included in the corresponding pixel may be calculated as the threshold voltage of the driving element. In the sensing drive, each digital-to-analog converter may adjust the level of the sensing data voltage based on the current tracking data until the driving current input through the reference voltage line 150 is within the target current range, and the level-adjusted sensing data voltage may be transmitted to the data line 140. In the sensing drive, because the level of the driving current satisfying the target current range is much lower than the level of the display driving current, the time taken for sensing is greatly shortened.

[0044] Each comparison and tracking unit of the data driving circuit 25 may convert the detected threshold voltage of the driving element into digital sensing result data, and may provide the digital sensing result data to the memory 50. The storage device memory 50 may be implemented as a flash memory, but is not limited thereto.

[0045] The compensation IC 30 may include a compensation circuit 31 and a compensation memory 32. The compensation memory 32 may transfer the digital sensing result data read from the storage device memory 50 to the compensation circuit 31. The compensation memory 32 may be a random access memory (RAM) (e.g., a double data rate synchronous dynamic RAM (DDR SDRAM)), but is not limited thereto. The compensation circuit 31 may calculate a compensation offset and a compensation gain for each pixel based on the digital sensing result data, correct the digital image data input from the host system 40 based on the calculated compensation offset and compensation gain, and provide the corrected image data to the driver IC 20.

[0046] The power supply circuit 60 may generate various power supply voltages required to drive the electroluminescent display device. The power supply circuit 60 may generate a reference voltage to be provided to the pixel PXL. The power supply circuit 60 may include a pixel power supply regulating circuit that differently generates a first source voltage and a second source voltage to be provided to the pixel PXL in display driving and sensing driving.

[0047] Figure 3 is a diagram illustrating a driving system for reducing a threshold voltage sensing time of a driving element in an electroluminescent display device according to an embodiment of the present disclosure. Figure 4 Is used to describe Figure 3 A diagram showing the principle of calculating the threshold voltage of a driving element using a specific driving current within a target current range in a driving system.

[0048] Reference Figure 3 and Figure 4According to an embodiment of the present disclosure, the electroluminescent display device can adaptively adjust the data voltage based on the tracking operation of the driving current in the sensing drive, thereby reducing the threshold voltage sensing time of the driving element. To this end, the driving system may include a pixel PXL, a comparison and tracking unit CTS, and a digital-to-analog converter DAC.

[0049] The pixel PXL may be connected to the data line 140 and the reference voltage line 150, and may include a driving element and a light emitting device. In the sensing drive, the driving element may be provided with a sensing data voltage through the data line 140, may be provided with a reference voltage through the reference voltage line 150, and may generate a driving current proportional to a voltage difference between the sensing data voltage and the reference voltage. The driving current may be provided to the comparison and tracking unit CTS through the reference voltage line 150, rather than to the light emitting device.

[0050] In addition, in display driving, the driving element may be provided with a display data voltage through the data line 140 and a reference voltage through the reference voltage line 150, and may generate a display driving current proportional to a voltage difference between the display data voltage and the reference voltage. The display driving current may be provided to the light emitting device to allow the light emitting device to emit light.

[0051] The comparison and tracking unit CTS may be connected to the pixel PXL through the reference voltage line 150. The comparison and tracking unit CTS may predetermine a target current range between a reference low current and a reference high current, and may perform a fast tracking feedback operation based on a current comparison operation until a driving current of the pixel PXL input through the reference voltage line 150 is within the target current range, thereby changing the current tracking data TDATA.

[0052] For example, Figure 4 As shown, the horizontal axis represents the gate-source voltage Vgs of the driving element, and the vertical axis represents the drain-source current Ids of the driving element, and in the current characteristic curve where the drain-source voltage Vds of the driving element is Y (where Y is a positive real number) V, the target current range may include the drain-source current Ids having a level of X (where X is a positive real number) nA. In this case, when the drain-source current Ids of the driving element is XnA, the gate-source voltage Vgs of the driving element may be the threshold voltage Vth of the driving element.

[0053] The driving element may be an analog element. Therefore, even when the gate-source voltage Vgs is the threshold voltage Vth, the driving element may not be turned off, and Figure 4As shown, a driving current of XnA can flow in the driving element. Because the level of the driving current is much lower than the level of the display driving current, the time of the fast tracking feedback operation (i.e., the current comparison and feedback operation) performed by the comparison and tracking unit CTS can be greatly shortened. Therefore, the time taken to detect the threshold voltage of the driving element (hereinafter referred to as the sensing additional time) can be significantly reduced.

[0054] The digital-to-analog converter DAC may adjust the level of the sensing data voltage to be proportional to the level of the current tracking data TDATA, and may provide the level-adjusted sensing data voltage to the data line 140 .

[0055] The electroluminescent display device according to an embodiment of the present disclosure may further include a pixel power supply regulating circuit PCT for preventing the light emitting device included in each pixel PXL from emitting undesired light in the sensing drive. This will be referred to below. Figure 5 Give a description.

[0056] Figure 5 It is shown in detail Figure 3 Diagram of the drive system. Figure 6 It is shown Figure 5 Diagram of the operating waveform of the drive system. Figure 7 It is shown for Figure 5 FIG. 1 is a diagram of a first source voltage and a second source voltage of a display driver and a sense driver in a driving system of FIG. 1 . Figure 8 It is shown in Figure 5 FIG. 1 is a diagram of an example of a current tracking feedback operation performed in a drive system.

[0057] Reference Figures 5 to 8 , the electroluminescent display device according to an embodiment of the present disclosure may include a pixel PXL, a comparison and tracking unit CTS, and a digital-to-analog converter DAC, and may further include a pixel power regulating circuit PCT.

[0058] The pixel PXL may include a light emitting element EL, a driving element DT, switching elements ST1 and ST2, and a storage capacitor Cst. The driving element DT and the switching elements ST1 and ST2 may be implemented with NMOS transistors, but are not limited thereto.

[0059] The light emitting device EL may emit light using the display driving current Ie1 provided from the driving element DT. The light emitting device EL may emit light only in display driving and not in sensing driving. The light emitting device EL may be implemented with an organic light emitting diode including an organic light emitting layer, or may be implemented with an inorganic light emitting diode including an inorganic light emitting layer. The anode electrode of the light emitting device EL may be connected to the second node N2, and the cathode electrode thereof may be connected to the input terminal of the second source voltage EVSS.

[0060] In display driving, the driving element DT may generate a first drain-source current Idt based on a first gate-source voltage (ie, VDIS-Vref), and the first drain-source current Idt may be a display driving current Ie1. In sensing driving, the driving element DT may generate a second drain-source current Idt based on a second gate-source voltage (ie, VSEN-Vref), and the second drain-source current Idt may be a driving current Isen. The gate of the driving element DT may be connected to a first node N1, its drain may be connected to a first power supply line PWL through an input terminal of a first source voltage EVDD, and its source may be connected to a second node N2.

[0061] The switching elements ST1 and ST2 can be turned on in display driving or sensing driving, and the gate electrode of the driving element DT can be connected to the data line 140, the source electrode of the driving element DT can be connected to the reference voltage line 150, and the gate-source voltage of the driving element DT can be set. The switching elements ST1 and ST2 can be turned on based on the same gate signal SCAN. The switching elements (e.g., the first and second switching elements) ST1 and ST2 can be continuously kept turned on in sensing driving.

[0062] The first switching element ST1 may be connected between the data line 140 and the first node N1, and may be turned on based on the gate signal SCAN from the gate line 160. The first switching element ST1 may be turned on in a program for display driving, or may be turned on in sensing driving. When the first switching element ST1 is turned on, a sensing data voltage VSEN or a display data voltage VDIS may be applied to the first node N1. The gate electrode of the first switching element ST1 is connected to the gate line 160, the source thereof may be connected to the data line 140, and the drain thereof may be connected to the first node N1.

[0063] The second switching element ST2 may be connected between the reference voltage line 150 and the second node N2, and may be turned on based on the gate signal SCAN from the gate line 160. The second switching element ST2 may be turned on in a program for display driving, and may transfer the reference voltage Vref (see Fig. 9 ) is applied to the second node N2. In the sensing drive, the second switching element ST2 can be turned on, and the reference voltage Vref (see Fig. 9 ) is applied to the second node N2, and may transmit the driving current generated by the driving element DT to the reference voltage line 150. The gate of the second switching element ST2 may be connected to the gate line 160, the drain thereof may be connected to the second node N2, and the source thereof may be connected to the reference voltage line 150.

[0064] The storage capacitor Cst may be connected between the first node N1 and the second node N2 and may store a gate-source voltage of the driving element DT.

[0065] The pixel power regulation circuit PCT can generate a first source voltage EVDD and can provide the first source voltage EVDD to an input terminal of the first source voltage EVDD through the first power line PWL, and further, can generate a second source voltage EVSS and can provide the second source voltage EVSS to an input terminal of the second source voltage EVSS included in the pixel PXL.

[0066] In display driving, the pixel power supply regulating circuit PCT can generate a first source voltage EVDD having a first value EVDD1, and can generate a second source voltage EVSS having a second value EVSS1. Figure 6 and Figure 7 As shown, since the first value EVDD1 is higher than the second value EVSS1, in display driving, the light emitting device EL of each pixel PXL may emit light using the display driving current Ie1.

[0067] In the sensing drive, the pixel power supply regulating circuit PCT may generate a first source voltage EVDD having a third value EVDD2, and may generate a second source voltage EVSS having a fourth value EVSS2. Figure 6 and Figure 7 As shown, the third value EVDD2 may be higher than the reference voltage Vref and may be lower than the fourth value EVSS2. Since the third value EVDD2 is higher than the reference voltage Vref, the driving current Isen may be generated in the sensing drive. In addition, since the third value EVDD2 is lower than the fourth value EVSS2, the driving current Isen may not flow to the light emitting device EL in the sensing drive and may flow to the reference voltage line 150, and the light emitting device EL may be prevented from emitting undesired light.

[0068] The comparison and tracking unit CTS may operate in the sensing drive and may not operate in the display drive. The comparison and tracking unit CTS may compare the driving current Isen input from the reference voltage line 150 with a predetermined reference low current REF-LOW and a predetermined reference high current REF-HIGH, and thus may check whether the driving current Isen is within a current phase (i.e., a target current range) between the reference low current REF-LOW and the reference high current REF-HIGH. In addition, the comparison and tracking unit CTS may perform a fast tracking feedback operation until the driving current Isen is within the target current range, and thus may change the current tracking data TDATA for adjusting the level of the sensing data voltage VSEN.

[0069] For example, Figure 6 As shown, when the first driving current Is1 corresponding to the first sensing data voltage VSEN1 is higher than the target current range, the comparing and tracking unit CTS may decrease the current tracking data TDATA to allow the second sensing data voltage VSEN2 to be applied to the pixel PXL. Subsequently, when the second driving current Is2 corresponding to the second sensing data voltage VSEN2 is lower than the target current range, the comparing and tracking unit CTS may increase the current tracking data TDATA to allow the third sensing data voltage VSEN3 to be applied to the pixel PXL.

[0070] When the driving current Isen having a specific value is within the target current range as a result of the fast tracking feedback operation, the comparison and tracking unit CTS may stop the operation of changing the current tracking data TDATA, and may calculate the threshold voltage of the driving element DT based on the driving current Isen having a specific value. In other words, the comparison and tracking unit CTS may calculate the gate-source voltage (VSEN-Vref) of the driving element DT corresponding to the driving current Isen having a specific value as the threshold voltage of the driving element DT.

[0071] For example, Figure 6 As shown, when the third driving current Is3 corresponding to the third sensing data voltage VSEN3 is within the target current range, the comparing and tracking unit CTS can calculate the gate-source voltage (VSEN3-Vref) of the driving element DT corresponding to the third driving current Is3 as the threshold voltage of the driving element DT.

[0072] Here, the gate-source voltage (VSEN3-Vref) of the driving element DT may be a difference voltage between the third sensing data voltage VSEN3 applied to the gate electrode of the driving element DT through the data line 140 and the reference voltage Vref applied to the source electrode of the driving element DT through the reference voltage line 150. The third sensing data voltage VSEN3 may be the sensing data voltage VSEN in which the level thereof is adjusted for the third driving current Is3, and the reference voltage Vref may have a fixed level regardless of the level of the driving current Isen.

[0073] In order to perform a fast tracking feedback operation, the comparing and tracking unit CTS may include a current buffer CBuF, a first current comparator COMP1, a second current comparator COMP2, a logic circuit CP, and an application specific integrated circuit ASIC.

[0074] The current buffer CBuF can provide a reference voltage Vref to the reference voltage line 150 (see Fig. 9), and can mirror the driving current Isen input through the reference voltage line 150 to output the mirrored driving current to the node Nx. The current buffer CBuF can prevent direct connection between the reference voltage line 150 and the node Nx to allow panel noise included in the driving current Isen not to be applied to the first current comparator COMP1 and the second current comparator COMP2. The current buffer CBuF can increase noise resistance to the driving current Isen as an ultra-low current.

[0075] The first current comparator COMP1 may compare the reference high current REF-HIGH with the driving current Isen input through the node Nx to output a first comparison result signal C1. The first current comparator COMP1 may include a first non-inverting input terminal (+) connected to the node Nx, a first inverting input terminal (-) connected to a first current source A1 generating the reference high current REF-HIGH, and a first output terminal outputting the first comparison result signal C1.

[0076] Since the first current comparator COMP1 compares the reference high current REF-HIGH of the first inverting input terminal (-) with the driving current Isen input through the first non-inverting input terminal (+), when Figure 8 When the driving current Isen is greater than the reference high current REF-HIGH, the first current comparator COMP1 can output the first comparison result signal C1 as a high logic value "1", and when the driving current Isen is less than or equal to the reference high current REF-HIGH, the first current comparator COMP1 can output the first comparison result signal C1 as a low logic value "0". Because the reference low current REF-LOW is lower than the reference high current REF-HIGH, the range in which the driving current Isen is lower than the reference low current REF-LOW can be included in the range in which the driving current Isen is lower than the reference high current REF-HIGH. Therefore, even in this case, as Figure 8 As shown, the first current comparator COMP1 may also output the first comparison result signal C1 as a low logic value “0”.

[0077] The second current comparator COMP2 may compare the reference low current REF-LOW with the driving current Isen input through the node Nx to output a second comparison result signal C2. The second current comparator COMP2 may include a second inverting input terminal (-) connected to the node Nx, a second non-inverting input terminal (+) connected to a second current source A2 generating the reference low current REF-LOW, and a second output terminal outputting the second comparison result signal C2.

[0078] Since the second current comparator COMP2 compares the reference low current REF-LOW of the second non-inverting input terminal (+) with the driving current Isen input through the second inverting input terminal (-), when Figure 8 When the driving current Isen is less than the reference low current REF-LOW, the second current comparator COMP2 can output the second comparison result signal C2 as a high logic value "1", and when the driving current Isen is greater than or equal to the reference low current REF-LOW, the second current comparator COMP2 can output the second comparison result signal C2 as a low logic value "0". Because the reference low current REF-LOW is lower than the reference high current REF-HIGH, the range in which the driving current Isen is higher than the reference high current REF-HIGH can be included in the range in which the driving current Isen is higher than the reference low current REF-LOW. Even in this case, as Figure 8 As shown, the second current comparator COMP2 can also output the second comparison result signal C2 as a low logic value “0”.

[0079] The logic circuit CP may be connected to the first output terminal of the first current comparator COMP1 and the second output terminal of the second current comparator COMP2. The logic circuit CP may generate a data adjustment signal FO based on the logic values ​​of the first comparison result signal C1 and the second comparison result signal C2.

[0080] When the logic value of the first comparison result signal C1 is different from the logic value of the second comparison result signal C2, the logic circuit CP can output one of the down control signal DN and the up control signal UP as the data adjustment signal FO, and when the logic value of the first comparison result signal C1 is the same as the logic value of the second comparison result signal C2, the logic circuit CP can output the hold control signal HOLD as the data adjustment signal FO.

[0081] exist Figure 8 In an embodiment, when the first comparison result signal C1 has a high logic value "1" and the second comparison result signal C2 has a low logic value "0", the logic circuit CP may output a down control signal DN as the data adjustment signal FO. When the first comparison result signal C1 has a low logic value "0" and the second comparison result signal C2 has a high logic value "1", the logic circuit CP may output an up control signal UP as the data adjustment signal FO. When each of the first comparison result signal C1 and the second comparison result signal C2 has a low logic value "0", the logic circuit CP may output a hold control signal HOLD as the data adjustment signal FO.

[0082] The application-specific integrated circuit ASIC may decrease, increase, or hold the current tracking data TDATA based on the data adjustment signal FO input from the logic circuit CP. The application-specific integrated circuit ASIC may decrease the value of the current tracking data TDATA based on the down control signal DN, may increase the value of the current tracking data TDATA based on the up control signal UP, and may hold the value of the current tracking data TDATA unchanged based on the hold control signal HOLD.

[0083] The current tracking data TDATA can be provided to the digital-to-analog converter DAC from the application-specific integrated circuit ASIC. Based on the reduction of the current tracking data TDATA, such as Figure 6 As shown, the digital-to-analog converter DAC may generate a second sensing data voltage VSEN2 which is less than the first sensing data voltage VSEN1 which is a previous value, and may provide the second sensing data voltage VSEN2 to the data line 140. Therefore, the driving current Isen output by the driving element DT to the reference voltage line 150 may be a second driving current Is2 which is lower than the first driving current Is1.

[0084] Based on the increase of current tracking data TDATA, such as Figure 6 As shown, the digital-to-analog converter DAC may generate a third sensing data voltage VSEN3 greater than the second sensing data voltage VSEN2 as a previous value, and may provide the third sensing data voltage VSEN3 to the data line 140. Therefore, the driving current Isen output by the driving element DT to the reference voltage line 150 may be the third driving current Is3 higher than the second driving current Is2.

[0085] Based on the maintained current tracking data TDATA, such as Figure 6 As shown, the digital-to-analog converter DAC may generate a third sensing data voltage VSEN3 as a previous value and may provide the third sensing data voltage VSEN3 to the data line 140. Therefore, the driving current Isen output by the driving element DT to the reference voltage line 150 may maintain the third driving current Is3 as a previous value.

[0086] In addition, since the hold control signal HOLD is generated when the driving current of the corresponding pixel is within the target current range, the application-specific integrated circuit ASIC can detect the gate-source voltage of the driving element included in the corresponding pixel based on the sensing data voltage corresponding to the hold control signal HOLD, and can calculate the gate-source voltage as the threshold voltage of the driving element.

[0087] Fig. 9 It is shown that the Figure 5 Figure 1 shows an example of a current buffer CbuF in a drive system. Fig. 9, the current buffer CbuF may include an input unit, a mirror unit and an output unit.

[0088] The input unit may provide a reference voltage Vref to the reference voltage line 150 , and may receive a driving current Isen through the reference voltage line 150 .

[0089] The input unit may include an input amplifier AMP and an input transistor T1. The input amplifier AMP may include a non-inverting input terminal (+) through which a reference voltage Vref is input, an inverting input terminal (-) connected to a reference voltage line 150, and an output terminal connected to a node Na. The input transistor T1 may include a gate electrode connected to the node Na, a drain electrode connected to the reference voltage line 150, and a source electrode connected to a node Nb. The driving current Isen may be buffered in the input unit and may be provided to the mirror unit.

[0090] The input unit may further include an initial switch SW connected between an inverting input terminal (-) and an output terminal of the input amplifier AMP. The initial switch SW may be turned on in a first period for providing a reference voltage Vref to the reference voltage line 150, and may be turned off in a second period for receiving a drive current Isen through the reference voltage line 150. When the initial switch SW is turned on in the first period, the time taken to charge the reference voltage Vref to the reference voltage line 150 may be shorter than the time in the absence of the initial switch SW, and thus, the sensing additional time may be further reduced.

[0091] The mirror unit may be connected to the input unit through a node Nb, and may mirror the drive current Isen to allow the drive current Isen to flow in a node Nc. The mirror unit may include a first mirror transistor T2 and a second mirror transistor T3. The gate and drain of the first mirror transistor T2 may be connected to the node Nb, and the source thereof may be connected to a ground voltage source GND. The gate of the second mirror transistor T3 may be connected to the node Nb, the drain thereof may be connected to the node Nc, and the source thereof may be connected to the ground voltage source GND.

[0092] The output unit can be connected to the mirror unit through the node Nc, and the mirrored drive current Isen can be output to the node Nx. The output unit may include a first output transistor T4 and a second output transistor T5. The gate electrode and the source electrode of the first output transistor T4 may be connected to the node Nc. The gate electrode of the second output transistor T5 may be connected to the node Nc, and its source electrode may be connected to the node Nx. The drain of the first output transistor T4 may be connected to the drain of the second output transistor T5.

[0093] Fig.10 It is shown that by Figure 5 FIG. 1 is a diagram showing the time taken for the threshold voltage of a driving element in a driving system of FIG. 1 to be driven by a driver of FIG. 1 , and a result obtained by comparing the time taken for the threshold voltage of a driving element in a driving system of FIG. 1 with that of the prior art.

[0094] like Figure 6 As shown, in display driving, the level of the first source voltage EVDD and the level of the data voltage can be relatively low compared to sensing driving. With respect to the first source voltage EVDD, EVDD2 for sensing driving can be lower than EVDD1 for display driving. With respect to the data voltage Vdata, the sensing data voltage VSEN can be lower than the display data voltage VDIS. Therefore, the driving current for sensing driving can be lower than the driving current for display driving. In this embodiment, since the driving current much lower than the display driving current is the comparison target for detecting the threshold voltage of the driving element, the sensing additional time can be easily reduced.

[0095] In addition, in order to detect the threshold voltage of the driving element, the following prior art is known, in which the gate voltage of the driving element is fixed to the sensing data voltage DRG, and the source voltage DRS of the driving element is increased by using a source follower based on the driving current. This technology increases the source voltage DRS of the driving element and the voltage of the reference voltage line until the gate-source voltage of the driving element is the threshold voltage of the driving element. However, in this technology, real-time sensing based on the vertical blank period is not feasible because the time taken to detect the threshold voltage of the driving element (ie, the sensing additional time TA) is long due to the parasitic capacitance of the reference voltage line connected to the source electrode of the driving element.

[0096] On the other hand, based on the fast tracking feedback configuration based on the current comparison operation, the driving system according to the present disclosure can quickly detect the threshold voltage of the driving element in a state where the influence of the parasitic capacitance of the reference voltage line is excluded, and therefore, the sensing additional time TB can be significantly reduced compared to the prior art. When the sensing additional time TB is reduced, real-time sensing and compensation can be performed, and the update period of the compensation value may be shorter, and therefore, the threshold voltage compensation performance of the driving element can be significantly improved.

[0097] According to an embodiment of the present disclosure, based on a fast tracking feedback configuration based on a current comparison operation, the threshold voltage of a driving element can be quickly detected while excluding the influence of the parasitic capacitance of a reference voltage line, and thus the additional sensing time can be greatly reduced. When the additional sensing time is reduced, real-time sensing and compensation can be performed, and the update period of the compensation value may be shorter, and thus, the threshold voltage compensation performance of the driving element can be greatly improved.

[0098] The effects according to the present disclosure are not limited to the above-mentioned examples, and other various effects may be included in the present specification.

[0099] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An electroluminescent display device, comprising: a pixel connected to a data line and a reference voltage line, the pixel comprising a driving element configured to generate a driving current based on a sensing data voltage provided through the data line and a reference voltage provided through the reference voltage line, and a level of the driving current is proportional to a level of the sensing data voltage; a comparison and tracking circuit configured to: predetermine a target current range between a reference low current and a reference high current, and change current tracking data for adjusting a level of the sensing data voltage until the driving current input through the reference voltage line is within the target current range; as well as a digital-to-analog converter configured to: adjust the level of the sensing data voltage to be proportional to the size of the current tracking data, and provide the level-adjusted sensing data voltage to the data line, When the driving current having a first value is within the target current range, the comparison and tracking circuit stops changing the current tracking data and calculates the threshold voltage of the driving element based on the driving current having the first value.

2. The electroluminescent display device according to claim 1, wherein: The comparison and tracking circuit calculates a gate-source voltage of the driving element corresponding to the driving current having the first value as a threshold voltage of the driving element, The gate-source voltage of the driving element is a voltage difference between a first sensing data voltage applied to the gate electrode of the driving element through the data line and a reference voltage applied to the source electrode of the driving element through the reference voltage line, The first sensing data voltage is a sensing data voltage whose level is adjusted so that the driving current has the first value, and The reference voltage has a fixed level independent of a level of the driving current.

3. The electroluminescent display device according to claim 1, wherein: The comparison and tracking circuit comprises: a current buffer configured to provide the reference voltage to the reference voltage line, and mirror the driving current input through the reference voltage line to output the mirrored driving current to a first node; a first current comparator configured to compare the reference high current with the driving current input through the first node to output a first comparison result signal; a second current comparator configured to compare the reference low current with the driving current input through the first node to output a second comparison result signal; a logic circuit configured to output a data adjustment signal based on a logic value of the first comparison result signal and a logic value of the second comparison result signal; and An application specific integrated circuit is configured to reduce, increase, or maintain the current tracking data based on the data conditioning signal.

4. The electroluminescent display device according to claim 3, wherein: The first current comparator includes a first non-inverting input terminal connected to the first node and a first inverting input terminal connected to a first current source generating the reference high current, and The second current comparator includes a second inverting input terminal connected to the first node and a second non-inverting input terminal connected to a second current source generating the reference low current.

5. The electroluminescent display device according to claim 3, wherein: When the logic value of the first comparison result signal is different from the logic value of the second comparison result signal, the logic circuit outputs one of a down control signal and an up control signal as the data adjustment signal, and when the logic value of the first comparison result signal is the same as the logic value of the second comparison result signal, the logic circuit outputs a hold control signal as the data adjustment signal.

6. The electroluminescent display device according to claim 5, wherein: When the logic value of the first comparison result signal is logic high and the logic value of the second comparison result signal is logic low, a down control signal is output as the data adjustment signal, When the logic value of the first comparison result signal is logic low and the logic value of the second comparison result signal is logic high, the up control signal is output as the data adjustment signal, and When each of the logic value of the first comparison result signal and the logic value of the second comparison result signal is logic low, a holding control signal is output as the data adjustment signal.

7. The electroluminescent display device according to claim 6, wherein: The ASIC performs the following operations: decreasing the value of the current tracking data based on the step-down control signal, increasing the value of the current tracking data based on the up control signal, and The current tracking data is maintained unchanged based on the hold control signal.

8. The electroluminescent display device according to claim 3, wherein: The current buffer comprises: an input circuit configured to provide the reference voltage to the reference voltage line and receive the drive current through the reference voltage line; a mirror circuit connected to the input circuit via a second node to mirror the drive current; and An output circuit is connected to the mirror circuit through a third node to output a mirrored driving current to the first node.

9. The electroluminescent display device according to claim 8, wherein: The input circuit comprises: an input amplifier including a non-inverting input terminal through which the reference voltage is input, an inverting input terminal connected to the reference voltage line, and an output terminal connected to a fourth node; and An input transistor includes a gate electrode connected to the fourth node, a drain electrode connected to the reference voltage line, and a source electrode connected to the second node.

10. The electroluminescent display device according to claim 9, wherein: The input circuit further includes an initial switch connected between the inverting input terminal and the output terminal of the input amplifier, and The initial switch is turned on in a first period for supplying the reference voltage to the reference voltage line, and is turned off in a second period for receiving the driving current through the reference voltage line.

11. The electroluminescent display device according to claim 1, wherein: The pixel further comprises: a first source voltage terminal connected to the drain electrode of the driving element, a light emitting device including an anode electrode connected to the source electrode of the driving element, and a second source voltage terminal connected to the cathode electrode of the light emitting device, A first source voltage applied to the first source voltage terminal is higher than the reference voltage and lower than a second source voltage applied to the second source voltage terminal, and The driving current does not flow to the light emitting device but flows to the reference voltage line.

12. A method for driving an electroluminescent display device, the electroluminescent display device comprising a pixel connected to a data line and a reference voltage line and comprising a driving element, the driving element being configured to generate a driving current based on a sensing data voltage provided through the data line and a reference voltage provided through the reference voltage line, and wherein: The level of the driving current is proportional to the level of the sensing data voltage, and the driving method includes: predetermining a target current range between a reference low current and a reference high current, and changing current tracking data for adjusting a level of the sensing data voltage until the driving current input through the reference voltage line is within the target current range; and adjusting the level of the sensing data voltage to be proportional to the size of the current tracking data, and providing the level-adjusted sensing data voltage to the data line, When the driving current having a first value is within the target current range, the operation of changing the current tracking data is stopped, and the threshold voltage of the driving element is calculated based on the driving current having the first value.

13. The driving method according to claim 12, wherein: Calculating the threshold voltage of the driving element includes: calculating a gate-source voltage of the driving element corresponding to the driving current having the first value as the threshold voltage of the driving element, The gate-source voltage of the driving element is a voltage difference between a first sensing data voltage applied to the gate electrode of the driving element through the data line and a reference voltage applied to the source electrode of the driving element through the reference voltage line, The first sensing data voltage is a sensing data voltage whose level is adjusted so that the driving current has the first value, and The reference voltage has a fixed level independent of a level of the driving current.

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